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2002 - PTR2000

Abstract: rs232 pc MAX232 AT90S2313 PIC16C MAX232 dip 68HC05 80C31 80c31-20
Text: PTR2000 19.2K MODEM ! ! 433MHz ! FSK ! DDS+PLL ! -105dBm ! +10dBm ! 2.7V 8uA. ! ! 20Kbit /s 9600bps ! 40mmx27mmx5mm ! CPU 8031 RS232 ! ! DIP RF 232 422/485 @3V 400 @400 20Kbit /s PWR=0 433.92MHz/434.33MHz FSK PLL <+10dBm -105dBm 20Kbit /s 2.75.25V 2030mA 10mA 8uA Pin1: VCC, 2.75.25V COPYRIGHT ©2002 ALL , DO 3 I/O 4 RTS PTR2000 MODEM -RTS 1 1 20Kbit /s 4800bps9600bps PTR2000


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PDF PTR2000 433MHz -105dBm 10dBm 20Kbit/s 9600bps 40mmx27mmx5mm RS232 20Kbit/s 92MHz/434 PTR2000 rs232 pc MAX232 AT90S2313 PIC16C MAX232 dip 68HC05 80C31 80c31-20
echo delay reverb ic

Abstract: delay reverb ic M50194P echo reverb ic echo delay reverb digital reverb processor diagram reverberation IC digital reverb ic Echo Processor IC delay reverb Processor IC
Text: pass filters and a 20K-bit SRAM, making it possible to form a low cost digital delay system. · Low , TIME CONTROL MODE CONTROL 20K-bit SRAM MODE'I I MUTE MODE2 uCOM/ËÂSY A-GND D-GND VCC VDD


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PDF M50194P M50194P 20K-bit LPF10UT 0P20UT 0P10UT LPF20UT DEM51 echo delay reverb ic delay reverb ic echo reverb ic echo delay reverb digital reverb processor diagram reverberation IC digital reverb ic Echo Processor IC delay reverb Processor IC
2002 - VOICE RECORDER playback system

Abstract: mp3 hardware decoder simple deep bass amplifier g723 Adaptive Differential Pulse Code Modulation Decoder TQFP44 STA015 STA013 mp3 decoder circuit mp3 decoder
Text: MMDSP+ mp3Pro Decoder < 25 MIPS; <10 kbit PROM; < 20kbit RAM mp3 Encoder < 50 MIPS; <20 kbit PROM; <35kbit RAM AAC Decoder < 25 MIPS; <6 kbit PROM; < 20kbit RAM SRS WOWTM < 25 MIPS; <4 kbit PROM


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PDF STA015 320Kbit/s 32kHz 32-bits G723-24, G723-40) TQFP44 VOICE RECORDER playback system mp3 hardware decoder simple deep bass amplifier g723 Adaptive Differential Pulse Code Modulation Decoder STA013 mp3 decoder circuit mp3 decoder
FCK 1

Abstract: circle surround IC digital to analog tv converter ic m65850p MITSUBISHI Digital Echo delay 8 ICs Operation Amplifier delay echo circuit diagram MITSUBISHI Digital Echo 4P4 amplifier
Text: generating clocks Delay time = 164 ms (Min. 15 ms to Max. 200 ims can be set) Built-in SRAM of 20Kbit Small , CONTROL M1 D01 000 20Kbit SRAM = r~ jp F i i= A/D - LPF1 IN LPF1 OUT ® OP1 OUT ©"


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PDF M65850P M65844P, M65850P M65844P M65844P M65850P. FCK 1 circle surround IC digital to analog tv converter ic MITSUBISHI Digital Echo delay 8 ICs Operation Amplifier delay echo circuit diagram MITSUBISHI Digital Echo 4P4 amplifier
ALL DIGITAL ECHO IC

Abstract: delay echo circuit diagram Digital ECHO microphone mixing circuit Karaoke Processor IC analog ECHO microphone mixing circuit diagram Echo Processor IC delay 16P2N analog ECHO microphone mixing circuit low pass filter with no ic or power supply M65855FP
Text: echo system with a single chip. • High performance digital echo circuit thanks to 20Kbit memory â , MAIN CONTROL MC M D1 DOO 20Kbit SRAM lpf1 A/D 10-11-12- ■to HH ft 13- J -1 -I GND


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PDF 20log 012pF, 4700pF, 164msec M65855FP ALL DIGITAL ECHO IC delay echo circuit diagram Digital ECHO microphone mixing circuit Karaoke Processor IC analog ECHO microphone mixing circuit diagram Echo Processor IC delay 16P2N analog ECHO microphone mixing circuit low pass filter with no ic or power supply M65855FP
1997 - karaoke CIRCUIT

Abstract: karaoke echo chip 16pin dip echo digital ic Karaoke Processor IC Digital Echo delay 16 Pin ICs 16 Pin Echo delay digital ICs karaoke amplifier CIRCUIT echo sound ic 6800P M65850FP
Text: Built-in 20Kbit SRAM · Built-in auto reset circuit (The IC reset as power is turned on) · Single power , CONTROL D1 MO MI DO0 20Kbit SRAM A / D LPF1 1 2 3 4 LPF1IN LPF1OUT OP1OUT OP1IN , RESET MAIN CONTROL MI D1 DO0 20Kbit SRAM A / D LPF1 2 3 4 5 LPF1IN LPF1OUT OP1OUT OP1IN


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PDF M65850P/FP M65850P/FP 3300p M65850FP karaoke CIRCUIT karaoke echo chip 16pin dip echo digital ic Karaoke Processor IC Digital Echo delay 16 Pin ICs 16 Pin Echo delay digital ICs karaoke amplifier CIRCUIT echo sound ic 6800P M65850FP
1998 - karaoke CIRCUIT

Abstract: Karaoke Processor IC karaoke Digital ECHO microphone mixing circuit echo sound ic karaoke amplifier CIRCUIT delay echo circuit diagram DIGITAL ECHO IC M65855FP m65855
Text: digital echo circuit thanks to 20Kbit memory · Thanks to the improvement A/D,D/A converters,decrease the , 1/2 Vcc CLOCK DO1 AUTO RESET MO RESET MAIN CONTROL MI D1 DO0 20Kbit SRAM


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PDF M65855FP M65855FP 4700p 3300p karaoke CIRCUIT Karaoke Processor IC karaoke Digital ECHO microphone mixing circuit echo sound ic karaoke amplifier CIRCUIT delay echo circuit diagram DIGITAL ECHO IC m65855
usb i2c spi converter

Abstract: i2c to rs485 converter 75176 usb spi converter rs485 to i2c master converter spi to usb RS485 to I2C RS-485 communication CONVERTER USB-2-X
Text: LIN specification rev 1.3 up to 20kBit /s Industry standard transceiver USB I²C Single master


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PDF RS485, RS485 20kBit/s 400kBit/s RS-485 RS485 usb i2c spi converter i2c to rs485 converter 75176 usb spi converter rs485 to i2c master converter spi to usb RS485 to I2C RS-485 communication CONVERTER USB-2-X
radio transmitter and receiver

Abstract: FM-RX1-433A QFMR5-434 QFMT5-434 FM RADIO TRANSMITTER AND RECEIVER
Text: QUASAR 1 S ^ ^ ~f I 433MHz FM Radio Transmitter and Receiver • MINIATURE SIL PACKAGE • FULLY SHIELDED • DATA RATES UP TO 20KBITS /S • RANGE UPTO 400 METRES • SINGLE SUPPLY VOLTAGE • INDUSTRY PIN COMPATIBLE QFMT5-434 • TEMP RANGE -20°C to +55°C • NO ADJUSTABLE COMPONENTS • GOOD SHOCK RESISTANCE QFMR5-434 • HIGH SENSITIVITY • ANALOUGE, DIGITAL OUTPUTS • SIGNAL STRENGTH , telemetry link upto 400 metres, and at data rates of up to 20Kbit /s The QFMT5 and QFMR5 modules will suit


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PDF 433MHz 20KBITS/S QFMT5-434 QFMR5-434 FM-TX1-433 FM-RX1-433A FM-TX2-433 -RX2-433A-5V files\ChopdatE\Desktop\CatalogueApr2001Vf solutions\0010 radio transmitter and receiver FM-RX1-433A QFMR5-434 QFMT5-434 FM RADIO TRANSMITTER AND RECEIVER
2014 - Not Available

Abstract: No abstract text available
Text: €“105.5dBm at 20Kbit /s/–109dBm at 2.4Kbit/s (433.92MHz) ● High ASK sensitivity: –111.5dBm at 10Kbit/s/â , (3V/TX with 5dBm/433.92MHz) ● Data rate 1 to 20Kbit /s Manchester FSK, 1 to 10Kbit/s Manchester ASK , switching of the power amplifier for ASK transmission. The device supports data rates of 1Kbit/s to 20Kbit , fhi_IF = 336kHz). The demodulator needs a signal to noise ratio of 8dB for 20Kbit /s Manchester with  , ). With an ideal inductor, for example, the sensitivity at 433.92MHz/FSK/ 20Kbit /s/ Â


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PDF ATA5823/ATA5824 20Kbit/s/â 109dBm 92MHz) 10Kbit/s/â 116dBm 5dBm/433 20Kbit/s
RS-485 to spi converter

Abstract: 75176 datasheet of 75176 S485
Text: rev 1.3 up to 20kBit /s Industry standard transceiver · I² C single master up to 400kBit/s 7


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PDF RS-485 RS485 20kBit/s 400kBit/s RS-485 RS-485 to spi converter 75176 datasheet of 75176 S485
echo delay reverb ic

Abstract: m50194ap delay reverb ic echo reverb ic echo delay reverb reverberation IC reverb Processor IC DIGITAL ECHO reverb IC digital reverb ic mitsubishi reverb
Text: an A - D , D -A converter ( Adaptive Delta Modulation), two low pass filters and a 20K-bit SRAM. ·


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PDF M50194AP M50194AP 20K-bit -90dBV 40P4B echo delay reverb ic delay reverb ic echo reverb ic echo delay reverb reverberation IC reverb Processor IC DIGITAL ECHO reverb IC digital reverb ic mitsubishi reverb
2012 - TH8062

Abstract: No abstract text available
Text: . 24 Figure 16 - Power dissipation LIN transceiver @ 20kbit , transceiver parameter according to LIN Physical Layer Spec. rev. 2.0, table 3.4 ( 20kbit /s) Conditions: Normal , . The bus transceiver is able to send with a max baud rate of 20kbit /s. The whole TH8062 is active , normal mode the slew rate is typical 1.6 V/µs (max. baudrate 20kbit /s) and in low slew mode typical 0.8 V , 2.0 specification for data rates up to 20kbit /s and the SAE specification J2602 for data rates up to


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PDF TH8062 J2602 V/70mA ISO9141 ISO14001 TH8062
HWD232

Abstract: Chengdu Sino Microelectronics System chengdu
Text: HWD232 +5V RS-232 HWD232 RS232 V.28 5V RS232±10V±12V HWD232 20Kbit /s EIA/TIA-232E V.28/V.24 0.5V RS-232 13 C1C1 VS+ 2 VS 2Vcc 45 C2C2 VS 6 VS 2Vcc 714 T_OUT 813 R_IN 912 R_OUT 1011 T_IN 15 GND 16 Vcc +4.5 ~ +5.5 1 HWD232 RS232 0.1F ESR VS VS 10 VSVS- Chengdu Sino Microelectronics System Co., LTD HWD232 +5V RS-232 2


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PDF HWD232 RS-232 RS232 RS232 20Kbit/s EIA/TIA-232E HWD232 Chengdu Sino Microelectronics System chengdu
2004 - Not Available

Abstract: No abstract text available
Text: ZMD44101 Single-Chip 868MHz to 928MHz RF Transceiver Features Description ♦ ♦ ♦ ♦ ♦ ♦ IEEE 802.15.4 compliant ISM band transceiver with RF and baseband Direct Sequence Spread Spectrum (DSSS) Burst data rate 20kbit /s (EU), 40kbit/s (US) Transmit range up to 100 meter (LoS) Low power consumption for battery operated devices ♦ SPI and parallel interfaces ♦ PHY and Thin MAC compliant ♦ Available in 48-lead MLFTM package The ZMD44101 is a fully integrated


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PDF ZMD44101 868MHz 928MHz 20kbit/s 40kbit/s 48-lead ZMD44101 902MHz 928MHz 40kbps
2007 - VOLT REGULATOR IC 79XX

Abstract: 742T smd code 724g logic ic 7270 multi point fuel injection 742r 772t its 4140n XC2364 428l2
Text: No file text available


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PDF transp35 B112-H6731-G16-X-7600 VOLT REGULATOR IC 79XX 742T smd code 724g logic ic 7270 multi point fuel injection 742r 772t its 4140n XC2364 428l2
M50197P

Abstract: m50197 echo sound processors M50197P M50197P diagram echo sound processors delay echo circuit diagram Single Chip Digital Echo Analog echo delay digital echo 40P4B
Text: low pass filters and a 20K-bit SRAM, making it possible to form a low cost digital delay system. · Low


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PDF M50197P M50197P, M50197FP 20K-bit M50197P) 0P20U m50197 echo sound processors M50197P M50197P diagram echo sound processors delay echo circuit diagram Single Chip Digital Echo Analog echo delay digital echo 40P4B
2002 - B102

Abstract: CECC00802 J-STD-020A KL30 TH8061
Text: dissipation LIN transceiver @ 20kbit 19 Figure 14 - Save operating area 20 Figure 15 - ESR Curves , guarantees data rates up to 20kbit within the complete bus load range under worst case conditions. The , implementation in RC-based slave nodes (oscillator tolerance <2% at baudrate 20Kbit /s )under all worst case , =10nF, Bitrate= 20kbit and duty cycle on TxD of 50% Figure 13 - Power dissipation LIN transceiver @ 20kbit


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PDF TH8061 ISO9141 QS9000, ISO14001 B102 CECC00802 J-STD-020A KL30 TH8061
2014 - Not Available

Abstract: No abstract text available
Text: dBm @ 915 MHz -110 dBm IEEE 802.15.4 20kBit /sec, 40kBit/sec, 250 kbit/s, 500 kbit/s, 1 Mbit/s


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PDF 15A02 deRFarm7-15A02 AT91SAM7X512 AT86RF212. 15A02 AT91SAM7X512. 128-Bit BN-027265 BN-027264
2002 - J2602

Abstract: SOIC14 TH8065 VD10
Text: . 25 Figure 18 - Power dissipation LIN transceiver @ 20kbit , to LIN Physical Layer Spec. rev. 2.0, table 3.4 ( 20kbit /s) Conditions: Normal slew mode; VSUP , 20kbit /s. The whole TH8065 is active. Switching to normal mode can be done via the following actions: - , specification according to LIN 2.0 specification for data rates up to 20kbit /s and the SAE specification J2602 , RL=500, CL=10nF, bit rate= 20kbit and duty cycle on TxD of 50% 50 45 40 PD [mW] 35 30 25


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PDF TH8065 J2602 V/70mA ISO9141 J2602 ISO/TS16949 ISO14001 SOIC14 TH8065 VD10
2002 - J2602

Abstract: TH8061 TH8062 VD10
Text: . 23 Figure 16 - Power dissipation LIN transceiver @ 20kbit. , ] LIN transceiver parameter according to LIN Physical Layer Spec. rev. 2.0, table 3.4 ( 20kbit /s , mode. The bus transceiver is able to send with a max baud rate of 20kbit /s. The whole TH8062 is active , rate. In normal mode the slew rate is typical 1.6 V/µs (max. baudrate 20kbit /s) and in low slew mode , according to LIN 2.0 specification for data rates up to 20kbit /s and the SAE specification J2602 for data


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PDF TH8062 J2602 V/70mA ISO9141 J2602 ISO/TS16949 ISO14001 TH8061 TH8062 VD10
2010 - GMLAN

Abstract: TLE 4209A tle 8209 smd code 724g TLE8718SA BTS6143D 742T BTS50080-1TMA TLE7240SL tle 7718
Text: No file text available


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PDF 12F-1, B124-H9343-G1-X-7600 GMLAN TLE 4209A tle 8209 smd code 724g TLE8718SA BTS6143D 742T BTS50080-1TMA TLE7240SL tle 7718
2002 - J2602

Abstract: TH8061 TH8062 VD10
Text: . 23 Figure 16 - Power dissipation LIN transceiver @ 20kbit , ( 20kbit /s) Conditions: Normal slew mode; VSUP =7.0V to 18V; BUS loads: 1k/1nF; 660/6.8nF; 500/10nF , This mode is the base mode. The bus transceiver is able to send with a max baud rate of 20kbit /s. The , mode depended slew rate. In normal mode the slew rate is typical 1.6 V/µs (max. baudrate 20kbit /s) and , physical layer specification according to LIN 2.0 specification for data rates up to 20kbit /s and the SAE


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PDF TH8062 J2602 V/70mA ISO9141 J2602 ISO/TS16949 ISO14001 TH8061 TH8062 VD10
2008 - 7259-2GE

Abstract: TLE8458 12v voltage regulator TLE 7259-2GE J2602 SEAT Electronics
Text: Product Brief TLE8458 LIN - LDO Family Features THE TLE8458 as monolithic integrated circuit integrates a transceiver and a low drop voltage regulator. The integrated transceiver is especially suitable to drive the bus line in LIN systems in automotive and industrial applications. LIN Transceiver compatible to LIN 2.1 ( 20kbit /s) or SAE J2602 (10.4kbit/s) 5V or 3.3V Low Drop Voltage Regulator 50mA output current capability To reduce current consumption, the TLE8458 offers a Sleep Mode and a


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PDF TLE8458 TLE8458 20kbit/s) J2602 B124-H9344-X-X-7600 NB08-1310 7259-2GE 12v voltage regulator TLE 7259-2GE J2602 SEAT Electronics
2011 - Not Available

Abstract: No abstract text available
Text: transceiver with approximately ±2.5MHz programmable tuning range High FSK sensitivity: –106dBm at 20Kbit , 20Kbit /s Manchester FSK, 1 to 10Kbit/s Manchester ASK ASK/FSK receiver uses a low-IF architecture with , switching of the power amplifier for ASK transmission. The device supports data rates of 1Kbit/s to 20Kbit , for 20Kbit /s Manchester with ±16kHz frequency deviation in FSK mode; thus, the resulting sensitivity at 433.92MHz is typically –106dBm at 20Kbit /s Manchester. Due to the low phase noise and spurious


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PDF ATA5428 106dBm 20Kbit/s/â 92MHz) 10Kbit/s/â 20Kbit/s 10Kbit/s 750kHz/61dB 10MHz,
Supplyframe Tracking Pixel