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motorola 68020 instruction set

Abstract: tc85r4400 CQFP-208 TC85R4000SC CQFP208 R4000SC R3000A TC85R4000PC-50 PGA44 MIPS R3000A
Text: for floating decimal point operation, and 16K-byte cache memory while its operating system is equipped , module groups consist of 2M- byte RAM module (expandable), serial I/O module, and disk control module. On the other hand, auxiliary memory devices compeise 70M- byte hard disk, 655K- byte floppy disk, and , R3081TM functional compatible · R3000A + I -Cache+D-Cache+R/W Buffer · l-Cache 8 or t6K Byte · D-Cache 8 or 4K Byte · 4 deep FVW Butler Power management mode. (Added feature to IDT R3081) 3.3V 33MHz


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PDF TDS68DVLP TLCS-68000 32-bit 67MHz 16K-byte /68TM) 70M-byte 655K-byte motorola 68020 instruction set tc85r4400 CQFP-208 TC85R4000SC CQFP208 R4000SC R3000A TC85R4000PC-50 PGA44 MIPS R3000A
TC85R4000

Abstract: TC85R4400 MIPS R3000A As3000
Text: decimal point operation and 16K-byte cache memory while its operating system is equipped with UNIX (SYSTEM , or L) can be run on PCs which have a memory space of 2M- byte and above and also have CPU of ¡386 and , consist of 2M- byte RAM module (expandable), serial I/O module, and disk control module. On the other hand, auxiliary memory devices compeise 70M- byte hard disk, 655K- byte floppy disk, and storming tape cartridge , compatible · R3000A + I -Cache+D-Cache+R/W Buffer · l-Cache 8 or 16K Byte · D-Cache 8 or 4K Byte · 4 deep R/W


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PDF SW87AS0-TPE TLCS-870 SW90RS0-TPE TLCS-90 SW90AS0-TPE SW90CSO-TPE SW90RS1-TPE SW90RS2-TPE SW90RSA-TPE SW90RSC-TPE TC85R4000 TC85R4400 MIPS R3000A As3000
1996 - dil40

Abstract: 8031 8-Bit Microcontroller OM424 8031 MICROCONTROLLER interfacing to ROM OM1077 8031 interfacing to rom CL411 OM1083 SO20 Package lCC44
Text: timers Timer with compare and capture, 2 PWM outputs, 8 10-bit ADC inputs, Byte I2C OM1092 + OM1095 , DIL40/LCC44 QFP44 UART, 2 timers Byte I2C OM1092 + OM1096 + OM4120S 83652PC(M) POD-C51B(N) 16,24 16,20 DIL40/LCC44 QFP44 UART, 2 timers Byte I2C OM1092 + OM1096 + OM4120S 83654(M) OM1092 + OM1096 + OM4120S 83654(M) 16 16 QFP44 UART, 2 timers Byte I2C , 256 6 DIP28, LCC28 UART, 2 timers 256 byte POD-C752(N) 2k byte EEPROM smart card


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PDF 80C51 80C31 80C51 87C51 DIL40, LCC44 QFP44 87C51 16MHz OM1092 dil40 8031 8-Bit Microcontroller OM424 8031 MICROCONTROLLER interfacing to ROM OM1077 8031 interfacing to rom CL411 OM1083 SO20 Package lCC44
1997 - M5M4V4169

Abstract: No abstract text available
Text: : SRAM Write Enable WE# : I/O Byte Control DQC(u/l) : SRAM Address As : Output Enable G# : Data I , Address Buffer DRAM Ad8 Address Input Ad7 Ad6 Mask 0 1 0 Byte mask RB1 1 2 7 , 256KX16 DRAM Row Decoder 8X16 Ad0-9 1 of 1024 Decode 8X16 Byte Mask MASK MASK Byte Mask DQ0-7 RB1 Lower Byte Upper Byte WB2 DQ8-15 Lower Byte Upper Byte As0-2 1 of 8 Decode RB2 As0-2 1 of 8 Decode 8X16 Lower Byte Upper Byte 16 bits DQs Lower Byte Upper


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PDF M5M4V4169CRT-10 256K-WORD 16-BIT) 1024-WORD M5M4V4169CRT 144-word 16-bit 1024word M5M4V4169
1997 - M93C46BN1

Abstract: PLCC32 512k M2716-1F1 ST24C04M1 M93S46RBN1 200N1 M24C32MN1 M27C1024-12F7 M28F512-15C1 M27C256B-20C7
Text: No file text available


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PDF M2716-1F1 M2716-1F6 M2716F1 M2716F6 M2732A-2F1 M2732AF1 M2732AF6 M2732A-3F1 M2764A-1F1 M2764A-20F1 M93C46BN1 PLCC32 512k ST24C04M1 M93S46RBN1 200N1 M24C32MN1 M27C1024-12F7 M28F512-15C1 M27C256B-20C7
VS064

Abstract: 8031 8-Bit Microcontroller OM1079 84C41 LCC44 D1L40 OPD-C51B DIP64 package OM1083 84c21a
Text: , 8 10-bit ADC inputs, Byte I2C As 8xC552 with PLL-oscitlator Auto scan ADC UART, 2 timers Timer with , interface. No l2C UART, 2 timers Byte l2C UART, 2 timers Byte l2C UART, 2 timers Byte l2C 83C654 with , output, 5 8-bit ADC inputs, Bit l2C (8XC752 only) UART, 2 timers 256 byte 2k byte EEPROM smart card , , CL51, P80C51 Piggyback CL580 Piggyback CL781, CL782, CL52 2 timers, UART 2 timers Byte l2C 3timers, UART Watchdog timer Byte I C, 1 PWM 4*8 bit ADC Stimers, UART Byte l2C OM1079 OM1079 OM1079 + OM5004


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PDF 80C51 80C31 87C51 83C51FA 87C51FA 83L51FA 87L51FA 87C51FB 83C51FB VS064 8031 8-Bit Microcontroller OM1079 84C41 LCC44 D1L40 OPD-C51B DIP64 package OM1083 84c21a
1997 - m5m4v4169

Abstract: M5M4V4169CRT-10 256K-WORD M5M4V4169TP 70P3S-M 256-kword 1-OF-128 1kx16
Text: Write Enable WE# : I/O Byte Control DQC(u/l) : SRAM Address As : Output Enable G# : Data I/O DQ , Mask 0 1 0 Byte mask RB1 1 2 7 Read Buffer1 Read Buffer2 WB2 Write Buffer 2 , Decoder 8X16 Ad0-9 1 of 1024 Decode 8X16 Byte Mask MASK MASK Byte Mask DQ0-7 RB1 Lower Byte Upper Byte WB2 DQ8-15 Lower Byte Upper Byte As0-2 1 of 8 Decode RB2 As0-2 1 of 8 Decode 8X16 Lower Byte Upper Byte 16 bits DQs Lower Byte Upper Byte MASK


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PDF M5M4V4169CRT-10 256K-WORD 16-BIT) 1024-WORD M5M4V4169CRT 144-word 16-bit 1024word m5m4v4169 M5M4V4169TP 70P3S-M 256-kword 1-OF-128 1kx16
1998 - 1kx16

Abstract: diode wb1 SCR table TK 69 TSOP
Text: : SRAM Clock Mask CMs# CC0#,CC1# : Control Clocks : Write Enable WE# : I/O Byte Control DQC(u/l , RB1 Lower Byte WB2 Lower Byte Upper Byte Upper Byte DQ0-7 As0-2 1of8Decode DQ8-15 8X16 As0-2 1of8 Decode RB2 Lower Byte Upper Byte 16 bits DQs WB1 Lower Byte Upper Byte 16 bits 8X16 8X16 Block 16 bits 8X16 16 bits SRAM 1KX16 As0-2 1of8Decode , Suspend No operation - - - - - Byte mask - - - - - - Hi-Z


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PDF M5M4V16169DTP/RT-7 16MCDRAM 16-BIT) 1024-WORD M5M4V16169DTP/RT 16M-bit 576-word 16-bit 1kx16 diode wb1 SCR table TK 69 TSOP
1996 - 256k x8 SRAM 5V

Abstract: ST95080 rom 1K x8 mod 10 asynchronous ST1335 M28V210 M6280 3.3 -35Y M48Z09
Text: 5.5V 2.5V to 5.5V Features Byte /page write 10ms Byte /page write 10ms Byte /page write 10ms Byte /page write 10ms Byte /page write 10ms Byte /page write 10ms Byte /page write 10ms Byte /page write 10ms Byte /page write 10ms Byte /page write 10ms Write control input Write control input Write control input Write , Organis. Access time(ns) 70 - 150 70 - 150 70 - 150 70 - 150 70 - 150 Byte /page write 2ms 2ms 2ms 5ms 5ms , Byte /page write 2ms 2ms 3ms 10ms 10ms Features Packages M28C64C M28C64X M28LV16 M28LV17 M28LV64


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PDF M27C64A M27C256B M87C257 M27C512 M27C1001* M27C1024* M27C2001* M27C405* M27C4001 M27C4002 256k x8 SRAM 5V ST95080 rom 1K x8 mod 10 asynchronous ST1335 M28V210 M6280 3.3 -35Y M48Z09
WT6563F

Abstract: xbox joystick WT6563 xbox controller USB KEYBOARD midi xbox one 64Byte midi keyboard xbox
Text: WT6563F General Description WT6563F is a micro-controller based Full Spaed USB device with embedded Flash ROM. It contains a Turbo 6062 CPU, 16K-byte Flash ROM. 512- byte SRAM, 12 channels of 12 , compatible CPU with 24 MHz operating frequency 16K-byte mask ROM 256 bytes SRAM 4 192 by les Exlemal SRAM , 1.0 and XBOX XID specification. «1 conlrol endpoinl, INiOUT each with 64 Bytes (8/16ï32/64- byte programmable) FIFO *3 Generic end points (IN/OUT programmable) each with 64- Byte (B/16Ï32Ï64 bytes


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PDF WT6563F WT6563F 16K-byte 512-byte 12-bit RS232 32/64-byte 64-Byte xbox joystick WT6563 xbox controller USB KEYBOARD midi xbox one 64Byte midi keyboard xbox
1997 - TK 69 TSOP

Abstract: 1024KX16 M5M4V16169RT-10 1-OF-128 7WB1 AD011 M5M4V16169TP-10
Text: : Write Enable WE# DQC(u/l) : I/O Byte Control : SRAM Address As : Output Enable G# : Data I/O DQ , of 4096 Decode 8X16 RB1 Lower Byte Upper Byte MASK MASK WB2 As0-2 1 of 8 Decode Lower Byte Upper Byte RB2 8X16 16 bits Lower Byte Upper Byte As0-2 1 of 8 Decode Lower Byte Upper Byte MASK MASK WB1 DQs 16 bits 8X16 X 16 bits 8X16 8X16 Block , WB2 WB2 Lower Byte Upper Byte 1X8 Set WB2 Lower Mask Set WB2 Upper Mask Set WB2 Lower


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PDF M5M4V16169RT-10 16MCDRAM 1024K-WORD 16-BIT) 1024-WORD M5M4V16169TP 16M-bit 576-word 16-bit TK 69 TSOP 1024KX16 1-OF-128 7WB1 AD011 M5M4V16169TP-10
Not Available

Abstract: No abstract text available
Text: MX29L8100T/B A16 BYTE GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 , BYTE Q11 Q12 Q4 4 A9 Q5 Q6 Q13 3 Q14 Q15 /A-1 Q7 2 WP A18 , OE WE RP WP BYTE VCC GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 , ( Byte mode) Chip Enable Input Output Enable Input Write Enable Reset/Deep Power-down Write Protect Word/ Byte Selection Input Power Supply Pin (2.7V - 3.6V) Ground Pin A B A12 A15 A16 C


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PDF MX29L8100T/B 8/512K 120ns 16K-block) 16K-block PM0460
D1-D16

Abstract: No abstract text available
Text: , BYTE ENABLES PIN ASSIGNMENT (Top View) 52-Pin PLCC (SC-2) 52-Pin PQFP (SC-5) 5 VO LT CACHE DATA , . Byte Enables: These active LOW inputs allow individual bytes to be selected, permitting direct , byte , D1-D8, is enabled. When BHE is LOW, the upper byte , D9-D16, is enabled. The device will be in low power standby mode when both Byte Enables are inactive (HIGH) or when either Chip Enable is inactive , orCE=HIGH) or both Byte Enables are inactive. Output Enable: This active LOW input enables the output


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PDF 386SL MT56C16K16B2 D1-D16
1989 - IC 3130

Abstract: IC-8638 IC-3130 uPD75P117H uPD75P117HGC-AB8 uPD75*GK*8A8 PD75116H BTM200 EEU-1421 Kyocera kbr
Text: (programmable · Compatible with the µPD75117H · Contains 16K-byte mode/24K- byte mode change func , ) . 12 3. 16K-BYTE MODE/24K- BYTE MODE CHANGE FUNCTION . 13 3.1 Differences between 16K-Byte Mode and 24K- Byte Mode . 13 3.2 16K-Byte Mode and 24K- Byte Mode Change Method , ) 24448 × 8 bits (one-time PROM) 16K-byte mode/24K- byte mode change function Mask option Pin


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PDF PD75P117H PD75P117H PD75117H 16K-byte mode/24K-byte PD75117H. PD75P117H, IC 3130 IC-8638 IC-3130 uPD75P117H uPD75P117HGC-AB8 uPD75*GK*8A8 PD75116H BTM200 EEU-1421 Kyocera kbr
Not Available

Abstract: No abstract text available
Text: 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 MX29L8100T/B A16 BYTE GND , CE Q0 Q1 7 A17 A6 Q8 Q9 Q10 6 Q2 Q3 Vcc 5 BYTE Q11 , PIN CONFIGURATIONS SYMBOL A0 - A18 Q0 - Q14 Q15/A-1 CE OE WE RP WP BYTE VCC GND 48 47 , A10 A13 A14 PIN NAME Address Input Data Input/Output Q15(word mode)/LSB addr( Byte mode) Chip Enable Input Output Enable Input Write Enable Reset/Deep Power-down Write Protect Word/ Byte


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PDF MX29L8100T/B 8/512K 120ns 16K-block) 16K-block APR/14/1997 AUG/22/1997 OCT/29/1997 JAN/12/1998 MAY/27/1998
1998 - SA02H

Abstract: 29l8100
Text: addr( Byte mode) CE Chip Enable Input OE Output Enable Input WE Write Enable RP Reset/Deep Power-down WP Write Protect BYTE Word/ Byte Selection Input VCC Power Supply , BYTE GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 , D11 D12 D4 D WP A18 RP BYTE A8 WE A9 D5 9 D7 B A13 A14 A15 Vss 10 , D6 4 3 A 2 1 MX29L8100T/B 1.2-1 MX29L8100T/B SECTOR ARCHITECTURE ( Byte Mode Addr


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PDF MX29L8100T/B 8/512K Bytes/64 120ns SA02H 29l8100
2005 - i2c bootloader

Abstract: AN2273 CY8C29xxx AN2273a Bootloader
Text: Application Note AN2273 I2C Bootloader for PSoCTM, 16- Byte Packet Transfer Author: Ernie , Note describes a bootloader for the PSoCTM device using I2C communication and 16- byte packet transfer , , where it waits for a 10- byte bootloader key from the master. If the previous bootloading failed (such , receiving a valid bootloader key from the master, the bootloader responds with a status byte informing , in 16- byte packets with some encoding bytes (explained in a later section). o The bootloader


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PDF AN2273 16-Byte CY8C21xxx, CY8C24xxxA, CY8C27xxx, CY8C29xxx AN2273a i2c bootloader AN2273 CY8C29xxx AN2273a Bootloader
IDT71586

Abstract: No abstract text available
Text: Integrated Device Technology, Inc. 16 BYTE INSTRUCTION/16K BYTE DATA CACHE MODULE FOR THE , compatible high speed CMOS static RAM modules to support the IDT79R3000 RISC CPU · Organized as a 16K byte instruction and 16K byte data cache · Operating frequencies to support 12MHz, 16.7MHz, 20MHz, and 25MHz , dual-banked 16K byte instruction cache and 16K byte data cache for the IDT79R3000 CPU. The IDT7MB6074 uses 8 , customers requiring a 16K byte instruction cache and a 16K byte data cache. The pent in-line package (PIP


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PDF INSTRUCTION/16K IDT79R3000 IDT7MB6074 12MHz, 20MHz, 25MHz IDT79R3000 IDT7MB6074 IDT71586
2000 - 24U16

Abstract: 24U17 24C166 24c16 6 24c16 device use and how to erase FM24C17UFLM8 24u16m8 24u16l 24U1 CHIP 8-PIN 24c16
Text: transfer protocol I Sixteen byte page write mode ­ Minimizes total write time per byte I Self timed write , ), followed by transmittal (by the MASTER) of byte (s) of information (Address/Data). For every byte of , DEFINITIONS 8 bits ( byte ) of data 16 sequential byte locations starting at a 16- byte address boundary, that , subsequent eight bit byte . In the read mode the FM24C16U/17U slave will transmit eight bits of data, release , with the Word address used to access any individual data byte . The last bit of the slave address


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PDF FM24C16U/17U 16K-Bit FM24C16U/17U FM24C17U 24U16 24U17 24C166 24c16 6 24c16 device use and how to erase FM24C17UFLM8 24u16m8 24u16l 24U1 CHIP 8-PIN 24c16
Not Available

Abstract: No abstract text available
Text: input latch Comm on data inputs and data outputs Dual Byte Enables for BYTE R EA D /W R IT E capability , enables, separate upper and low er byte enables and a fast output enable. The device is ideally suited for "pipelined " systems and systems that benefit from a wide data bus requiring separate byte enables. Address , and WRITE cycles by guaranteeing address hold time in a simple fashion. Dual byte enables (BH E and , falling edge. When ALE is HIGH, the latch is transparent. Byte Enables: These active LOW inputs allow


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PDF MT56LC16K16C3 386SL 52-Pin
AN82527F8

Abstract: AS82527F8 SB82558B TL82543GC S82595FX TA80960KB25 SB82371SB sb82371sbsu093 ku82596sx20sz713 GD82559ERSL3TU
Text: Cache . . . . . . . . . . . . . . . . . . . . 132-PGA 803435-ND 16MHz, i960KA, 32-Bit MPU, 512 Byte Cache . . . . . . . . . . . . . . . . . . . . 132-PGA 803490-ND 25MHz, i960KA, 32-Bit MPU, 512 Byte Cache . . . . . . . . . . . . . . . . . . . . 132-PGA 803496-ND 16MHz, i960KB, 32-Bit MPU, 512 Byte Cache . . . . . . . . . . . . . . . . . . . . 132-PGA 803516-ND 20MHz, i960KB, 32-Bit MPU, 512 Byte Cache . . . . . . . . . . . . . . . . . . . . 132-PGA 803535-ND 25MHz, i960KB, 32-Bit MPU, 512 Byte


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PDF A80960JA3V25 A80960JA3V33 A80960JD3V33 A80960JD3V50 A80960JD3V66 A80960JF3V25 A80960JF3V33 A80960KA16 A80960KA25 A80960KB16 AN82527F8 AS82527F8 SB82558B TL82543GC S82595FX TA80960KB25 SB82371SB sb82371sbsu093 ku82596sx20sz713 GD82559ERSL3TU
IDT79R3000

Abstract: MIPS R3000 idt71586
Text: 31 Integrated Device Technology, Inc. 16 BYTE INSTRUCTION/16K BYTE DATA CACHE MODULE FOR THE , compatible high speed CMOS static RAM modules to support the IDT79R3000 RISC CPU · Organized as a 16K byte instruction and 16K byte data cache · Operating frequencies to support 12MHz, 16.7MHz, 20MHz, and 25MHz , dual-banked 16K byte instruction cache and 16K byte data cache for the IDT79R3000 CPU. The IDT7MB6074 uses 8 , customers requiring a 16K byte instruction cache and a 16K byte data cache. The pent in-line package (PIP


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PDF INSTRUCTION/16K IDT79R3000 IDT7MB6074 12MHz, 20MHz, 25MHz IDT79R3000 IDT7MB6074 MIPS R3000 idt71586
50 pin flat ribbon cable

Abstract: F3870 Guide to Programming f8 family Fairchild F8 F3870 FD360 FD3700 FD3712
Text: debug program, as well as an additional 16K-byte RAM module. Also a part of the Mark II is the , Hardware Formulator Processor Module 16K-Byte RAM Module Formulator Card Cage and Motherboard Processor , Parallel Interface Module PROM Boot Loader Module 16K-Byte RAM Module Quad I/O Port Module Communications , Module 16K-Byte RAM Module Quad I/O Port Module 4K- Byte PROM Module Communications Module Byte Parallel , Unit devices. The Fairbug debug program, a 1K- byte monitor debug package, is included in the Program


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PDF
2005 - AN2273a

Abstract: i2c bootloader CY7C27443-24PVI AN2273 CY8C27xxx
Text: Programming - I2C Bootloader for PSoC, 78- Byte Packet Transfer AN2273a Author: Ernie , communication and 78- byte packet transfer. 4. Modify the flashsecurity.txt file to allow writing to Flash , master, the bootloader responds with a status byte informing the master that it is ready to receive the Flash image. The master sends the updated user code in 64- byte packets with some encoding bytes , entered by addressing the I2C bootloader and sending the correct 10- byte authentication key. If


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PDF 78-Byte AN2273a CY8C21xxx, CY8C24xxxA, CY8C27xxx, CY8C29xxx AN2273 AN2273a i2c bootloader CY7C27443-24PVI AN2273 CY8C27xxx
Not Available

Abstract: No abstract text available
Text: Data Input/Output Q15(word mode)/LSB addr( Byte mode) Chip Enable Input Output Enable Input Write Enable Reset/Deep Power-down Write Protect W ord/ Byte Selection Input Power Supply Pin (2.7V - 3.6V) Ground Pin , 100 milliamps on address and data pin from -1V to VCC +1V. WE RP WP BYTE VCC GND 1.1 PINOUTS 48 , 37 A16 BYTE GND DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQO OE , X2 9 L 8 1 0 0 T / B 1 .2-1 MX29L8100T/B SECTOR ARCHITECTURE ( Byte Mode Addr. A-1 ~ A18) LL LL


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PDF 120ns 16K-block) 16K-block -100mA 100mA 150ns@
Supplyframe Tracking Pixel