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16020-3

Abstract: Wirewound Resistors 640 Ohms 6201R R20J
Text: Type 160-10R0-FBW 160-20R0-FBW 160-1001-FBW 160-5001-FBW 160-1002-FBW 160-R20-JBW 160-R47-JBW 160-2R0- JBW 160-4R7- JBW 160-5R0- JBW 160-5R1- JBW 160-100- JBW 160-101- JBW 160-201- JBW 160-471- JBW 160-501- JBW 160-102- JBW 160-502- JBW 160-103- JBW 160-203- JBW Ohms 10 20 1K 5K 10K 0.2 0.47 2 4.7 5 5.1 10 100 200 470 500 1K 5K 10K , -R50-JBW 135-5R0- JBW 135-100- JBW 135-220- JBW 135-101- JBW 135-151- JBW 135-201- JBW 135-102- JBW Ohms 0.05 0.1 2 10 50 , AUTOMATION & CONTROL 70183877 70183879 70183884 70183885 70183887 175-1000-FBW 175-1002-FBW 175-102- JBW


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PDF 620-R100-FBW 620-R500-FBW 620-1R00-FBW 620-2R00-FBW 620-5R00-FBW 620-10R0-FBW 620-15R0-FBW 620-25R0-FBW 620-50R0-FBW 620-1000-FBW 16020-3 Wirewound Resistors 640 Ohms 6201R R20J
zenor

Abstract: JBW05-3R0 JBW12-0R9 JBW12-1R3 JBW15-0R7 EN55022-B B3P5 AC240V
Text: (1/23) 001-06 / 20040511 / ea122_jbw.fm Power Supplies J Series JBW (10 to 50W) AC Input , IDENTIFICATION JBW (1) EMC REGULATIONS FCC Class-B, VCCI Class-B, EN-55011-B and EN55022-B meet. 05 (2 , -2R1 (2/23) 001-06 / 20040511 / ea122_jbw.fm Power Supplies J Series JBW (10 to 50W) AC Input , Power Supplies J Series JBW (10 to 50W) AC Input Single Output, General-Purpose UL/CSA, EN60950 , ) 001-06 / 20040511 / ea122_jbw.fm Power Supplies J Series JBW (10 to 50W) AC Input Single Output


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PDF EN60950 UL1950, CSA950-95, zenor JBW05-3R0 JBW12-0R9 JBW12-1R3 JBW15-0R7 EN55022-B B3P5 AC240V
JBW10

Abstract: T221-01 JBW12-0R9 JBW05-6R0 JBW05-3R0 H221-04 H221 EN55022-B B3P5 AC240V
Text: (1/23) 001-04 / 20030827 / ea122_jbw.fm Power Supplies J Series JBW (10 to 50W) AC Input , point) JBW (1) 05 (2) ­ 2R0 (3) PART NUMBERS AND RATINGS Output voltage (V) 5 12 , / ea122_jbw.fm Power Supplies J Series JBW (10 to 50W) AC Input Single Output, General-Purpose UL/CSA , J Series JBW (10 to 50W) AC Input Single Output, General-Purpose UL/CSA, EN60950 Recognized , / 20030827 / ea122_jbw.fm Power Supplies J Series JBW (10 to 50W) AC Input Single Output


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PDF EN60950 UL1950, JBW10 T221-01 JBW12-0R9 JBW05-6R0 JBW05-3R0 H221-04 H221 EN55022-B B3P5 AC240V
MAX3872

Abstract: Phase Frequency detector
Text: to the jitter transfer bandwidth ( JBW ) for a given data rate determines the loop-damping coefficient. The typical and maximum values for JBW are given in the MAX3872 datasheet for the standard , achieved by setting fz lower than JBW by a factor of approximately 100, which produces a large damping , considered overdamped when fZ is at least four times smaller than JBW . Under this condition, the jitter , approximations of JP using typical values of JBW . To avoid excessive peaking and loop instability, use a filter


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PDF HFDN-25 MAX3872 155Mbps 67Gbps, 52Mbps Phase Frequency detector
2006 - SIS 650

Abstract: specifications for oc-48 of edfa amplifier G3255 MAX3745 MAX3874 MAX3874AEGJ MAX3874EGJ
Text: Bandwidth Jitter Peaking Threshold adjust disabled, Figure 1 (Note 6) BER 10 JBW JP -10 10 1600 1.5 MAX3874A mVP-P 0.7 f JBW 2.0 0.1 3.1 0.62 0.93 f = 10MHz 0.44 , bandwidth ( JBW ) below 2MHz. The external capacitor (CFIL) connected from FIL to VCC_VCO sets the PLL , overdamped system (fZ / JBW < 0.25), the jitter peaking (JP) of a 2nd-order system can be approximated by: CFIL = 0.01µF H(j2f) (dB) f JP = 20 log1 + Z JBW where JBW is the jitter transfer


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PDF 488Gbps/2 667Gbps 488Gbps 10mVP-P MAX3874 OC-48 OC-48 MAX3745 MAX3874 SIS 650 specifications for oc-48 of edfa amplifier G3255 MAX3874AEGJ MAX3874EGJ
2007 - Not Available

Abstract: No abstract text available
Text: -3 Jitter Peaking JBW JP 80 130 OC-12 370 500 OC-48 Jitter Transfer Bandwidth 1500 2000 3.1 8.0 f = 1MHz Sinusoidal Jitter Tolerance OC-48 f ≤ JBW f = 100kHz , according to: fZ = HO(j2πf) (dB) DATA RATE: 2.488Gbps  f  JP = 20 log1 + Z  JBW   where JBW is the jitter transfer bandwidth for a given data rate. The recommended value of , For an overdamped system (fZ / JBW < 0.25), the jitter peaking (JP) of a 2nd-order system can be


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PDF MAX3872 OC-12, OC-24, OC-48, OC-48 25Gbps/2 MAX3872
2003 - sis 650

Abstract: MAX3745 MAX3861 MAX3874 MAX3874AEGJ MAX3874EGJ
Text: 10 Differential Input Voltage (SLBI±) JBW JP -10 1600 mVP-P 50 800 mVP-P MAX3874 1.5 MAX3874A 0.7 f JBW 2.0 0.1 3.1 0.93 0.44 MHz dB 8.0 0.62 , a jitter transfer bandwidth ( JBW ) below 2MHz. The external capacitor (CFIL) connected from FIL to , an overdamped system (fZ / JBW < 0.25), the jitter peaking (JP) of a 2nd-order system can be approximated by: CFIL = 0.01µF H(j2f) (dB) f JP = 20 log1 + Z JBW where JBW is the jitter


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PDF 488Gbps/2 667Gbps 488Gbps 10mVP-P 65UIP-P 170mV MAX3874 MAX3874 sis 650 MAX3745 MAX3861 MAX3874AEGJ MAX3874EGJ
Ringing Choke Converter

Abstract: 100W UPS tdk dc-dc converter ce RCC Ringing Choke Converter 12 pulse ac-dc converter 1000 va ups ic dk 17 pfe tdk-lambda RCC1000 1000W mosfet
Text: 1960 NASA 1965 1970 TDK 1972 TDK 1974 1976 TDK 1978 1995 TDK HEV DC-DC 2000 TDK RKW JBW 2004 T DK HWS 2005 TDK UPS 2006 2008 TDK-Lambda 13 234 EMC RoHS TDK 150W 550cm 3 , DC-DC 2000 TDK RKW JBW 2004 T DK HWS 2005 TDK


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PDF 550cm 1200cm 1300cm 3800cm 4500cm SGS-COC-004380 Ringing Choke Converter 100W UPS tdk dc-dc converter ce RCC Ringing Choke Converter 12 pulse ac-dc converter 1000 va ups ic dk 17 pfe tdk-lambda RCC1000 1000W mosfet
2005 - MAX3745

Abstract: MAX3872 MAX3872EGJ OC-24
Text: mVP-P OC-3 JBW 80 130 OC-12 370 500 OC-48 Jitter Transfer Bandwidth 1500 , OC-48 3.1 f = 1MHz JP f JBW f = 100kHz f = 10MHz Jitter Peaking 0.42 0.64 , integrated PLL is a classic 2nd-order feedback system, with a jitter transfer bandwidth ( JBW ) below 2.0MHz , an overdamped system (fZ / JBW < 0.25), the jitter peaking (JP) of a 2nd-order system can be approximated by: f JP = 20 log1 + Z JBW where JBW is the jitter transfer bandwidth for a given data


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PDF MAX3872 OC-12, OC-24, OC-48, OC-48 25Gbps/2 T2855-6. MAX3745 MAX3872EGJ OC-24
2003 - G3255

Abstract: sis 650 MAX3745 MAX3861 MAX3874 MAX3874AEGJ MAX3874EGJ
Text: 10 Differential Input Voltage (SLBI±) JBW JP -10 1600 mVP-P 50 800 mVP-P MAX3874 1.5 MAX3874A 0.75 f JBW 2.0 0.1 3.1 0.93 0.44 MHz dB 8.0 0.62 , integrated PLL is a classic second-order feedback system, with a jitter transfer bandwidth ( JBW ) below 2MHz , CFIL = 0.01µF H(j2f) (dB) For an overdamped system (fZ / JBW < 0.25), the jitter peaking (JP) of a second-order system can be approximated by: f JP = 20 log1 + Z JBW where JBW is the


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PDF 488Gbps/2 667Gbps 488Gbps 10mVP-P 65UIP-P 170mV MAX3874 MAX3874 G3255 sis 650 MAX3745 MAX3861 MAX3874AEGJ MAX3874EGJ
2003 - sis 650

Abstract: MAX3745 MAX3861 MAX3874 MAX3874AEGJ MAX3874EGJ
Text: adjust disabled, Figure 1 (Note 6) BER 10 JBW JP -10 1600 mVP-P 50 800 mVP-P MAX3874 1.5 MAX3874A 0.7 f JBW 2.0 0.1 3.1 0.93 0.44 MHz dB 8.0 0.62 , a jitter transfer bandwidth ( JBW ) below 2MHz. The external capacitor (CFIL) connected from FIL to , an overdamped system (fZ / JBW < 0.25), the jitter peaking (JP) of a 2nd-order system can be approximated by: CFIL = 0.01µF H(j2f) (dB) f JP = 20 log1 + Z JBW where JBW is the jitter


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PDF 488Gbps/2 667Gbps 488Gbps 10mVP-P 65UIP-P 170mV MAX3874 MAX3874 sis 650 MAX3745 MAX3861 MAX3874AEGJ MAX3874EGJ
2003 - specifications for oc-48 of edfa amplifier

Abstract: sis 650 MAX3745 MAX3861 MAX3872 MAX3872EGJ OC-24
Text: OC-3 Jitter Peaking JBW JP Sinusoidal Jitter Tolerance OC-48 130 OC-12 370 500 OC-48 Jitter Transfer Bandwidth 80 1500 2000 f JBW f = 100kHz 3.1 8.0 0.1 , integrated PLL is a classic 2nd-order feedback system, with a jitter transfer bandwidth ( JBW ) below 2.0MHz , an overdamped system (fZ / JBW < 0.25), the jitter peaking (JP) of a 2nd-order system can be approximated by: f JP = 20 log1 + Z JBW where JBW is the jitter transfer bandwidth for a given data


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PDF MAX3872 OC-12, OC-24, OC-48, OC-48 25Gbps/2 MAX3872 specifications for oc-48 of edfa amplifier sis 650 MAX3745 MAX3861 MAX3872EGJ OC-24
2005 - CAZ MARKING

Abstract: sis 315 MAX3745 MAX3874 MAX3874AEGJ MAX3874EGJ T2055-4
Text: 10 Differential Input Voltage (SLBI±) JBW JP -10 1600 mVP-P 50 800 mVP-P MAX3874 1.5 MAX3874A 0.7 f JBW 2.0 0.1 3.1 0.93 f = 10MHz 0.44 MHz dB , bandwidth ( JBW ) below 2MHz. The external capacitor (CFIL) connected from FIL to VCC_VCO sets the PLL , overdamped system (fZ / JBW < 0.25), the jitter peaking (JP) of a 2nd-order system can be approximated by: CFIL = 0.01µF H(j2f) (dB) f JP = 20 log1 + Z JBW where JBW is the jitter transfer


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PDF 488Gbps/2 667Gbps 488Gbps MAX3874 OC-48 OC-48 T2855-6. CAZ MARKING sis 315 MAX3745 MAX3874AEGJ MAX3874EGJ T2055-4
2003 - sis 650

Abstract: MAX3745 MAX3861 MAX3872 MAX3872EGJ OC-24
Text: -3 JBW 80 OC-12 370 500 OC-48 Jitter Transfer Bandwidth 1500 2000 0.44 0.65 , -48 3.1 f = 1MHz JP f JBW f = 100kHz f = 10MHz Jitter Peaking 130 dB UIP-P UIP-P , integrated PLL is a classic 2nd-order feedback system, with a jitter transfer bandwidth ( JBW ) below 2.0MHz , an overdamped system (fZ / JBW < 0.25), the jitter peaking (JP) of a 2nd-order system can be approximated by: f JP = 20 log1 + Z JBW where JBW is the jitter transfer bandwidth for a given data


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PDF MAX3872 OC-12, OC-24, OC-48, OC-48 25Gbps/2 MAX3872 sis 650 MAX3745 MAX3861 MAX3872EGJ OC-24
2007 - edfa amplifier for OC-48 specifications

Abstract: sis 650 MAX3745 MAX3872 MAX3872EGJ OC-24
Text: 10-10 Differential Input Voltage (SLBI±) 50 800 mVP-P OC-3 JBW 80 130 OC , OC-12 8.0 f = 25kHz Sinusoidal Jitter Tolerance OC-48 3.1 f = 1MHz JP f JBW f , 1 fZ = HO(j2f) (dB) DATA RATE: 2.488Gbps f JP = 20 log1 + Z JBW where JBW is the , 0.01F fZ = 24.5kHz CFIL = 0.82F fZ = 299Hz 1 2(650)CFIL For an overdamped system (fZ / JBW , transfer bandwidth ( JBW ) below 2.0MHz. The external capacitor (CFIL) connected from FIL to VCC_VCO sets


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PDF MAX3872 OC-12, OC-24, OC-48, OC-48 25Gbps/2 MAX3872 edfa amplifier for OC-48 specifications sis 650 MAX3745 MAX3872EGJ OC-24
2006 - Not Available

Abstract: No abstract text available
Text: Swing Clock-to-Q Delay tCLK-Q JGEN -20log | S11 | tr, tf JBW JP VID SYMBOL CONDITIONS MAX3874 (RATESET = , UIP-P MAX3874 MAX3874A f JBW f = 100kHz f = 1MHz f = 10MHz f = 1MHz (Note 7) f = 10MHz (Note 7) f = , -order feedback system, with a jitter transfer bandwidth ( JBW ) below 2MHz. The external capacitor (CFIL) connected , Figure 6. Open-Loop Transfer Function For an overdamped system (fZ / JBW < 0.25), the jitter peaking , JP = 20 log1 + Z J BW where JBW is the jitter transfer bandwidth for a given data rate. The


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PDF 488Gbps/2 667Gbps 488Gbps 10mVP-P 65UIP-P 170mV 32-Pin MAX3874 T3255
2002 - AN42

Abstract: Si5310 Si5311 Si5311-BM PLL 2400 MHZ
Text: Clock Input (MHz) = 150.000 to 167.000 JBW 0.37 Clock Input (MHz) = 300.000 to 334.000 , :0] = 01, MULTOUT = 1200 to 1336 MHz)* JBW Clock Input (MHz) = 300.000 to 334.000 - , Transfer Bandwidth (MULTSEL[1:0] = 10, MULTOUT = 600 to 668 MHz)* JBW Clock Input (MHz) = 37.500 , 150 to 167 MHz)* JBW Jitter Transfer Peaking (MULTSEL[1:0] = 00, MULTOUT = 2400 to 2672 MHz , values: Jitter Transfer Bandwidth MULTSEL=00 ( JBW all Typ/Max) Updated values: Jitter Transfer


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PDF
2002 - Not Available

Abstract: No abstract text available
Text: Jitter Peaking Jitter Transfer Bandwidth tCLK-Q JP JBW SYMBOL RATESET = low RATESET = high Figure 2 (Note , loop bandwidth ( JBW ) below 2.0MHz. The external capacitor, CF, can be adjusted to set the loop damping , approximated by: fz JP = 20 log 1 + JBW HO(j2f) (dB) H(j2f) (dB) CF = 2000pF 0 CLOSED-LOOP


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PDF MAX3873A 488Gbps/ 67Gbps MAX3873A
9S20

Abstract: Z1w 56
Text: THIS DRAV1W )S UNPUfllJSHEfl. | LEASED fQft HIBU CAT! O H · AM P jnwwHAi RSI/1 SIOWS J KEACT -2 4 £ REV PER EC 0730-00 65-96 8- jb-w 1. MATERIAL: CONNECTOR- NYLON U L 9 4 V - 2 ( WHI TE ). C ONTACT S- 0 . 3 0 r . 0 7 2J7 THK COPPE R A L L O Y CBRJGHT T J N 0 . 0 0 2 0 3 [ , 0 0 0 0 8 0 2 M I N TK K) . C O N T A C T S ACCEPT # 2 4 AWG S O L )D, FU SED STRANDED Oft STRANDED C? STRANDS) WIRE W J T H 2 . 4 7 T . O S S J MAX INSULATfON DIA. B O W, J N A N Y D i RECT J ON, NOT TO


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PDF iO-22-31 9S20 Z1w 56
2004 - Not Available

Abstract: No abstract text available
Text: 1. When ordering, please specify tolerance and packaging codes: 0402PA-8N2X JBW Tolerance: G = 2% J


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PDF 0402PA 0402CS
2011 - KE 9AA

Abstract: K9BD acgf
Text: ) > J"bW # ) ;J5) >J $ ; Y ) ;J 1 ) >J 1 ( Y V ) ;J 1 ) >J 1 ( Y V " 4F 8 E BGD 68 , @ 5> 2?5<91 B<9@ .42 ) > J"bW #5U"( Y ) >J5) ;J $ ; Y % # ! % ) # ! )' )%


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PDF
2001 - Not Available

Abstract: No abstract text available
Text: Jitter Peaking Jitter Transfer Bandwidth tCLK-Q JP JBW SYMBOL RATESET = Low RATESET = High Figure 2 (Note , loop bandwidth ( JBW ) below 2.0MHz. The external capacitor, CF, can be adjusted to set the loop damping , approximated by: fz JP = 20 log 1 + JBW HO(j2f) (dB) H(j2f) (dB) CF = 2000pF 0 CLOSED-LOOP


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PDF MAX3873 488Gbps/ 67Gbps MAX3873
1999 - Internal diagram of ic 7495

Abstract: lg1600axd LG1600FXH LG1600FXH0553 LG1600FXH0622 LG1600FXH2488 LG1605DXB TF1004A wolaver
Text: - s H ( s ) = -1 s + b 1 + - s JBW b = KdRxKo , 10 °C 25 °C 2.4 25 °C JBW (MHz) JBW (MHz) 0.8 0.6 70 °C 70 °C 1.8 0.4 , Bandwidth JGEN JBW Output Reference Voltage Jitter Tolerance VREF JTOL Acquisition/Recovery


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PDF LG1600FXH OC-12 OC-96/STM-4 STM-32 DS99-186HSPL DS96-237FCE) Internal diagram of ic 7495 lg1600axd LG1600FXH0553 LG1600FXH0622 LG1600FXH2488 LG1605DXB TF1004A wolaver
2001 - Not Available

Abstract: No abstract text available
Text: Jitter Peaking Jitter Transfer Bandwidth tCLK-Q JP JBW SYMBOL RATESET = Low RATESET = High Figure 2 (Note , loop bandwidth ( JBW ) below 2.0MHz. The external capacitor, CF, can be adjusted to set the loop damping , approximated by: fz JP = 20 log 1 + JBW HO(j2f) (dB) H(j2f) (dB) CF = 2000pF 0 CLOSED-LOOP


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PDF MAX3873 488Gbps/ 67Gbps MAX3873
2007 - FASTRACK

Abstract: 20-PIN MAX3873A MAX3873AEGP
Text: Jitter Transfer Bandwidth MIN TYP JBW MAX 2.488 RATESET = high Serial Input Data , feedback system, with a loop bandwidth ( JBW ) below 2.0MHz. The external capacitor, CF, can be adjusted to , second-order system can be approximated by: fz JP = 20 log 1 + JBW For example, using CF = 2000pF


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PDF MAX3873A 488Gbps/ 67Gbps MAX3873A FASTRACK 20-PIN MAX3873AEGP
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