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Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
TMPM3HMFZAFG TMPM3HMFZAFG ECAD Model Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003
TMPM3HPFYAFG TMPM3HPFYAFG ECAD Model Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP128-1414-0.40-001
TMPM3HMFDAFG TMPM3HMFDAFG ECAD Model Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP80-1212-0.50-003
TMPM3HPFDAFG TMPM3HPFDAFG ECAD Model Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP128-1414-0.40-001
TMPM3HNFYAFG TMPM3HNFYAFG ECAD Model Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP100-1414-0.50-002
TMPM3HQFYAFG TMPM3HQFYAFG ECAD Model Toshiba Electronic Devices & Storage Corporation Arm Cortex-M3 Core Based Microcontroller/32bit/P-LQFP144-2020-0.50-002

16/32-Bit Datasheets Context Search

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2003 - crystal Oscillator circuit diagram with 4047 IC

Abstract: K00-K05 S1C88649 TC180 Cordless Phone system block diagram ic 4047 Q21CA301 CI 40478 ic CD 4047
Text: S1C88649 8- bit Single Chip Microcomputer e ltag Vo ion Lowerat ts Op oduc Pr Original , The S1C88649 is an 8- bit microcomputer for portable equipment with an LCD display that has a built-in , possible to display kanji characters without any external kanji font ROM. This 8- bit CPU has up to 16MB , . FEATURES Core CPU . S1C88 (MODEL3) CMOS 8- bit core CPU , general output port WR signal: 1 bit when not used as a bus) RD signal: 1 bit Input port


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PDF S1C88649 S1C88649 16-dot 12-dot crystal Oscillator circuit diagram with 4047 IC K00-K05 TC180 Cordless Phone system block diagram ic 4047 Q21CA301 CI 40478 ic CD 4047
2013 - BGA256

Abstract: No abstract text available
Text: NXP 204-MHz, 32- bit Cortex-M4/ Cortex-M0 MCU LPC4300 series Cortex-M4 MCUs with Cortex-M0 , `` 204 MHz, 32- bit ARM Cortex-M4 with FPU `` 204 MHz, 32- bit ARM Cortex-M0 coprocessor `` Up to 1 , FEATURES `` 8-channel GPDMA controller ``  wo 8-channel, 400 Ksps 10- bit ADCs and one 10- bit DAC, T the optional 12- bit 80Msps ADC `` Motor Control PWM and Quadrature Encoder Interface `` Four UARTs , includes two 8-channel, 10- bit ADCs running at 400 Ksps or a 6-channel, 12- bit ADC running at 80 Msps, and


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PDF 204-MHz, 32-bit LPC4300 32-bit 10/100T LPC4370 BGA256
2011 - Not Available

Abstract: No abstract text available
Text: NXP 204 MHz, 32- bit Cortex-M4 /Cortex-M0 DSC LPC4300 series First asymmetrical, dual-core , development environment. Key features  204 MHz, 32- bit ARM Cortex-M4  204 MHz, 32- bit ARM Cortex-M0 , Serial GPIO  Two CAN 2.0B  AES Decryption with 128- bit secure OTP key storage  Up to 164 GPIO , ½ Two 8-channel, 400 Ksps 10- bit ADCs and one 10- bit DAC  Motor Control PWM and Quadrature Encoder , checksum calculation, a high-resolution color LCD controller, and AES decryption, including two 128- bit


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PDF 32-bit LPC4300 32-bit 10/100T LQFP208, BGA256, BGA180
2010 - BGA180

Abstract: No abstract text available
Text: NXP 150 MHz, 32- bit Cortex-M4 /Cortex-M0 DSC LPC4300 series First asymmetrical, dual-core , development environment. Key features `` 150 MHz, 32- bit ARM Cortex-M4 `` 150 MHz, 32- bit ARM Cortex-M0 , 146 GPIO Additional features `` 8-channel GPDMA controller ``  wo 8-channel, 10- bit ADCs and one 10- bit DAC ` T (400 K samples per second) `` Motor Control PWM and Quadrature Encoder Interface , calculation, a high-resolution color LCD controller, and AES decryption, including two 128- bit secure OTP


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PDF 32-bit LPC4300 32-bit LQFP208, BGA256, BGA180 BGA180
2010 - BGA256

Abstract: lpc1800 TBGA100 LQFP144 LPC1810 LPC1833 LPC1837 LPC1850 LQFP208 LPC1817
Text: NXP 150 MHz, 32- bit Cortex-M3TM microcontrollers LPC1800 Fastest Cortex-M3 MCU, Largest SRAM , . Key features 4 50 MHz, 32- bit ARM Cortex-M3 1 4 p to 1 MB Flash U 4 p to 200 KB SRAM U 4 , 4 p to 80 GPIO U Additional features 4 -channel GPDMA controller 8 4 wo 8-channel 10- bit ADCs and 10- bit DAC T (400 K samples per second) 4 otor Control PWM and Quadrature Encoder , AES decryption including two 128- bit secure OTP memories for key storage. Versions with AES


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PDF 32-bit LPC1800 LPC1800 32-bit 10-bit LQFP208, BGA256, BGA180 BGA256 TBGA100 LQFP144 LPC1810 LPC1833 LPC1837 LPC1850 LQFP208 LPC1817
2011 - Not Available

Abstract: No abstract text available
Text: NXP 180 MHz, 32- bit Cortex-M4 /Cortex-M0 DSC LPC4300 series First asymmetrical, dual-core , development environment. Key features `` 180 MHz, 32- bit ARM Cortex-M4 `` 180 MHz, 32- bit ARM Cortex-M0 , Serial GPIO `` Two CAN 2.0B `` AES Decryption with 128- bit secure OTP key storage `` Up to 164 GPIO , 8-channel, 400 Ksps 10- bit ADCs and one 10- bit DAC `` Motor Control PWM and Quadrature Encoder , 128- bit secure OTP memories for key storage. Versions with AES encryption are available on request


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PDF 32-bit LPC4300 32-bit 10/100T LQFP208, BGA256, BGA180
2013 - L9D3256M32DBG2

Abstract: No abstract text available
Text: No file text available


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PDF L9D3256M32DBG2 L9D3512M32DBG2 256-512M DDR3-1866 L9D3256M32DBG2x125 DDR3-1600 L9D3256M32DBG2x15 DDR3-1333 L9D3512M32DBG2x125 L9D3256M32DBG2
2013 - LQFP144

Abstract: No abstract text available
Text: , NXP’s LPC family provides developers a scalable continuum of 32- bit ARM based microcontrollers with both software and hardware reusability and portability. NXP’s microcontrollers include the latest 32- bit , products, based on 32- bit ARM cores, are the most cost effective series compared to 8/16- bit solutions and , interface 1.8 - 3.6 I/O pins 30 SD/MMC 6 LCD controller 1 Comparator 1 DAC (10- bit , and 3.3V VDD for HVQFN33 package Available dual 1.8V and 3.3V VDD for HVQFN33 package DAC (10- bit


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PDF 32-bit LQFP144
2003 - S1C88649

Abstract: MF1565-01a S1C88348
Text: MF1565-01a CMOS 8- BIT SINGLE CHIP MICROCOMPUTER S1C88649 Technical Manual S1C88649 , an 8- bit microcomputer for portable equipment with an LCD display that has a built-in LCD , FONT"). This 8- bit CPU has up to 16MB accessible address space allowing easy implementation of a , of the S1C88649. Table 1.1.1 Main features Core CPU S1C88 (MODEL3) CMOS 8- bit core CPU Main , as a bus) CE signal: 4 bits WR signal: 1 bit (also usable as a general output port when not used


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PDF MF1565-01a S1C88649 S1C88649 otherwis-91976 E-08190 MF1565-01a S1C88348
2003 - PTM33

Abstract: S5U1C88000R1 FK05
Text: MF1565-01a CMOS 8- BIT SINGLE CHIP MICROCOMPUTER S1C88649 Technical Manual S1C88649 , an 8- bit microcomputer for portable equipment with an LCD display that has a built-in LCD controller , characters without any external kanji font ROM (Refer to Appendix B, "USING KANJI FONT"). This 8- bit CPU has , features Core CPU S1C88 (MODEL3) CMOS 8- bit core CPU Main (OSC3) oscillation circuit Crystal oscillation , bits WR signal: 1 bit (also usable as a general output port when not used as a bus) RD signal: 1 bit 8


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PDF MF1565-01a S1C88649 S1C88649 E-08190 PTM33 S5U1C88000R1 FK05
2003 - PX105

Abstract: PW401
Text: (unswitched) in order to achieve minimum standby current. 6. DPD is enabled when configuration register bit CR , bit in the CR has been set HIGH (CR[4] = 1). PAR can be initiated by bring the ZZ# pin to the LOW , Figure 7.) Driving the ZZ# pin LOW will place the device in the PAR mode if the SLEEP bit in the CR has , . The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4] = 0). DPD is , sleep mode bit determines which low-power mode is to be entered when ZZ# is driven LOW. If CR[4] = 1


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PDF 32Mb--standard) 32Mb--low-power MT45W2MW16PAFA MT45W2ML16PAFA MT45W1MW16PAFA 09005aef80d481d3 PX105 PW401
BCY-W2/D3.1

Abstract: 4M XTAL Crystal Oscillator BCY-W2/D3.1 7805 internal circuit diagram XTAL,Crystals,Oscillators Regulated Power Supply design using 7805 ht1632 7805 internal circuit diagram of LED matrix display HT48R10A-1 bcy-w2
Text: TEMP_ADDR = TEMP_ADDR-4. When writing to the HT1632, writing an HT1632 address requires a 14- bit data transmission. These 14-bits are composed of: 101 (3- bit write instruction), A6A5A4A3A2A1A0 (7- bit address) and D0D1D2D3 (4- bit data). The address is transmitted in a highest bits first format while the data


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PDF HT1632 HT1632 HA0136E outbits/16 470uF BCY-W2/D3.1 4M XTAL Crystal Oscillator BCY-W2/D3.1 7805 internal circuit diagram XTAL,Crystals,Oscillators Regulated Power Supply design using 7805 7805 internal circuit diagram of LED matrix display HT48R10A-1 bcy-w2
Not Available

Abstract: No abstract text available
Text: No file text available


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PDF L9D3256M32DBG2 L9D3512M32DBG2 256-512M 3057X /202897X1-203X 304oo. 493dcnnu 3022oo LDS-L9D3xxxM32DBG2
ES9016K2M

Abstract: No abstract text available
Text: CONFIDENTIAL ADVANCE INFORMATION ES9016K2M Ultra 32- bit Stereo Mobile Audio DAC Product Brief Analog Reinvented The ES9016K2M SABRE32 Ultra DAC is a high-performance 32- bit , 2-channel audio D/A , workstations. Using the critically acclaimed ESS patented 32- bit Hyperstream DAC architecture and Time , SABRE32 Ultra DAC’s 32- bit Hyperstream architecture can handle up to 32- bit PCM data via I2S, 384kHz , mode (<1mW in standby mode). FEATURE DESCRIPTION Patented 32- bit Hyperstream DAC o 122dB


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PDF ES9016K2M 32-bit ES9016K2M SABRE32 32-bit, 122dB -110dB,
Not Available

Abstract: No abstract text available
Text: CONFIDENTIAL ADVANCE INFORMATION Reference DACC 32- bit Hyperstream™ Audio DAC Product Brief Analog Reinvented 32 The SABRE Reference audio DAC series is the world’s highest performance 32- bit , audio workstations. I2S/DSD Input Yes SPDIF Input Yes Jitter Reduction -120 32- bit DAC , 64-LQFP 135 (mono) 133 (stereo) 129 (8ch) 133 Yes 32 With ESS patented 32- bit , satisfy the most demanding audio enthusiasts. 32 The SABRE Reference audio DAC’s 32- bit


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PDF 32-bit 32-bit ES9018 SABRE32 64-LQFP ES9012 ES9018
2010 - ES9018

Abstract: sabre es9018 ES9012 SPDIF i2s RECEIVER ES901 SABRE32 ESS sabre dac dsd i2s RECEIVER SABRE spdif receiver
Text: CONFIDENTIAL ADVANCE INFORMATION Reference DACC 32- bit HyperstreamTM Audio DAC Product Brief , performance 32- bit audio DAC solution targeted for consumer applications such as Blu-ray player, audio , (stereo) 129 (8ch) 133 THD (dB) -120 32- bit DAC Yes I2S/DSD Input Yes -120 Yes Yes SPDIF Jitter Input Reduction Yes Yes Yes Yes With ESS patented 32- bit Hyperstream , satisfy the most demanding audio enthusiasts. 32 The SABRE Reference audio DAC's 32- bit Hyperstream


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PDF 32-bit ES9018 SABRE32 64-LQFP ES9012 32-bit ES9018 sabre es9018 SPDIF i2s RECEIVER ES901 ESS sabre dac dsd i2s RECEIVER SABRE spdif receiver
2004 - PW400

Abstract: PX404 PW105 PW401
Text: (unswitched) in order to achieve minimum standby current. 6. DPD is enabled when configuration register bit , bit in the CR has been set HIGH (CR[4] = 1). PAR can be initiated by bring the ZZ# pin to the LOW , # pin LOW will place the device in the PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = , operation. The device can only enter DPD if the SLEEP bit in the CR has been set LOW (CR[4] = 0). DPD is , The sleep mode bit determines which low-power mode is to be entered when ZZ# is driven LOW. If CR[4


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PDF MT45W2MW16PAFA MT45W2ML16PAFA MT45W1MW16PAFA MT45W1ML16PAFA 48-Ball 32Mb--standard) 32Mb--low-power 09005aef80d481d3 PW400 PX404 PW105 PW401
ES9018

Abstract: No abstract text available
Text: 123456789A2B92C9D7 32 The SABRE Reference audio DAC series is the world’s highest performance 32- bit audio DAC , workstations. I2S/DSD Input Yes SPDIF Input Yes Jitter Reduction -120 32- bit DAC Yes -120 , (mono) 133 (stereo) 129 (8ch) 133 Yes 32 With ESS patented 32- bit Hyperstream1 DAC , most demanding audio enthusiasts. 32 The SABRE Reference audio DAC’s 32- bit Hyperstream1 architecture can handle full 32- bit PCM data via I2S input, 32 1 as well as DSD or SPDIF data. The SABRE


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PDF AC712345675489A71 123456789A2B92C9D7 32-bit 32-bit ES9018 SABRE32 64-LQFP ES9012
nexus 5 plc program terminal

Abstract: PLC programming elap PLC programming 240x128 ELAP NEXUS serial port rs232
Text: , frequency 500 KHz · AXIS COMMAND: 2 to 4 ±10Vdc analogue outputs with 12 bit resolution (15 bit , bit resolution · ALARMS: 1 contact for system watch-dog · COMUNICATION: 2 serial ports , · CPU 32 bit RISC · Flash Memory 256Kbyte, 32 Kbyte reserved for the PLC program · RAM Memory for


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PDF 240x128 nexus 5 plc program terminal PLC programming elap PLC programming ELAP NEXUS serial port rs232
ES9018K2M

Abstract: ES9018 ES901
Text: CONFIDENTIAL ADVANCE INFORMATION ES9018K2M 32- bit Stereo Mobile Audio DAC Product Brief Analog Reinvented The ES9018K2M SABRE32 Reference DAC is a high-performance 32- bit , 2-channel audio D , workstations. Using the critically acclaimed ESS patented 32- bit Hyperstream DAC architecture and Time , SABRE32 Reference DAC’s 32- bit Hyperstream architecture can handle up to 32- bit PCM data via I2S , FEATURE DESCRIPTION Patented 32- bit Hyperstream DAC o 127dB DNR o -120dB THD+N o Patented


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PDF ES9018K2M 32-bit ES9018K2M SABRE32 32-bit, 127dB 120dB, ES9018 ES901
HT1632C

Abstract: HT48R30A-1 ht1632 LM7805 LM7805 5V INI16 HA0127T HT48R30A
Text: HT1632C MCU Memory 8bit LED RAM 4bit 8bit 4bit RAM HT1632C 8 bit RAM 144*8 LED


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PDF HT1632C HA0127T HT1632C HT48R30A-1 ht1632 LM7805 LM7805 5V INI16 HA0127T HT48R30A
1991 - WS60-367-1

Abstract: U10661J U10691JJ3V0DS00 U10082J IEEE754 PD70732 uPD70732GC uPD70732GD uPD70732R V810
Text: r15 r16 r17 0 r18 r19 r20 0 r21 r22 r23 r24 r25 r26 String Source Bit Offset , 31 PC 12 String Destination Bit Offset r27 Program Counter 0 0 µPD70732 . , Significant Bit A 7 0 A HALFWORD 16 15LSBLeast Significant BitMSBMost Significant Bit15AA, A1 , V8101632 8 bit -128127 16 bit -3276832767 32 bit -21474836482147483647 . 1632 8 bit 0255 16 bit 065535 32 bit 04294967295 . 232-1 A B31


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PDF PD70732 V810TM PD70732 V810NECV810TM V810RISC V805TM, U10661J U10082J IEEE754 108-0171NEC WS60-367-1 U10661J U10691JJ3V0DS00 U10082J IEEE754 uPD70732GC uPD70732GD uPD70732R V810
2004 - Not Available

Abstract: No abstract text available
Text: enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled. 09005aef80d481d3 , only enters PAR mode if the SLEEP bit in the CR has been set HIGH (CR[4] = 1). PAR can be initiated by , bit in the CR has been set HIGH (CR[4] = 1). The device should not be put into DPD using CR , bit in the CR has been set LOW (CR[4] = 0). DPD is initiated by bringing the ZZ# pin to the LOW , Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled The sleep mode bit determines which low-power


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PDF MT45W2MW16PAFA MT45W2ML16PAFA MT45W1MW16PAFA MT45W1ML16PAFA 48-Ball 09005aef80d481d3
ES9010K2M

Abstract: es901
Text: Analog Reinvented The ES9010K2M SABRE Premier DAC is a high-performance 32- bit , 2-channel audio D/A , €™s Hyperstream architecture can handle up to 32- bit PCM data via I2S, 384kHz input sampling rates , FEATURE DESCRIPTION Patented 32- bit Hyperstream DAC o 116B DNR o -106dB THD+N o Patented Time Domain Jitter Eliminator Integrated DSP Functions o o o o o o o o 32- bit audio DAC , (I2S, LJ 16-32- bit ) or DSD input Customizable output configuration I2C control 28-QFN (5mm x 5mm


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PDF ES9010K2M ES9010K2M 32-bit, 116dB -106dB, es901
U850

Abstract: V821 V810TM PD70732 uPD70741 uPD70741GC V810 CAXI tm016 U11678JJ4V0DSJ1
Text: /O24 224-1 LSBLeast Significant BitMSBMost Significant Bit LSB MSB V821 I/O , 0 r18 r19 r20 0 r21 r22 r23 0 r24 r25 r26 String Destination Bit Offset r27 String Source Bit Offset r28 String Length r29 String Destination r30 String , LSBLeast Significant BitMSBMost Significant Bit A 7 0 A HALFWORD 16 15LSBLeast Significant , A 23 µPD70741 V8211632 8 bit -128127 16 bit -3276832767 32


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PDF PD70741 V821TM PD70741V82132PD70732 V810TMDRAM/ROMDMA V821U10077J V810TMU10082J 32V810CPU U11678JJ4V0DSJ1 PD70741GC-25-8EU U850 V821 V810TM PD70732 uPD70741 uPD70741GC V810 CAXI tm016 U11678JJ4V0DSJ1
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