The Datasheet Archive

Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
111560-HMC441LH5 111560-HMC441LH5 ECAD Model Analog Devices 111560-HMC441LH5
0011150188 0011150188 ECAD Model Molex SNAP RING 5555-18
0511151601 0511151601 ECAD Model Molex 4.0MM WTW CONNECTOR
0732511150 0732511150 ECAD Model Molex RF SMA Connector, 1 Contact(s), Board Mount, Surface Mount Terminal, Locking,
0761551115 0761551115 ECAD Model Molex IMPACT BP 4X10 LW SN
0395111503 0395111503 ECAD Model Molex TERM BLOCK HDR 3POS VERT 3.81MM

1115 sire lad Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
Not Available

Abstract: No abstract text available
Text: ) .0 9 6 * .005 (2.44*0.13) DM. Sire 9-51 JACKPOST (9-51) 12-56 UNC2BTW. .1 2 0 * 005 (3.05 , ) .355 (9.02) .555 (14.10) 1.800 (45.72) 1.115 (28.32) 1.335 (33.91) .884 (22.45) .185 , ) 1.115 (28.32) 1.335 (33.91) .952 (24.18) .253 (6.43) .308 (7.82) .16514.19) .355 (9.02 , ) .455 (11.56) .308 (7.82) MDM-31PBR* 2.040 (51.82) 1.800 (45.72) 1.115 (28.32) .884 , ) 1.115 (28.32) .952 (24.18) .253 (6.43) .455 (11.56) .308 (7.82) MDM-37PBR* 2.340


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LC1-D09

Abstract: schneider LC1-D09 LC1-D40 LC1 d12008 contactor LC1 D25004 LC1 D25008 LC1-D25 LC1-D65004 LC1-D80 LC1-D80004
Text: 95.5 111.5 (1) 120.5 (1) 127.5 (1) 84 86 117 129 137 141 DT20 & DT25 85 98 114 129 , - D115 D150 120 174 185 188 188 132 136 150 155 168 172 12,5 ( LAD -8) c1 c2 c3 D40008 D80 D65004 85 135 135 142 150 125 130 150 158 170 178 182 44 a 12,5 ( LAD , 98 100 131 143 151 155 LA4 c 12 12,5 ( LAD -8) D40.D65 a b1 with LA4-DA2 , 12,5 ( LAD -8) c 45 DT203 & DT253 99 ­ ­ ­ ­ 90 92 123 135 143 147 LC1-D80 and


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PDF LC1-D09. LC1-D25. LC1-DT20. LC2-DT20. 21/NC 13/NO LC1-D09 schneider LC1-D09 LC1-D40 LC1 d12008 contactor LC1 D25004 LC1 D25008 LC1-D25 LC1-D65004 LC1-D80 LC1-D80004
lad6k10

Abstract: LC1 D25004 LC1 d12008 contactor LC1 D25008 LC1-D65004 LC1D65004 LP1D12004 schneider electric LC1 D25 LC1 d40008 LC1 D093
Text: 117 129 137 141 D099. D189 80 95.5 111.5 (1) 120.5 (1) 127.5 (1) 84 86 117 129 137 , 172 12,5 ( LAD -8) c1 c2 c3 D40008 D80 D65004 85 135 135 142 150 125 130 150 158 170 178 182 44 a 12,5 ( LAD -8) D80004 D80008 96 135 ­ 142 150 125 ­ , 12,5 ( LAD -8) D40.D65 LAD -8 LA4 D115004 D115006 D150006 D1150046 150 174 185 188 , . DT60 91 ­ ­ ­ ­ 98 100 131 143 151 155 b1 b1 12,5 ( LAD -8) c 45 DT203 &


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PDF LC1-D09. LC1-D25. LC1-DT20. LC2-DT20. 21/NC 13/NO lad6k10 LC1 D25004 LC1 d12008 contactor LC1 D25008 LC1-D65004 LC1D65004 LP1D12004 schneider electric LC1 D25 LC1 d40008 LC1 D093
2002 - plx 9030

Abstract: plx 9030 176-pin pqfp PCI9030 93cs66l marking ld25 plx 9052 93CS56L PPC401 TMS320C6202 9030-AA60BI
Text: 2-3 2.2.3.2.1.2. LAD [31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.6. Debug Interface . . . . . . . . , . . . . . . 11-15 11-13 JTAG Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


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PDF 9030-ms Index-11 plx 9030 plx 9030 176-pin pqfp PCI9030 93cs66l marking ld25 plx 9052 93CS56L PPC401 TMS320C6202 9030-AA60BI
Not Available

Abstract: No abstract text available
Text: INTEGRATED FLOATING POINT UNIT CONTENTS page 1.0 THE i960® PROCESSOR . 1-115 CONTENTS , Environment I 462bl75 01 b b 4 7 7 2^4 m 1-115 80960KB 1.1 Key Performance Features The , . DT/R never changes state when DEN is asserted. READY indicates that data on LAD lines can be , clock (CLK) to 1.5V on the falling edge and 1.5V on the rising edge of the L-Bus address/data ( LAD , LA D , 9 1 2 3 0 0 < LAD2 5 BADAC 0 0 H O LD v ss lad LA D , 3


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PDF 80960KB 32-BIT 512-Byte 132-Lead 80960KB 4fl2bl75 01bb514
A4490

Abstract: 80960MC LAD26 80960KA 80960KB i960 mc errata
Text: , greatly simplify the task of software test and debug. 1.1.15 Fault Detection The 80960MC has an , the 80960MC. READY I READY indicates that data on LAD lines can be sampled or removed. When READY is , ) to 1,5V on the falling edge and 1,5V on the rising edge of the L-Bus address/data ( LAD ) signals , 0.45 V and 0.55 Vcc. OUTPUTS: LAD 31:0 ADS W/R, DEN BE3:0 HLDA/HOLDR CACHE LOCK, INTA r-^v.r-v , Vcc N.C. N.C. C o o o o o o o o o o 0 o o o C HOLD lad25 badac Vcc Vss lad20 LAD


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PDF 80960MC, 32-bit 512-byte 80960MC A80960MC. A4490 LAD26 80960KA 80960KB i960 mc errata
Hysol C9-4215

Abstract: No abstract text available
Text: ) .884 (22.45) .950 (24.13) .270 (6.86) .308 (7.83) 1.115 (28.32) .185 (4.70) .140 (3.99) 1.335 (33.91) .952 (24.18) .950 (24.13) .270 (6.66) .308 (7.83) 1.115 (28.32 , ) .801 (20.34) .252 (6.40) .965 (24.51) .951 (24.16) .252 (6.40) 1.115 (28.34) 1.101 , Head Configuration Rug and Receptacle Low and High PmSe Sire 9-51 Size 9-51 .125 (3.18) HEX


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Power Supply Supervisor iw 1688

Abstract: 754for
Text: of software test and debug. 1.1.15 Fault Detection The 80960MC has an automatic mechanism to handle , data on LAD lines can be sampled or removed. When READY is not asserted during a Td cycle, the Td cycle , edge and 1.5V on the rising edge of the L-Bus address/data ( LAD ) signals. 1-694 PRELIMINARY , 0.45 V and 0.55 Vc c . EDGE V OUTPUTS; LAD 31:0 ÄDS W /fi, PEN 8E3.0 HLDA/HOLDR CACHE LGCK.ÌKÌTA , N.C. o o LAD2e ALE o o o 0 O O 0 O O N.C. O O O CO CO O N.C. LAD jo READY BE


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PDF 80960MC 32-BIT 80-Bit 512-Byte 80960MC A80960MC. Power Supply Supervisor iw 1688 754for
MEJ 301

Abstract: lvj taiwan semiconductor VIC 2A 94v-0 lrj 59 AK 061 marking c08 LXJ Series P6SMB33A ltj LXJ 72 P6SMB11A
Text: 14.5 0.073 P0SMB11 KQJ 9.00 12.1 1.0 8.92 5.0 98 10.2 0.075 P6SMB11A KRJ 111.5 11.6 1.0 9.40 5.0 40 , 5.0 1.9 323.9 0.108 Notes: 1. Vbr mfla&nrad attar happl lad for 300us, lr=E


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PDF SMB/DO-214AA pre63MB130 6M8130A SMB200 P3SMB200A SMB220 6M822BA 300us, P63MB5 P6SMB220A. MEJ 301 lvj taiwan semiconductor VIC 2A 94v-0 lrj 59 AK 061 marking c08 LXJ Series P6SMB33A ltj LXJ 72 P6SMB11A
2009 - Marking DIODE ph41

Abstract: No abstract text available
Text: — TSPICC + 3.0 × 111.5 TC + 5 — ns Wide 0.5 × TSPICC + 3.0 × 206.5 TC + 5 — ns


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PDF DSP56720EC DSP56720/DSP56721 DSP56720 144-Pin DSP56720/DSP56721 DSP5672x DSP56300 24-bit Marking DIODE ph41
2006 - NMI120

Abstract: No abstract text available
Text: 111.5 TC + 5 0.5 x TSPICC + 3.0 x 206.5 TC + 5 - - 3.0 x TC 0 0 15 HREQ in deassertion to last SCK


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PDF DSP56720 DSP56721 DSP56721 DSP56720/DSP56721 DSP5672x DSP56300 24-bit NMI120
2009 - sony tc-200

Abstract: 144 QFP body size DSP56720 DSP56300 DSP56721 power meter hack TOP MARKING HA2 SDO51 SDO21
Text: 49.5 - ns Narrow 0.5 × TSPICC + 3.0 × 111.5 TC + 5 - ns Wide 0.5 × TSPICC +


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PDF DSP56720EC DSP56720/DSP56721 DSP56720 144-Pin DSP56720/DSP56721 DSP5672x DSP56300 24-bit sony tc-200 144 QFP body size DSP56720 DSP56721 power meter hack TOP MARKING HA2 SDO51 SDO21
Not Available

Abstract: No abstract text available
Text: 80 5 940 1075 825 96 0 1095 C L K to Q (S E ) 74 5 930 1115 755 940 , 1115 S E L to Q 74 5 970 1195 755 980 1205 775 1000 1225 600 800 , ed and the re is a d e sire to save th re s h o ld s fo r the s in g le -e n d e d in pu ts w ill , e sire d state. are d e p e n d e n t on the relative po sitio n of the V b b sw itch ing


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PDF C10E211/D /100E MC10E211 MC100E211
TW2816

Abstract: RDD 17-33 skr 12/08 CFL blast circuit information XcxxX BT550 ibm rev.1.5 panel diagram 4342414 plx 9054 MODEM WIS MMI
Text: .2-2 2.4.1.1. LAD [


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PDF 32-bit 33-MHz 176-pin 225-pin 480-AA66PI 225-pin 480-AA66BI TW2816 RDD 17-33 skr 12/08 CFL blast circuit information XcxxX BT550 ibm rev.1.5 panel diagram 4342414 plx 9054 MODEM WIS MMI
Not Available

Abstract: No abstract text available
Text: VGS=0.0 V Pinch-off Voltage Vds=3.0 V IDS=1.0mA Gate-to-Source Breakdown Voltage lqs=-0.4 mA. lad , .80 .86 .72 .59 .51 -26.6 -49.1 -66.5 -82.3 -95.8 - 111.5 -154.2 159.1 120.2 98.2 79.8


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2001 - computer motherboard circuit diagram g31 chipset

Abstract: sac 187 sac 187 datasheet DQR43 460GX MDA 2500 t187 945 MOTHERBOARD CIRCUIT diagram 95 A B N05 82466GX
Text: .11-14 SMBus Timing Diagrams. 11-15 , 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 11-15 11-16 11-17 11-18 11-19 11-20 , .11-14 SMBus Timing. 11-15 SMBus Timeout Timing. 11-15 , .11-9 Intel® 460GX Chipset Datasheet 11-14 11-15 11-16 12-1 12-2 12-3 12-4 12-5 General


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PDF 460GX IA-64 82461GX 82465GX 64-bit, 66-MHz 82466GX 32-bit, 33-MHz computer motherboard circuit diagram g31 chipset sac 187 sac 187 datasheet DQR43 MDA 2500 t187 945 MOTHERBOARD CIRCUIT diagram 95 A B N05 82466GX
2000 - RF transistor W2W

Abstract: RDD 17-33 BF190 iop480 DWDA B-23 B-31 93CS66L ix 2933 RISCwatch
Text: . LAD [31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . 11-15 11.7.3.3. Save/Restore Registers 2 and 3 (SRR2­SRR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.7.3.4. Exception Vector Prefix Register (EVPR


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PDF 480-lf Index-36 RF transistor W2W RDD 17-33 BF190 iop480 DWDA B-23 B-31 93CS66L ix 2933 RISCwatch
1997 - a4490

Abstract: 80960MC A80960MC25 i960 mc errata 80960KA 80960KB M8259A intel packaging handbook 240800
Text: . 8 1.1.15 Fault Detection , . 1.1.15 Fault Detection The 80960MC has an automatic mechanism to handle faults. There are ten fault , 80960MC. READY LOCK I I/O O.D. READY indicates that data on LAD lines can be sampled or


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PDF 80960MC 32-BIT 80-Bit 512-Byte LAD31_ A4492-01 A80960MC. a4490 80960MC A80960MC25 i960 mc errata 80960KA 80960KB M8259A intel packaging handbook 240800
2004 - a4490

Abstract: 80960MC Intel i960 architecture 80960KA 80960KB M8259A 273123
Text: . 8 1.1.15 Fault Detection , . 1.1.15 Fault Detection The 80960MC has an automatic mechanism to handle faults. There are ten fault , 80960MC. READY LOCK I I/O O.D. READY indicates that data on LAD lines can be sampled or


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PDF 80960MC 32-BIT 80-Bit 512-Byte LAD31_ A4492-01 a4490 80960MC Intel i960 architecture 80960KA 80960KB M8259A 273123
2000 - Not Available

Abstract: No abstract text available
Text: 2.4.1.1. LAD [31:0] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . 11-15 11.7.3.3. Save/Restore Registers 2 and 3 (SRR2–SRR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-15 11.7.3.4. Exception Vector Prefix Register


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PDF 480-elf Index-36
1995 - doorbell application

Abstract: la2 d2 timer PIN CONFIGURATION pci 32 bit 5 v PCI9060ES PCI9060SD 10B5 9060ES 93CS56 NM93CS46
Text: No file text available


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PDF 9060ES 100ns 150ns 200ns 250ns 300ns 350ns 400ns 450ns A31-29 doorbell application la2 d2 timer PIN CONFIGURATION pci 32 bit 5 v PCI9060ES PCI9060SD 10B5 9060ES 93CS56 NM93CS46
1997 - a4490

Abstract: 80960MC LAD12 80960KA 80960KB M8259A i960 mc errata
Text: . 8 1.1.15 Fault Detection , , greatly simplify the task of software test and debug. 1.1.15 Fault Detection The 80960MC has an , drain-output of the 80960MC. READY LOCK I I/O O.D. READY indicates that data on LAD lines can


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PDF 80960MC 32-BIT 80-Bit 512-Byte LAD31_ A4492-01 A80960MC. a4490 80960MC LAD12 80960KA 80960KB M8259A i960 mc errata
1995 - NM93CS46

Abstract: PCI9060ES PCI9060SD 10B5 9060ES 93CS56
Text: No file text available


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PDF 9060ES 100ns 150ns 200ns 250ns 300ns 350ns 400ns 450ns A31-29 NM93CS46 PCI9060ES PCI9060SD 10B5 9060ES 93CS56
Not Available

Abstract: No abstract text available
Text: (each w ith its ow n register which the user loads to specify the d e sire d in p u t fo r th a t o u , Figures 1.1-1.5 ) (@ Vd d = 5.0 V ±10% Vss=0 V, Ta =0 to 70°C. Outputs loaded and timing measured at


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PDF SC11320 100-PIN
ATA 2388

Abstract: No abstract text available
Text: equivalent combination of time and temperature. Burr-Brown IC D ata Book 6 . 1-115 Vol. 33 , . T his sw itching allows a co n stan t cu rren t to be m ain tain ed in each lad der leg independent , one-bit cu rren t d rain through the lad d er term i­ Burr-Brown 1C D ata Book DYNAMIC PERFORM ANCE


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PDF 117313LS OD144DD DAC7541A 12-Bit 7521/7541/7541A 12-bit, ATA 2388
Supplyframe Tracking Pixel