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USB1T1104MHX Fairchild Semiconductor Corporation Rochester Electronics 10,382 $0.72 $0.59

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2002 - PCS6105CT

Abstract: transistor 6 pin SMD Z2 TAJD336K016R SMD resistors 0805 koa SLMA004 SLMA002 RM73Z2A PCS6105CT-ND IC vertical panasonic GRM40Z5U104M050A
Text: least 10 X the highest operating frequency ( 1.104MHz is the highest ADSL operating frequency). 20X or


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PDF THS6093EVM SLOU141 THS6093 THS6093 PCS6105CT transistor 6 pin SMD Z2 TAJD336K016R SMD resistors 0805 koa SLMA004 SLMA002 RM73Z2A PCS6105CT-ND IC vertical panasonic GRM40Z5U104M050A
1999 - HC6094

Abstract: HC6094IN
Text: Peak to Peak GP Across 1.104MHz Bandwidth - 0.2 0.6 dB Stopband Attenuation GS , FREQUENCY RESPONSE Gain Ripple Peak to Peak GP Across 1.104MHz Bandwidth Stopband Attenuation


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PDF 14-Bit HC6094 5o-16o 5M-1982. HC6094IN
DAC Combo

Abstract: Combo Driver DPS8001 DPS8100
Text: 138kHz/ 276kHz TX Out PAA and Line Driver 16 ADC 4.4MS/s RX LPF 552kHz/ 1.104MHz


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PDF DPS8100 14-bit DAC Combo Combo Driver DPS8001
2000 - GC114

Abstract: reverb effect AFE1302 TQFP-48 adsl modem input circuit
Text: ) Data Word Clock = 4.416MHz (2 Bits) Data Word Clock = 2.208MHz (2 Bits) Data Word Clock = 1.104MHz (2


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PDF AFE1302 144dBm/Hz 570mW TQFP-48 AFE1302 328MHz, 832MWordion GC114 reverb effect adsl modem input circuit
Not Available

Abstract: No abstract text available
Text: Across 1.104MHz Bandwidth - 0.2 0.6 dB Stopband Attenuation GS At 2.65MHz 14 , RX q u t ) RECEIVER FREQUENCY RESPONSE Gain Ripple Peak to Peak GP Across 1.104MHz


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PDF HC6094 14-Bit HC6094 1-800-4-HARRIS
2000 - adsl lite

Abstract: ADSL Modem circuit diagram ATM timing diagram 8309 teaklite interleaver Motorola cell phone transceiver chip 100 MHz S5N8944B adsl modem input circuit Motorola cell phone transceiver chip 100 MHz to 4
Text: , should be 1.104MHz (276kHz) . DMT inherently transmits an optimized time-variable spectrum. This spectrum , ns Figure 5: AFE Data I/F Timing Diagram t2 t3 AFE_SEN_N AFE_SCL ( 1.104MHz ) AFE_SDO


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PDF S5N8944B adsl lite ADSL Modem circuit diagram ATM timing diagram 8309 teaklite interleaver Motorola cell phone transceiver chip 100 MHz S5N8944B adsl modem input circuit Motorola cell phone transceiver chip 100 MHz to 4
2000 - Dittmer RTD

Abstract: sp 201 adsl splitter circuit diagram LTC2400 rtd sp 201 adsl splitter D link schematic circuit diagram adsl modem board RSB 7900 ADSL Central Office CO Chipset international rectifier databook Implementation of qam on TMS320C54x SAMSUNG ADAPTER 19v
Text: No file text available


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PDF 24-Bit OT-23 24-Bit 1-800-4-LINEAR Dittmer RTD sp 201 adsl splitter circuit diagram LTC2400 rtd sp 201 adsl splitter D link schematic circuit diagram adsl modem board RSB 7900 ADSL Central Office CO Chipset international rectifier databook Implementation of qam on TMS320C54x SAMSUNG ADAPTER 19v
2003 - AN 7085

Abstract: IDC bh DN70EP7-A100 SIEMENS BST N 45 b 110 DNW45 AL320 10BASE5 10BASE MgZn ic 7085
Text: 1.104MHz ADSL30kHz1.1MHz 10Mbps 12 2.2MHz ADSL 14 ADSL12 ADSL 14ADSL


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PDF 5M80MHz 25k1MHz 16k65kHz 1k500kHz 1M300MHz 140Ts 11CDFSDF e/AN31/2 1986pp 210Ethernet AN 7085 IDC bh DN70EP7-A100 SIEMENS BST N 45 b 110 DNW45 AL320 10BASE5 10BASE MgZn ic 7085
1998 - Not Available

Abstract: No abstract text available
Text: frequency bands (138 KHz, 1.104MHz ) - LNA input = ”11” (max attenuation) - VCO dac and Echo path


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PDF MTC-20144 December1998 MTC-20144 12-bit 13bit 12/98-DS254c
1995 - Not Available

Abstract: No abstract text available
Text: ) Data Word Clock = 1.104MHz (2 Bits) Clear CLIP Signal: X = 1, RX is Clipping; X = 0, CLIP Cleared


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PDF AFE1302 144dBm/Hz 570mW TQFP-48 AFE1302 328MHz, 832MWords/s.
DIGITAL ECHO pcb

Abstract: 400khz xtal 150De Digital TV transmitter receivers block diagram atu-c HFC2 TQFP64 STLC60135 STLC60134 35. 328m
Text: . selection: Fc = 1.104MHz (¡nit) 0 0 1 1 0 1 0 HC freq. selection: Fc = 1.104MHz-43.75 % = 621kHz , Frequency band 1.104MHz (0%setting, see below) Frequency tuning -43.75%->+0% Max. in-band ripple 1dB , Out-of-band noise 1.6|xVHz1/2 1.6|xVHz1/2 150nVHz~1/2 @ 34.5kHz -138kHz @138kHz @ 250kHz - 1.104MHz For min


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PDF STLC60134 -60dB STLC60134 STLC60135 TQFP64 TQFP64 DIGITAL ECHO pcb 400khz xtal 150De Digital TV transmitter receivers block diagram atu-c HFC2 STLC60135 35. 328m
2001 - ST70235

Abstract: ST70134 ST70134A ST70135 ST70135A TQFP64
Text: uc d 1Vpd 3rd order butterworth 1.104MHz (0% setting, see below) -43.75% -> +0% 1dB [B, A , group delay < 50µs @ 138kHz < f < 1.104MHz Total RX filter group delay distortion < 15µs @ 138kHz < f < 1.104MHz 8/22 s) t( ST70134A Figure 5 : HC Filter Mask for RX Amplitude ±1dB , -138kHz 500nVHz-1/2 @ 34kHz -138kHz @ 250kHz - 1.104MHz For min AGC setting (=-15dB) In-band , ) * SC freq. selection: Fc ~ 170kHz HC freq. selection: Fc = 1.104MHz 0 * SC freq. selection


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PDF ST70134 ST70134A -60dB TQFP64 ST70134 TQFP64) ST70135A ST70235 ST70134A ST70135 TQFP64
ST TX01

Abstract: lt 5234 VCO 35.328 MHz oscillator HC1 MTC-20146 MTC-20144TQ-I MTC-20144TQ-C 1104MH mtc diode mtc 110 16
Text: minimum value. - Nominal filter frequency bands (138 KHz, 1.104MHz ) - LNA input = "11" (max attenuation


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PDF MTC-20144 December1998 MTC-20144 12-bit 13bit 12/98-DS254c ST TX01 lt 5234 VCO 35.328 MHz oscillator HC1 MTC-20146 MTC-20144TQ-I MTC-20144TQ-C 1104MH mtc diode mtc 110 16
1999 - TXM TX 2E

Abstract: TMS320C6xx TLV320AD11A
Text: consists of two programmable-gain amplifiers, a frequency equalizer, a 1.104-MHz low-pass analog filter, a 14-bit high speed ADC, and a 1.104-MHz low-pass digital filter. The clock circuit divides a 35.328 , the high resolution ADC. The receiver channel also has a 1.104-MHz low-pass filter with a 4.416 MSPS


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PDF TLV320AD11A SLWS087B 14-Bit 12-Bit 16-bit TXM TX 2E TMS320C6xx TLV320AD11A
2000 - AFE1302

Abstract: TQFP-48 GC114
Text: ) Data Word Clock = 4.416MHz (2 Bits) Data Word Clock = 2.208MHz (2 Bits) Data Word Clock = 1.104MHz (2


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PDF AFE1302 144dBm/Hz 570mW TQFP-48 AFE1302 328MHz, 832MWordplications GC114
1995 - 24GC0

Abstract: rfid key
Text: ) Data Word Clock = 1.104MHz (2 Bits) Clear CLIP Signal: X = 1, RX is Clipping; X = 0, CLIP Cleared


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PDF AFE1302 144dBm/Hz 570mW TQFP-48 AFE1302 328MHz, 832MWords/s. 24GC0 rfid key
1999 - TXM TX 2E

Abstract: No abstract text available
Text: programmable-gain amplifiers, a frequency equalizer, a 1.104-MHz low-pass analog filter, a 14-bit high speed ADC, and a 1.104-MHz low-pass digital filter. The clock circuit divides a 35.328-MHz frequency from an , receiver channel also has a 1.104-MHz low-pass filter with a 4.416 MSPS and a 14-bit ADC to provide a 2X


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PDF TLV320AD11A SLWS087B 14-Bit 12-Bit 16-bit SGLB002, SGYC003B, TLV320AD11APZ TLV320AD11APZR TXM TX 2E
2005 - phone and modem splitter block diagram

Abstract: phone line splitter circuit diagram phone and modem splitter circuit diagram low pass filter circuit 3.4khz NEC Tokin SPLITTER ADSL tokin PSR-1180 PSR 57 adsl splitter circuit diagram
Text: (300kHz to 1.104MHz ) > =15(30kHz to 300kHz) > =55(300kHz to 1.104 MHz) ADSL POTS Splitter Shapes


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PDF BF-2005) PSR-1080) BF-2008) PSR-1180) PSR-1080 1004Hz) 0241ADSL07VOL02E phone and modem splitter block diagram phone line splitter circuit diagram phone and modem splitter circuit diagram low pass filter circuit 3.4khz NEC Tokin SPLITTER ADSL tokin PSR-1180 PSR 57 adsl splitter circuit diagram
1995 - Not Available

Abstract: No abstract text available
Text: ) Data Word Clock = 1.104MHz (2 Bits) Clear CLIP Signal: X = 1, RX is Clipping; X = 0, CLIP Cleared


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PDF AFE1302 144dBm/Hz 570mW TQFP-48 AFE1302 328MHz, 832MWorm
2009 - Midcom

Abstract: HP3326A LT1329 4-wire to 2-wire hybrid HP3326 JP16 LTC1440 LT1795 LT1368 LT1358
Text: 40.0 1MHz 1.104MHz 30.0 20.0 10.0 0.0 5 7.5 10 20 30 40 50 60 70 , 300KHz 80 100 400KHz 1MHz 110 1.104MHz 110 50 90 80 70 90 100 70


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PDF DC261A-A DC261A LT1795 LT1358 pin11) /-10V /-12V /-15V Midcom HP3326A LT1329 4-wire to 2-wire hybrid HP3326 JP16 LTC1440 LT1795 LT1368 LT1358
1999 - 59 PAA

Abstract: TMS320C6xx scr7 TLV320AD12A TLV320AD11A THS6032 THS6012 AD12 TXM RX 23 Receiver TXM RX 28 Receiver
Text: ), clock, reference, and host interface. The transmit channel consists of a 25.875-kHz to 1.104-MHz digital band-pass filter, a 14-bit, 8.832-MSPS DAC, a 1.104-MHz analog low-pass filter, and a transmit , TLV320AD11A remote terminal-side (RT) codec. The TLV320AD12A transmit channel consists of a 1.104-MHz , -megabyte samples-per-second (MSPS) digital-to-analog converter (DAC), a 1.104-MHz analog LPF, and a programmable amplifier


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PDF TLV320AD12A SLWS088A 800-kbit/s 14-Bit 59 PAA TMS320C6xx scr7 TLV320AD12A TLV320AD11A THS6032 THS6012 AD12 TXM RX 23 Receiver TXM RX 28 Receiver
1999 - TXM TX 2E

Abstract: TLV320AD11A TMS320C6XX SCR11
Text: consists of two programmable-gain amplifiers, a frequency equalizer, a 1.104-MHz low-pass analog filter, a 14-bit high speed ADC, and a 1.104-MHz low-pass digital filter. The clock circuit divides a 35.328 , the high resolution ADC. The receiver channel also has a 1.104-MHz low-pass filter with a 4.416 MSPS


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PDF TLV320AD11A SLWS087B 14-Bit 12-Bit 16-bit TXM TX 2E TLV320AD11A TMS320C6XX SCR11
2000 - AFE1302

Abstract: TQFP-48 adsl hybrid filter
Text: ) Data Word Clock = 4.416MHz (2 Bits) Data Word Clock = 2.208MHz (2 Bits) Data Word Clock = 1.104MHz (2


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PDF AFE1302 144dBm/Hz 570mW TQFP-48 AFE1302 328MHz, 832MWordplifiers adsl hybrid filter
2002 - Not Available

Abstract: No abstract text available
Text: frequency ( 1.104MHz is the highest ADSL operating frequency). 20X or even larger may be preferable. 3-6


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PDF THS6053EVM SLOU140 THS6053 THS6053
2001 - 8309

Abstract: ADSL Modem circuit diagram interleaver VDD23 S5N8951 S5N8952 S5N8952X
Text: , the frequency band, 0 to 1.104MHz , is divided into 256 equi-spaced subchannels with 4.3125KHz tone , Figure 5: AFE Data I/F Timing Diagram t2 t3 AFE_SEN_N AFE_SCK ( 1.104MHz ) AFE_SDO CS1


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PDF S5N8952X 8309 ADSL Modem circuit diagram interleaver VDD23 S5N8951 S5N8952 S5N8952X
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