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Top Results (6)

Part Manufacturer Description Datasheet Download Buy Part
RH73X1E10GKTN (1879237-4) TE Connectivity (1879237-4) RH73 1E 10G 10% 1000PPM
2231705-1 TE Connectivity (2231705-1) QSFP+, 10G FLEXIBLE, 1M, 30AWG
RH73X2B10GKTN (1625862-8) TE Connectivity (1625862-8) RH73 2B 10G 10% 1000PPM
2231705-2 TE Connectivity (2231705-2) QSFP+, 10G FLEXIBLE, 2M, 28AWG
RH73X2A10GNTN (1625862-1) TE Connectivity (1625862-1) RH73 2A 10G 30% 1000PPM
2231705-5 TE Connectivity (2231705-5) QSFP+, 10G FLEXIBLE, 5M, 26AWG

10G BERT Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2004 - tx 2G transmitter

Abstract: tx 2G 10G BERT 10G serdes bert BCM8040 BCM8702
Text: loopback, BIST, 10G BERT , and random Ethernet packet generation Compact 23-mm × 23-mm package with no , Cross-Link Application Diagram Rx OVERVIEW 10G XAUI_0 10G XAUI_2 Channel_0 (1­3.2G , ) Channel_3 (1­3.2G) Channel_3 (1­3.2G) Bus Mux 10G XAUI_1 10G XAUI_3 Channel_4 (1­3.2G


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PDF BCM8040 IEEE802 10-Gigabit 40-Gbps 8040-PB04-R tx 2G transmitter tx 2G 10G BERT 10G serdes bert BCM8040 BCM8702
2006 - BROADCOM "heat sink"

Abstract: BCM8020 BCM8702 BROADCOM "heat sink" 7 10G BIST PRBS
Text: Serial and parallel loopback, BIST, 10G BERT , and random Ethernet packet generation · IEEE (1149.1 , RX OVERVIEW 10G XAUI_0 10G XGMII_0 Channel_0 (1­3.2G) Channel_0 (TBI, RTBI , _3 (1­3.2G) Channel_3 (TBI, RTBI) (Control/Clocking) Bus MUX 10G XAUI_1 10G XGMII_1 Channel


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PDF BCM8020 OC-48 10-Gigabit 8020-PB05-R BROADCOM "heat sink" BCM8020 BCM8702 BROADCOM "heat sink" 7 10G BIST PRBS
2003 - 10G serdes bert

Abstract: 10G serdes 2.5 xaui 10G BERT BCM8020 BCM8702 10G serdes 2.5 quad 10G BIST PRBS
Text: Serial and parallel loopback, BIST, 10G BERT , and random Ethernet packet generation · IEEE (1149.1 , 10G XAUI_0 10G XGMII_0 Channel_0 (1­3.2G) Channel_0 (TBI, RTBI) Channel_1 (1­3.2G , Channel_3 (TBI, RTBI) (Control/Clocking) 10G XAUI_1 10G XGMII_1 Channel_4 (1­3.2G) Channel


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PDF BCM8020 OC-48 10-Gigabit 10-Gigabit 10-Gbps 8020-PB03-R-04-15-03 10G serdes bert 10G serdes 2.5 xaui 10G BERT BCM8020 BCM8702 10G serdes 2.5 quad 10G BIST PRBS
2003 - Not Available

Abstract: No abstract text available
Text: interconnects • Enhanced test capability • Full loopback, BIST, 10G BERT , and random Ethernet packet , Rx B C M 8 0 4 0 O V E R V I E W BCM8040 Block Diagram 10G XAUI_0 10G XAUI_2 Channel , ) Channel_2 (1–3.2G) Channel_3 (1–3.2G) Bus Mux Channel_3 (1–3.2G) 10G XAUI_1 10G XAUI


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PDF BCM8040 IEEE802 40-Gbps 8040-PB03-R-04-15-03
2002 - Not Available

Abstract: No abstract text available
Text: capability • •Enhanced testBIST, 10G BERT , and random Ethernet packet Full loopback, generation â , CML I/O. • 1GbE and 10GbE LAN, MAN, WAN Switches and Routers • 1x, 2x, or 10G Fibre Channel


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PDF BCM8040 10GbE 8040-PB00-R-3
2004 - 10G serdes 2.5 quad

Abstract: 10G BERT 10G serdes bert 10G BIST PRBS tx 2G transmitter tx 2G BCM8020 BCM8702
Text: equalization for copper interconnects Enhanced test capability · Serial and parallel loopback, BIST, 10G BERT , × XGMII/TBI 2× XAUI 2 Independent Quad SerDes Application Diagram Rx OVERVIEW 10G XAUI_0 10G XGMII_0 Channel_0 (1­3.2G) Channel_0 (TBI, RTBI) Channel_1 (1­3.2G) Channel_1 (TBI , ) Bus Mux (Control/Clocking) 10G XAUI_1 10G XGMII_1 Channel_4 (1­3.2G) Channel_4 (TBI


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PDF BCM8020 10-Gigabit 10-Gbps 8020-PB04-R 10G serdes 2.5 quad 10G BERT 10G serdes bert 10G BIST PRBS tx 2G transmitter tx 2G BCM8020 BCM8702
2002 - Not Available

Abstract: No abstract text available
Text: parallel loopback, BIST, 10G BERT , and random Serial and Decreases complexity and reduces â , , 2x, or 10G Fibre Channel, Infiniband, SONET Network Cards • Advanced Test Equipment (ATE


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PDF BCM8020 1875Gbps. OC-48 8020-PB00-R-3
2006 - 10G BERT

Abstract: CX4 connector BCM8040
Text: for copper interconnects Enhanced test capability · Full loopback, BIST, 10G BERT , and random


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PDF BCM8040 IEEE802 8040-PB06-R 10G BERT CX4 connector BCM8040
2006 - Not Available

Abstract: No abstract text available
Text: loopback, BIST, 10G BERT , and random Ethernet packet generation Compact 23-mm × 23-mm package with no


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PDF BCM8040 IEEE802 10-Gigabit 40-Gbps 8040-PB05-R
2004 - 10G BERT

Abstract: MultiBERT PICMG 3.0 Revision 1.0 XAPP537 XC2VP70 UG024
Text: connection tests over an ATCA backplane. MultiBERT is based on the Xilinx ATCA 10G 4X4 Line Card (hereafter , Introduction BERT BERT BERT Serial Mesh Backplane BERT BERT BERT PPC Platform ATCA Card PPC Platform ATCA Card Ethernet BERT BERT BERT PPC Platform ATCA Card X537 , Acronym Definition ATCA Advanced Telecom Computing Architecture BERT Bit Error Rate Test , system consists of the following components: · ATCA Backplane · ATCA 10G 4X4 Line Card ·


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PDF XAPP537 10G BERT MultiBERT PICMG 3.0 Revision 1.0 XAPP537 XC2VP70 UG024
2002 - 10G BERT

Abstract: GR-253-CORE STM64 STM-64 eprom ic VC4-64c
Text: sublayers of the 10G Ethernet and Fibre Channel standards. For WAN applications a standard OC-192/STM , bit error rate tester ( BERT ) usable for multiple atspeed diagnostic scenarios Includes the XGXS, PCS , Line Interface Gbit/s BERT BERT Framer Framer 4x 3.125 Sync & Sync & Deskew Deskew , XGXS Clock LA TIA Photodiode E²PROM I²C Interface Transponder Module 10G Ethernet


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PDF OC-192c 51875Gbit/s. OC-192/STM-64 10G BERT GR-253-CORE STM64 STM-64 eprom ic VC4-64c
2008 - Not Available

Abstract: No abstract text available
Text: over SONET/SDH. • Packet BERT : Highly versatile and independent module used to gener ate and , , a SONET/SDH Framer, POS Mapper/DeMapper, and Packet Bit Error Rate Test ( BERT ). The Framer: STS , network cores from 10G (OC -192) to 40G (OC-768) to support higher -bandwidth “triple-play” (voice , RxDCC/RxTOH/RxPOH 3 3 3 POS Mapper POS De-Mapper Packet BERT Generator TxDCC/TxTOH , Interlaken Interface Packet BERT Monitor SONET/SDH Framer Rx FIF O and C trl 17 L i ne Inter


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PDF CS1999 OC-768
2008 - interlaken network processor

Abstract: OC-768 10G serdes bert overhead processor Cortina Systems
Text: with industry standard 40G optical modules. The industry is upgrading network cores from 10G (OC , /DeMapper, and Packet Bit Error Rate Test ( BERT ). The 16 (data) 16 (address) 40G POS Mapper is connected , path overhead. POS Mapper: Single 40G mapper that maps packets over SONET/SDH. Packet BERT : Highly , POS Mapper POS De-Mapper Packet BERT Generator 16 RxDCC/RxTOH/RxPOH TxDCC/TxTOH/TxPOH GPIO , Overhead Processor Path Overhead Processor Interlaken Interface SFI-5.1 Packet BERT Monitor


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PDF CS1999 OC-768 OC-192) OC-768) interlaken network processor 10G serdes bert overhead processor Cortina Systems
2002 - 10G BERT

Abstract: K line interface
Text: Integrated bit error rate tester ( BERT ) usable for multiple atspeed diagnostic scenarios Includes the XGXS , Block Diagram XAUI Interface 4x 3.125 Gbit/s Sync & Sync & Deskew Deskew BERT BERT 8B , Module Management Interface I²C Interface E²PROM (optional) 10G Ethernet / Fibre Channel


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2002 - "programmable on-chip termination"

Abstract: MDIO clause 22 lazer diode LXT11001 LXT35401 10G BERT 10G serdes bert lazer intel xenpak
Text: budgets. Data I/O is handled by two 10G Attachment Unit Interface (XAUI) ports. Configuration , ) for re-timing, deserializer, code word synchronizer, lane aligner, Idle/ BERT logic, serializer , /S Idle and Bert Logic Idle and Bert Logic P/S Equalizer and FAUI XMTR I n ter , polarity · Programmable on-chip termination resistors s BERT generators/checkers with error counters , resistors s BERT generators/checkers with error counters s Helps reduce time and equipment for


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PDF LXT35401 10Gbps LXT35401 10GBASE-LX4 USA/0102/5K/MGS/DC "programmable on-chip termination" MDIO clause 22 lazer diode LXT11001 10G BERT 10G serdes bert lazer intel xenpak
MAX15059

Abstract: 10G APD 1310nm MAX3799 10G CDR EAM Laser Driver XFP-10 APD for 10Gbps PRBS231-1 1310nm fiber optic for 10Gbps 14-Gbps
Text: 10G Electrical Loopback BERT CLK TXREFCLK TXPICLK DEMUX 622M x16 MUX Optical TX , phase delay element, a CDR (clock-anddata-recovery) unit, and a serial BERT (bit-error-rate tester). At , TDIP TDIN 0-100ps DELAY 50 ohm 10G CDR RxREFCLK TCOP RDIP TDOP Figure 4. Setup , signal to received signal delay is varied by one UI (100-psec). Device under test is a 10G bidirectional , Integrated Products Page 6 of 9 TITLE: 10G BIDIRECTIONAL TRANSCEIVER CHIP 10G BIDIRECTIONAL TRANSCEIVER


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PDF HFTA-12 MAX15059 10G APD 1310nm MAX3799 10G CDR EAM Laser Driver XFP-10 APD for 10Gbps PRBS231-1 1310nm fiber optic for 10Gbps 14-Gbps
1310nm 10Gbps DML

Abstract: hall 04E 1550nm optical detector 10Gbps XFP-10 10G APD chip MAX3943 MAX3872 hall ic 01e hall effect 44e MAX3658* application note
Text: 10G Electrical Loopback BERT CLK TXREFCLK TXPICLK DEMUX 622M x16 MUX Optical TX , phase delay element, a CDR (clock-anddata-recovery) unit, and a serial BERT (bit-error-rate tester). At , TDIP TDIN 0-100ps DELAY 50 ohm 10G CDR RxREFCLK TCOP RDIP TDOP Figure 4. Setup , signal to received signal delay is varied by one UI (100-psec). Device under test is a 10G bidirectional , Integrated Products Page 6 of 9 TITLE: 10G BIDIRECTIONAL TRANSCEIVER CHIP 10G BIDIRECTIONAL TRANSCEIVER


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PDF HFTA-12 1310nm 10Gbps DML hall 04E 1550nm optical detector 10Gbps XFP-10 10G APD chip MAX3943 MAX3872 hall ic 01e hall effect 44e MAX3658* application note
2002 - Not Available

Abstract: No abstract text available
Text: BCM8320 PRODUCT Brief DUAL 10G B C M 8 3 2 0 FABRIC F E AT U R E S • Highly integrated, scalable switch fabric • Single-chip bandwidth of up to 40 Gbps interfaces side • •Supports two CSIX32, 64, or 128to line speeds up to Each CSIX supports bits at 166 MHz â , scheduling • •Proven high-speed 3.125 Gbps SerDes technology Built-in BERT INTERFACE S U M M A R , . • Supports dual 10G interfaces in a single device. • Excellent redundancy: all links that are


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PDF BCM8320 CSIX32, 128to 96-byte 112-byte 125-Gbps 8320-PB02-R-6
2003 - 10G serdes bert

Abstract: BCM8320 BCM8332 data link block diagram
Text: BCM8320 PRODUCT Brief ® DUAL 10G B C M 8 3 2 0 FABRIC F E AT U R E S · Highly integrated, scalable switch fabric · Single-chip bandwidth of up to 40 Gbps interfaces side · ·Supports two CSIX32, 64, or 128to line speeds up to Each CSIX supports bits at 166 MHz · HSTL Class 1 , technology Built-in BERT INTERFACE S U M M A R Y O F B E N E F I T S Service through the , with no interference from other channels. · Supports dual 10G interfaces in a single device


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PDF BCM8320 CSIX32, 128to 96-byte 112-byte 125-Gbps 8320-PB03-R-6 10G serdes bert BCM8320 BCM8332 data link block diagram
2003 - tsmc cmos 0.13 um

Abstract: P802 10G serdes bert
Text: BUILT-IN BERT SYSTEM BER FOR DIAGNOSTICS, CHARACTERIZATION, AND MANUFACTURING Figure 1. Features and , protocol compatibility (using protocolagnostic operation), includes the following: - XAUI (P802.3ae 10G , , programmable BERT can be programmed to generate and test the following: - Arbitrary length framed or


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PDF SDM6G13 SDM6G13 A10-712-4106) PB03-125SRDS tsmc cmos 0.13 um P802 10G serdes bert
microstripline FR4

Abstract: rogers 4403 rogers rogers* 4403 microstripline MK322 10G BERT 5GHz of FR4 frequency of FR4 RocketIO
Text: full-duplex 10G Serial RocketIOTM X transceivers (embedded) Up to 2 IBM® PowerPC® RISK Processor blocks , Backplane Daughtercard 0XT SIP 1000 MK 322 MK322 TX Thru RX TX DCA BERT LoopBack , sent out to Agilent 71612 BERT box · Better than 10-12 BER for 10Gb/s NRZ after 32" FR4 and 2 0XT , k Src Agilent 71612C BERT Rack 50 Conclusion · Importance of crosstalk in high-speed


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PDF 10Gb/s+ 6100A 81134ACl 71612C 10Gb/s microstripline FR4 rogers 4403 rogers rogers* 4403 microstripline MK322 10G BERT 5GHz of FR4 frequency of FR4 RocketIO
2002 - Not Available

Abstract: No abstract text available
Text: — 33 mm  Designed for 10G serial interface  400 signal balls, 1020 total balls Parallel , /HDLC GFP ATM Packet BERT System Interface System Interface SPI-4 Phase 2 JTAG Test


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PDF CS1777 OC-192c STS-192c/48c GR-253-CORE STS-192c STS-48c STS-192
1980 - fm transistor radio mini project

Abstract: hdmi to SDI IC Nelco-4000 ibis sata 10G serdes bert LMH0346 ibis CAT-5 Sdi IC Nelco-4000-6 Ten Ways to Bulletproof RS-485 Interfaces IC 922
Text: 10G (bps) 1-6. 3 LVDS.national.com/jpn 13 14 ( ) ( (PCB , NEXT FEXT NEXT 1012 1015 1 (BER) ( BERT ) BERT 54 6.3 , ) 6-12. InfiniBand 2.5Gbps BERT BER T11.2 / Project 1316-DT/ Rev 2.0 (Fiber , ") 20 10 0.0 10M 100M freq (Hz) 1G 10G 7-10. ( ) ( ) LVDS.national.com , ( BERT ) CDR (IJT) LMH0346 0.6 UI ISI CDR 7.6 (BER) ( ) (RJ) (DJ) 2 DJ


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PDF 550062-004-JP fm transistor radio mini project hdmi to SDI IC Nelco-4000 ibis sata 10G serdes bert LMH0346 ibis CAT-5 Sdi IC Nelco-4000-6 Ten Ways to Bulletproof RS-485 Interfaces IC 922
2009 - GFP 740

Abstract: EoPDH E1 to ethernet converter circuit HDB3 to LVDS 10G BERT DS26514 DS34T101 DS34T104GN TDK78P7200 DS2174
Text: EMULATION ENGINE 10/100 ETHERNET MAC FRAMERS BERT AND CAS LIUs CLAD (PLL) BUFFER MANAGER , require minimum order quantities. 4 First line-card timing IC to enable 1G and 10G Synchronous , ( BERT ) 16-CHANNEL LIU REPLACES COMPETITION'S 8-CHANNEL SOLUTION TO SAVE SPACE AND COST 100 , , built-in BERT and CLAD 16-port, short-haul LIU, internal software-selectable transmit-/receive-side line termination, hitless protection switching support, 128-bit crystal-less jitter attenuator, built-in BERT and


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2004 - router extender block diagram

Abstract: 8b/10b encoder BCM8703 XGXS XAUI 10G serdes bert
Text: BCM8703 ® SERIAL 10-G ETHERNET/FIBRE CHANNEL TRANSCEIVER WITH XAUI INTERFACE SUMMARY OF BENEFITS FEATURES · IEEE 802.3ae compliant · Support for XENPAK and XPAK Standards · Xenpak support optimized for Xenpak/XPAK layout and thermal · Fully integrated CMU, CDR, and SerDes · Integrated limiting amplifier and EyeOpenerTM for interfacing to XFP modules · PMD interface with serial 10.3125 , BERT test support · EEPROM interface support XENPAK/XPAK fiber-optic modules LAN/WAN switches


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PDF BCM8703 25-MHz BCM8703 8703-PB04-R router extender block diagram 8b/10b encoder XGXS XAUI 10G serdes bert
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