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Part ECAD Model Manufacturer Description Datasheet Download Buy Part
TPS610987DSER TPS610987DSER ECAD Model Texas Instruments Low input voltage, 4.3V output voltage, synchronous boost converter with VSUB active discharger 6-WSON -40 to 85
PDRV10987SPWPR PDRV10987SPWPR ECAD Model Texas Instruments 50W, 12V to 24V, Three-Phase Sensorless BLDC Motor Driver 24-HTSSOP -40 to 85
TPS610987DSET TPS610987DSET ECAD Model Texas Instruments Low input voltage, 4.3V output voltage, synchronous boost converter with VSUB active discharger 6-WSON -40 to 85
DRV10987DPWPR DRV10987DPWPR ECAD Model Texas Instruments 50W, 12V to 24V, Three-Phase Sensorless BLDC Motor Driver 24-HTSSOP -40 to 125
DRV10987SPWPR DRV10987SPWPR ECAD Model Texas Instruments 50W, 12V to 24V, Three-Phase Sensorless BLDC Motor Driver 24-HTSSOP -40 to 125
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0987-RZ-TC-10 TERMINAL BLOCK, BARRIER, 10 POSITION, 24-8AWG; No. of Rows:2 Row; No. of Positions:10Positions; Wire Size AWG Min:24AWG; Wire Size AWG Max:8AWG; Pitch Spacing:12.1mm; Rated Current:50A; Rated Voltage:600V; Product Range:987 Series RoHS Compliant: Yes
0987-RZ-TC-10 ECAD Model
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Master Electronics 0987-RZ-TC-10 18 $57.34 $52.46 $52.46 $52.46 $52.46 Buy Now
Marathon Special Products
0987RZTC10 0987RZTC10
0987RZTC10 ECAD Model
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Allied Electronics & Automation 0987RZTC10 Bulk 0 1 $58.03 $53.39 $49.91 $49.91 $49.91 Get Quote

0987-RZ-TC-10 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2006 - Not Available

Abstract: No abstract text available
Text: 10 -Gigabit Ethernet Optical Transmitters 8× and 10 × Fibre Channel Optical Transmitters SONET OC , OLE BIASC 8 PDP FAULT Analog Reference RZTC BGV TS RZTC BGV TS ENA OLE BIASC , data rising edge at STOP 50 100 10 50 10 10 DESCRIPTION Time required from data falling edge to clock falling edge at START MIN MAX 10 10 10 UNIT ns ns ns ns ns ns ns ns ns REGISTER MAPPING The register , ONET1191V VCSEL driver is supplied by a single 3.3-V ± 10 % supply voltage connected to the VCC pins. This


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PDF ONET1191V SLLS750A 20-Pin 10-Gigabit OC-192/SDH STM-64
2006 - apc ups 640

Abstract: BLM15HG102SN1D STM-64 SFP SFP fiber optic pinout s0212 STM-64 resistor 284 ONET1191V modc7 15-V
Text: · · 10 -Gigabit Ethernet Optical Transmitters 8× and 10 × Fibre Channel Optical Transmitters , BIAS FAULT PDP FLT RZTC RZTC BGV BGV TS TS Analog Reference 8 ENA , START 10 CLKR, DTAR Clock and data rise time Clock and data rise time ns CLKF, DTAF , setup time Minimum time from data rising edge to clock rising edge 10 ns DTAWT Data wait , Minimum time from clock falling edge to data falling edge 10 ns STOPSTP STOP setup time


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PDF ONET1191V SLLS750 20-Pin 10-Gigabit OC-192/SDH STM-64 apc ups 640 BLM15HG102SN1D STM-64 SFP SFP fiber optic pinout s0212 resistor 284 ONET1191V modc7 15-V
2006 - BLM15HG102sn1d

Abstract: No abstract text available
Text: MOD+ MOD­ MONB MONP PD RZTC SCK SDA TS VCC NO. 11 16 14 7 8 1 10 6, 9, EP 18 19 12 13 15 2 4 5 3 17 , °C Surface-Mount, Small-Footprint, 4-mm × 4-mm, 20-Pin QFN Package APPLICATIONS · · · · · 10 -Gigabit Ethernet Optical Transmitters 8× and 10 × Fibre Channel Optical Transmitters SONET OC-192/SDH STM-64 Optical , MONP PD COMP B0072-02 RZTC BGV TS RZTC BGV TS Bias Current Generator and Automatic Power , from clock rising edge to data rising edge at STOP 50 100 10 50 10 10 DESCRIPTION Time required from


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PDF ONET1191V SLLS750 20-Pin 10-Gigabit OC-192/SDH STM-64 BLM15HG102sn1d
2006 - BLM15HG102SN1

Abstract: 15-V BLM15HG102SN1D ONET1191V STM-64 MS501 chemical control process block diagram
Text: RZTC 15 PD 14 COMP 2 TS 3 13 MONP EP 6 7 8 9 10 GND FLT 11 , 4-mm, 20-Pin QFN Package · · · 10 -Gigabit Ethernet Optical Transmitters 8× and 10 × Fibre , RZTC RZTC BGV BGV TS TS ENA OLE BIASC Bias Current Generator and , edge to clock falling edge at START 10 CLKR, DTAR Clock and data rise time Clock and data , edge 10 ns DTAWT Data wait time Minimum time from data falling edge to data rising edge


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PDF ONET1191V SLLS750A 20-Pin 10-Gigabit BLM15HG102SN1 15-V BLM15HG102SN1D ONET1191V STM-64 MS501 chemical control process block diagram
2006 - Not Available

Abstract: No abstract text available
Text: 10 -Gigabit Ethernet Optical Transmitters 8× and 10 × Fibre Channel Optical Transmitters SONET OC , OLE BIASC 8 PDP FAULT Analog Reference RZTC BGV TS RZTC BGV TS ENA OLE BIASC , data rising edge at STOP 50 100 10 50 10 10 DESCRIPTION Time required from data falling edge to clock falling edge at START MIN MAX 10 10 10 UNIT ns ns ns ns ns ns ns ns ns REGISTER MAPPING The register , ONET1191V VCSEL driver is supplied by a single 3.3-V ± 10 % supply voltage connected to the VCC pins. This


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PDF ONET1191V SLLS750A 20-Pin 10-Gigabit OC-192/SDH STM-64
2006 - Not Available

Abstract: No abstract text available
Text: RZTC 15 PD 14 COMP 2 TS 3 13 MONP EP 6 7 8 9 10 GND FLT 11 , 85°C Surface-Mount, Small-Footprint, 4-mm × 4-mm, 20-Pin QFN Package • • • 10 , RZTC RZTC BGV BGV TS TS ENA OLE BIASC Bias Current Generator and , Time required from data falling edge to clock falling edge at START 10 CLKR, DTAR Clock and , data rising edge to clock rising edge 10 ns DTAWT Data wait time Minimum time from data


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PDF ONET1191V SLLS750A 20-Pin 10-Gigabit
2012 - CIRCUIT DIAGRAM APC UPS 700

Abstract: APC Back UPS 500 CIRCUIT apc ups 700 ONET1141L
Text: € DIS 4 15 COMP 13 MONB 9 10 11 12 RZTC 8 GND 7 DIN+ DIN - SDA 6 GND , Compliant QFN Package APPLICATIONS • • • • • 10 Gigabit Ethernet Optical Transmitters , Settings Settings 10 Bit Register IMOD 10 Bit Register IBIAS 8 Bit Register 8 Bit Register , Digital Conversion Bias Current Fault 10 Bit Register BIAS Bias Current MONB Generator/ MONP , , Analog References, Power supply Monitor & Temperature Sensor ADC Power-On Reset PSM RZTC TS


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PDF ONET1141L 145mA CIRCUIT DIAGRAM APC UPS 700 APC Back UPS 500 CIRCUIT apc ups 700 ONET1141L
2007 - Not Available

Abstract: No abstract text available
Text: 16 BIAS VCC VCC DIS 1 RZTC 2 TS 3 SCK 4 SDA 5 15 PD ONET 8501V 20 Pin QFN 14 COMP 13 MONP 12 MONB 11 BGV 6 7 8 9 10 GND TERMINAL FUNCTIONS TERMINAL PIN NO. 1 2 3 4 5 7 8 10 11 12 NAME DIS RZTC TS SCK SDA DIN+ DIN­ FLT BGV MONB Analog-out TYPE Digital-in , RoHS compliant QFN Package APPLICATIONS · · · · · 10 Gigabit Ethernet Optical Transmitters 8x and , COMP RZTC Band-Gap & Analog References BGV Power-On Reset Temperature Sensor TS RZTC BGV TS 2


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PDF ONET8501V SLLS837B
2006 - Not Available

Abstract: No abstract text available
Text: 10 -Gigabit Ethernet Optical Transmitters 8× and 10 × Fibre Channel Optical Transmitters SONET OC , OLE BIASC 8 PDP FAULT Analog Reference RZTC BGV TS RZTC BGV TS ENA OLE BIASC , data rising edge at STOP 50 100 10 50 10 10 DESCRIPTION Time required from data falling edge to clock falling edge at START MIN MAX 10 10 10 UNIT ns ns ns ns ns ns ns ns ns REGISTER MAPPING The register , ONET1191V VCSEL driver is supplied by a single 3.3-V ± 10 % supply voltage connected to the VCC pins. This


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PDF ONET1191V SLLS750A 20-Pin 10-Gigabit OC-192/SDH STM-64
2006 - BLM15HG102SN1

Abstract: 15-V BLM15HG102SN1D ONET1191V STM-64
Text: RZTC 15 PD 14 COMP 2 TS 3 13 MONP EP 6 7 8 9 10 GND FLT 11 , 4-mm, 20-Pin QFN Package · · · 10 -Gigabit Ethernet Optical Transmitters 8× and 10 × Fibre , RZTC RZTC BGV BGV TS TS ENA OLE BIASC Bias Current Generator and , edge to clock falling edge at START 10 CLKR, DTAR Clock and data rise time Clock and data , edge 10 ns DTAWT Data wait time Minimum time from data falling edge to data rising edge


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PDF ONET1191V SLLS750A 20-Pin 10-Gigabit BLM15HG102SN1 15-V BLM15HG102SN1D ONET1191V STM-64
2006 - Not Available

Abstract: No abstract text available
Text: RZTC 15 PD 14 COMP 2 TS 3 13 MONP EP 6 7 8 9 10 GND FLT 11 , 85°C Surface-Mount, Small-Footprint, 4-mm × 4-mm, 20-Pin QFN Package • • • 10 , RZTC RZTC BGV BGV TS TS ENA OLE BIASC Bias Current Generator and , Time required from data falling edge to clock falling edge at START 10 CLKR, DTAR Clock and , data rising edge to clock rising edge 10 ns DTAWT Data wait time Minimum time from data


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PDF ONET1191V SLLS750A 20-Pin 10-Gigabit
2006 - Not Available

Abstract: No abstract text available
Text: 10 -Gigabit Ethernet Optical Transmitters 8× and 10 × Fibre Channel Optical Transmitters SONET OC , OLE BIASC 8 PDP FAULT Analog Reference RZTC BGV TS RZTC BGV TS ENA OLE BIASC , data rising edge at STOP 50 100 10 50 10 10 DESCRIPTION Time required from data falling edge to clock falling edge at START MIN MAX 10 10 10 UNIT ns ns ns ns ns ns ns ns ns REGISTER MAPPING The register , ONET1191V VCSEL driver is supplied by a single 3.3-V ± 10 % supply voltage connected to the VCC pins. This


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PDF ONET1191V SLLS750A 20-Pin 10-Gigabit OC-192/SDH STM-64
2012 - CIRCUIT DIAGRAM APC UPS 700

Abstract: APC UPS CIRCUIT DIAGRAM UPS APC 800 CIRCUIT UPS APC CIRCUIT ups 800 APC UPS 800 CIRCUIT DIAGRAM UPS APC CIRCUIT diagram APC UPS CIRCUIT layout APC BR 800 IN UPS CIRCUIT APC UPS 700 APC BR 600 IN UPS
Text: , 11, 17, GND 20, 23, EP 9 10 12 13 DIN+ DIN­ RZTC MONB 14 MONP Analog-out 15 16 18 19, 24 , Small Footprint 4mm × 4mm 24 Pin RoHS Compliant QFN Package APPLICATIONS · · · · · 10 Gigabit , 8 Bit Register 8 Bit Register SDA SCK DIS 10 Bit Register 10 Bit Register 8 Bit Register 8 Bit , to Digital Conversion ADR0 ADR1 ADR1 8 Bit Register 10 Bit Register ADR2 2-Wire Interface , RZTC RZTC Figure 1. Simplified Block Diagram of the ONET1141L PACKAGE The ONET1141L is


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PDF ONET1141L 145mA OC-192/SDH CIRCUIT DIAGRAM APC UPS 700 APC UPS CIRCUIT DIAGRAM UPS APC 800 CIRCUIT UPS APC CIRCUIT ups 800 APC UPS 800 CIRCUIT DIAGRAM UPS APC CIRCUIT diagram APC UPS CIRCUIT layout APC BR 800 IN UPS CIRCUIT APC UPS 700 APC BR 600 IN UPS
2005 - Not Available

Abstract: No abstract text available
Text: PACKAGE (TOP VIEW) 20 19 18 17 DIS RZTC TS SCK SDA 1 2 3 4 5 10 6 7 8 9 16 15 14 , 4 5 6, 9, 14 7 8 10 11 NAME DIS RZTC TS SCK SDA VCC DIN+ DIN­ FLT MONB TYPE CMOS-in Analog , BIASC PDP FAULT BIAS MONB BIAS MONB MONP MD COMP RZTC TS RZTC TS Bias Current , time from clock rising edge to data rising edge at STOP 50 100 10 50 10 10 DESCRIPTION Time required from data falling edge to clock falling edge at START MIN 10 10 10 MAX UNIT ns ns ns ns ns ns ns ns ns


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PDF ONET4291VA SLLS674 20-Pin ONET4291VA
2005 - Not Available

Abstract: No abstract text available
Text: PACKAGE (TOP VIEW) 20 19 18 17 DIS RZTC TS SCK SDA 1 2 3 4 5 10 6 7 8 9 16 15 14 , 4 5 6, 9, 14 7 8 10 11 NAME DIS RZTC TS SCK SDA VCC DIN+ DIN­ FLT MONB TYPE CMOS-in Analog , BIASC PDP FAULT BIAS MONB BIAS MONB MONP MD COMP RZTC TS RZTC TS Bias Current , time from clock rising edge to data rising edge at STOP 50 100 10 50 10 10 DESCRIPTION Time required from data falling edge to clock falling edge at START MIN 10 10 10 MAX UNIT ns ns ns ns ns ns ns ns ns


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PDF ONET4291VA SLLS674 20-Pin ONET4291VA
2008 - s0319

Abstract: B0285 S0320 VQFN ONET1101L SDD11 STM-64 SLLS883
Text: 16 VCC EP 12 MONB RZTC 13 11 6 GND SDA 10 MONP DIN­ 14 9 , -Pin, RoHS-compliant QFN Package APPLICATIONS · · · · · 10 Gigabit Ethernet Optical Transmitters 8x and 10x , Register SDA Settings 10 Bit Register 10 Bit Register BIAS Bias MONB Current MONP , Control Logic Power-On Reset Band-Gap and Analog References RZTC BIAS MONB MONP FLT PD COMP RZTC B0285-01 Figure 1. Block Diagram of the ONET1101L PACKAGE The ONET1101L is


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PDF ONET1101L SLLS883 24-Pin, s0319 B0285 S0320 VQFN ONET1101L SDD11 STM-64 SLLS883
2006 - BLM15HG102SN1D

Abstract: s0212 15-V ONET1191V STM-64 P0031-04
Text: RZTC 15 PD 14 COMP 2 TS 3 13 MONP EP 6 7 8 9 10 GND FLT 11 , 4-mm, 20-Pin QFN Package · · · 10 -Gigabit Ethernet Optical Transmitters 8× and 10 × Fibre , RZTC RZTC BGV BGV TS TS ENA OLE BIASC Bias Current Generator and , edge to clock falling edge at START 10 CLKR, DTAR Clock and data rise time Clock and data , edge 10 ns DTAWT Data wait time Minimum time from data falling edge to data rising edge


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PDF ONET1191V SLLS750A 20-Pin 10-Gigabit BLM15HG102SN1D s0212 15-V ONET1191V STM-64 P0031-04
2006 - Not Available

Abstract: No abstract text available
Text: 10 -Gigabit Ethernet Optical Transmitters 8× and 10 × Fibre Channel Optical Transmitters SONET OC , OLE BIASC 8 PDP FAULT Analog Reference RZTC BGV TS RZTC BGV TS ENA OLE BIASC , data rising edge at STOP 50 100 10 50 10 10 DESCRIPTION Time required from data falling edge to clock falling edge at START MIN MAX 10 10 10 UNIT ns ns ns ns ns ns ns ns ns REGISTER MAPPING The register , ONET1191V VCSEL driver is supplied by a single 3.3-V ± 10 % supply voltage connected to the VCC pins. This


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PDF ONET1191V SLLS750A 20-Pin 10-Gigabit OC-192/SDH STM-64
2005 - SLLS674

Abstract: No abstract text available
Text: PACKAGE (TOP VIEW) 20 19 18 17 DIS RZTC TS SCK SDA 1 2 3 4 5 10 6 7 8 9 16 15 14 , 4 5 6, 9, 14 7 8 10 11 NAME DIS RZTC TS SCK SDA VCC DIN+ DIN­ FLT MONB TYPE CMOS-in Analog , BIASC PDP FAULT BIAS MONB BIAS MONB MONP MD COMP RZTC TS RZTC TS Bias Current , time from clock rising edge to data rising edge at STOP 50 100 10 50 10 10 DESCRIPTION Time required from data falling edge to clock falling edge at START MIN 10 10 10 MAX UNIT ns ns ns ns ns ns ns ns ns


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PDF ONET4291VA SLLS674 20-Pin ONET4291VA SLLS674
2008 - 10 Gbps Modulator Driver

Abstract: S0319
Text: 16 BIAS GND VCC COMP MONP MONB EP 4 5 6 15 14 13 DIN+ 10 GND GND RZTC FLT , DESCRIPTION PIN 1 3, 16, 19, 24 4 5 6 7 9 10 12 13 NAME PD VCC DIS SCK SDA FLT DIN+ DIN­ RZTC MONB TYPE , APPLICATIONS · · · · · 10 Gigabit Ethernet Optical Transmitters 8x and 10x Fibre Channel Optical Transmitters , Register 10 Bit Register 10 Bit Register 8 Bit Register 7 Bit + Sign 3 Bit + Sign 1 Bit Settings Settings , Logic Band-Gap and Analog References RZTC RZTC B0285-01 Figure 1. Block Diagram of the


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PDF ONET1101L SLLS883 24-Pin, OC-192/SDH STM-64 10 Gbps Modulator Driver S0319
2008 - Not Available

Abstract: No abstract text available
Text: Footprint 4mm × 4mm 24-Pin, RoHS-compliant QFN Package APPLICATIONS • • • • • 10 , SCK SCK DIS DIS 8 Bit Register Settings 4 Bit Register SDA Settings 10 Bit Register 10 Bit Register BIAS Bias MONB Current MONP Generator FLT and PD APC COMP IMOD , and Analog References RZTC BIAS MONB MONP FLT PD COMP RZTC B0285-01 Figure 1 , 18 BIAS GND 2 17 GND VCC 3 16 VCC EP 12 MONB RZTC 13 11


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PDF ONET1101L SLLS883 24-Pin,
2007 - LQW15ANR10J00

Abstract: bgv DIODE BLM15HG102SN1D BLM15HD102SN1 ONET8501V SDD11 STM-64 vcsel receiver
Text: Small Footprint 4mm × 4mm 20 Pin RoHS compliant QFN Package APPLICATIONS · · · · · 10 , Current MONP Generator FLT & APC PD COMP Cp Adjust RZTC Band-Gap & Analog References BGV Power-On Reset Temperature Sensor TS BIAS MONB MONP FLT PD COMP RZTC BGV TS Figure , 17 16 15 PD DIS 1 RZTC 2 14 COMP ONET 8501V 20 Pin QFN TS 3 13 MONP 6 7 8 9 10 GND FLT 11 BGV DIN- SDA 5 DIN+ 12 MONB GND SCK 4 TERMINAL


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PDF ONET8501V SLLS837B LQW15ANR10J00 bgv DIODE BLM15HG102SN1D BLM15HD102SN1 ONET8501V SDD11 STM-64 vcsel receiver
2007 - bgv DIODE

Abstract: No abstract text available
Text: 16 BIAS VCC VCC DIS 1 RZTC 2 TS 3 SCK 4 SDA 5 15 PD ONET 8501V 20 Pin QFN 14 COMP 13 MONP 12 MONB 11 BGV 6 7 8 9 10 GND TERMINAL FUNCTIONS TERMINAL PIN NO. 1 2 3 4 5 7 8 10 11 12 NAME DIS RZTC TS SCK SDA DIN+ DIN­ FLT BGV MONB Analog-out TYPE Digital-in , RoHS compliant QFN Package APPLICATIONS · · · · · 10 Gigabit Ethernet Optical Transmitters 8x and , COMP RZTC Band-Gap & Analog References BGV Power-On Reset Temperature Sensor TS RZTC BGV TS 2


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PDF ONET8501V SLLS837B bgv DIODE
2007 - Not Available

Abstract: No abstract text available
Text: 16 BIAS VCC VCC DIS 1 RZTC 2 TS 3 SCK 4 SDA 5 15 PD ONET 8501V 20 Pin QFN 14 COMP 13 MONP 12 MONB 11 BGV 6 7 8 9 10 GND TERMINAL FUNCTIONS TERMINAL PIN NO. 1 2 3 4 5 7 8 10 11 12 NAME DIS RZTC TS SCK SDA DIN+ DIN­ FLT BGV MONB Analog-out TYPE Digital-in , RoHS compliant QFN Package APPLICATIONS · · · · · 10 Gigabit Ethernet Optical Transmitters 8x and , COMP RZTC Band-Gap & Analog References BGV Power-On Reset Temperature Sensor TS RZTC BGV TS 2


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PDF ONET8501V SLLS837B
2005 - Not Available

Abstract: No abstract text available
Text: PDP FAULT PDP FAULT FLT 8 RZTC TS RZTC TS Analog Reference ENA OLE , -Wire Interface Timing Diagram Table 1. 2-Wire Interface Timing PARAMETER DESCRIPTION MIN MAX 10 , setup time Minimum time from data rising edge to clock rising edge 10 ns DTAWT Data wait , Minimum time from clock falling edge to data falling edge 10 ns STOPSTP STOP setup time Minimum time from clock rising edge to data rising edge at STOP 10 ns 10 ns 10 ns


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PDF ONET4291VA SLLS674 20-Pin
Supplyframe Tracking Pixel