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Not Available

Abstract: No abstract text available
Text: SAM S UN G E L E C T R O N I C S INC b?E D 7^4145 DQlb'i74 b32 SP1GK CMOS MASK ROM KM23C2100 2M-Bit (256K x 8/128K x 16) CMOS MASK ROM FEATURES GENERAL DESCRIPTION • Switchable organization Byte Mode: 262,144 x 8 Word Mode: 131, 072x16 • Fast access time: 150ns (max.) • Supply voltage: single + 5V • Current consumption Operating: 50mA (max.) Standby: 100^A (max.) • Fully static operation • All inputs and outputs TTL compatible • Three state outputs • Polarity


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PDF KM23C2100 8/128K 072x16 150ns 40-pin KM23C2100 KM23C2100)
27C240-200V10

Abstract: UPD27C4096DZ-15 UPD27C4096DZ-12 27C4096 MBM27C4096-15 HN27C4096H-85 HM27C4096G-15 HM27C4096G-12 HM27C4096G-10 HM27C4096CC-15
Text: 0.8 2.0 14 0. 45/2.1 2. 4/0. 4 16 -163- 4M n/CMOS UV-EPROM (131, 072X16 ) 27C4096 Vppm |40| Vdu


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PDF 27C240-I50V10 27C240-200V10 1M27C4096CC-10 HM27C4096CC-12 HM27C4096CC-15 16bitCPUi-; 27C4096 UPD27C4096DZ-15 UPD27C4096DZ-12 MBM27C4096-15 HN27C4096H-85 HM27C4096G-15 HM27C4096G-12 HM27C4096G-10
Not Available

Abstract: No abstract text available
Text: . iÖ J T (131, 072x16 )/ (262,144x8) Y Buffers and Decoder Ao — This device operates


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PDF KM23C2100A ib414E 256Kx8/128Kx 100ns 50/iA 40-pln KM23C2100A KM23C2100A)
23c2100

Abstract: KM23C2
Text: Decoder M EM O RY CELL MATRIX (131, 072x16 )/ (262,144 x 8) Ao - A-1 - Y Buffers and Decoder


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PDF KM23C2 8/128K 100ns 40-pln 23C2100A KM23C210QA-12 KM23C2100A-15 KM23C2100A KM23C2100A) 23c2100
48-pin TSOP I flash memory

Abstract: No abstract text available
Text: mA MACHONK. INC. u ijw v y IN/IX28F2100 SM-BITISBBK x 8] CMOS FLASH MEMORY FEA T U R ES 262,144x8/131, 072x16 SWitchable Fast access time: 90/120/150ns Low power consumption - 50mA maximum active current - 100 nA maximum standby current Programming and erasing voltage 12V ± 5% Command register architecture - Byte/Word Programming (50 ns typical) - Chip Erase (1 sec typical) - Auto chip erase 30 sec typical (including preprogramming time) - Block Erase (16384 bytes by 16 blocks or 8,912 words by 16


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PDF IN/IX28F2100 144x8/131 072x16 90/120/150ns A0-A16 Q0-Q14 Q15/A-1 48-pin TSOP I flash memory
Not Available

Abstract: No abstract text available
Text: MROM LH532600 MEMORY MATRIX (26 2 ,1 4 4 x8 ) (13 1, 072x16 ) CE BUFFER TIMING GENERATOR


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PDF LH532600 40-pin, 600-mil 525-mil 48-pin, 8/128K 48TSOP
Not Available

Abstract: No abstract text available
Text: u s e r o p tio n m o d e . FUNCTIONAL BLOCK DIAGRAM B u ffers and (131, 072x16 )/ D e c o


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PDF KM23C2100 8/128K 150ns 2100F
48-PIN

Abstract: A12C A15C LH532000B-1
Text: o o < MEMORY MATRIX (262,144 x 8) (131, 072x16 ) COLUMN SELECTOR TIMING GENERATOR SENSE AMPLIFIER


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PDF LH532000B-1 8/128K 40-pin DIP/40-pin 40-pin, 600-mil 525-mil 48-pin, 12x18 48-PIN A12C A15C LH532000B-1
Not Available

Abstract: No abstract text available
Text: , 072X16 )/ (2 6 2 ,1 4 4 x 8 ) a 2c A lC AoC C E/C E C Vss C B u ffe rs SEN SE AMP DATA O ÿT


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PDF KM23C2100H 8/128K 100ns 40-pin 44-pin KM23C2100H KM23C2100H) KM23C2100HFP)
1998 - HY57V41610

Abstract: No abstract text available
Text: HY57V41610 2 Banks x 128K x 16 Bit Synchronous DRAM DESCRIPTION PRELIMINARY The Hyundai HY57V41610 is a 4,194,304 bits CMOS Synchronous DRAM. HY57V41610 is organized as 2 banks of 131, 072x16. HY57V41610 is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL


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PDF HY57V41610 HY57V41610 072x16. 1SD10-03-FEB98.
Not Available

Abstract: No abstract text available
Text: $, and 35ns • 131,072 x 128 bit memory array field • 131, 072x16 bit Data ECC field • 131,072x7


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PDF EDI8F176128C 128Kx176 EDI8F176128C 072x176bitmemory R4000 EDI8F176128C20MXC EDI8F176128C25MXC EDI8F176128C35MXC
23c2100

Abstract: No abstract text available
Text: LI L IL IL I 1^ ^ ^ ^ ^ CO (·) (O co co 2 2 ? Z OCDCO S (Olí) 34 (131, 072x16 )1 (26 2,1 44 x8


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PDF KM23C2100 8/128K 150ns 40-pin 44-pin KM23C2100 KM23C2100) KM23C2100FP) 23c2100
HY512264

Abstract: HY512264TC
Text: "H Y U N D A I DESCRIPTION The HY512264 Series is a high perform ance CM O S fast dynam ic RAM organized 131, 072x16 -b it config-uration. Independent read and w rite o f upper and low er byte is controlled by 2 separate /C A S inputs. Refresh control is provided through /RAS -only, /C AS before-/R AS, hidden refresh and se lf refresh modes. M ultiplexed address inputs p erm it the HY512264 to be packaged in a 400m il 40pin SO J and 40/44pin TSO P-II and reverse TS O P -II packages. HY512264 Series


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PDF HY512264 072x16 40pin 40/44pin HY512264JC HY512264LJC HY512264SLJC HY512264TC
ZJ 37

Abstract: T22J
Text: ( « « Y U H P IU > DESCRIPTION - -· HY57V41610 PRELIMINARY 2 Banks x 128K x 16 Bit Synchronous DRAM The Hyundai HY57V41610 is a 4,194,304 bits CMOS Synchronous DRAM. HY57V41610 is organized as 2 banks of 131, 072x16. HY57V41610 is offering fully synchronous operation referenced to a positive edge dock. All Inputs and outputs are synchronized with the rising edge of the clock Input The data paths are internally pipelined to achieve very high band width. All input and output


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PDF HY57V41610 HY57V41610 072x16. ZJ 37 T22J
Not Available

Abstract: No abstract text available
Text: /00-1/015 MEMORY ARRAY 131, 072x16 t C C 10-2 Integrated S ilicon Solution, Inc


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PDF 40-pin IS41C16128 16-bit ThelS41C16128 OlfittJ/97 SR9641CT6128 IS41C16128 IS41C16128-40K IS41C16128-40T
LRS1339

Abstract: No abstract text available
Text: memory organized as 1,048,576X16 bit flash memory and 131, 072X16 bit static RAM in one package


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PDF LRS1339 S1339) LRS1339
MX28F2100T

Abstract: No abstract text available
Text: INDEX PRELIMINARY MX28F2100T 2M-BIT [256K x 8/128K x 16] CMOS FLASH MEMORY FEATURES · 262,144x8/131, 072x16 switchable · Fast access time: 70/90/120ns · Low power consumption ­ 50mA maximum active current ­ 100 uA maximum standby current · Programming and erasing voltage 12V ± 7% · Command register architecture ­ Byte/Word Programming (50 us typical) ­ Auto chip erase 5 sec typical (including preprogramming time) ­ Block Erase (Any one from 5 blocks:16K-Byte x1, 8K-Byte x2, 96K-Byte x1, and 128K


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PDF MX28F2100T 8/128K 144x8/131 072x16 70/90/120ns 16K-Byte 96K-Byte 128K-Byte PM0383 MX28F2100T
TCS 5513

Abstract: MX28F2100TTC
Text: i\/!X2BF21 OOT 2M-BITC256K x 8 / 1 2 8 K x 1 6 ) CMOS FLASH MEMORY FEATURES · 262,144x8/131, 072x16 switchable · Fast access time: 70/90/120ns · Low power consumption - 50mA maximum active current - lOOnAmaximum standby current · Programming and erasing voltage 12V + 7% · Command register architecture - Byte/Word Programming (50ns typical) - Auto chip erase 5 sec typical (including preprogramming time) - Block Erase (Any one from 5 blocks: 16K-Byte x1, 8 K-Byte x2, 96K-Byte x1, and 128K-Byte x1) - Auto Erase with


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PDF X2BF21 2M-BITC256K 144x8/131 072x16 70/90/120ns 16K-Byte 96K-Byte 128K-Byte 100mA XX90H TCS 5513 MX28F2100TTC
block diagram for automatic room power control layout

Abstract: 28F2100B
Text: M X 2 8 F 2 1 OOB 2 M -B IT (2 5 6 K X 8 / 1 2 8 K X T6 ) CM OS FLASH M EM O R Y FEATURES · 262,144x8/131, 072x16 switchable · Fast access time: 70/90/120ns · Low power consumption - 50mA maximum active current - 100[iAmaximum standby current · Programming and erasing voltage 12V + 7% · Command register architecture - Byte/Word Programming (50jas typical) - Auto chip erase 5 sec typical (including preprogramming time) - Block Erase (Any one from 5 blocks: 16K-Byte x1, 8K-Byte x2, 96K-Byte x1, and 128K-Byte x


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PDF 144x8/131 072x16 70/90/120ns 50jas 16K-Byte 96K-Byte 128K-Byte 100mA X28F2100B block diagram for automatic room power control layout 28F2100B
Not Available

Abstract: No abstract text available
Text: \p M E u m m h M Y IW K IC M X 2 8 F 2 1 OOB 2M-BIT(256K x 8/ 1 28 K x 1 6) CM OS FLASH M EM ORY FEATURES • 262,144x8/131, 072x16 switchable • Fast access time: 70/90/120ns • Low power consumption - 50mA maximum active current - 10OnAmaximum standby current • Programming and erasing voltage 12V ± 7% • Command register architecture - Byte/Word Programming (50|as typical) - Auto chip erase 5 sec typical (including preprogramming time) - Block Erase (Any one from 5 blocks


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PDF 144x8/131 072x16 70/90/120ns 10OnAmaximum 16K-Byte 96K-Byte 128K-Byte 44-PIN 48-PIN
h5ra

Abstract: NTE 5432
Text: IV IX 2 S F 2 1 O O B 2M BIT[256K x 8 / 1 28K x 1 6} CMOS FLASH MEMORY FEA TU RES 262,144x8/131, 072x16 switchable Fast access time: 70/90/120ns Low power consumption - 50mA maximum active current - 100nAmaximum standby current Programming and erasing voltage 12V ± 7% Command register architecture - Byte/Word Programming (5 0 ns typical) - Auto chip erase 5 sec typical (including preprogramming time) - Block Erase (Any one from 5 blocks: 16K-Byte x1, 8K-Byte x2, 96K-Byte x1, and 128K-Byte x1) -


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PDF 144x8/131 072x16 70/90/120ns 100nAmaximum 16K-Byte 96K-Byte 128K-Byte 100mA Q0-Q15 XX90H h5ra NTE 5432
1998 - MX28F2100T

Abstract: MX28F2100TTC90
Text: Introduction Selection Guide PRELIMINARY MX28F2100T 2M-BIT(256K x 8/128K x 16) CMOS FLASH MEMORY FEATURES · 262,144x8/131, 072x16 switchable · Fast access time: 70/90/120ns · Low power consumption ­ 50mA maximum active current ­ 100 µAmaximum standby current · Programming and erasing voltage 12V ± 7% · Command register architecture ­ Byte/Word Programming (50 µs typical) ­ Auto chip erase 5 sec typical (including preprogramming time) ­ Block Erase (Any one from 5 blocks:16K-Byte x1


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PDF MX28F2100T 8/128K 144x8/131 072x16 70/90/120ns 16K-Byte 96K-Byte 128K-Byte MX28F2100T MX28F2100TTC90
28F2100

Abstract: block diagram for automatic room power control MX28F2100B 28F2100B-70
Text: PRELIMINARY MX28F2100B 2M-BIT [256K x 8/128K x 16] CMOS FLASH MEMORY FEATURES · 262,144x8/131, 072x16 switchable · Fast access time: 70/90/120ns · Low power consumption ­ 50mA maximum active current ­ 100uA maximum standby current · Programming and erasing voltage 12V ± 7% · Command register architecture ­ Byte/Word Programming (50 us typical) ­ Auto chip erase 5 sec typical (including preprogramming time) ­ Block Erase (Any one from 5 blocks:16K-Byte x1, 8K-Byte x2, 96K-Byte x1, and 128K


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PDF MX28F2100B 8/128K 144x8/131 072x16 70/90/120ns 100uA 16K-Byte 96K-Byte 128K-Byte PM0382 28F2100 block diagram for automatic room power control MX28F2100B 28F2100B-70
1998 - MX28F2100B

Abstract: No abstract text available
Text: Introduction Selection Guide PRELIMINARY MX28F2100B 2M-BIT(256K x 8/128K x 16) CMOS FLASH MEMORY FEATURES · 262,144x8/131, 072x16 switchable · Fast access time: 70/90/120ns · Low power consumption ­ 50mA maximum active current ­ 100 µAmaximum standby current · Programming and erasing voltage 12V ± 7% · Command register architecture ­ Byte/Word Programming (50 µs typical) ­ Auto chip erase 5 sec typical (including preprogramming time) ­ Block Erase (Any one from 5 blocks:16K-Byte x1


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PDF MX28F2100B 8/128K 144x8/131 072x16 70/90/120ns 16K-Byte 96K-Byte 128K-Byte MX28F2100B
Not Available

Abstract: No abstract text available
Text: 2 M -B IT (2 5 6 K x 8 / 1 2 8 K x 1 6 ) C M O S F L A S H M E M O R Y FEATURES • 262,144x8/131, 072x16 switchable • Fast access time: 70/90/120ns • Low power consumption - 50mA maximum active current - 10OnAmaximum standby current • Programming and erasing voltage 12V ± 7% • Command register architecture - Byte/Word Programming (50|as typical) - Auto chip erase 5 sec typical (including preprogramming time) - Block Erase (Any one from 5 blocks:16K-Byte x1


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PDF 144x8/131 072x16 70/90/120ns 10OnAmaximum 16K-Byte 96K-Byte 128K-Byte MX28F2100T 44-PIN 48-PIN
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