The Datasheet Archive

Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
5962-8876002PA 5962-8876002PA ECAD Model Texas Instruments Dual Precision Operational Amplifier 8-CDIP -55 to 125
5962-9065002PA 5962-9065002PA ECAD Model Texas Instruments High Efficiency Regulator Controller 8-CDIP -55 to 125
5962-8771002PA 5962-8771002PA ECAD Model Texas Instruments Dual General Purpose Bipolar Operational Amplifier 8-CDIP -55 to 125
TVP3026-175CPCE TVP3026-175CPCE ECAD Model Texas Instruments 1280X1024 PIXELS PALETTE-DAC DSPL CTLR, PQFP160, PLASTIC, QFP-160
LM2502SQ/NOPB LM2502SQ/NOPB ECAD Model Texas Instruments Mobile Pixel Link (MPL) Display Interface Serializer and Deserializer 40-WQFN -30 to 85
TVP3026-230CPCE TVP3026-230CPCE ECAD Model Texas Instruments 1280X1024 PIXELS PALETTE-DAC DSPL CTLR, PQFP160, PLASTIC, QFP-160

002pA/pixel Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
72x096

Abstract: No abstract text available
Text: No file text available


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PDF CWN-HK-21. 72x096
siliconix 3n163

Abstract: No abstract text available
Text: No file text available


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PDF 3N163/164_ 3N163 3N164 3N163/164 P-37404--Rev. 3N163/164 siliconix 3n163
7S1 zener diode

Abstract: CH8398 STG1703 gi 9440 diode stg170
Text: CH8398 CHRONTEL True-Color ChronDAC™ with 16-bit Interface Features 16-bit pixel bus , frequencies, and the memory clock PLL provides 8 programmable frequencies. The CH8398 pixel bus is 16 bits , with higher resolution while maintaining a lower pixel transfer rate. Upon power up, the video clock is , .4-68 Pixel Data, BLANK* Control Signal, and Mode Switch Timing.4-68 DAC Output , Name / Description 1.4, 23, 25, 52-59, 64-67 P12, P13, P14, P15, P0-P7, P8-P11 I Pixel . TTL compatible


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PDF CH8398 16-bit ATT20C498 CH8398 7S1 zener diode STG1703 gi 9440 diode stg170
MP2481

Abstract: SW-SPDT DATA13 PIN91 cbc 182 HDA570ST-V j6 con4 PQFP208 PIN163 AT45DB161
Text: Pin147 UART2 RTS Pin145 VCORE 1.2V UART2 SCK Pin143 PIXEL DATA23 Pin142 PIXEL DATA22 Pin141 PIXEL , DATA11 Pin130 DATA12 Pin129 DATA13 Pin128 DATA14 Pin127 DATA15 Pin126 SDRAM DQM0 Pin125 PIXEL , Z1 5V 4 PC Pin52 Hsync / LP Pin53 Vsync / FO Pin54 PIXEL DATA2 Pin74 PIXEL DATA3 Pin78 PIXEL DATA4 Pin80 PIXEL DATA5 Pin81 PIXEL DATA6 Pin82 PIXEL DATA7 Pin83 PIXEL DATA 10 Pin23 PIXEL DATA 11 Pin25 PIXEL DATA12 Pin69 PIXEL DATA13 Pin71 PIXEL DATA14 Pin73 PIXEL DATA15 Pin75 PIXEL


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PDF HDA570ST-V 3036-0007-01HT 0309BR-B1K 0309CC-B1K 33-pin 1000mA MP2481 SW-SPDT DATA13 PIN91 cbc 182 j6 con4 PQFP208 PIN163 AT45DB161
1999 - EK9840

Abstract: 225NS BVOS2 ek98
Text: databus. End of conversion signal from ADC indicating that new pixel data is available. Output enable pin , PH2 RS OS CDS SPL CCLK CD0 | CD7 /EOC DD0 | DD11 (/RD tied low) Pixel N-6 Pixel N-5 Pixel N-4 Pixel N-3 Pixel N-2 Pixel N-1 Pixel N Pixel N+1 Pixel N+2 Pixel N-1 Pixel N-1 Pixel N-1 Pixel N Pixel N Pixel N Pixel N+1 Pixel N+1 Pixel N+1 Pixel N+2 Pixel N+2 Pixel N+2 Fig 1.2 1-Line Scan Pixel Pipeline Timing , CDS SPL CCLK CD0 | CD7 /EOC DD0 | DD11 R:N-2 G:N-2 B:N-2 R:N-1 G:N-1 Pixel N-1 Pixel N-1 Pixel N


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PDF 36-Bit 12-bit EK9840 EK9840 DD0-DD11 LM4041-1 EK68512J-15 225NS BVOS2 ek98
Not Available

Abstract: No abstract text available
Text: 100 MHz applied to this pin provides the reference clock for the programmable pixel and system clock , programming values for the pixel PLL, Divided Dot Clock. The output of the . pixel PLL, divided by 1, 2, 4, 8 or 16. The divide factor is undeE:;regis.ter coStarol, In 24 BPP Packed pixel mode the SCLK signal can be seleefcedfor this output instead of the divided pixel PLL output, under register control. This output can be instated under register control. Serial Clock. A'divideekversion of the pixel PLL, where


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PDF RGB526/RGB526DB
gi 9440 diode

Abstract: CH8398 STG1703 7S1 zener diode
Text: CH8398 CHRONTEL True-Color ChronDAC™ with 16-bit Interface Features 16-bit pixel bus interface , frequencies, and the memory clock PLL provides 8 programmable frequencies. The CH8398 pixel bus is 16 bits , with higher resolution while maintaining a lower pixel transfer rate. Upon power up, the video clock is , .4-68 MPU Write Timing .4-68 Pixel Data, BLANK , P12, P13, P14, P15, P0-P7, P8-P11 I Pixel . TTL compatible. Pixel data is latched on the rising edge of


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PDF CH8398 16-bit ATT20C498 D0023E gi 9440 diode STG1703 7S1 zener diode
Not Available

Abstract: No abstract text available
Text: Output P = Power Supply Pin # Type 1 GND P Ground 2 PC O Pixel Clock 3 Hsync O Hsync Signal 4 Vsync O Vsync Signal 5 GND P Ground 6 Pixel Data 2 O R2 7 Pixel Data 3 O R3 8 Pixel Data 4 O R4 9 Pixel Data 5 O R5 10 Pixel Data 6 O R6 11 Pixel Data 7 O R6 12 GND 13 Pixel Data 10 O G2 14 Pixel Data 11 O G3 15 Pixel Data 12 O G4 16


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PDF 640x480 AGB75LC04-QU-E 32megabit 64megabit
ups052

Abstract: AGB75LC04-QU-E GRAPHICAL LCD interfacing with ARM7TDMI PIN AT45DB321D JESD97 MO-205 MS-029 AGB75LC04 multi Touch Controller land pattern PQFP 132
Text: displays up to 24 bits per pixel · USB 2.0, TWI, UART, and SPI Interfaces · Power Management Controller , Y+ Touch X+ A2D LCD Signals Pixel Data 0 - 23 Pixel Clock / DCLK Frame Clock Active High , Touch panel X+ An. Input A2D or GPIO Output LCD Pixel Data LCD Drive Signal. LCD crystal , 3.3V DATA26 Reset DATA25 N/C DATA24 CommU RXD Pixel Data 8 CommU TXD Pixel Data 9 VCORE 1.2V Pixel Data 10 GND Pixel Data 11 Program Mode TPCal ADDR6 ADDR7 VCC 3.3V ADDR8 ADDR9 N/C


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PDF AGB75LC04-QU-E AGB75LC04-BG-E ups052 AGB75LC04-QU-E GRAPHICAL LCD interfacing with ARM7TDMI PIN AT45DB321D JESD97 MO-205 MS-029 AGB75LC04 multi Touch Controller land pattern PQFP 132
Bt445

Abstract: ECL IC NAND
Text: pixel clock frequency. The second PLL oper ates from the same crystal or oscillator input as the pixel , CPU system, SCSI, and Ethernet clocks. The Bt445's input pixel port can be software-configured to be , to 60 pins. A pixel display order can be selected to start from the lower-numbered bits of the input pixel port (LSB unpacking) or from the higher-numbered bits (i.e., the pixel port width, MSB un packing , fully programmable pixel widths (one to 32 bits per pixel , any integer value). The only restrictions are


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PDF Bt445 Bt458 MCLK20 MCLK25 Bt445 ECL IC NAND
1999 - LIS-1024

Abstract: linear cmos IMAGE SENSOR LIS1024 LIS-1024A-LG LIS-1024D-DE CCD Linear Image Sensor
Text: Dynamic Pixel ResetTM or DPR, Frame Reset, and non-destructive. In DPR mode, each pixel is reset as it is read, guaranteeing each pixel integrates for the same amount of time, making the LIS-1024 ideal for , exceptional control over exposure time and pixel read out. A key feature when compared with traditional CCD , frequency equal to the desired pixel read rate, a reset mode selection, and an external reset to initiate , sensor MODEL LIS-1024 ARRAY SIZE 1 x 1024 PIXEL SIZE h x w(pitch) 125u X 7.8u LIS


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PDF LIS-1024 LIS-1024 PDS0001 linear cmos IMAGE SENSOR LIS1024 LIS-1024A-LG LIS-1024D-DE CCD Linear Image Sensor
Not Available

Abstract: No abstract text available
Text: Passive and Active displays up to 24 bits per pixel • USB 2.0, TWI, UART, and SPI Interfaces â , A2D or GPIO AGB75LC04 Datasheet 2.4 - 0112 LCD Signals Pixel Data 0 - 23 Output Pixel , Output Output I/O I/O I/O Output Input Output Input Output Input Output   LCD Pixel Data , 3.3V DATA26 Reset DATA25 N/C DATA24 CommU RXD Pixel Data 8 CommU TXD Pixel Data 9 VCORE 1.2V Pixel Data 10 GND Pixel Data 11 Program Mode TPCal ADDR6 ADDR7 VCC 3.3V ADDR8 ADDR9 N/C


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PDF AGB75LC04-QU-E AGB75LC04-BG-E
UPS052

Abstract: TXD LCD TFT 1.44" 27 pin atmel 0609 IS42S32200E IS42S32200E-6TL TCA 700 y AGB75LC04 AT45DB321D JESD97 MO-205
Text: displays up to 24 bits per pixel · USB 2.0, TWI, UART, and SPI Interfaces · Power Management Controller , Signals Pixel Data 0 - 23 Output Pixel Clock / DCLK Output Frame Clock Output Hsync , Output Input Output LCD Pixel Data LCD Drive Signal. LCD crystal polarization clock. Clock , DATA29 RSVD DATA28 GND DATA27 VCC 3.3V DATA26 Reset DATA25 N/C DATA24 CommU RXD Pixel Data 8 CommU TXD Pixel Data 9 VCORE 1.2V Pixel Data 10 GND Pixel Data 11 Program Mode TPCal ADDR6


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PDF AGB75LC04-QU-E AGB75LC04-BG-E UPS052 TXD LCD TFT 1.44" 27 pin atmel 0609 IS42S32200E IS42S32200E-6TL TCA 700 y AGB75LC04 AT45DB321D JESD97 MO-205
Not Available

Abstract: No abstract text available
Text: p in provides th e reference clock fo r th e p ro g ra m m a b le pixel and system clock P L L s. W , ivid e fa cto r is u n d e r re g is te r c o n tro l. In 24 BPP Packed pixel m ode th e S C L K sig n , id th and th e pixel fo rm a t (b its per pixel ). S C L K is equal to th e pixe l P L L o u tp u t w , ,91, 5,4,153,152,151, 111,110,109,108,107 61,60,59,58,57,56,55,54 Pixel d a ta in fro m V R A M s , da ta in o r V G A pixel d a ta in. W h e n th e V R A M size is 64 o r 32 (n o t 128), th e n these


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PDF RGB528A PIX156)
j637

Abstract: plasma 640x480 "FRC" RLF100-11/12/fujitsu plasma 640x480
Text: ·UH M · IHM H · ·· ·····MM · ·· ··· · m u n ir a Flat Panel Pixel Timing This section , (DD) - 8 pixels/clock, 1 bit/ pixel Dual panel-Single drive (PS) -1 pixel /clock, 6 bits/ pixel - 2 pixels/clock, 4 bits/ pixel - 4 pixels/clock, 2 bits/pixels - 8 pixels/clock, 1 bit/ pixel Single panel-Single drive (SS) -1 pixel /clock, 6 bits/ pixel - 2 pixels/clock, 4 bits/ pixel - 4 pixels/clock, 2 bits/pixels - 8 pixels/clock, 1 bit/ pixel Single panel-Single drive (SS) Color - 2 2/3 pixels/clock, 1 bit


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PDF
MP2481

Abstract: SW-SPDT cbc 182 IS42S32200E 16 x 32 touch panel j6 con4 JTP 55 diode pin187 PQFP208 HDA570ST-VH
Text: Pin147 UART2 RTS Pin145 VCORE 1.2V UART2 SCK Pin143 PIXEL DATA23 Pin142 PIXEL DATA22 Pin141 PIXEL , DATA11 Pin130 DATA12 Pin129 DATA13 Pin128 DATA14 Pin127 DATA15 Pin126 SDRAM DQM0 Pin125 PIXEL , Z1 5V 4 PC Pin52 Hsync / LP Pin53 Vsync / FO Pin54 PIXEL DATA2 Pin74 PIXEL DATA3 Pin78 PIXEL DATA4 Pin80 PIXEL DATA5 Pin81 PIXEL DATA6 Pin82 PIXEL DATA7 Pin83 PIXEL DATA 10 Pin23 PIXEL DATA 11 Pin25 PIXEL DATA12 Pin69 PIXEL DATA13 Pin71 PIXEL DATA14 Pin73 PIXEL DATA15 Pin75 PIXEL


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PDF HDA570ST-VH 3036-0007-01HT 0309BR-B1K 0309CC-B1K 33-pin 1000mA MP2481 SW-SPDT cbc 182 IS42S32200E 16 x 32 touch panel j6 con4 JTP 55 diode pin187 PQFP208
p31a diode

Abstract: DIODE P31A DIODE P31B
Text: CMYK-to-RGB Conversion 100 MHz Operation 4:1-128:1 Multiplexed Pixel Port Three 256 x 9 Color Palette RAMs lx to 16x Integer Zoom Support 1, 2, 4, 8, 16, or 32 Bits per Pixel Pixel Panning Support Simultaneous Support of Zoom, Panning, and Pixel Unpacking Programmable Setup (0 or 7.5 IRE) 9-Bit DACs , graphics used in printer pre­ press and desktop color applications. The multiple pixel ports and , palette RAMs, 4:1 input multiplexing of the pixel port, bit plane masking, pro­ grammable setup (0 or


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PDF Bt496 207-pin Bt496 50-percent 10-percent t496K p31a diode DIODE P31A DIODE P31B
svi 2003

Abstract: LIS-1024 LIS-1024A-LG PDS0001 LIS-1024D-DE LIS-1024D-LG linear cmos IMAGE SENSOR svi 2003 a Silicon Video LIS1024
Text: multiple read out modes, including: NonDestructive, Dynamic Pixel ResetTM (DPR), and Frame Reset. The , device ideally suited for any high performance measurement application. In DPR mode, each pixel is reset as it is read, ensuring each pixel integrates for the same amount of time. Other reset modes are also provided to give exceptional control over exposure time and pixel read out. The Sensor also , . The only external signals required are a clock with a frequency equal to the desired pixel read rate


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PDF LIS-1024 LIS-1024 LIS-1024D-LG 16-pin PDS0001 svi 2003 LIS-1024A-LG LIS-1024D-DE LIS-1024D-LG linear cmos IMAGE SENSOR svi 2003 a Silicon Video LIS1024
2004 - SVI 2004 A

Abstract: SVI 2004 SVI 2004 C linear cmos IMAGE SENSOR LIS-1024 LIS-1024A-LG LIS-1024D-LG panavision LIS1024
Text: Charge-Coupled Devices (CCD's). The device has multiple read out modes, including: NonDestructive, Dynamic Pixel , application. In DPR mode, each pixel is reset as it is read, ensuring each pixel integrates for the same , pixel read out. The Sensor also operates over an extended power supply range of 2.8-5.0 VDC. Operation , to the desired pixel read rate, a reset mode selection, and an external reset to initiate read-out , and Control Replaces CCD systems, not just the sensor 1 x 1024 pixel resolution 7.8 micron pitch x


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PDF LIS-1024 LIS-1024 LIS-1024D-LG 16-pin PDS0001 SVI 2004 A SVI 2004 SVI 2004 C linear cmos IMAGE SENSOR LIS-1024A-LG LIS-1024D-LG panavision LIS1024
2000 - high speed CCD sensor

Abstract: EK9830 225NS BBL3 9830v
Text: from ADC indicating that new pixel data is available. Output enable pin. Taking this pin low places the , DD0 | DD9 (/RD tied low) Pixel N-6 Pixel N-5 Pixel N-4 Pixel N-3 Pixel N-2 Pixel N-1 Pixel N Pixel N+1 Pixel N+2 Pixel N-1 Pixel N-1 Pixel N-1 Pixel N Pixel N Pixel N Pixel N+1 Pixel N+1 Pixel N+1 Pixel N+2 Pixel N+2 Pixel N+2 Fig 1.2 1-Line Scan Pixel Pipeline Timing Overview 11 Revision 2.2 Dec , | CD7 /EOC DD0 | DD9 R:N-2 G:N-2 B:N-2 R:N-1 G:N-1 Pixel N-1 Pixel N-1 Pixel N-1 Pixel N Pixel N


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PDF 30-Bit 10-bit EK9830 EK9830 LM4041-1 EK68512J-15 high speed CCD sensor 225NS BBL3 9830v
Not Available

Abstract: No abstract text available
Text: generate the pixel clock frequency. The second PLL oper­ ates from the same crystal or oscillator input as the pixel PLL, and is not program­ mable. For example, it may be used to provide additional clock outputs for the CPU system, SCSI, and Ethernet clocks. The Bt445’s input pixel port can be , may be set to 60 pins. A pixel display order can be selected to start from the lower-numbered bits of the input pixel port (LSB unpacking) or from the higher-numbered bits (i.e., the pixel port width


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PDF Bt445 Bt458 Bt858 DD32522
1999 - smartasic

Abstract: I2C E2ROM SD1210 SD1200 OSD microcontroller LCD monitor OSD microcontroller vga crt monitor 24x08 ASD1210
Text: Pixel (left pixel ) SmartASIC Confidential 6 SmartASIC, Inc. R_OUT1_E R_OUT2_E R_OUT3_E , Red Even Pixel (left pixel ) Output Color Red Even Pixel (left pixel ) Output Color Red Even Pixel (left pixel ) Default HSYNC generated by ASIC (active LOW) Default VSYNC generated by ASIC (active LOW) Ground Output Color Red Even Pixel (left pixel ) Power Supply Power Supply Output Color Red Even Pixel (left pixel ) Ground Output Color Red Even Pixel (left pixel ) Output Color Red Even Pixel (left pixel


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PDF SD1210 SD1210 DAT-SD1210-1199-B DAT-SD1210-1099-A resp829 smartasic I2C E2ROM SD1200 OSD microcontroller LCD monitor OSD microcontroller vga crt monitor 24x08 ASD1210
1998 - 1df28

Abstract: 0F026 DIODE A16 nec display vga Pixel L240 Y160 Y153
Text: gray scale display: 4 gray scales (frame thinning-out) · Memory management: packed pixel system · 8 , latches 160- pixel data from the RAM. (11) Data latch (2) Latches 160- pixel data synchronously with the , the display is in four gray scales, each pixel consists of two bits. The RAM is configured with four pixels (8 pixels per word) using the packed pixel system. (1) BMODE = L Byte-unit (8 bits) access D0 D1 Pixel 1 D2 D3 Pixel 2 D4 D5 Pixel 3 D6 D7 Pixel 4 D8 D9 D10


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PDF PD16661A PD16661A PD16666 PD16661 PD16661A. 8/16-bit 1df28 0F026 DIODE A16 nec display vga Pixel L240 Y160 Y153
CH8398

Abstract: CH8398A STG1703 TQD4133 stg170
Text: CH8398A CHRONTEL True-Color ChronDAC™ with 16-bit Interface Features 16-bit pixel bus , programmable frequencies, and the memory clock PLL provides 8 programmable frequencies. The CH8398A pixel bus , support more colors with higher resolution while maintaining a lower pixel transfer rate. Upon power up , .44 Pixel Data, BLANK* Control Signal, and Mode Switch Timing.44 DAC Output , , 52-59, 64-67 P12. P13, P14, P15, P0-P7, P8-P11 I Pixel . TTL compatible. Pixel data is latched on the


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PDF CH8398A 16-bit ATT20C498 T004133 CH8398 CH8398A STG1703 TQD4133 stg170
2000 - Not Available

Abstract: No abstract text available
Text: UXGA Resolution (Output Pixel D D D D D Rates up to 165 MHz) Digital Visual Interface (DVI 1.0 , / Pixel , 16.7M Colors at 1 or 2-Pixels per Clock Laser Trimmed (50 ) Input Stage for Optimum Fixed Impedance Matching Skew Tolerant up to One Pixel Clock Cycle (High Clock and Data Jitter Tolerance) D 4x , Pixel Outputs Lowest Noise and Best Power Dissipation Using PowerPAD Packaging Advanced Technology Using , to UXGA in 24-bit true color pixel format. The TFP403 offers design flexibility to drive one or two


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PDF TFP403 SLDS125A TFP501
Supplyframe Tracking Pixel