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Part Manufacturer Description Datasheet Download Buy Part
LTC7541ABSW#TR Linear Technology LTC7541A - Improved Industry Standard CMOS 12-Bit Multiplying DAC; Package: SO; Pins: 18; Temperature Range: -40°C to 85°C
LTC7541AJSW Linear Technology LTC7541A - Improved Industry Standard CMOS 12-Bit Multiplying DAC; Package: SO; Pins: 18; Temperature Range: 0°C to 70°C
LTC7541ABN#PBF Linear Technology LTC7541A - Improved Industry Standard CMOS 12-Bit Multiplying DAC; Package: PDIP; Pins: 18; Temperature Range: -40°C to 85°C
LTC7541AJSW#TR Linear Technology LTC7541A - Improved Industry Standard CMOS 12-Bit Multiplying DAC; Package: SO; Pins: 18; Temperature Range: 0°C to 70°C
LTC7541AKN Linear Technology LTC7541A - Improved Industry Standard CMOS 12-Bit Multiplying DAC; Package: PDIP; Pins: 18; Temperature Range: 0°C to 70°C
LTC7541ABSW#TRPBF Linear Technology LTC7541A - Improved Industry Standard CMOS 12-Bit Multiplying DAC; Package: SO; Pins: 18; Temperature Range: -40°C to 85°C

0.5-um CMOS standard cell library Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
1999 - MOS RM3

Abstract:
Text: 0.35 µm CMOS Process Family XO035 MIXED-SIGNAL FOUNDRY EXPERTS 0.35 Micron Modular CMOS , RF performance - High Density up to 18000 gates per mm2 - I/O cell library with 4kV HBM ESD , world is analog. XO035 - Foundry-specific optimized libraries - Standard core library for high , Standard MOS module SIngle poly, triple metal CMOS 3.3V NMOS/PMOS and resistors This main module can , optimized for best synthesis results in high speed applications. - The standard low noise core library


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PDF XO035 XO035 35micron MOS RM3 mos rm3 data Silicon Image 1364 cmos transistor 0.35 um ESD "p-well" n-well" analog devices transistor tutorials 6E-08 opto mos application varactor diode spice model transistor time extraction
b55qs

Abstract:
Text: perspective view CMOS 0.25 µm , Shallow Trench Isolation, M1: Tungsten 2/15 CB55000 Series 1 GENERAL DESCRIPTION The CB55000 standard cell series uses a high performance, low-voltage, 0.25 µm drawn (0.20 µm effective), six metal levels CMOS process HCMOS7 to a 90 pico-second internal delay , organized into three categories: ­ SSI cell library ­ I/O cell library ­ Macrofunctions 3.1 SSI Cell , CB55000, one 80 µm pad in line pitch library and one 50 µm staggered pad library to support pad limited


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PDF CB55000 b55qs ultra fine pitch BGA CB45000 CB55Q ST-100 D950 CMOS GATE ARRAY BGA stmicroelectronics b55q 8mm pitch BGA 256 pin 14x14
1999 - 0.25-um CMOS standard cell library inverter

Abstract:
Text: General Description The CB55000 standard cell series uses a high performance, low-voltage, 0.25 µm drawn (0.20 µm effective), six metal levels CMOS process HCMOS7 to a 90 pico-second internal delay , : · SSI cell library · I/O cell library · Macrofunctions 3.1 SSI Cell Library , offered with CB55000, one 80 µm pad in line pitch library and one 50 µm staggered pad library to support , differential receivers and converts them into standard CMOS receivers. This allows lddq test methodologies to


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PDF CB55000 0.25-um CMOS standard cell library inverter CMOS GATE ARRAY stmicroelectronics OLIVETTI
8mm pitch BGA 256 pin 14x14

Abstract:
Text: perspective view CMOS 0.25 µm , Shallow Trench Isolation, M1: Tungsten 2/15 CB55000 Series 1 GENERAL DESCRIPTION The CB55000 standard cell series uses a high performance, low-voltage, 0.25 µm drawn (0.20 µm effective), six metal levels CMOS process HCMOS7 to a 90 pico-second internal delay , organized into three categories: ­ SSI cell library ­ I/O cell library ­ Macrofunctions 3.1 SSI Cell , CB55000, one 80 µm pad in line pitch library and one 50 µm staggered pad library to support pad limited


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PDF CB55000 8mm pitch BGA 256 pin 14x14 CB45000 ultra fine pitch BGA ST100 ST10 of BGA Staggered pins D950 CMOS GATE ARRAY BGA stmicroelectronics bga 10x10
1999 - CMOS

Abstract:
Text: 0.8 µm CMOS Process CX08 MIXED-SIGNAL FOUNDRY EXPERTS 0.8 Micron Modular Mixed Signal , target applications are standard cell , semi-custom and full custom designs for Industrial, Tele­ om , optimized libraries - Standard core library for high speed digital blocks - Low-power library , 50% less , ] Spacing [ µm ] Standard N-well 5.0 5.0 HV deep N-well 5.0 11.0 HV shallow N-well , applications. The standard core library includes more then 200 cells. Functionality and layouts are optimised


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1999 - MOS RM3

Abstract:
Text: 0.35 µm CMOS Process Family XO035 MIXED-SIGNAL FOUNDRY EXPERTS 0.35 Micron Modular CMOS , Competitive RF performance - High Density up to 18000 gates per mm2 - I/O cell library with 4kV HBM ESD , Foundry-specific optimized libraries - Standard core library for high speed digital blocks - Pad-limited IO , bandwidth photo diodes arrays or CMOS image sensors for such applications as optical data storage, optical , the art 0.35 μm CMOS Processes. Comprehensive design rules, accurate SPICE models, analog and


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PDF XO035 XO035 35-micron MOS RM3
1999 - MOS RM3

Abstract:
Text: 0.35 µm CMOS Process Family XA035 MIXED-SIGNAL FOUNDRY EXPERTS 0.35 Micron High Temperature , beyond AEC Q100 requirement. - High Density up to 18000 gates per mm2 - I/O cell library with 4kV HBM , libraries - Standard core library for high speed digital blocks - Pad-limited IO library - Core-limited , Applicaitons MOS 14 Standard MOS module SIngle poly, triple metal CMOS 3.3V NMOS/PMOS and , Cell height for core limited I/O cells is 248.8m and minimum pad pitch is 173m - The TTL and CMOS


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PDF XA035 XA035 35-micron XH035 MOS RM3 "X-Fab" Core cell library mos rm3 data ESD "p-well" n-well" 0.18 um CMOS Spiral Inductor technology RM3 transistors bsim3v3 XH035 library MICRON RESISTOR Mos
1999 - mos rm3 data

Abstract:
Text: 0.35 µm CMOS Process Family XA035 MIXED-SIGNAL FOUNDRY EXPERTS 0.35 Micron High Temperature Modular CMOS Technology Description The XA035 Series is X-FAB`s 0.35 Micron High Temperature CMOS , beyond AEC Q100 requirement. - High Density up to 18000 gates per mm2 - I/O cell library with 4kV HBM , libraries - Standard core library for high speed digital blocks - Pad-limited IO library - Core-limited , Applicaitons MOS 14 Standard MOS module SIngle poly, triple metal CMOS 3.3V NMOS/PMOS and


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PDF XA035 XA035 35-micron XH035 mos rm3 data MOS RM3 BSIM3V3 RM4L bsim3 DCELL ESD "p-well" n-well" XH035 library MICRON POWER RESISTOR Mos
2006 - AMIS500CXASCM

Abstract:
Text: Standard and slew rate limited availability · PCI 33MHz compliant · CMOS , TTL, LVCMOS, LVTTL, PCI (33MHz) levels SC5 0.5µ µm CMOS Standard Cell Feature Sheet · Automatic test program generation (ATPG) · , AMI Semiconductor SC5 0.5µm CMOS Standard Cell Key Features · Excellent performance: · 590MHz , simple analog functions to ASIC designs. SC5 0.5µm CMOS Standard Cell -Feature Feature Sheet Sheet , design: · Complete primary cell and I/O library · Synchronous ROM compiler from 64x1 to 16Kx32 bits ·


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PDF 590MHz 103ps 128ps 16Kx32 M-20523-001 AMIS500CXASCM 0.5um amis cmos
1999 - zener diode phc

Abstract:
Text: Core Library Cells X-FAB provides a standard cell library optimized for most typical applications , Digital Standard Cell Core Library is available in X-FAB XDM10 technology Name Voltage Range , . - The I/O cell library requires the CMOS module. - I/O cells are optimized for 5.0V +/-10% , / µm ] max. VTB [V] PWELLD rpwd CORE 1530 5 - 50 PWELL rpw CMOS , : 2.86 standard digital applications library density: kGE/mm at given routing factor (GE = NAND2


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PDF XDM10 XDM10 zener diode phc zener phc 12 zener diode phc 10 zener PH-C zener diode phc 16 zener diode phc 24 zener PH-C 15 zener diode phc 12 nd25d zener diode phc 15
1999 - zener diode phc 24

Abstract:
Text: [Ω] Zener Zap dzap CMOS 4.8 50 50 Digital Core Library Cells X-FAB provides a standard cell library optimized for most typical applications in mixed signal ASIC. The XDM10 standard cells can be used double-metal routing. The following Digital Standard Cell Core Library is , library cells are available for core-limited designs. - The I/O cell library requires the CMOS module. - , 1.0 µm BCD Process XDM10 MIXED-SIGNAL FOUNDRY EXPERTS Modular 1.0µm 350V Trench Insulated


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PDF XDM10 XDM10 zener diode phc 24 -20/zener diode phc 24 350v ZENER DIODE
1999 - nmos transistor 0.35 um

Abstract:
Text: Foundry-specific optimized libraries - Standard core library for high speed digital blocks - Low-noise, standard , 0.6 µm BiCMOS Process Family XHB06 MIXED-SIGNAL FOUNDRY EXPERTS 0.6 Micron Modular HV BCD Technology Description The XHB06 is X-FAB's 0.6 Micron High-Voltage Bipolar CMOS DMOS (BCD) Technology , 0.6 process family. Reliable design rules, precise SPICE models, cell libraries, IP's and , transistors - 5V I/O with improved ESD robustness - High precision BSIM3V3 SPICE models for CMOS and Gummel


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PDF XHB06 XHB06 nmos transistor 0.35 um npn pnp rf transistor bipolar cross reference l24c using a zener diode as a varicap bsim3 model for 0.18 micron technology for hspice NMOS depletion pspice model bsim3 model cmos nand four open collector fuse rm2 bsim3 0.18 micron parameters
1999 - spice model Tunnel diode

Abstract:
Text: per mm2 (2ML/3ML) - Pad-limited 5V I/O cell libraries with CMOS / TTL interfacing capability - , state of the art 0.6 µm CMOS processes. For analog applications several capacitor and resistor , combination of these modules, the 0.6 µm Trench SOI CMOS process family XT06 offers a wide variety of proven , in class results of area, speed, low power and low noise. - The standard core library is , low power library less than standard library NMOS, PMOS with separated bulk supply Digital I/O


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1999 - Not Available

Abstract:
Text: world is analog. XB06 - Foundry-specific optimized libraries - Standard core library for high speed digital blocks - Low-noise, standard core library with separate bulk supply for reduced , for best synthesis results in high speed applications. - The standard low noise core library , 0.6 µm BiCMOS Process Family XB06 MIXED-SIGNAL FOUNDRY EXPERTS 0.6 Micron Modular BiCMOS , 0.6 process family. Reliable design rules, precise SPICE models, cell libraries, IP’s and


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1999 - "X-Fab" Core cell library

Abstract:
Text: Digital Core Library Cells X-FAB provides a standard cell library optimized for most typical , Digital Standard Cell Core Library is available in X-FAB XDM10 technology Name Voltage Range , library cells are available for core-limited designs. - The I/O cell library requires the CMOS module. - , . CMOS Devices Device Device Name Available with module |VT| [V] min. gate length [ µm ] |BVDS| [V] IDSAT [µA/ µm ] max. VDS [V] max. VGS [V] 5V NMOS ne CMOS 0.80 1.2


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PDF XDH10 XDH10 "X-Fab" Core cell library nd65d RM3 transistors analog devices transistor tutorials pnp transistor 650v 20 PHB zener mos rm3 data nd35b MOS RM3
2004 - atmel 0726

Abstract:
Text: Available Gates 0.5 µm Drawn CMOS , 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized , 10/20/2004 Product Description Rad Hard 190K Used Gates 0.5 µm CMOS Sea of Gates , Programmable Pads Standard 3, 6, 12 and 24 mA I/Os Versatile I/O Cell : Input, Output, I/O, Supply, Oscillator , 190K Used Gates 0.5 µm CMOS Sea of Gates MG2RTP · · · · · · · · · Description The MG2RTP , : 1. Not available for new designs. Libraries The MG2RTP cell library has been designed to take


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PDF 4116J atmel 0726 OAI22 0.5-um CMOS standard cell library
NZ70008H

Abstract:
Text: ) Ti-Silicide CMOS technology Ultra high density cell structure · Optimised 3.3 Volt transistor , ratio Minimum device cost for high I/O requirement · Large I/O cell library including LVTTL,HSTL , standard devices. 22 The CB-C9VX 3.3 V library features a typical gate delay of 75 ps for a 2 , by connecting basic hard macros Interface Macro Support The CB-C9VX/VM standard interface library , DATA SHEET PRODUCT LETTER CB-C9VX/VM 0.35-Micron CMOS Cell-Based ASICs Description Figure 1


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PDF 35-Micron 35micron 27-micron GB-MK14 NZ70008H STEPS 30175 STR 6755 k2736 NZ70 V30MX NEC V30MX k 246 K398 nec 2508
1999 - ST100

Abstract:
Text: Libraries Two basic buffer libraries are offered with CB65000, one 80 µm pad in line pitch library and one 50 µm staggered pad library to support pad limited designs. Apart from standard ESD and latch-up , PRELIMINARY CB65000 Series 1 General Description The CB65000 standard cell series uses a high , library is organized into three categories: · SSI cell library · I/O cell library · Macrofunctions 3.1 SSI Cell Library Overview The design of the CB65000 family has been optimized to


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PDF CB65000 85K/mm2, 30nanoWatt/Gate/MHz/Stdload. ST100 CB55000 D950 ST10 ST20 tristate nand gate
0.18-um CMOS technology characteristics

Abstract:
Text: , LVTTL level, GTL+,HSTL, PCI, pECL Standard cell 0.25 µm (0.18 µm effective) silicon gate CMOS ; 3,4 or 5 , .) Ti-Silicide CMOS process Ultra high density cell structure at high performance · Extensive support of , CMOS -10 and EA-C10 product letters to get more information to the 0.25 µm gate array and embedded , DATA SHEET PRODUCT LETTER CB-C10 2.5 Volt 0.25-Micron CMOS Cell-Based ASIC PRELIMINARY Figure 1. Chip Size Package (CSP) Description NEC's 0.25 µm (0.18 µm eff.) CB-C10 family incorporates


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PDF CB-C10 25-Micron CB-C10 GB-MK14 0.18-um CMOS technology characteristics NEC 71055 NEC V30MX DSPG A1246 CMOS-10 Z80 Manual nec asic product letter RAC RAMBUS STEPS 30175
2003 - star delta wiring diagram with timer

Abstract:
Text: Matrices with up to 480K Available Gates 0.5 µm Drawn CMOS , 3 Metal Layers, Sea of Gates RAM and DPRAM , Matrices with a Max of 484 Fully Programmable Pads Standard 3, 6, 12 and 24 mA I/Os Versatile I/O Cell , Rad Tolerant 350K Used Gates 0.5 µm CMOS Sea of Gates MG2RT Description The MG2RT series is , Libraries Total Gates 481143 336800 507 484 The MG2RT cell library has been designed to , °C, Process typical (all values in ns) VDD Cell Description Load BINCMOS CMOS input buffer 15


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PDF 4115H star delta wiring diagram with timer atmel 422 ATMEL 634 atmel 946 star delta connection circuit diagrams MG2360E MG2265E MG2194E MG2091E ttl buffer
2002 - fan 7320

Abstract:
Text: Gates 0.5 µm Drawn CMOS , 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized for , Full Programmable Pads Standard 3, 6, 12 and 24 mA I/Os Versatile I/O Cell : Input, Output, I/O , .5) QML Q and V with SMD 5962-00B03 Rad Hard 350 Kb Used Gates 0.5 µm CMOS Sea of Gates MG2RTP , layers CMOS process. The MG2RTP series base cell architecture provides high routability of logic with , availability. The MG2RTP cell library has been designed to take full advantage of the features offered by


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PDF 4116G fan 7320 LA 4440 circuit diagram 0.5-um CMOS standard cell library atmel 936 MG2014P MG2044P MG2142P TM1019
1998 - IC MASTER 2001 CD-ROM

Abstract:
Text: must be kept low. In addition, because many development tools and standard cell libraries are available , /VM Standard cell SC-4 SC-5 Custom micro CMICRO-4 CMICRO-5 EA-C10 Embedded , building block type standard cell design technique. Cell-based ICs cannot only realize a density higher , X13769XJ2V0CD00 05-26 Semi-Custom IC Gate Array CMOS Gate Array s CMOS -6/6A/6S Family q Library I/O , % ( CMOS level), 5 V ± 5 % (TTL level) * 2-input NAND conversion * Cell utilization rate: 75 % Output


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PDF X13769XJ2V0CD00 IC MASTER 2001 CD-ROM DIN 53018 upc5032 PD65800 uPD65656 UPD65625 PD65654 0.25-um standard cell library CMOS-5 NEC V30MX
2002 - atmel 946

Abstract:
Text: Matrices up to 700K Cells 0.5 µm Drawn CMOS , 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers , Matrices with a Max of 582 Fully Programmable Pads Standard 3, 6, 12 and 24 mA I/Os Versatile I/O Cell , Rad Tolerant 500K Used Gates 0.5 µm CMOS Sea of Gates MG2RT Description The MG2RT series is , : Libraries 1. Check for availability. The MG2RT cell library has been designed to take full advantage , in ns) VDD Cell Description Load BINCMOS CMOS input buffer 15 fan 0.66 0.9


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PDF 4115G atmel 946 X-TAL 20m atmel 422 AtMEL 624 ATMEL 634 OAI22 atmel 034 ATMEL 644 ATD-TS-WF-R0181 MG2044E
Not Available

Abstract:
Text: manufactured using SCMOS 2/2, a 0.6 micron drawn, 3 metal layers CMOS process. The MG1 series base cell , Standard 3, 6, 12m, 24mA I/Os, parallelism up to 48mA Versatile I/O Cell : Input, Output, I/O, Supply , c o n d u c t o r s Libraries The MG1 cell library has been designed to take full advantage of , VDD Cell D escription L oad T ransition BINCMOS CMOS input buffer 15 12 1.78 , Temic MG1 S e m i c o n d u c t o r s MG1 Sea of Gates Series 0.6 Micron CMOS Description


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PDF BOUT12
2004 - AtMEL 624

Abstract:
Text: 0.5 µm Drawn CMOS , 3 Metal Layers, Sea of Gates RAM and DPRAM Compilers Library Optimized for , Programmable Pads Standard 3, 6, 12 and 24 mA I/Os Versatile I/O Cell : Input, Output, I/O, Supply, Oscillator , Gates 0.5 µm CMOS Sea of Gates MG2RT · · · · · · · · · Description The MG2RT series is a 0.5 , . Libraries The MG2RT cell library has been designed to take full advantage of the features offered by both , values in ns) VDD Cell BINCMOS Description CMOS input buffer Load 15 fan Tphl Tplh BINTTL TTL input


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PDF 4115J AtMEL 624 XTAL SMD Packages atmel 946 0.5-um CMOS standard cell library atmel 044
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