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TSW4200 Texas Instruments Dual ADC and Dual DAC Development Platform for Xilinx Virtex VI FPGA Dev. Platform visit Texas Instruments
PMP6776 Texas Instruments Xilinx Kintex 7 Low Cost reference design visit Texas Instruments
PMP7804 Texas Instruments Xilinx 7 Series Power Module Reference design visit Texas Instruments
PMP8251.3 Texas Instruments Power Solution for Xilinx FPGA Zynq 7 visit Texas Instruments
PMP6577.3 Texas Instruments Power Solution for Xilinx 7-Series MGT with 5V input voltage (1.8V @ 2.6A) visit Texas Instruments
PMP7804.6 Texas Instruments Xilinx 7 Series Power Module Reference design(1V@6A) visit Texas Instruments

xilinx digital Pre-distortion

Catalog Datasheet MFG & Type PDF Document Tags

xilinx digital Pre-distortion

Abstract: adaptive algorithm dpd × 2.32mm LGA Xilinx Digital Predistortion LogiCORE IP Core The Xilinx digital predistortion , Digital Predistortion Solutions TRANSMIT PATH DSP DAC DPD PA ADC FEEDBACK PATH , and is a significant factor in the operating expense for the service provider. Since complex digital , is most efficient. To improve PA efficiency, designers use digital techniques to reduce the crest factor and improve PA linearity, allowing it to run closer to saturation. Digital predistortion (DPD) has
Linear Technology
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GMSK simulink

Abstract: xilinx digital Pre-distortion the Xilinx® Cascaded Integrator Comb (CIC) Compiler [Ref 2], Direct Digital Synthesizer (DDS , Application Note: Virtex-5 Family Designing Efficient Digital Up and Down Converters for , Kostarnov Digital Up Converters (DUC) and Digital Down Converters (DDC) are key components of RF systems , implementations can be created by leveraging Xilinx® DSP tools and IP portfolio for increased productivity and , functions onto building blocks and IP cores for Xilinx® FPGAs in System Generator software, and how to
Xilinx
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R_10024

Abstract: Avateq, NXP and Xilinx join to meet design challenge Avateq, NXP and Xilinx join to meet design challenge digital broadcast repeater Rev. 2 â'" 11 , Semiconductors Avateq, NXP and Xilinx join to meet design challenge NXP Semiconductors digital broadcast repeater 1. Introduction Conversion to digital broadcast technologies requires transmission stations to , 5 Avateq, NXP and Xilinx join to meet design challenge NXP Semiconductors digital broadcast , amplifiers has become an important issue in digital broadcast equipment design. In response to these new
NXP Semiconductors
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Xilinx DLC5 JTAG Parallel Cable III

Abstract: dlc5 provides digital outputs which are accessible through standard logic analyzer headers and differential , the CPLD is input/output signal conditioning to provide for digital 2 output from the ISL5239 , . Install the parallel port JTAG programming cable XILINX Model Number DLC5, Parallel Cable III from the , user's needs via the a JTAG programming interface J9. U2 is a Xilinx XC95288XL6PQ208C CPLD, and is required for basic board functions. U3 is a Xilinx XC18V01VQ44C SPROM which supports optional FPGA
Intersil
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ISL5239EVAL1 AN1024 ISL5217 ISL5216 ISL5416 Xilinx DLC5 JTAG Parallel Cable III dlc5 fpga JTAG Programmer Schematics xilinx digital Pre-distortion dlc5 parallel cable III mpi cable pin details ISL5929

Xilinx lcd display controller design

Abstract: Xilinx lcd display controller Xilinx floating point unit (FPU) coprocessor. An FPU connected to the PowerPC auxiliary processor unit , reference design provided includes a completed design created using the Xilinx Embedded Development Kit , are frequently required for embedded systems and DSP applications such as image processing, digital , ) controller and fully supported by the Xilinx GNU compiler to ensure hardware abstraction and ease of use , included reference design is built using the Xilinx EDK. A step-by-step tutorial for building the design
Xilinx
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XAPP547 DS302 Xilinx lcd display controller design Xilinx lcd display controller FIR FILTER implementation xilinx DSP48 ML403 fpu coprocessor IEEE-754- DS535 UG243

Spartan-6 LX45

Abstract: Spartan-6 FPGA LX9 mitigate risk in rapidly changing and fickle markets. Accelerate Innovation Xilinx® Targeted Design , innovation. They comprise advanced FPGA silicon and design tools, Xilinx and third-party IP cores and , , differentiating value. The Foundation for Targeted Design Platforms Xilinx Virtex®-6 and Spartan®-6 FPGA , forces are driving the adoption of field programmable gate arrays (FPGAs) in the heart of digital , reduction (CFR) and digital pre-distortion (DPD) algorithms to increase power amplifier efficiency by up
Xilinx
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Spartan-6 LX45 Spartan-6 FPGA LX9 Xilinx Spartan-6 LX9 LX550T SPARTAN-6 image processing spartan 6 LX150 FTG256 CSG324 FGG484 FGG676

adaptive algorithm dpd

Abstract: DSP48E1 development tool support that enables Xilinx customers to meet the demands of markets with evolving standards , integration Targeted Design Platforms · Targeted Design Platforms from Xilinx and its network of third , using third-generation Xilinx ASMBLTM architecture, the Virtex-6 FPGA family is supported by a new , requirements ASIC/ Xilinx FPGA (Traffic Manager or Backplane) · Simplify interfacing to DDR3, RLDRAM , interface standards. · Integrate crest factor reduction (CFR) and digital pre-distortion (DPD) algorithms
Xilinx
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adaptive algorithm dpd DSP48E1 SX475T FPGA Virtex 6 Ethernet virtex GTH Virtex 6

matlab codes for wcdma rake receiver

Abstract: 3G HSDPA circuits diagram Interface Low Noise Amp ADC Analog RF TX Analog RF TX ADC ADC Digital Down Conversion Digital Filtering & Antenna Diversity Symbol Encoding Modulation & Spreading , E1, T1 Frame Relay or IP Network (Gigabit Ethernet etc.) Main Processor Digital Up Conversion Pre-Distortion & Digital Filtering Chip-Rate Demodulation & Despreading Central , efforts as a baseline to eventually merge the development efforts into © 2005 Xilinx, Inc. All rights
Xilinx
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matlab codes for wcdma rake receiver 3G HSDPA circuits diagram HSDPA matlab wcdma simulink turbo encoder circuit, VHDL code mimo model simulink XAPP726

simulation for prbs generator in matlab

Abstract: block diagram prbs generator in matlab Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL , external microcontroller interface Table 1: Example Implementation Statistics for Xilinx® FPGAs Fmax , February 5th , 2008 © 2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx, Inc. MW_ATSC Transport data receiver , The MW_ATSC Modulator Core performs the digital baseband functions required for the transmission side
Xilinx
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simulation for prbs generator in matlab block diagram prbs generator in matlab vhdl code for pseudo random sequence generator in vhdl code for 16 prbs generator vhdl code for pseudo random sequence generator pulse shaping FILTER implementation xilinx 16VSB
Abstract: Data Converter Solutions Analog, Digital & Mixed-Signal ICs, Modules, Subsystems & Instrumentation , ) Receivers â'¢ Macro BTS & Small Cells â'¢ â'¢ Test & Instrumentation Digital Oscilloscopes Magnetic , Connected to Xilinx Standard FMC Board â'¢ EasyStackâ"¢: Firmware Code Stack Available for Xilinx  , , such as: Digital Down Conversion, Image Rejection F & Oscilloscope Triggers 2 hittite.com , CLOCK DIVIDE 1 - 8X SPI 75 IP0 IN0 ADC Digital Gain LVDS DP0 (13:0) DN0 (13:0 Hittite Microwave
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ADC-0713 13-BIT 12-BIT 14-BIT 16-BIT 10-BIT

AD-MSDPDA900-EVB

Abstract: LTE baseband Mixed Signal Digital Predistortion Evaluation Platform AD-MSDPD-EVB High performance RF and , interface with intuitive user interface Interfaces for both the Altera HSMC and the Xilinx FMC mezzanine , coupled with a suitable digital predistortion algorithm. A full observation path is also included that , Tx output connector Auxiliary Rx IF output Auxiliary clock reference input Xilinx FMC connector or , complex IF output of ~184.32 MHz. ESD CAUTION Rev. 0 | Page 10 of 12 Package Option Xilinx FMC
Analog Devices
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AD-MSDPDX2150-EVB AD-MSDPDA900-EVB AD-MSDPDA2600-EVB LTE baseband GSM 900 modulation matlab ADF4350 AD8375 CDMA2000 AD-MSDPDX900-EVB AD-MSDPDX1850-EVB AD-MSDPDX2000-EVB AD-MSDPDX2350-EVB

vhdl code for ofdm

Abstract: vhdl code for ofdm transmitter Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL , Table 1: Example Implementation Statistics for Xilinx® FPGAs Fmax Family Example Device (MHz , and clocks are routed off-chip February 5, 2008 © 2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx Logo, and other designated brands included herein are trademarks of Xilinx, Inc. DVB-T , General Description The MW_DVB-T/H_P Modulator Core performs the digital baseband functions required for
Xilinx
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vhdl code for ofdm vhdl code for ofdm transmitter OFDM Matlab code ofdm code in vhdl OFDM QPSK simulation VHDL PROGRAM for ofdm

LM2596 schematic constant current

Abstract: XILINX/SPARTAN 3E STARTER BOARD National Semiconductor's Solutions for Xilinx® Field Programmable Gate Arrays (FPGAs) Design , 's Power Supply Kit Page 9 Xilinx Family Selection Tables & Reference Designs Spartan-3, 3E, 3L Page , 18 Virtex-II Pro Page 20 Virtex, Virtex-E Page 22 Voltage References & Supervisors Xilinx , that supports Xilinx Field Programmable Gate Arrays (FPGAs). National provides analog signal , sensor Receiver path Analog signal processing ADC Interface Digital PCI processing
National Semiconductor
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LM2596 schematic constant current XILINX/SPARTAN 3E STARTER BOARD new-era voltage regulator interfacing rj45 with spartan-3 fpga schematic usb to rj45 cable extender SPARTAN 3E STARTER BOARD FBGA-49L TQFP-64 AEM-NSCGUIDE/01

LTE DUC

Abstract: xilinx XAPP1123 The Xilinx® LogiCORETM IP DUC/DDC Compiler implements high-performance, optimized Digital Upand , Frequency Max. Freq.(5) 368.64 368.64 368.64 Features · Generates Digital Up-Converter modules for a range of output sample rates between 30.76 and 245.76 MHz Generates Digital Down-Converter modules for a , ) features: resource and latency estimation, frequency and phase raster reporting For use with Xilinx CORE , Support Provided by Xilinx@ www.xilinx.com/support 1. 2. 3. 4. 5. 6. 7. · · · For a complete
Xilinx
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LTE DUC xilinx XAPP1123 XAPP1123 DSP48E1s DFE digital front end DPD amplitude demodulation using xilinx system generator DS766 TM-7000

schematic diagram 180v dc motor speed controller

Abstract: schematic diagram 48v dc motor speed controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18-23 High-End Consumer Market Digital , , Microcontrollers, Power MOSFET Drivers, and Digital Signal Processing. www.intersil.com/design/designmodels.asp , /DVD Drive Desktop Computers Desktop Server Digital Still Camera Inkjet Printer Keyboard Video Mouse (KVM) Laser Printer Multifunction Printer Notebook Computers Portable Digital Assistant (PDA , Drive Digital Projector Digital Still Camera DSL Modem (CPE) DVD Recorder E-Bike Game Console GPS
Intersil
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schematic diagram 180v dc motor speed controller schematic diagram 48v dc motor speed controller 300khz 600V mosfet driver IC e bike motor controller e-bike CCTV SCHEMATIC camera board ISL29007 ISL29002 X95840 X93156 X9110 X9420

ISL59310

Abstract: CAT5 cable cable losses. The first is a digital solution using the non ideality of a step response. A B , TRANSMITTER XILINX FPGA 8 VIDEO X98017 X9C102 SYNC MEMORY MAP TO HOST PC I2C BUS 3 USB TRANSCEIVER DIGITAL POTENTIOMETER CONTROL BUS FIGURE 18. AUTOMATIC EQUALIZATION LOOP BLOCK
Intersil
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AN1307 ISL59310 CAT5 cable CAT 5 cable 519MHz EL5175 EL5177

QUBiC4X

Abstract: BGX7300 transmission chain, bringing digital signals closer to the antenna. Another is a digital signals transmitter , digital interfaces including JESD204A (in the CGV product line), as well as CMOS LVCMOS and LVDS DDR , PLL VCO LPF DIGITAL BASEBAND & CONTROL SER Q-DAC BPF SER ADC PLL VCO LPF SER ADC VGA IF mixer Rx BPF , signals generated in the "Digital Baseband & Control" block follow the air interface standard requirements , derive coefficients for the digital pre-distortion algorithm. Since power levels vary, the observation is
NXP Semiconductors
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HTQFP100 QUBiC4X BGX7300 power amplifier NXP BLF7G20LS-90P BGA7202 BLP7G10S-140P printed antenna dcs 1800 HVQFN64 HTQFP80 LQFP48

1LQ1

Abstract: picocell Output LVDS SLVS CT Modulator Digital Decimation Filter Output Serializer LVDS , 12 IF B ADC DVGA LC CLK SCK_IN 12 Serial Out A/B ADC Dual Digital Tuner
National Semiconductor
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IEEE-1588 LMH6550 LMH6551 LMH6555 LMH6515 SCAN25100 1LQ1 picocell LM201 LM5035 DS15CP154 LMH7332 CDMA2000TD-SCDMA ADC14155/105C/080C

stk 086 g

Abstract: 802.11a matlab code Acquisition and Switching 6 Digital Input Output 7 Digital Multimeters 8 Digitizers 9 Digital to Analog Converters 10 Function and Arbitrary Waveform Generators 11 Logic Analysis , 1 ® 2 PXI BIT E RROR R A T E T ES T ERS ( B ERT S ) N2099A 2 PXI Digital , Module 4 PXI DIGITA L INPU T O U T P U T M9187A PXI Digital IO: 32-ch, 0.3 to 50 V 4 PXI DIGITA L MUL T I MET ERS M9181A M9182A PXI Digital Multimeter: 6½ digit M9183A 4 PXI Basic
dataTec
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stk 086 g 802.11a matlab code M9252A M9156CH40 M9157CH40 M9120A M9121A M9122A M9128A

HDMI TO VGA MONITOR PINOUT

Abstract: SEMINAR ON 4G TECHNOLOGY Modulator Digital Decimation Filter Output Serializer LVDS SLVS 8 Channels LM97593 ­ Integrated Dual ADC with Digital Downconverter and Automatic Gain Control for Communications Applications , bandwidth · 68 dBFS SFDR at fin=250 MHz, Nyquist bandwidth · Digital downconverter composed of 4 , Serial Out A/B ADC 8 12 ADC DVGA LC Dual Digital Tuner / AGC Serial Out B SCK SFS RDY , analog supply, 1.8V digital · Available in PQFP-128 packaging Data Conversion Selected High-Speed
National Semiconductor
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HDMI TO VGA MONITOR PINOUT SEMINAR ON 4G TECHNOLOGY GSM BTS antenna sot23-5 code BBB GSM repeater HDMI to vga pinout
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