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xaui Datasheet

Part Manufacturer Description PDF Type
XAUI-E3-U1 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE XAUI 10GB ECP3 USER CONF Original
XAUI-E3-UT1 Lattice Semiconductor Software, Programmers, Development Systems, SITE LICENSE XAUI 10GB ECP3 CONF Original
XAUI-PM-U1 Lattice Semiconductor Software, Programmers, Development Systems, IP CORE XAUI 10GB ECP2M CONF Original
XAUI-PM-UT1 Lattice Semiconductor Software, Programmers, Development Systems, SITE LICENSE XAUI 10GB ECP2M Original

xaui

Catalog Datasheet MFG & Type PDF Document Tags

sfp reference design

Abstract: SFP reference design kit 12 XAUI_RX_2N1 8 XAUI_RX_2N2 4 XAUI_RX_2N3 14 XAUI_RX_2P0 10 XAUI_RX_2P1 6 XAUI_RX_2P2 2 XAUI_RX_2P3 31 XAUI_TX_1N0 27 XAUI_TX_1N1 23 XAUI_TX_1N2 19 XAUI_TX_1N3 29 XAUI_TX_1P0 25 XAUI_TX_1P1 21 XAUI_TX_1P2 17 XAUI_TX_1P3 15 XAUI_TX_2N0 11 XAUI_TX_2N1 7 XAUI_TX_2N2 3 XAUI_TX_2N3 13 XAUI_TX_2P0 , TXONOFF2 XAUI_RX_1N0 28 XAUI_RX_1N1 24 XAUI_RX_1N2 20 XAUI_RX_1N3 30 XAUI_RX_1P0
TerasIC Technologies
Original
sfp reference design SFP reference design kit BCM8727 XXXX0111

leaky

Abstract: ASIC, FCBGA is an advanced Ethernet aggregation device containing two 10 Gbps XAUI ports plus a SPI-4.2 host interface. It supports the conversion from XAUI to SPI-4.2 by transferring packets between each XAUI , enhancement to the standard XAUI interface in terms of channelization and granular flow-control. Highlights · Dual 10 GbE MAC · Dual XAUI line interface and SPI-4.2 host interface · Operates in three modes , GbE line cards · SPI-4 extension over XAUI backplanes · Ethernet over SONET line cards 2 × 10 GbE
Vitesse Semiconductor
Original
leaky ASIC, FCBGA VSC7350 VPPD-02129

PRBS7

Abstract: AN1473 National Semiconductor Application Note 1541 Leo Chang December 2006 TABLE 1. XAUI Jitter , , DS40MB200, and DS42BR400 equalize XAUI backplane FR4 traces and reduce data dependent jitter to within XAUI specifications. The XAUI data rate is 3.125 Gbps with a nominal unit interval (UI) of 320 ps , reduces jitter to meet XAUI input jitter tolerance and interconnect jitter budget requirements. This , 0.65 This study uses a Tyco HM-Zd XAUI Test Backplane. Note that different backplanes may have
National Semiconductor
Original
DS42MB100 PRBS7 AN1473 AN1541 an-1541 national AN-1541

88X2040

Abstract: 88X2040-BAN reference clock for XAUI. The reference clock is multiplied internally by 20 to achieve a 10 Gbps data rate , LatticeECP3 Marvell XAUI 10 Gpbs Physical Layer Interoperability June 2009 Technical Note TN1194 Introduction This technical note describes a physical layer 10-gigabit Ethernet: XAUI (10 Gbps , discusses the following topics: · Overview of LatticeECP3 and Marvell Alaska 88X2040 devices. · XAUI Physical layer interoperability setup, testing and results. XAUI Interoperability XAUI is a high-speed
Lattice Semiconductor
Original
88X2040-BAN xGMII to rj45 phy marvell IEEE 946 motherboard 1-800-LATTICE

TN1176

Abstract: IPUG68 , then right-click and select Properties. 2. In the Properties windows, enter .\XAUI_IP\XAUI_1_2_core. , implemented in the LatticeECP3 FGPA provides a complete XAUI-to-XGMII solution. The LatticeECP3 XAUI soft IP , device 1bitstream file name points to \XAUI\Bitstreams\xaui_demo.bit and that , \Xaui_Demo.syn. This will load the Verilog-based project as shown in Figure 6. Figure 6. Project Navigator , through the full synthesis, place and route flow and generate a new xaui_demo.bit file. 12
Lattice Semiconductor
Original
TN1176 IPUG68 LFE395 alarm clock design of digital verilog CRPAT ECP3-95

88X2040

Abstract: 88X2040-BAN The built-in 156.25 MHz clock oscillator sources the Marvell 88X2040 reference clock for XAUI. The , oscillator sources the LatticeECP2M PCS reference clock for XAUI. The reference clock is multiplied , LatticeECP2M Marvell XAUI 10 Gbps Physical Layer Interoperability November 2008 Technical Note TN1191 Introduction This technical note describes a physical layer 10 Gigabit Ethernet XAUI , Alaska 88X2040 devices * XAUI physical layer interoperability setup, testing, and results XAUI
Lattice Semiconductor
Original
xaui evaluation board free download capacitor data sheet Marvell 8001
Abstract: module that consists of a 1550nm wavelength optical transmitter and receiver, XAUI interface, Mux and , Photo-detector. XAUI electrical interface: 4 lanes @ 3.125 GBd. Hot Z-Pluggable. SC Connectors Up to 40km on , 0.84 V uA V IN=1.2V B. XAUI I/O DC Charateristics (TXLANE[0.3]; RXLANE[0.3 , Min Typ Max Unit Remarks A. XAUI Input AC Characteristics (TXLANE[0.3]) Baud Rate , ps Crossing Point 0.65 UIPP IEEE 802.3ae B. XAUI Output AC Characteristics (RXLANE Agilent Technologies
Original
10GBASE-ER SMC10GXEN-ER-AS
Abstract: transceiver module that consists of a 850nm wavelength VCSEL optical transmitter and receiver, XAUI interface , . XAUI electrical interface: 4 lanes @ 3.125 GBd. Hot Z-Pluggable. SC Connectors. Up to 300m on MMF , 0.84 V uA V IN=1.2V B. XAUI I/O DC Charateristics (TXLANE[0.3]; RXLANE[0.3 , , TC=0 to 70 Parameter Symbol Min Typ Max Unit Remarks A. XAUI Input AC , GHz 75 ps Crossing Point 0.65 UIPP IEEE 802.3ae B. XAUI Output AC Charateristics Agilestar
Original
10110-AS 10GBASE-SR

10113a

Abstract: transceiver module that consists of a 1550nm wavelength optical transmitter an d APD receiver, XAUI interface , Photo-detector. XAUI electrical interface: 4 lanes @ 3.125 GBd. Hot Z-Pluggable. SC Connectors Up to 80km on , 0.84 V uA V IN=1.2V B. XAUI I/O DC Charateristics (TXLANE[0.3]; RXLANE[0.3 , A. XAUI Input AC Characteristics (TXLANE[0.3]) Baud Rate BRXAUI_IN Baud Rate Tolerance , 802.3ae B. XAUI Output AC Characteristics (RXLANE[0.3]) Baud Rate BRXAUI_OUT Baud Rate
Agilestar
Original
10113a 10113-AS 10GBASE-ZR
Abstract: , XAUI interface, Mux and Demux with clock and data recovery (CDR). In addition, it complies with the , . APD Photo-detector. XAUI electrical interface: 4 lanes @ 3.125 GBd. Hot Z-Pluggable. SC Connectors , 0.84 V uA V IN=1.2V B. XAUI I/O DC Charateristics (TXLANE[0.3]; RXLANE[0.3 , Min Typ Max Unit Remarks A. XAUI Input AC Characteristics (TXLANE[0.3]) Baud Rate , ps Crossing Point 0.65 UIPP IEEE 802.3ae B. XAUI Output AC Characteristics (RXLANE Agilent Technologies
Original
10G-XNPK-ZR-AS
Abstract: optical transmitter and receiver, XAUI interface, Mux and Demux with clock and data recovery (CDR). In , stabilized EML transmitter. 100GHz ITU Grid, C Band APD Photo-detector. XAUI electrical interface: 4 lanes , 0.84 V uA VIN=1.2V B. XAUI I/O DC Charateristics (TXLANE[0.3]; RXLANE[0.3 , Symbol Min Typ Max Unit Remarks A. XAUI Input AC Characteristics (TXLANE[0.3]) Baud , 2.5 GHz 75 ps Crossing Point 0.65 UIPP IEEE 802.3ae B. XAUI Output AC Agilestar
Original
DWDM-X2-43 73-AS 100GH

VSC7280

Abstract: XAUI SerDes Transceiver XAUI-A XENPAK Optical Module XAUI-B Backplane Backplane Interconnect , XAUI-B CMU Serial Port A Serial Port B DIAG Core PB-VSC7280-001 VSC7280 Dual XAUI ­ , required in today's high-end Data Communication systems. XGMII-A XAUI-A XAUI-A XGMII-A XAUI Retimer A or B XAUI-B XGMII-B XGMII-B · Dual Port XAUI/XGMII - Port-to-Port Switch - Any , Diagnostics XAUI-B · XAUI Loop-Through - XAUI Retimer/Switch - XGMII Bypass - Supervisor · High
Vitesse Semiconductor
Original
XAUI IEEE802 8B/10B 10GFC

BCM8727

Abstract: 10GBASE-X 10-Gbps Ethernet MAC and XAUI PHY Interoperability Hardware Demonstration Reference Design AN , of the Altera® 10-Gbps Ethernet (10GbE) Media Access Controller (MAC) and XAUI PHY IP cores with a Dual XAUI to small form factor pluggable plus (SFP+) high-speed mezzanine card (HSMC) board. This , f For more information about the 10GbE MAC and XAUI PHY IP cores, refer to the 10-Gbps Ethernet MAC , in the Broadcom PHY BCM8727 chip on the Dual XAUI to SFP+ HSMC board. External optical
Altera
Original
10GBASE-X Broadcom shell bcm872 avalon mdio register xaui xgmii ip core altera SFP altera AN-638-1

infiniband PHY

Abstract: M27205 used as a 10 GbE PHY device performing XGXS functions such as XGMII to XAUI conversion extending the reach of the Media Access Controller (MAC). It can be used as a XAUI re-timer in > K E Y F E AT U , by providing support for high speed XAUI redundancy and multiple clocking modes to simplify board and ASIC design. traffic monitoring functions. XAUI redundancy enables system vendors to achieve , Encoder Serializer BIST Clock Synthesizer JTAG HSTL 32+4 Redundant XAUI 4 x 3.125
Mindspeed Technologies
Original
M27205 infiniband PHY 10GEA
Abstract: module that consists of a 1550nm wavelength optical transmitter and receiver, XAUI interface, Mux and , Photo-detector. XAUI electrical interface: 4 lanes @ 3.125 GBd. Hot Z-Pluggable. SC Connectors Up to 40km on , 20 V 0.36 0.84 V uA V IN=1.2V B. XAUI I/O DC Charateristics (TXLANE[0.3 , Min Typ Max Unit Remarks A. XAUI Input AC Characteristics (TXLANE[0.3]) Baud Rate , ps Crossing Point 0.65 UIPP IEEE 802.3ae B. XAUI Output AC Characteristics (RXLANE Agilestar
Original
10112-AS

10GBASE-SR

Abstract: receiver, XAUI interface , Mux and Demux with clock and data recovery (CDR). In addition, they comply with , Photo-detector. XAUI electrical interface: 4 lanes @ 3.125 GBd. Hot Z-Pluggable. SC Connectors. Up to 300m on , 120 20 V 0.36 0.84 V uA V IN=1.2V B. XAUI I/O DC Charateristics (TXLANE[0.3 , Remarks A. XAUI Input AC Characteristics (TXLANE[0.3]) Baud Rate BRXAUI_IN Baud Rate Tolerance , B. XAUI Output AC Charateristics (RXLANE[0.3]) Baud Rate BRXAUI_OUT Baud Rate Variation
Agilestar
Original
10GBASE-SR-AS

DWDM

Abstract: optical transmitter and receiver, XAUI interface, Mux and Demux with clock and data recovery (CDR). In , stabilized EML transmitter. 100GHz ITU Grid, C Band APD Photo-detector. XAUI electrical interface: 4 lanes , 0.84 V uA VIN=1.2V B. XAUI I/O DC Charateristics (TXLANE[0.3]; RXLANE[0.3 , Symbol Min Typ Max Unit Remarks A. XAUI Input AC Characteristics (TXLANE[0.3]) Baud , 2.5 GHz 75 ps Crossing Point 0.65 UIPP IEEE 802.3ae B. XAUI Output AC
Agilestar
Original
DWDM DWDM-X2-34 25-AS
Abstract: optical transmitter and receiver, XAUI interface, Mux and Demux with clock and data recovery (CDR). In , stabilized EML transmitter. 100GHz ITU Grid, C Band APD Photo-detector. XAUI electrical interface: 4 lanes , 0.84 V uA VIN=1.2V B. XAUI I/O DC Charateristics (TXLANE[0.3]; RXLANE[0.3 , Symbol Min Typ Max Unit Remarks A. XAUI Input AC Characteristics (TXLANE[0.3]) Baud , 2.5 GHz 75 ps Crossing Point 0.65 UIPP IEEE 802.3ae B. XAUI Output AC Agilestar
Original
DWDM-X2-50 12-AS

J8438A-AS

Abstract: Photodiode pin sensitivity that consists of a 1550nm wavelength optical transmitter and receiver, XAUI interface, Mux and Demux , -ER application. Compliant with X2 MSA. Temperature stabilized EML transmitter. PIN Photo-detector. XAUI , 120 20 V 0.36 0.84 V uA VIN=1.2V B. XAUI I/O DC Charateristics (TXLANE[0.3 , 70 Parameter Symbol Min Typ Max Unit Remarks A. XAUI Input AC Characteristics , 2.5 GHz 75 ps Crossing Point 0.65 UIPP IEEE 802.3ae B. XAUI Output AC
Agilestar
Original
J8438A-AS Photodiode pin sensitivity APS 5-3

photodetector 1550nm pin 10gb

Abstract: 10Gb receiver, XAUI interface, Mux and Demux with clock and data recovery (CDR). In addition, they comply with , transmitter. PIN Photo-detector. XAUI electrical interface: 4 lanes @ 3.125 GBd. MDIO, DOM (Digital Optics , V IN=1.2V B. XAUI I/O DC Charateristics (TXLANE[0.3]; RXLANE[0.3]) Differential Input , . XAUI Input AC Characteristics (TXLANE[0.3]) Baud Rate BRXAUI_IN Baud Rate Tolerance , 802.3ae B. XAUI Output AC Characteristics (RXLANE[0.3]) Baud Rate BRXAUI_OUT Baud Rate
Agilestar
Original
photodetector 1550nm pin 10gb 10Gb photodiode 1550nm 10gb X2-10GB-ER-AS
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