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vhdl code 8 bit LFSR

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Abstract: Customizable VHDL source code available, allowing generation of different netlist versions · Customized , set of generics in the synthesizable VHDL source code of the core. Parameters allow the user to , Number of channel input bits - Number of channel output bits per channel input bit (allows emulation of , Generator (LFSR) definition parameters: LFSR size, LFSR feedback polynomial, LFSR seed (reset value , with Core Documentation User Manual Design File Formats EDIF netlist, XNF netlist, VHDL source ... Xilinx
Original
datasheet

5 pages,
34.12 Kb

address generator logic vhdl code FPGA Virtex 6 S40 FSM VHDL vhdl code for 1 bit error generator X9066 CDVO code 24 bit LFSR LFSR vhdl verilog code 8 bit LFSR application pseudo random generator 8 bit LFSR VHDL CODE verilog code 5 bit LFSR verilog code 32 bit LFSR verilog code 16 bit LFSR verilog code 8 bit LFSR vhdl code 10 bit LFSR vhdl code 4 bit LFSR vhdl code 8 bit LFSR vhdl code 16 bit LFSR TEXT
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Abstract: SRLE16 SRLE16 clk X220_08_091100 Figure 8: 32-bit, 4-tap Parallel LFSR The code has been tested on the , shown in Figure 7. In the 32bit LFSR it will only use five SRL16s (Figure 8). Likewise a 64-bit LFSR , on the LUT that implements the SRL16E SRL16E. An example of a 16-bit LFSR implemented in VHDL and Verilog , : Multicycle Tap Access LFSR HDL Code The reference design was written in both VHDL and Verilog HDL. The , : Utilization Summary (Appendix A Code 16 bit length LFSR) Synopsys FPGA Express v3.4 Synplicity Synplify ... Xilinx
Original
datasheet

10 pages,
121.82 Kb

vhdl code for gold code vhdl code for 8 bit parity generator XAPP220 vhdl code gold sequence code LFSR verilog code 5 bit LFSR vhdl code for 9 bit parity generator VHDL 32-bit pn sequence generator verilog code 32 bit LFSR SRL16 8 shift register by using D flip-flop verilog hdl code for parity generator simple LFSR vhdl code 8 bit LFSR verilog code 8 bit LFSR vhdl code 16 bit LFSR verilog code 16 bit LFSR TEXT
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Abstract: 17: 52-bit LFSR Gold Code Generator Gold code generators are used in CDMA systems to generate , . This document provides generic VHDL and Verilog submodules and reference code examples for , as the output, emulating an 8-bit shift register. Note that since the address lines control the mux , Primitive Initialization in VHDL and Verilog Code A shift register can be initialized in VHDL or Verilog code for both synthesis and simulation. For synthesis, the INIT attribute is attached to the 16-bit ... Xilinx
Original
datasheet

17 pages,
208.97 Kb

shift register by using D flip-flop verilog code 8 bit LFSR vhdl code for gold code vhdl code for time division multiplexer vhdl code for rs232 receiver SRLC16E gold code generator verilog code 32 bit LFSR vhdl code for 8 bit shift register vhdl code for rs232 receiver using fpga fpga cdma by vhdl examples SRL16 vhdl code for pn sequence generator SRL16 SRL16 SRL16 verilog code 16 bit LFSR VHDL 32-bit pn sequence generator vhdl code 16 bit LFSR TEXT
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Abstract: first bit of the new fill code is required to be output from the LFSR. The new serial fill sequence , -stage, 2-tap LFSR with SRL16s in a Virtex-II Device HDL Code Verilog and VHDL code examples have been , LFSR width are parameterizable. In the VHDL code, the number of taps, as well as, the tap points, and , of period seven bits at time it = 0 (Table 1). If the 7-bit code were to be repeating within a , level, a Gold Code generator is usually described by two polynomials that indicate the LFSR structure ... Xilinx
Original
datasheet

10 pages,
87.82 Kb

gold code generator verilog hdl code for parity generator verilog code 5 bit LFSR vhdl code for pn sequence generator 16 bit qpsk VHDL CODE 4 bit pn sequence generator simple LFSR PN generator circuit vhdl code for 9 bit parity generator qpsk modulation VHDL CODE vhdl code 8 bit LFSR verilog code 8 bit LFSR vhdl code 16 bit LFSR verilog code 16 bit LFSR pn sequence generator TEXT
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Abstract: are fixed, however the tap points and LFSR width are parameterizable. In the VHDL code, the number of , of period seven bits at time t = 0 (Table 1). If the 7-bit code were to be repeating within a , LFSR structure to be implemented. LFSR 1 Gold Code Out LFSR 2 x211_01_012400 Figure 1 , , the following HDL code (Table 3) will infer a 64-bit shift register using SRLs rather than FFs. Table 3: 64-Bit SRL Shift Register Example VHDL Verilog Always @(posedge clk) begin process (clk ... Xilinx
Original
datasheet

10 pages,
103.45 Kb

verilog code 32 bit LFSR verilog code 5 bit LFSR verilog code 8 bit LFSR vhdl code 10 bit LFSR c code 4 bit LFSR vhdl code gold sequence code pn sequence generator LFSR 4 bit pn sequence generator vhdl code 12 bit LFSR qpsk modulation VHDL CODE vhdl code for pn sequence generator vhdl code 16 bit LFSR vhdl code 8 bit LFSR TEXT
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Abstract: must know in advance when the first bit of the new fill code is required to be output from the LFSR , parameterizable. In the VHDL code, the number of taps, as well as, the tap points, and LFSR width are all , of period seven bits at time t = 0 (Table 1). If the 7-bit code were to be repeating within a , system level, a Gold Code generator is usually described by two polynomials that indicate the LFSR structure to be implemented. LFSR 1 Gold Code Out LFSR 2 x211_01_012400 Figure 1: Gold Code ... Xilinx
Original
datasheet

8 pages,
52.07 Kb

XAPP211 pn sequence generator verilog code 8 bit LFSR application vhdl code 8 bit LFSR vhdl code 16 bit LFSR fpga cdma by vhdl examples vhdl code PN code generator simple 32 bit LFSR using verilog vhdl code for pn sequence generator verilog code 5 bit LFSR verilog code 32 bit LFSR vhdl code 12 bit LFSR verilog code 8 bit LFSR verilog code 16 bit LFSR TEXT
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Abstract: : Number of DIs: Number of GLB Levels: VHDL 32-bit CRC Serial Implementation VHDL code was written to implement a 32-bit serial CRC calculation. A 32-bit LFSR with clock enable is constructed by instantiating , itself. Thus, a 32-bit summing checksum has the same probability of missing a bit error as an 8-bit , 32-Bit Error Checking Using the ispLSI 2128E 2128E ® and original data. CRCCs are very effective for , the checksum is internally consistent (i.e. multiple bit errors resulting in the same checksum). ... Lattice Semiconductor
Original
datasheet

2 pages,
39.51 Kb

CRC-32 crc 16 LFSR 16 bit register vhdl CRC-16 simple LFSR CRC-16 ccitt vhdl code for 1 bit error generator vhdl code 10 bit LFSR CRC-32 Ethernet CRC-16 and CRC-32 CRC-16 and CRC-32 Ethernet 32-bit LFSR 2128E vhdl code 32bit LFSR 2128E vhdl code 12 bit LFSR 2128E vhdl code 16 bit LFSR 2128E simple 32 bit LFSR using vhdl 2128E vhdl code CRC 32 2128E vhdl code 8 bit LFSR 2128E vhdl code CRC 2128E 2128E 2128E TEXT
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Abstract: XOR16 XOR16 Data In VHDL 32-bit CRC Serial Implementation VHDL code was written to implement a 32-bit serial CRC calculation. A 32-bit LFSR with clock enable is constructed by instantiating 32 D-type , a bit error as an 8-bit checksum when the data transmitted is in byte form. The problem can only be , 32-Bit Error Checking Using the ispLSI 2128E 2128E ® Introduction Error detection techniques allow a , that occur so that the checksum is internally consistent (i.e. multiple bit errors resulting in the ... Lattice Semiconductor
Original
datasheet

2 pages,
35.31 Kb

8 bit LFSR advantages CRC-32 LFSR vhdl code 4 bit LFSR vhdl code for 1 bit error generator vhdl code 32bit LFSR crc32 lfsr vhdl code CRC 32 vhdl code 10 bit LFSR vhdl code 8 bit LFSR vhdl code for crc16 using lfsr 2128E TEXT
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Abstract: : Number of DIs: Number of GLB Levels: VHDL 32-bit CRC Serial Implementation VHDL code was written to implement a 32-bit serial CRC calculation. A 32-bit LFSR with clock enable is constructed by instantiating , itself. Thus, a 32-bit summing checksum has the same probability of missing a bit error as an 8-bit , 32-Bit Error Checking Using the ispLSI 2128E 2128E ® and original data. CRCCs are very effective for , the checksum is internally consistent (i.e. multiple bit errors resulting in the same checksum). ... Lattice Semiconductor
Original
datasheet

2 pages,
30.99 Kb

CRC-32 CRC-16 CRC-12 XOR16 32-bit LFSR vhdl code 32bit LFSR vhdl code 8 bit LFSR vhdl code for 1 bit error generator vhdl code for 8 bit shift register CRC-16 and CRC-32 vhdl code for crc32 using lfsr 16 bit register vhdl simple 32 bit LFSR using vhdl 2128E CRC-16 and CRC-32 Ethernet 2128E vhdl code 12 bit LFSR 2128E vhdl code 16 bit LFSR 2128E vhdl code 10 bit LFSR 2128E vhdl code CRC 32 2128E vhdl code for crc16 using lfsr 2128E 2128E 2128E TEXT
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Abstract: primarily for operation with a transmission code known as 8B/10B 8B/10B. This code maps all possible 8-bit data , Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , 10-Bit Data Appendix C. Descrambler VHDL Source Code - DCSRAMRX.VHD - x9 + x4 + 1 descrambler , serial transmission and reception. The specific mappings of the of 8-bit data characters to 10-bit ... Cypress Semiconductor
Original
datasheet

21 pages,
299.5 Kb

8b/10b scrambler parallel scrambler vhdl code for 4 bit barrel shifter prbs generator using vhdl vhdl code cy7b933 8 bit barrel shifter vhdl code scrambler vhdl code for a 9 bit parity generator prbs using lfsr vhdl code for 16 prbs generator vhdl code for 8 bit common bus vhdl code for 8 bit parity generator 8B/10B vhdl code for 9 bit parity generator 8B/10B vhdl code 8 bit LFSR 8B/10B vhdl code for 8 bit barrel shifter 8B/10B VHDL CODE FOR 16 bit LFSR in PRBS 8B/10B 8B/10B 8B/10B TEXT
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Archived Files

Abstract Saved from Date Saved File Size Type Download
, 8-Bit FIR Filter Application Note (175 kb) This application note describes the functionality and integration of a 16-Tap, 8-Bit Finite Impulse Response (FIR) filter macro with predefined information via E-mail at dsp@xilinx.com . 16-Tap, 8-Bit FIR Filter Application Note (175 kb) This application note describes the functionality and integration of a 16-Tap, 8-Bit Finite Impulse case studies-a 16-tap, 8-bit fixed-point FIR filter and a 24-bit Viterbi decoder-demonstrate the
/datasheets/files/xilinx/weblinx/products/appsweb.htm
Xilinx 19/09/1996 24.83 Kb HTM appsweb.htm
Shift-Register (LFSR) counters to address the RAM makes the design even simpler. This application note describes 4- and 5-bit universal LFSR counters, very efficient RAM-based 32-bit and 100-bit shift registers timing paths. The design was created and simulated using Verilog. 16-Tap, 8-Bit FIR Filter 16-Tap, 8-Bit Finite Impulse Response (FIR) filter macro with predefined coefficients (e.g. low pass , LFSR Counters, and Long Psuedo-Random Sequence Generators (72 kB) Shift registers longer
/datasheets/files/xilinx/weblinx/apps/fpga-v1.htm
Xilinx 25/09/1996 10.88 Kb HTM fpga-v1.htm
Title Slide Presentation Title Here CryptoBlaze: 8-Bit Security Microcontroller 8-bit registers Set of Cryptographic processor architecture extensions ("KryptoKit") Field operations 12 macrocells Gates+flops GF(28) multiplier 8 bit 24 macrocells macrocells Serial input AES S-box 8 bit 384 ANDs,8 ORs Flops unused LFSRs Log (28) 8 bit 383 ANDs,8 ORs Flops unused Exp (28) 8 bit 370 ANDs,8 ORs
/datasheets/files/xilinx/files/cpld _modules/cryptoblaze.pps
Xilinx 08/03/2004 1209 Kb PPS cryptoblaze.pps
4- and 5-bit universal LFSR counters, very efficient RAM-based 32-bit and 100-bit shift registers 40 KB XAPP028 XAPP028 FPGAs VIEW logic   OrCAD Serial Code Conversion between BCD Asynchronous FIFO Designs 120 KB XAPP051 XAPP051 XC4000 XC4000   Efficient Shift Registers, LFSR Counters XC9500 XC9500 XC9536 XC9536 ISP Demo Board 50 KB XAPP078 XAPP078 XC9500 XC9500 ABEL   VHDL   4Mbit XC9500 XC9500 A CPLD VHDL Introduction 60 KB XAPP105 XAPP105 XC9500 XC9500 DES
/datasheets/files/xilinx/docs/wcd00002/wcd00206-v1.htm
Xilinx 16/02/1999 79.91 Kb HTM wcd00206-v1.htm
This application note describes 4- and 5-bit universal LFSR counters, very efficient RAM-based 32-bit XAPP010 XAPP010 XC4000 XC4000   LCA Speed Estimation: Asking the Right Question 8 kB XAPP011 XAPP011 OrCAD Serial Code Conversion between BCD and Binary 18 kB XAPP029 XAPP029 XC3000 XC3000 VIEW Designs 125 kB XAPP051 XAPP051 XC4000 XC4000   Efficient Shift Registers, LFSR Counters, and Long XAPP078 XAPP078 XC9500 XC9500 ABEL VHDL   CPLD-Based 1Mbit Virtual SPROM Downloader for XC4000-Series
/datasheets/files/xilinx/weblinx/apps/xapp.htm
Xilinx 11/04/1997 40.83 Kb HTM xapp.htm
high-speed FIFOs using the Block SelectRAM+ memory in the Spartan-II FPGAs. Verilog and VHDL code VHDL, UNIX Verilog, PC Verilog, UNIX /s DDR SDRAM Controller 100 KB 64-bit, PC 64-bit, UNIX 16-bit, PC 16-bit application note describes the reference controller design for a 64-bit DDR SDRAM. At a clock rate of
/datasheets/files/xilinx/docs/rp00001/rp001ed.htm
Xilinx 19/03/2000 25.07 Kb HTM rp001ed.htm
simpler. This application note describes 4- and 5-bit universal LFSR counters, very Serial Code Conversion between BCD and Binary 20 KB XAPP029 XAPP029 Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators 70 KB XAPP052 XAPP052 Board 50 KB XAPP078 XAPP078 XC9500 XC9500 ABEL VHDL   CPLD VHDL Introduction 60 KB XAPP105 XAPP105 XC9500 XC9500
/datasheets/files/xilinx/docs/rp00003/rp00319.htm
Xilinx 19/03/2000 192.75 Kb HTM rp00319.htm
AVR 8-Bit RISC Biometrics Bluetooth TM division of 8- and 16-bit signed and unsigned numbers. See Software section to download doc1973.zip . , updated 8/01) This Application Note explains how to use VHDL with IP Core Generator to implement the MARC4 4-bit Architecture Military & Avionics   AT94K AT94K Series Configuration (38 pages, updated 8/01) Configuration is the process by
/datasheets/files/atmel/atmel/prod318-v1.htm
Atmel 07/05/2002 74.52 Kb HTM prod318-v1.htm
AVR 8-Bit RISC Biometrics Bluetooth TM division of 8- and 16-bit signed and unsigned numbers. See Software section to download doc1973.zip . , updated 8/01) This Application Note explains how to use VHDL with IP Core Generator to implement the MARC4 4-bit Architecture Military & Avionics   AT94K AT94K Series Configuration (38 pages, updated 8/01) Configuration is the process by
/datasheets/files/atmel/atmel/prod318.htm-v1.bak
Atmel 07/05/2002 74.52 Kb BAK prod318.htm-v1.bak
No abstract text available
/download/39162463-995960ZC/xapp288.zip ()
Xilinx 26/04/2004 67.11 Kb ZIP xapp288.zip