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vhdl code 8 bit LFSR

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Abstract: Customizable VHDL source code available, allowing generation of different netlist versions · Customized , set of generics in the synthesizable VHDL source code of the core. Parameters allow the user to , Number of channel input bits - Number of channel output bits per channel input bit (allows emulation of , Generator (LFSR) definition parameters: LFSR size, LFSR feedback polynomial, LFSR seed (reset value , with Core Documentation User Manual Design File Formats EDIF netlist, XNF netlist, VHDL source Xilinx
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vhdl code 16 bit LFSR vhdl code 4 bit LFSR vhdl code 10 bit LFSR verilog code 8 bit LFSR verilog code 16 bit LFSR verilog code 32 bit LFSR I-10148 S40-3 V50-6
Abstract: SRLE16 clk X220_08_091100 Figure 8: 32-bit, 4-tap Parallel LFSR The code has been tested on the , shown in Figure 7. In the 32bit LFSR it will only use five SRL16s (Figure 8). Likewise a 64-bit LFSR , on the LUT that implements the SRL16E. An example of a 16-bit LFSR implemented in VHDL and Verilog , : Multicycle Tap Access LFSR HDL Code The reference design was written in both VHDL and Verilog HDL. The , : Utilization Summary (Appendix A Code 16 bit length LFSR) Synopsys FPGA Express v3.4 Synplicity Synplify Xilinx
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XAPP220 SRL16 simple LFSR verilog hdl code for parity generator 8 shift register by using D flip-flop VHDL 32-bit pn sequence generator vhdl code for 9 bit parity generator XAPP211 XAPP217
Abstract: 17: 52-bit LFSR Gold Code Generator Gold code generators are used in CDMA systems to generate , . This document provides generic VHDL and Verilog submodules and reference code examples for , as the output, emulating an 8-bit shift register. Note that since the address lines control the mux , Primitive Initialization in VHDL and Verilog Code A shift register can be initialized in VHDL or Verilog code for both synthesis and simulation. For synthesis, the INIT attribute is attached to the 16-bit Xilinx
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vhdl code for pn sequence generator fpga cdma by vhdl examples vhdl code for rs232 receiver using fpga vhdl code for 8 bit shift register gold code generator vhdl code for gold code XAPP465 RS232 DS228
Abstract: first bit of the new fill code is required to be output from the LFSR. The new serial fill sequence , -stage, 2-tap LFSR with SRL16s in a Virtex-II Device HDL Code Verilog and VHDL code examples have been , LFSR width are parameterizable. In the VHDL code, the number of taps, as well as, the tap points, and , of period seven bits at time it = 0 (Table 1). If the 7-bit code were to be repeating within a , level, a Gold Code generator is usually described by two polynomials that indicate the LFSR structure Xilinx
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pn sequence generator qpsk modulation VHDL CODE PN generator circuit 4 bit pn sequence generator 16 bit qpsk VHDL CODE verilog code 5 bit LFSR
Abstract: are fixed, however the tap points and LFSR width are parameterizable. In the VHDL code, the number of , of period seven bits at time t = 0 (Table 1). If the 7-bit code were to be repeating within a , LFSR structure to be implemented. LFSR 1 Gold Code Out LFSR 2 x211_01_012400 Figure 1 , , the following HDL code (Table 3) will infer a 64-bit shift register using SRLs rather than FFs. Table 3: 64-Bit SRL Shift Register Example VHDL Verilog Always @(posedge clk) begin process (clk Xilinx
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vhdl code 12 bit LFSR LFSR vhdl code gold sequence code c code 4 bit LFSR
Abstract: must know in advance when the first bit of the new fill code is required to be output from the LFSR , parameterizable. In the VHDL code, the number of taps, as well as, the tap points, and LFSR width are all , of period seven bits at time t = 0 (Table 1). If the 7-bit code were to be repeating within a , system level, a Gold Code generator is usually described by two polynomials that indicate the LFSR structure to be implemented. LFSR 1 Gold Code Out LFSR 2 x211_01_012400 Figure 1: Gold Code Xilinx
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simple 32 bit LFSR using verilog vhdl code PN code generator verilog code 8 bit LFSR application XCV50-6
Abstract: : Number of DIs: Number of GLB Levels: VHDL 32-bit CRC Serial Implementation VHDL code was written to implement a 32-bit serial CRC calculation. A 32-bit LFSR with clock enable is constructed by instantiating , itself. Thus, a 32-bit summing checksum has the same probability of missing a bit error as an 8-bit , 32-Bit Error Checking Using the ispLSI 2128E ® and original data. CRCCs are very effective for , the checksum is internally consistent (i.e. multiple bit errors resulting in the same checksum). Lattice Semiconductor
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vhdl code CRC vhdl code CRC 32 simple 32 bit LFSR using vhdl vhdl code 32bit LFSR 32-bit LFSR CRC-16 and CRC-32 Ethernet 150MH
Abstract: XOR16 Data In VHDL 32-bit CRC Serial Implementation VHDL code was written to implement a 32-bit serial CRC calculation. A 32-bit LFSR with clock enable is constructed by instantiating 32 D-type , a bit error as an 8-bit checksum when the data transmitted is in byte form. The problem can only be , 32-Bit Error Checking Using the ispLSI 2128E ® Introduction Error detection techniques allow a , that occur so that the checksum is internally consistent (i.e. multiple bit errors resulting in the Lattice Semiconductor
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vhdl code for crc16 using lfsr crc32 lfsr vhdl code for 1 bit error generator CRC-32 LFSR 8 bit LFSR advantages 1-800-LATTICE
Abstract: : Number of DIs: Number of GLB Levels: VHDL 32-bit CRC Serial Implementation VHDL code was written to implement a 32-bit serial CRC calculation. A 32-bit LFSR with clock enable is constructed by instantiating , itself. Thus, a 32-bit summing checksum has the same probability of missing a bit error as an 8-bit , 32-Bit Error Checking Using the ispLSI 2128E ® and original data. CRCCs are very effective for , the checksum is internally consistent (i.e. multiple bit errors resulting in the same checksum). Lattice Semiconductor
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16 bit register vhdl vhdl code for crc32 using lfsr CRC-16 and CRC-32 CRC-12 CRC-16 CRC-32
Abstract: primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data , Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , 10-Bit Data Appendix C. Descrambler VHDL Source Code - DCSRAMRX.VHD - x9 + x4 + 1 descrambler , serial transmission and reception. The specific mappings of the of 8-bit data characters to 10-bit Cypress Semiconductor
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VHDL CODE FOR 16 bit LFSR in PRBS vhdl code for 8 bit barrel shifter vhdl code for 8 bit parity generator vhdl code for 8 bit common bus vhdl code for 16 prbs generator prbs using lfsr CY7B923/933
Abstract: primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data , Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , 10-Bit Data Appendix C. Descrambler VHDL Source Code - DCSRAMRX.VHD - x9 + x4 + 1 descrambler , serial transmission and reception. The specific mappings of the of 8-bit data characters to 10-bit Cypress Semiconductor
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vhdl code scrambler prbs generator using vhdl vhdl code for 4 bit barrel shifter Using HOTLink vhdl code for nrz prbs pattern generator using vhdl
Abstract: application note describes 4- and 5-bit universal LFSR counters, very efficient RAM-based 32-bit and 100-bit , Verilog or VHDL code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade. XAPP132 , code (VHDL or Verilog) as well as "C" code are provided to augment the development of Handspring , Virtex 13 of FPGA, an analog comparator, and a few resistors and capacitors. An 8-bit ADC can be , FIFOs using the Block SelectRAM+ memory in the Spartan-II FPGAs. Verilog and VHDL code is available for Xilinx
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XAPP029 adc controller vhdl code verilog rtl code of Crossbar Switch XAPP172 Insight Spartan-II demo board verilog code for cdma transmitter Q4-01 XAPP004 XAPP005 XC3000 XAPP007 XAPP008
Abstract: period seven bits at time t = 0 (Table 1). If the 7-bit code were to be repeating within a discrete , feedback bit. LFSR Implementation There are two implementation styles of LFSRs, Galois implementation , Code Out LFSR 2 x217_03_0060700 Figure 3: Gold Code Generator Gold Code Generators using the LFSRs Implemented in Virtex Devices A 16-bit LFSR uses one slice in a Virtex device. A Virtex slice is , www.xilinx.com 1-800-255-7778 5 R Gold Code Generators in Virtex Devices Figure 4 is an 8-stage 4 Xilinx
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lfsr galois verilog hdl code for modulation direct sequence spread spectrum virtex GOLD CODE gold sequence generator XILINX CROSS REFERENCE
Abstract: of period seven bits at time t = 0 (Table 1). If the 7-bit code were to be repeating within a , . LFSR Terminology The basic functional block in Gold code generators are LFSRs. LFSRs sequence , generate the "parity" feedback bit. LFSR Implementation There are two implementation styles of LFSRs , Gold Code Out LFSR 2 x217_03_0060700 Figure 3: Gold Code Generator Gold Code Generators using the LFSRs A 16-bit LFSR uses one slice in a Virtex device. Each Virtex series CLB contains four logic Xilinx
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lfsr fibonacci vhdl code PN code 16bit pn sequence generator polynomial XCV50
Abstract: Grades) Xilinx FPGAs Source Code Provided Yes Source Code Format VHDL, Verilog Design , circuit that generates or checks a PRBS sequence is based on a linear feedback shift register (LFSR). In this application note, the bit sequence is indicated by the term PRBS, and the circuit that generates or checks it is indicated by the term LFSR. Table 1: PRBS Generator/Checker Attributes Attribute , OUT_BITS. Bit 0 is the oldest. In generate mode, this input is used to insert an error in the Xilinx
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XAPP884 XC5VLX30-FF324-1 verilog code of prbs pattern generator verilog code 16 bit LFSR in PRBS verilog prbs generator XC6VLX75T-FF484 XC6SLX4-TQG144-2
Abstract: .84 6-5 Convert Netlist Type.84 6-6 .85 E-1 8-bit LFSR.104 E , Output Decode - Gray Code Counter - LFSR Counter with Dynamic Count-to Flag - LFSR , DecoderNEC_SM01_DECODE 8-bit SM03, SM04 bit NEC_SM03_BICTR_DECODE Width = 8 NEC_SM03_BICTR_SCNTO , . 6. 7. OA AV 8 , · M7A98.8 4 A14353JJ3V0UM00 CB-C7 CB-7 CB-C8 CB-8 CB-C9 NEC
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vhdl code for Wallace tree multiplier vhdl code Wallace tree multiplier wallace-tree VERILOG 16 bit carry lookahead subtractor vhdl binary coded decimal adder Vhdl code vhdl code for wallace tree A14353JJ3V0UM003 CB-C10CB-10EA-C9EA-9EA-C9HDEA-9HD EA-C10EA-10 CB-10
Abstract: 124.4 MHz output (for des32.zip) or 8-bit 77 MHz output (for pbd_4chan_vlog.zip and pbd_4chan_vhdl.zip). Each channel has its own 16 5-bit (or 8-bit) word buffer. Since the 622 Mb/s input data stream , Modifying the Reference Design The elastic buffer itself has 16 5-bit (8-bit) locations. At reset, the read , des32.vhd RTL code provided in the reference design, the 5-bit output ports of the output elastic buffers , to the backend portion of the design. Similarly, modify the 8-bit output ports in pbd_4chan_vlog and Xilinx
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XAPP671 vhdl code for clock and data recovery CLK180 testbench vhdl ram 16 x 4 PPC405 XC2V1000
Abstract: Application Note: CoolRunner-II CPLDs R CryptoBlaze: 8-Bit Security Microcontroller XAPP374 , www.xilinx.com 1-800-255-7778 1 R CryptoBlaze: 8-Bit Security Microcontroller 8 8 Port Address Control READ_STROBE 8 WRITE_STROBE 8 IN_PORT PORT_ID 8 Registers 8-bit 8 8 , , sY www.xilinx.com 1-800-255-7778 XAPP374 (v1.0) September 26, 2003 R CryptoBlaze: 8-Bit , www.xilinx.com 1-800-255-7778 3 R CryptoBlaze: 8-Bit Security Microcontroller Table 2: Krypto Kit Xilinx
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XC2C64 gf multiplier vhdl program binary multiplier gf Vhdl code picoblaze architecture gf multiplier program picoblaze galois field theory XC2C32 XC2C128 XC2C256 XC2C384 XC2C512
Abstract: 8-bit LFSR ddr_cke lfsr_data ddr_cs lfsr_clk ddr_ras int_cmd Initialization & Test , 100 MHz operation. The VHDL code described here can be found in VHDL Code, page 19. Introduction , VHDL code. Table 1: DDR SDRAM Signal Definitions Manufacturer Specification Xilinx CPLD VHDL , ] Bidirectional 8-bit data bus. DQS ddr_dqs Description Command signals that define current operation , 31% Registers 50 128 39% Function Block Inputs VHDL Code Used 103 320 Xilinx
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XAPP384 vhdl sdram MT45V16M8 8 bit LFSR XC2C256-6TQ144 MT46V16M8 TN-46-05
Abstract: structural VHDL · Probability density function (PDF) deviates less than 0.2 percent from the Gaussian , and 11 bits of fraction Design File Formats · 760-bit internal seed selectable through , Provided with Core Documentation Verification Product Specification VHDL UCF MATLAB + ModelSim + Hardware VHDL Wrapper Additional Items BER Measurement of Uncoded BPSK in Hardware , measuring the bit error rate (BER) performance of a communication system. Simulation ModelSim PE 5.4e Xilinx
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DS210 BPSK modulation VHDL CODE vhdl code for bpsk modulation hardware implementation of bpsk bpsk simulink matlab QPSK using xilinx qpsk simulink matlab XIP2229
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