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vhdl code for pseudo random sequence generator

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vhdl code for 32 bit pn sequence generator

Abstract: vhdl code 8 bit LFSR Verilog and VHDL code examples have been written for the PN Generator module. The PN Generator provides , being transmitted is spread across a wide radio spectrum using a pseudo random binary sequence unique to each user. Every data bit of a user signal is multiplied by many bits of a pseudo random binary sequence. This sequence is created by a PN generator and often referred to as a PN-Code. The PN-Codes , m-sequences (S), for a given length of shift register is defined by: S (L - 1) ÷ N Gold Code Generator
Xilinx
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pn sequence generator

Abstract: verilog code 16 bit LFSR being transmitted is spread across a wide radio spectrum using a pseudo random binary sequence unique to each user. Every data bit of a user signal is multiplied by many bits of a pseudo random binary sequence. This sequence is created by a PN generator and often referred to as a PN-Code. The PN-Codes , schemes. The PN Generator HDL code therefore implements two LFSRs, one for the "I" channel and one for , Generators A Pseudo-random Noise (PN) sequence/code is a binary sequence that exhibits randomness
Xilinx
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simulation for prbs generator in matlab

Abstract: block diagram prbs generator in matlab 16-bit pseudo random binary sequence (PRBS) generator which is initialized at beginning of a Data , 2 for MW_ ATSC Modulator Core emission mask. Core Modifications Source code uses VHDL generics , Provided with Core Documentation S.r.l. User Guide Design File Formats VHDL synthesizable source code, NGC implementation file MindWay S.r.l. Constraints Files Centro Direzionale , Xilinx ISE User Constrains File VHDL Test Bench and Test Vectors Instantiation Templates VHDL
Xilinx
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verilog code 16 bit LFSR

Abstract: verilog code 8 bit LFSR being transmitted is spread across a wide radio spectrum using a pseudo random binary sequence unique to each user. Every data bit of a user signal is multiplied by many bits of a pseudo random binary sequence. This sequence is created by a PN generator and often referred to as a PN-Code. The PN-Codes , Using the SRL Macro HDL Code R Verilog and VHDL code examples have been written for the PN , Generator HDL code therefore implements two LFSRs, one for the "I" channel and one for the "Q" channel. In
Xilinx
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vhdl code for ofdm

Abstract: vhdl code for ofdm transmitter block inverts a sync byte every eight sync byte received.The polynomial for the pseudo random binary sequence (PRBS) generator is: 1 + x14 + x15. The sync byte of the first packet is bit-wise inverted from 47HEX to B8HEX, and the PRBS generator is loaded with the seed sequence "100101010000000". During the , the mother code are G1=171OCT for X output and G2=133 OCT for Y output. The two bit stream, X and Y , insertion. Core Modifications Source code uses VHDL generics in order to customize MW_DVB-T/H Modulator
Xilinx
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vhdl code for ofdm vhdl code for ofdm transmitter OFDM Matlab code ofdm code in vhdl OFDM QPSK simulation VHDL PROGRAM for ofdm

vhdl code for ofdm

Abstract: ofdm matlab simulation block for the pseudo random binary sequence (PRBS) generator is: 1 + x14 + x15. The sync byte of the first packet is bit-wise inverted from 47HEX to B8HEX, and the PRBS generator is loaded with the seed sequence , for a range of puntured convolutional codes, based on a mother convolutional code of rate 1/2 with 64 , polynomials of the mother code are G1=171OCT for X output and G2=133 OCT for Y output. The two bit stream, X , symbols by guard interval insertion. Core Modifications Source code uses VHDL generics in order to
Xilinx
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ofdm matlab simulation block vhdl code for 16 prbs generator prbs generator using vhdl vhdl code for pseudo random sequence generator vhdl code for block interleaver 4585 dvb

vhdl code 16 bit LFSR

Abstract: verilog code 16 bit LFSR . This document provides generic VHDL and Verilog submodules and reference code examples for , in the proper data. This requires predictable timing for the load command. VHDL Inference Code , design. Templates for the SHIFT_REGISTER_16_C module are provided in VHDL and Verilog code as an , special type of PN sequence is a Gold code generator, which can be created from SRL16-based LFSRs. · , Primitive Initialization in VHDL and Verilog Code A shift register can be initialized in VHDL or Verilog
Xilinx
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SRL16 vhdl code 16 bit LFSR verilog code 16 bit LFSR VHDL 32-bit pn sequence generator vhdl code for 32 bit pn sequence generator vhdl code for shift register using d flipflop vhdl code for pn sequence generator XAPP465 SRL16E RS232 DS228

vhdl code CRC 32

Abstract: vhdl code for pseudo random sequence generator in backoff. A maximal length pseudo random sequence generator is seeded and is used to generate the integer , padding. RANDOM_SEED[9:0] Input Seed value for random number generator used to compute backoff LOAD_RANDOM_SEED Input Goes high for a period more than one clock in order to load RANDOM_SEED into backoff random , perform special modifications for additional charge. However source code is available for each core for , detection Extensive statistics information on transmit frames for RMON and MIBs Media Independent Interface
Xilinx
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vhdl code CRC 32 vhdl code for pseudo random sequence generator in vhdl code for ethernet mac spartan 3 4000EX 4028EX-2 V150-4 V200-4 V300-4 4028EX

VHDL CODE FOR 16 bit LFSR in PRBS

Abstract: vhdl code for 8 bit barrel shifter . The full VHDL source code for the PLDs in this application note is listed in Appendixes B and C. This , Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data , documented in this application note. Schematics and VHDL code are included in this document. Serial
Cypress Semiconductor
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VHDL CODE FOR 16 bit LFSR in PRBS vhdl code for 8 bit barrel shifter vhdl code 8 bit LFSR vhdl code for 9 bit parity generator vhdl code for 8 bit parity generator vhdl code for 8 bit common bus CY7B923/933

vhdl code scrambler

Abstract: prbs generator using vhdl . The full VHDL source code for the PLDs in this application note is listed in Appendices B and C. This , Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data , documented in this application note. Schematics and VHDL code are included in this document. Serial
Cypress Semiconductor
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vhdl code scrambler vhdl code for 4 bit barrel shifter vhdl code for 7 bit pseudo random sequence generator vhdl code for 16 bit Pseudorandom Streams Generation Using HOTLink vhdl code for nrz

vhdl code for ethernet mac spartan 3

Abstract: vhdl code for 8-bit calculator pseudo random sequence generator is seeded and is used to generate the integer. January 10, 2000 , Input TRUE enables short frame padding. RANDOM_SEED[9:0] Input Seed value for random number generator used to compute backoff LOAD_RANDOM_SEED Input Goes high for a period more than one clock in order to load RANDOM_SEED into backoff random number generator. Host Interface TXMITTER_ENB Input , perform special modifications for additional charge. However source code is available for each core for
Xilinx
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vhdl code for 8-bit calculator CRC-32 vhdl code CRC 4000X

vhdl code for 16 prbs generator

Abstract: vhdl code for 9 bit parity generator Frame Personal Computer Performance Monitor Pseudo Random Bit Sequence Remote Defect Indication , Generator transmits codes to the C-bit parity FEAC channel via the TXFRMR. The idle code is used to disable , . Software generates a pseudo random payload bit pattern with a length of 216-to-1. The result is fed back , . rndata Input Line receive negative data for dual rail interface lcv Input Line code , countries. Altera Corporation acknowledges the trademarks of other organizations for their respective
Altera
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free verilog code of prbs pattern generator verilog code for pseudo random sequence generator in vhdl code for a 9 bit parity generator sonet testbench CRC-16 GR-499-CORE

simple 32 bit LFSR using verilog

Abstract: verilog hdl code for traffic light control functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators Support for , ; the MegaWizard Plug-In Manager supports VHDL and Verilog HDL. For this example, select Verilog HDL , industry-standard VHDL and Verilog HDL simulators. c You may use these models only for simulation and not for , for products or services. UG-0705-1.10 Contents Chapter 1. About This MegaCore Function , ) File Generation (For the Verilog HDL Testbench) . . . . . . . . . . . . . . . . 5­8 Testbench Time-Out
Altera
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simple 32 bit LFSR using verilog verilog hdl code for traffic light control cyclic redundancy check verilog source 25.263 verilog code 10 bit LFSR in scrambler verilog code 8 bit LFSR in scrambler

vhdl code for traffic light control

Abstract: vhdl code for crc16 using lfsr series Lane order reversal IP functional simulation models for use in Altera-supported VHDL , . 4. Select the output file type for your design; the MegaWizard Plug-In Manager supports VHDL , requires cyclic redundancy code (CRC) checking, turn on the Enable CRC option for your chosen packet type , allows for fast functional simulation of IP using industry-standard VHDL and Verilog HDL simulators. c , for products or services. UG-0705-1.11 Contents Chapter 1. About This MegaCore Function
Altera
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vhdl code for traffic light control vhdl code for crc16 using lfsr SerialLite verilog code for traffic light control vhdl code 16 bit LFSR with VHDL simulation output 8B10B

vhdl code for pseudo random sequence generator in

Abstract: vhdl code for pseudo random sequence generator backoff. A maximal length pseudo random sequence generator is seeded and is used to generate the integer , Input TRUE enables short frame padding. RANDOM_SEED[9:0] Input Seed value for random number generator used to compute backoff LOAD_RANDOM_SEED Input Goes high for a period more than one clock in order to load RANDOM_SEED into backoff random number generator. Host Interface TXMITTER_ENB Input , additional charge. However source code is available for each core for additional cost where the customer can
Xilinx
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implement 16-bit CRC in transmitter and receiver am transmitter and receiver circuit diagram 802.3 CRC32 vhdl 4-bit binary calculator vhdl code for 4 bit pseudo random sequence generator XC4028EX-2

LEON3FT

Abstract: M Meiko ) Single-vector trapping for reduced code size Advanced debug support unit Optional IEEE-STD-754 compliant FPU , VHDL source code or as a pre-synthesized netlist. The LEON3-FT core is available as a pre-synthesized , -2 divider (non-restoring) · Single-vector trapping for reduced code size Copyright Aeroflex Gaisler , trapping (SVT) is an SPARC V8e option to reduce code size for embedded applications. When enabled, any , policies can be selected: least-recentlyused (LRU), least-recently-replaced (LRR) or (pseudo-) random. If
Aeroflex Gaisler
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LEON3FT M Meiko multiplier accumulator MAC code VHDL algorithm leon3 leon processor interrupt vhdl fpu coprocessor IEEE-754

vhdl code for 16 prbs generator

Abstract: verilog code for pseudo random sequence generator in randomizer is a pseudo random binary sequence (PRBS) generator whose output is XORed with the clear data , Experience For the source code version, users should be familiar with Verilog HDL entry, synthesis , convolutional code rates of: 1/2, 2/3, 3/4, 5/6, and 7/8 · Supports uncoded (1/1) operation · DC to 45+ MHz symbol rate (RS) · DC to 70+ MHz bit rate (at 7/8 code rate). Supports SONET STS-1 bit rate at code , xfmoddvb.ucf Verification Verilog Testbench Instantiation Templates VHDL, Verilog Reference Designs &
Xilinx
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qpsk modulation VHDL CODE EN-300-421 0x47 interleaver by vhdl Convolutional Puncturing vhdl V50-4

verilog hdl code for encoder

Abstract: X9013 .1.2, describes a data randomizer to "ensure adequate binary transitions". The randomizer is a pseudo random binary sequence (PRBS) generator whose output is XORed with the clear data stream on the transmitter side , of Puncturing with RATE_SEL[2:0] Recommended Design Experience For the source code version, users , Selectable convolutional code rates of: 1/2, 2/3, 3/4, 5/6, and 7/8 Supports uncoded (1/1) operation DC to 45+ MHz symbol rate (RS) DC to 70+ MHz bit rate (at 7/8 code rate). Supports SONET STS-1 bit rate at code
Xilinx
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verilog hdl code for encoder X9013 digital FIR Filter verilog code polyphase QPSK using xilinx

RTAX2000

Abstract: leon3 ) Single-vector trapping for reduced code size Advanced debug support unit Optional IEEE-STD-754 compliant FPU , available in VHDL source code or as a pre-synthesized netlist. The LEON3-FT core is available as a , ) Single-vector trapping (SVT) is an SPARC V8e option to reduce code size for embedded applications. When enabled , policies can be selected: least-recentlyused (LRU), least-recently-replaced (LRR) or (pseudo-) random. If , cache or as a multi-set cache with associativity of 2 - 4 implementing either LRU or (pseudo-) random
Aeroflex Gaisler
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RTAX2000 RTAX2000S vhdl code 64 bit FPU IEEE-1754 leon3 vhdl model 32x32-Bit

verilog code for dual port ram with axi interface

Abstract: XC6SLX25T-2CSG324 Generator v7.1 RAM will see the following sequence of addresses for Read requests: 0x04h, 0x08h, 0x0Ch , Memory Generator to the latest version of the Block Memory Generator. 3. For the supported versions of , Optimized VHDL and Verilog behavioral models for fast simulation times; structural simulation models for , Block Memory Generator core produce optimized solutions to provide convenient access to memories for a , , the Block Memory Generator core provides byte-Write support for memory widths which are multiples of
Xilinx
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verilog code for dual port ram with axi interface XC6SLX25T-2CSG324 UG473 verilog code for dual port ram with axi lite interface blk_mem_gen hamming code in vhdl DS512
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