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LT5534ESC6PBF Linear Technology RF/Microwave Detector, 50 MHz - 3000 MHz RF/MICROWAVE LINEAR DETECTOR, LEAD FREE, PLASTIC, SC-70, MO-203AB, 6 PIN visit Linear Technology - Now Part of Analog Devices
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vhdl code for phase frequency detector for FPGA

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vhdl code for loop filter of digital PLL

Abstract: vhdl code for All Digital PLL ) Testbenches for the CDR (VHDL) X868_08_121707 Figure 8: Reference Design Analysis Directory Code , Application Note: Virtex and Spartan FPGA Families Clock Data Recovery Design Techniques for E1 , telecommunications applications (digital oscillator, phase detector, and filter design criteria) and evaluates them , to "Reference Design Analysis," page 8 for how to customize the center frequency of the VCO. For , pins available. If n is the number of channels, the FPGA slices for all the channel (Rn) are given by
Xilinx
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vhdl code for phase frequency detector for FPGA

Abstract: vhdl code for PLL Frequency Fine Tuning and Clock Dithering Using Actel FPGA Devices The following is an example of VHDL , different operating point (phase or frequency) to compensate for the phase difference at the inputs of the , /frequency of the signal sent to the phase detector feedback input. This causes the VCO to operate faster or , Application Note AC231 Frequency Fine Tuning and Clock Dithering Using Actel FPGA Devices , extremely sensitive to the frequency changes. In these cases it is vital for the PLL to remain locked while
Actel
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vhdl code for phase frequency detector for FPGA vhdl code for PLL vhdl code for phase frequency detector vhdl code up down counter vhdl code for frequency divider TUNER 500 MHz module

vhdl code for demultiplexer

Abstract: vhdl GPCM .5 UPM Read and Write Access Waveforms .8 VHDL Code for the FPGA System Bus Interface , Freescale Semiconductor VHDL Code for the FPGA System Bus Interface 3 VHDL Code for the FPGA , drives the clock tree of FPGA logic. The remainder of this section presents the VHDL code for the FPGA , . FPGA System Bus Interface for MSC81xx, Rev. 0 Freescale Semiconductor 9 VHDL Code for the , Bus Interface for MSC81xx, Rev. 0 10 Freescale Semiconductor VHDL Code for the FPGA System Bus
Freescale Semiconductor
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vhdl code for demultiplexer vhdl GPCM digital clock vhdl code vhdl code for multiplexer 4 to 1 using 2 to 1 vhdl code for multiplexer 32 BIT BINARY vhdl code for time division multiplexer AN2823 MSC81

vhdl code for phase frequency detector

Abstract: vhdl code for multiplexer 64 to 1 using 8 to 1 FPGA Handbook Digital Clock Managers (DCMs) R Frequency Mode for Frequency Synthesis This , distribution network (but it can also be from an output pin). The phase detector steers the controller to , DCM, which also includes phase adjustment, frequency synthesis, and spread spectrum techniques that , the input frequency. The reset input signal is asynchronous and should be held HIGH for at least 2 ns. It takes approximately 120 µs for the DCM to achieve lock after a reset in the slowest frequency
Xilinx
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vhdl code for multiplexer 64 to 1 using 8 to 1 vhdl code for DCM vhdl code for Digital DLL CLK2X180 UG012

vhdl code for phase frequency detector

Abstract: vhdl code for DCM drives the select inputs of this multiplexer. The phase detector in this controller compares the incoming , output pin). The phase detector steers the controller to adjust the tap selection, and thus the , input clock whenever that is mathematically possible. For example, M=9 and D=5, multiply the frequency , every 9 output periods. · Phase Shifting: Three outputs drive the same frequency as CLCK0 but are , circuit is part of the DCM, which also includes phase adjustment, frequency synthesis, and spread spectrum
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CLKFX180 dcm verilog code UG002 CLK90 CLK180

MCP8260

Abstract: vhdl code for n bit generic counter System Bus Interface for the MPC8260, Rev. 0 Freescale Semiconductor 7 VHDL Code For the FPGA System Bus Interface 3 VHDL Code For the FPGA System Bus Interface This section covers the , MPC8260, Rev. 0 8 Freescale Semiconductor VHDL Code For the FPGA System Bus Interface , Semiconductor 9 VHDL Code For the FPGA System Bus Interface signal signal signal signal signal , Semiconductor 11 VHDL Code For the FPGA System Bus Interface i_module_reset p_reset
Freescale Semiconductor
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AN2889 MRC6011 MCP8260 vhdl code for n bit generic counter SW11 vhdl code for 32bit parity generator AN2890

vhdl code

Abstract: MDR 14 pin Single-Bus mode FPGA MDR Interface for the MRC6011, Rev. 0 4 Freescale Semiconductor VHDL Code For , BlockRAM. FPGA MDR Interface for the MRC6011, Rev. 0 16 Freescale Semiconductor VHDL Code For , the Xilinx® field-programmable gate array (FPGA) using VHDL. VHDL is an acronym that stands for , .4 System Bus .4 VHDL Code For the , FPGA implementation consult AN2889, FPGA System Bus Interface for the MPC8260: A VHDL Reference Design
Freescale Semiconductor
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vhdl code MDR 14 pin final year fpga project vhdl code for 16 bit dsp processor MDR connector vhdl code for digital clock

vhdl code for 8 bit barrel shifter

Abstract: verilog code for barrel shifter The phase detector (PD) looks for transitions in the incoming data, continuously comparing the phase , polynomial x15 + 1. The VHDL and Verilog code for both the generator and the checker can be found in the , frequency to minimize the phase error, thus realizing the phase-locked loop (PLL) functionality of the , RST pin is provided for debug and simulation purposes. The Virtex-5 FPGA GTP/GTX transceivers need , MHz Notes: 1. For details, refer to the Virtex-5 FPGA data sheet [Ref 7]. For any choice of
Xilinx
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vhdl code for 8 bit barrel shifter verilog code for barrel shifter vhdl code for 16 prbs generator vhdl code for loop filter of digital PLL vhdl code for 4 bit barrel shifter ML523 XAPP875 DS202

verilog code for barrel shifter

Abstract: vhdl code for 8 bit barrel shifter The phase detector (PD) looks for transitions in the incoming data, continuously comparing the phase , the generator and the checker is based on the polynomial x15 + 1. The VHDL and Verilog code for both , frequency to minimize the phase error, thus realizing the phase-locked loop (PLL) functionality of the , for debug and simulation purposes. The Virtex-5 FPGA GTP/GTX transceivers need to be reset , -3 187.5 MHz Notes: 1. For details, refer to the Virtex-5 FPGA data sheet [Ref 7].
Xilinx
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XAPP868 vhdl code Pseudorandom Streams Generator prbs pattern generator using vhdl vhdl code for clock and data recovery prbs generator using vhdl verilog code for 16 bit barrel shifter verilog code of parallel prbs pattern generator

4x4 unsigned multiplier VERILOG coding

Abstract: 32x32 multiplier verilog code frequency locked to REFCLK for proper operation. Clock from FPGA used to clock RX data and status between , the FPGA logic (42 ports for GT_ETHERNET and GT_FIBRE_CHAN). Table 2-1 contains the port descriptions , multiplied for parallel/serial conversion) and clock recovery. REFCLK frequency is accurate to ± 100 ppm , -bit interface to the FPGA core. See the 8B/10B section for more details. If 8B/10B encoding is enabled, this bus , Virtex-II Pro Platform FPGA Handbook Rocket I/O Transceiver Table 2-4: Default Attribute Values for
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4x4 unsigned multiplier VERILOG coding 32x32 multiplier verilog code vhdl code for lvds driver 12v relay interface with cpld in vhdl MULT18X18 verilog/verilog code for lvds driver PCI64 DO-DI-PCI64-IP

XAPP029

Abstract: adc controller vhdl code available for implementing state machines in FPGA devices. In particular, the one-hot-encoding scheme for medium-sized state machines is discussed. XAPP028 Frequency/Phase Comparator for Phase Locked Loops The , FIFOs using the Block SelectRAM+ memory in the Spartan-II FPGAs. Verilog and VHDL code is available for , Scan Emulator for XC3000 CLBs are used to emulate IEEE 1149.1 Boundary Scan. The FPGA device is , the XC3000 series of FPGA devices. This information supplements the data sheets, and is provided for
Xilinx
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XAPP029 adc controller vhdl code verilog rtl code of Crossbar Switch 12-bit ADC interface vhdl code for FPGA Insight Spartan-II demo board vhdl code for pn sequence generator Q4-01 XAPP004 XAPP005 XAPP007 XAPP008 XAPP009

4x4 unsigned multiplier VERILOG coding

Abstract: 4x4 signed multiplier VERILOG coding the IBUFG and BUFG when the corresponding input signal is used as a clock in the VHDL or Verilog code. A high frequency or adapted (frequency, phase, and so forth) clock distribution with low skew is , Templates" on page 170) for all primitives and submodules. In VHDL, each template has a component , multiplexer. The phase detector in this controller compares the incoming clock signal (CLKIN) against a , the internal clock distribution network (but it can also be from an output pin). The phase detector
Xilinx
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XC2V1000-4 4x4 signed multiplier VERILOG coding 80C31 instruction set verilog code of 4 bit magnitude comparator image enhancement verilog code VHDL CODE FOR HDLC controller 3x3 multiplier USING PARALLEL BINARY ADDER XC2V1000 FG456-5 XC2V1000-5

matched filter in vhdl

Abstract: XAPP012 in XC3000 Series Implementing State Machines in FPGA Devices Frequency/Phase Comparator for Phase , Register Based FIFO Boundary Scan Emulator for XC3000 Complex Digital Waveform Generator Harmonic Frequency , Question Quadrature Phase Detector Using the Dedicated Carry Logic in XC4000E Ultra-Fast Synchronous , CPLD VHDL Introduction v2.0 (08/30/01) Synopsys/Xilinx High Density Design Methodology Using FPGA , Virtex-E Device to a Pentium Processor v1.0 (12/15/00) Synthesizable FPGA Interface for Retrieving ROM
Xilinx
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XAPP012 matched filter in vhdl vhdl code for crossbar switch verilog code for cdma transmitter verilog code for 16 kb ram verilog code for crossbar switch XC4000 XC4000/XC5200 XAPP010 XAPP011 XAPP013
Abstract: a design and generates programming files for FPGA design files, a similar flow exists in the , quartus_asm executable to generate programming files for FPGA configuration. The following example creates , The programing files are used to program and configure the FPGA. 1 For command line help, type , Design Flow for Xilinx Users March 2013 Altera Corporation Quartus II Approach to FPGA Design , following subsections present the Altera equivalents for Xilinx ISE GUI features. Figure 2. Typical FPGA Altera
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AN-307-7

XAPP1064

Abstract: BUFIO2 and phase detector circuitry. ISERDES and OSERDES Guidelines Each Spartan-6 FPGA input/output , , further CAL functions do not require an RST. Phase Detector and Board Deskew The Spartan-6 FPGA , the phase detector mode. Specifically, two data lines cannot enter the device in adjacent master and , or less and the phase detector mode is not being used because the SerDes is not cascaded. However, by not using the phase detector mode, data loss will occur during calibration and the application
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XAPP1064 BUFIO2 ISERDES2 iodelay ISERDES spartan 6 OSERDES

vhdl code for traffic light control

Abstract: UG070 match new Figure 7-12. "IDELAY VHDL and Verilog Instantiation Template": Changed port map for C, CE , Event 4. "Frequency Synthesizer Characteristics" in Chapter 2: Added note to indicate no need for the , Block RAM Initialization in VHDL or Verilog Code . . . . . . . . . . . . . . . . . . . . . . . . 130 , Virtex-4 FPGA User Guide UG070 (v2.6) December 1, 2008 R R Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in
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vhdl code for traffic light control byb 504 sso-12 RAMB16 MAX6627 FPGA Virtex 6 PCI33 PCI66 SSTL18

circuit diagram of 8-1 multiplexer design logic

Abstract: Signal Path Designer a phase detector and filter, adjusts the oscillator phase to compensate for the clock distribution , Xilinx Design Reuse Methodology for ASIC and FPGA Designers SYSTEM-ON-A-CHIP DESIGNS REUSE , years ago. In the past, FPGA were primarily used for prototyping and lower volume applications; custom , year 2004, the state-of-the-art FPGA will exceed 10 million system gates, allowing for multimillion , of new FPGA architectures designed for system level integration and FPGA design tools that are
Xilinx
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circuit diagram of 8-1 multiplexer design logic Signal Path Designer verilog code for distributed arithmetic VERILOG Digitally Controlled Oscillator

vhdl code for phase frequency detector

Abstract: vhdl code for phase frequency detector for FPGA -state phase frequency detector and a delay line phase detector are used in this design for clock recovery and data synchronization. There are two phase frequency detectors (PFDs) in the phase detector block. One , both phase and frequency detector (PFD). A state diagram for the circuit is shown in Figure 4. State , includes a delay-line phase detector, a standard phase and frequency detector (PFD), a VCO, a loop filter , switches the VCO correction values to the inputs of the delay line phase ­ frequency detector (DLPFD). The
Xilinx
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XAPP250 XAPP224 maxim vco XAPP224 DATA RECOVERY verilog code for phase detector wolaver vhdl code for DCO

OSERDES

Abstract: oserdes2 DDR spartan6 and phase detector circuitry. ISERDES and OSERDES Guidelines Each Spartan-6 FPGA input/output , , further CAL functions do not require an RST. Phase Detector and Board Deskew The Spartan-6 FPGA , the phase detector mode. Specifically, two data lines cannot enter the device in adjacent master and , or less and the phase detector mode is not being used because the SerDes is not cascaded. However, by not using the phase detector mode, data loss will occur during calibration and the application
Xilinx
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oserdes2 DDR spartan6 oserdes2 serdes clock_generator_ddr_s8_diff testbench of a oserdes2 in verilog Clock-Generator

vhdl code for phase frequency detector for FPGA

Abstract: vhdl projects abstract and coding Verilog HDL and VHDL code examples, for getting the best performance and resource utilization from your , from the phase frequency detector (PFD) pfdena PLL lock status locked LOCK (1 indicates , References Chapter 7 83 Attributes and Preferences for FPGA Designs 85 About Attributes 86 , Resource GSR for fMAX Improvement 116 Instantiating Dedicated Resource GSR in RTL Code 116 Improving , of FPGA to another offers many challenges. "Moving Designs from Altera " on page 3 (for former users
Lattice Semiconductor
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SRL16 vhdl projects abstract and coding design of FIR filter using vhdl abstract FIR filter verilog abstract virtex ucf file 6 L6MUX21 xilinx vhdl code for floating point square root o
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