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LTC1093CSW#PBF Linear Technology LTC1093 - 1, 2, 6 and 8 Channel, 10-Bit Serial I/O Data Acquisition Systems; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1093CSW#TRPBF Linear Technology LTC1093 - 1, 2, 6 and 8 Channel, 10-Bit Serial I/O Data Acquisition Systems; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1093CSW Linear Technology LTC1093 - 1, 2, 6 and 8 Channel, 10-Bit Serial I/O Data Acquisition Systems; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1093CSW#TR Linear Technology LTC1093 - 1, 2, 6 and 8 Channel, 10-Bit Serial I/O Data Acquisition Systems; Package: SO; Pins: 16; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC1093CN Linear Technology LTC1093 - 1, 2, 6 and 8 Channel, 10-Bit Serial I/O Data Acquisition Systems; Package: PDIP; Pins: 16; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
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vhdl code for binary data serial transmitter

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cyclic redundancy check verilog source

Abstract: vhdl code manchester encoder data cell, and a logic "0" is represented by a low level. Manchester code represents binary values by , . A UART is a serial communication circuit which uses NRZ code. To sample at mid-bit of the data cell , as reference for clock recovery, center sampling mdi Input Serial manchester data input , for the transmitter and receiver to distinguish between a command and data. Since the 3-bit wide , Verilog) Code Download Manchester Encoder-Decoder for Xilinx CPLDs VHDL (or Verilog) source code
Xilinx
Original

vhdl code manchester encoder

Abstract: manchester verilog decoder _01_032700 Figure 1: Binary Values for NRZ and Manchester Codes Relative Advantages of NRZ/ Manchester Code , 1-800-255-7778 5 Manchester Encoder-Decoder for Xilinx CPLDs VHDL (or Verilog) Code Download R VHDL (or Verilog) source code and test benches are available for this design. THE DESIGN IS PROVIDED , Encoder-Decoder for Xilinx CPLDs Summary This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder. The reasons to use Manchester code are
Xilinx
Original

vhdl code manchester encoder

Abstract: vhdl code for manchester decoder _01_032700 Figure 1: Binary Values for NRZ and Manchester Codes Relative Advantages of NRZ/ Manchester Code , www.xilinx.com 1-800-255-7778 5 Manchester Encoder-Decoder for Xilinx CPLDs VHDL (or Verilog) Code Download R VHDL (or Verilog) source code and test benches are available for this design. THE DESIGN , Encoder-Decoder for Xilinx CPLDs Summary This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder. The reasons to use Manchester code are
Xilinx
Original

lms algorithm using verilog code

Abstract: lms algorithm using vhdl code Data Communication (Telecom and Datacom) Digital Signal Processing (DSP) For additional details on , directly for an authorization code; the AMPP partner will generate this code based on your MAX+PLUS II PC , File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL instantiation templates Megafunction , II software. The MAX+PLUS II software for PCs uses an embedded license system, based on the serial , offer pre-synthesized and pre-verified solutions for standard serial and parallel buses. Using AMPP
Altera
Original

16650 uart

Abstract: uart 16650 timing communication bits (start, stop, and parity) to or from the serial data In UART mode receiver and transmitter , for INT buff. Parallel data output Driver disable output Transmitter ready output Receiver ready , Asynchronous Receiver/Transmitter (UART) functionally identical to the OX16C950. The D16950 allows serial , and increase system efficiency by automatically controlling serial data flow through the RTS output , synchronize by external clock connected to RI ( for receiver and transmitter) or to DSR ( only for receiver
Digital Core Design
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16650 uart uart 16650 timing vhdl code for fifo and transmitter uart 16750 baud rate "flow control" test bench verilog code for uart 16550 verilog code for 8 bit shift register D16450 D16550 D16750 D16552 D16752 D16754

16750 UART texas instruments

Abstract: vhdl code for fifo and transmitter Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C750. The D16750 allows serial , 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions , efficiency by automatically controlling serial data flow through the RTS output and the CTS input signals , receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data Independently controlled transmit, receive, line status, and data set
Digital Core Design
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16750 UART texas instruments uart 16750 verilog code for 8 bit fifo register uart 16750 baud rate vhdl code for binary data serial transmitter parallel to serial conversion verilog D16X50

design IP Uarts using verilog HDL

Abstract: uart vhdl code fpga serial data In UART mode receiver and transmitter are double buffered to eliminate a need for , VHDL, Verilog source code called HDL Source serial-interface Single Design license for , Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C750. The D16750 allows serial , 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions , efficiency by automatically controlling serial data flow through the RTS output and the CTS input signals
Digital Core Design
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design IP Uarts using verilog HDL uart vhdl code fpga verilog hdl code for parity generator asynchronous fifo design in verilog uart vhdl fpga vhdl code for uart communication

vhdl code for asynchronous fifo

Abstract: verilog hdl code for parity generator Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial , 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions , Copyright 1999-2007 DCD ­ Digital Core Design. All Rights Reserved. Serial Data communications , serial data The DLL, DLM and THR registers are reset to all zeros In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU
Digital Core Design
Original
vhdl code for asynchronous fifo verilog code for baud rate generator verilog code for UART baud rate generator uart false start vhdl code for Digital DLL APEX20K

test bench verilog code for uart 16550

Abstract: verilog code for UART baud rate generator bits (start, stop, and parity) to or from the serial data In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data , Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial , 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions , Copyright 1999-2009 DCD ­ Digital Core Design. All Rights Reserved. Serial Data communications
Digital Core Design
Original
test bench code for uart 16550 vhdl code for 4 bit even parity generator address generator logic vhdl code baud rate generator vhdl vhdl code for serial transmitter vhdl 8 bit parity generator code

test bench verilog code for uart 16550

Abstract: test bench code for uart 16550 , stop, and parity) to or from the serial data In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data , to 12 months. Single Design license for Source VHDL, Verilog source code called HDL , Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial , 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions
Digital Core Design
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verilog code for uart communication in fpga verilog code for uart communication VHDL Bidirectional Bus verilog hdl code for uart APEX20KC APEX20KE

verilog code 16 bit processor

Abstract: uart vhdl code fpga parity) to or from the serial data In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data Independently , time of use is limited to 12 months. Single Design license for VHDL, Verilog source code , producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use , programmable characteristics: serial-interface DELIVERABLES Source code: VHDL Source Code or/and
Digital Core Design
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TL16C450 verilog code 16 bit processor verilog code for ring counter vhdl code for 8 bit parity generator design of UART by using verilog verilog code for uart vhdl code for parallel to serial shift register

VHDL CODE FOR 16 bit LFSR in PRBS

Abstract: vhdl code for 8 bit barrel shifter character or characters. By sending this Sync code, and searching for it in the serial data stream, the , bits. Because of its numerous advantages for serial data transmission, the 8B/10B code has been , Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data
Cypress Semiconductor
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VHDL CODE FOR 16 bit LFSR in PRBS vhdl code for 8 bit barrel shifter vhdl code 8 bit LFSR vhdl code for 9 bit parity generator vhdl code for 16 prbs generator vhdl code for 8 bit common bus CY7B923/933

vhdl code scrambler

Abstract: prbs generator using vhdl character or characters. By sending this Sync code, and searching for it in the serial data stream, the , bits. Because of its numerous advantages for serial data transmission, the 8B/10B code has been , Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data
Cypress Semiconductor
Original
vhdl code scrambler prbs generator using vhdl vhdl code for pseudo random sequence generator vhdl code for 4 bit barrel shifter vhdl code for 7 bit pseudo random sequence generator vhdl code for 16 bit Pseudorandom Streams Generation

verilog code for UART baud rate generator

Abstract: vhdl code for uart communication communication bits (start, stop, and parity) to or from the serial data In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial , Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C550A. The D16550 allows serial , 1 to (216-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are , . APPLICATIONS Serial Data communications applications Modem interface KEY FEATURES Software
Digital Core Design
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VHDL description for an 8-bit even/odd parity vhdl code for 8-bit parity generator interrupt controller verilog code download UART using VHDL vhdl code for 8 bit ODD parity generator vhdl code parity

XAPP029

Abstract: adc controller vhdl code . XAPP029 Serial Code Conversion Between BCD and Binary Binary-to-BCD and BCD-to-binary conversions are performed between serial binary values and parallel BCD values. XAPP030 Megabit FIFO in Two Chips: One LCA , FIFOs using the Block SelectRAM+ memory in the Spartan-II FPGAs. Verilog and VHDL code is available for , The design strategies for loadable and non-loadable binary counters are significantly different. This , the XC3000 series of FPGA devices. This information supplements the data sheets, and is provided for
Xilinx
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adc controller vhdl code verilog rtl code of Crossbar Switch 12-bit ADC interface vhdl code for FPGA Insight Spartan-II demo board vhdl code for pn sequence generator XAPP172 Q4-01 XAPP004 XAPP005 XAPP007 XAPP008 XAPP009

32-Bit Parallel-IN Serial-OUT Shift Register

Abstract: 32-Bit sipo Shift Register shifted out through a PISO shift register for transmission. At the receiver, the incoming data stream is , interleavers (block or convolutional) are popular techniques for protecting data from noise. Interleavers are , the transmitter (TX) and one de-interleaver in the receiver (RX). Consider a data stream, D_IN , are reserialized by a parallel-in, serial-out (PISO) register, and the serial output data flow, D_OUT , transmitter to reconstruct the data stream. In TX and RX circuits, a counter provides the correct timing and
Xilinx
Original
XAPP222 SRL16 32-Bit Parallel-IN Serial-OUT Shift Register 32-Bit sipo Shift Register vhdl code for interleaver vhdl code for block interleaver vhdl code for sipo vhdl code for asynchronous piso DS022 DS003 DS001 XAPP210

OPCODE SHEET FOR 8051 MICROCONTROLLER

Abstract: vhdl code for 16 BIT BINARY DIVIDER , data sheet, instruction set details Design File Formats EDIF netlist, ngo, VHDL, Verilog RTL source , memory. Extra DPP (Data Page Pointer) register is used for the segments swapping. The DR8051 RISC , ) module includes the Serial Configuration register (SCON), the serial receiver, and the transmitter , write enable Internal data memory read User SFR write enable User SFR read Serial receiver output Serial transmitter output The DR8051 microcontroller has also been verified using a DCD testing board
Xilinx
Original
OPCODE SHEET FOR 8051 MICROCONTROLLER vhdl code for 16 BIT BINARY DIVIDER program for 8051 16bit square root IEEE754 testbench single port ram testbench vhdl 4 bit binary multiplier Vhdl code

LIN Verilog source code

Abstract: LIN VHDL source code is a serial communication protocol designed primarity for use in automotive application. Compared to , their respective owners. Source code: VHDL Source Code VERILOG Source Code VHDL & VERILOG test , , store the divisor in the 15-bit binary format. Receiver Control & Shift Register ­ is responsible for , Design. All Rights Reserved. Provides necessery function for data reception, frame timming and error checking. Data Buffer ­ stores the receive or transmit data. Transmitter Control & Shift Register ­
Digital Core Design
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LIN Verilog source code LIN VHDL source code

8251 intel microcontroller architecture

Abstract: vhdl source code for 8086 microprocessor asynchronous receiver/transmitter Universal synchronous/asynchronous receiver/transmitter Universal serial bus Universal test and operations physical layer interface for ATM data path interface Virtual , >.tdf), VHDL, Verilog HDL, or AHDL file Symbol File (.sym) for use in MAX+PLUS II , translates all PCI access information for the target device to a 486-style internal bus. Address and data , VHDL- or Verilog HDL-based design files that are optimized for the Altera FLEX 10K device family
Altera
Original
8251 intel microcontroller architecture vhdl source code for 8086 microprocessor 8251 usart verilog coding for asynchronous decade counter verilog code for 8254 timer verilog code for median filter

verilog code for 32 BIT ALU multiplication

Abstract: vhdl code for watchdog timer data pointers (DPTR0 & DPTR1) for faster data transfers De-multiplexed Address/Data Bus to allow easy , external data memory. Extra DPP (Data Page Pointer) register is used for the segments swapping. It has the , Receiver & Transmitter (UART) module includes the Serial Configuration register (SCON0) and the serial , instructions. UART1 Universal Asynchronous Receiver & Transmitter module includes the Serial Configuration register (SCON1) and the serial receiver and transmitter buffer (SBUF1) registers. The module functions in
Xilinx
Original
verilog code for 32 BIT ALU multiplication vhdl code for watchdog timer architecture of 8052 vhdl source code for i2c memory read and write 8052 microcontroller 32 BIT ALU design with vhdl code DR8052EX
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