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vhdl code for DES algorithm

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vhdl code for DES algorithm

Abstract: verilog code for implementation of des NIST certified DES core 128-bit key or two independent 64-bit keys supported Suitable for ECB mode , Functional Description This core is a full implementation of the triple DES encryption algorithm and , DES algorithm was proposed by IBM when it became clear that the security of the DES had been compromised by advances in computer technology. Compared to the DES algorithm, the triple DES algorithm , of each KEY0 and KEY1 inputs are considered by the core, according to the triple DES algorithm
Xilinx
Original

verilog code for implementation of des

Abstract: vhdl code for cbc : fpga@avnet.com URL: www.avnet.com (with source code only) Instantiation Templates VHDL, Verilog Features , Implementation in VHDL or Verilog Additional Items Single and Triple DES operation Configurable to support all DES options and configurations NIST Certificate Number 31 Suitable for implementation in , of integration Includes Verilog or VHDL source code Warranty by AvnetCore Simulation Tool Used , software alternatives. DES is a block-oriented encryption algorithm. Plaintext data is loaded 64-bits at a
Xilinx
Original

verilog code for implementation of des

Abstract: vhdl code for DES algorithm each round of the Triple DES algorithm. Data In 4. Parity check logic ­ checks for odd-parity , , Actel provides example VHDL and Verilog 10 v5.0 source code for the TCBC (TDEA Cipher Block , Electronic Codebook) Implementation Per ANSI Standard X9.52 · Example Source Code Provided for TCBC , VHDL Core Source Code ­ Pause/Resume Functionality to Continue Encryption or Decryption at Will , provides a means of securing data. The Triple DES algorithm is described in the Federal Information
Actel
Original

vhdl code for DES algorithm

Abstract: vhdl code for cbc Logic for Cipher Key · Verilog or VHDL Core Source Code ­ Key Features Fully to · , data values at each round of the DES algorithm. 4. Parity check logic ­ checks for odd-parity , provides example VHDL and Verilog source code for the CBC (Cipher Block Chaining), CFB (Cipher Feedback , Source Code Provided for CBC, CFB and OFB Modes · Provides Data Security within a Secure Actel , means of securing data. The DES algorithm is described in Federal Information Processing Standards
Actel
Original

verilog code for implementation of des

Abstract: APA150-STD VHDL Core Source Code ­ Core Synthesis Scripts · Actel-Developed Testbench (Verilog and VHDL) · , ), which provides a means of securing data. The Triple DES algorithm is described in the Federal , Encryption Standard) algorithm (Figure 1 on page 2) and also described in FIPS PUB 46-3. The Triple DES , Left and Right data halves after Round 16 Figure 1 · DES Algorithm The Triple DES encryption algorithm is executed in the specific sequential order shown in Figure 2. 2. Decrypt using DES with
Actel
Original

vhdl code for DES algorithm

Abstract: verilog code for implementation of des VHDL Core Source Code · Whenever Data is Transmitted across an Accessible Medium (wires, wireless , implements the Data Encryption Standard (DES), which provides a means of securing data. The DES algorithm , illustrates the 16-iteration DES algorithm, as described in detail in FIPS PUB 46-3. · Netlist Version ­ , f(R15,K16) L16 = R15 Left and Right data halves after Round 16 Figure 1 · DES Algorithm , intermediate data values at each round of the DES algorithm. 2. Iteration state machine logic ­ keeps
Actel
Original

GSM 900 simulink matlab

Abstract: verilog code for ofdm transmitter system- DES core, Altera has Rijndael, SHA-1, and MD5 cores. electronic code book (ECB) or , , the turbo decoder features a max-logMAP algorithm for maximum error correction and includes a 3GPP , generate high-level simulation output files for the MATLAB and Simulink software as well as and VHDL or , ® Signal Processing IP Megafunctions Signal Processing Solutions for System-on-a , for Existing Designs portfolio-including MegaCore® and Altera Megafunction Signal processing IP
Altera
Original

vhdl code for DES algorithm

Abstract: verilog code for implementation of des description of the DES algorithm in Electronic Code Book (ECB) mode is presented below. For complete details , symmetric encryption algorithm where the same key is used for both encryption and decryption. DES takes a , an ideal platform for DES implementation. Triple DES Algorithm The US government agencies had , ., 48 cycles for each copy of DES. DES HDL Code and Simulation This application note provides , Encryption Algorithm (IDEA) and others, each having strengths and weaknesses. DES is the most widely used
Xilinx
Original

vhdl code for AES algorithm

Abstract: vhdl code for DES algorithm VHDL or Verilog RTL source code · Self-checking testbenches · Vectors for testbenches · Simulation , implementation of the AES (Advanced Encryption Standard) algorithm. Simple, fully synchronous design with low gate count. Compared to the DES and the triple DES algorithms the AES provides an even higher level of , available in VHDL or Verilog Test benches provided Applications Electronic financial , core supports both encryption and decryption according to the AES algorithm. The key must be provided
Cast
Original

vhdl code for DES algorithm

Abstract: vhdl code for rsa Code Validation Tools chain including the VHDL Emulator, must be used for both the hardware, software , CLOCK FREQUENCY SENSORS MEMORY s HIGHLY RELIABLE CMOS EEPROM TECHNOLOGY ­ Error Correction Code for , The ST22 core includes dedicated DES instructions for Secret Key cryptography, and a fast Multiply , general purpose registers instruction ­ Hardware DES and 3DES instructions ­ Fast Multiply and Accumulate instructions for Public Key and Elliptic Curve Cryptography s CPU DPA/SPA COUNTERMEASURES s
-
Original

vhdl code for rsa

Abstract: vhdl code for DES algorithm Code Validation Tools chain including the VHDL Emulator, must be used for both the hardware, software , CLOCK FREQUENCY SENSORS MEMORY s HIGHLY RELIABLE CMOS EEPROM TECHNOLOGY ­ Error Correction Code for , The ST22 core includes dedicated DES instructions for Secret Key cryptography, and a fast Multiply , general purpose registers instruction ­ Hardware DES and 3DES instructions ­ Fast Multiply and Accumulate instructions for Public Key and Elliptic Curve Cryptography s CPU DPA/SPA COUNTERMEASURES s
STMicroelectronics
Original

CRT2380

Abstract: 32 bit risc processor using vhdl Hardware DES and 3DES instructions ­ Fast Multiply and Accumulate instructions for Public Key and , Code for single bit fail within a 32-bit word ­ 10 years data retention, 500,000 Erase/Write cycles , Algorithm RSA 1024 bits RSA 2048 bits DES 1) 2) 2/7 Function Time 1) Signature with CRT , core includes dedicated DES instructions for Secret Key cryptography, and a fast Multiply and , the Code Validation Tools chain. ­ SPTLA 3) The SmartJTM Platform Technology License Agreement for
STMicroelectronics
Original

vhdl code for DES algorithm

Abstract: vhdl AES 512 algorithm complete Code Validation Tools chain including the VHDL Emulator, must be used for both the hardware , DES and 3DES instructions ­ Fast Multiply and Accumulate instructions for Public Key and Elliptic , DES SHA-1 AES-128 1. 2. June 2004 For further information contact your local ST sales office , MEMORY I HIGHLY RELIABLE CMOS EEPROM TECHNOLOGY ­ Error Correction Code for single bit fail within a , core includes dedicated DES instructions for Secret Key cryptography, and a fast Multiply and
STMicroelectronics
Original
ST22N256 vhdl code for DES algorithm vhdl AES 512 algorithm vhdl code 16 bit processor vhdl code for AES algorithm ST22 32-BIT 24-BIT

vhdl code for DES algorithm

Abstract: vhdl coding for pipeline complete Code Validation Tools chain including the VHDL Emulator, must be used for both the hardware , area for efficient algorithm coding using a set of advanced functions. RSA, signature/ verification , Algorithm RSA 1024 bits RSA 2048 bits DES SHA-1 AES-128 Function Signature with CRT Signature , I HIGHLY RELIABLE CMOS EEPROM TECHNOLOGY ­ Error Correction Code for single bit fail within a 32 , core includes dedicated DES instructions for Secret Key cryptography, and a fast Multiply and
STMicroelectronics
Original
ST22L128 vhdl coding for pipeline NOR flash controller vhdl code L032 L064

vhdl code for multiplexer 64 to 1 using 8 to 1

Abstract: vhdl code for cbc solution to dedicated hardware or software alternatives. DES is a block-oriented encryption algorithm , and 16 clocks later the plaintext is available. Triple-DES consists of applying the DES algorithm on , Features · · · · · · Single- and triple-DES operation - Configurable to support all DES options and configurations NIST Certificate Number 31 Suitable for implementation in ECB, CBC, CFB, and , Instructions Design File Format Verilog or VHDL RTL Constraint Files TimeSpecs Verification Tool
Xilinx
Original
vhdl code for multiplexer 64 to 1 using 8 to 1 vhdl code for cbc data encryption standard vhdl DC-172 XC4000E/XL

vhdl code for multiplexer 64 to 1 using 8 to 1

Abstract: Triple DES Configurable to support all DES options and configurations NIST Certificate Number 31 Suitable for , dedicated hardware or software alternatives. DES is a block-oriented encryption algorithm. Plaintext data , later the plaintext is available. Triple-DES consists of applying the DES algorithm on the data three , Design File Format Verilog or VHDL RTL Constraint Files TimeSpecs Verification Tool Testbench and , /Foundation 1.5 Entry/Verification Verilog/ VHDL Synthesis Tools Tools Model Technology ModelSim
Xilinx
Original
Triple DES verilog code for implementation of rom verilog code for rsa algorithm verilog code for implementation of des vhdl code for multiplexer 8 to 1 using 2 to 1

vhdl code for des decryption

Abstract: Triple Data Encryption Standard Triple DES . DES is a block-oriented encryption algorithm. Plaintext data is loaded 64-bits at a time along with , . Triple-DES consists of applying the DES algorithm on the data three times. Encryption in Triple-DES is , waveform in Figure 2 shows the interface timing for the DES core. Data is presented to the core on the , outputs for control of key multiplexer in Triple-DES modes. InfoGard Laboratories NVLAP Lab Code , Format Verilog or VHDL RTL Constraint Files .ucf Verification Testbench Reference Design Sample
Xilinx
Original
vhdl code for des decryption Triple Data Encryption Standard Triple DES XC2S100-5

home security system block diagram

Abstract: verilog code for aes encryption , settop boxes, digital cameras, etc. These applications also require the DES algorithm for data , core is a fully compliant hardware implementation of the DES encryption algorithm, suitable for a , Corporation, and was adopted as the American National Standard (ANSI) X3.92-1981/R1987. The DES algorithm was , fixed length which are then enciphered using the secret key. The DES is the algorithm in which a 64 , DES has more than 72 quadrillion (72 x 1015) possible encryption keys that can be used. For each
Xilinx
Original
home security system block diagram verilog code for aes encryption automated teller machine design using vhdl verilog code for 32 bit AES encryption CYLINK Voice encryption WP115

lms algorithm using verilog code

Abstract: lms algorithm using vhdl code directly for an authorization code; the AMPP partner will generate this code based on your MAX+PLUS II PC , File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL instantiation templates Megafunction , set of AHDL and VHDL backend reference designs that designers can customize for their own project , printing date, but megafunction specifications and availability are subject to change. For the most current , Data Communication (Telecom and Datacom) Digital Signal Processing (DSP) For additional details on
Altera
Original
lms algorithm using verilog code lms algorithm using vhdl code ATM machine working circuit diagram using vhdl verilog code for lms adaptive equalizer verilog code for lms adaptive equalizer for audio digital IIR Filter VHDL code

CRC matlab

Abstract: dsp processor design using vhdl Algorithm Design Using MATLAB/Simulink Write Assembly or C Code DSP Libraries Algorithm , Solutions Figure 4. DSP Builder-Based Design Flow for Altera FPGAs Algorithm Design Using MATLAB , and cost requirements. DSP processors are used for implementing many of these DSP applications , blocks, and fixed data widths. The DSP processor's fixed hardware architecture is not suitable for , reconfigurable solution for implementing DSP applications as well as higher DSP throughput and raw data
Altera
Original
CRC matlab dsp processor design using vhdl turbo encoder model simulink how dsp is used in radar radar dsp processor VHDL code of DCT by MAC
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