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LTC6993MPS6-3#TRPBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: SOT; Pins: 6; Temperature Range: -55°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LTC6993MPS6-4#PBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: SOT; Pins: 6; Temperature Range: -55°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy
LTC6993CS6-4#TRPBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: SOT; Pins: 6; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC6993IS6-1#TRPBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: SOT; Pins: 6; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC6993CDCB-1#TRMPBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: DFN; Pins: 6; Temperature Range: 0°C to 70°C visit Linear Technology - Now Part of Analog Devices Buy
LTC6993HDCB-2#TRMPBF Linear Technology LTC6993 - TimerBlox: Monostable Pulse Generator (One Shot); Package: DFN; Pins: 6; Temperature Range: -40°C to 125°C visit Linear Technology - Now Part of Analog Devices Buy

vhdl code for 8 bit ODD parity generator

Catalog Datasheet MFG & Type PDF Document Tags

verilog code for uart apb

Abstract: UART actel proasic3e VHDL for the number of data bits is 7. The option PRG_bit8 sets the serial bitstream to 8-bit data mode. Parity The PRG_PARITY parameter sets the parity enabled/disabled. It also sets parity Even/Odd. 8 , listed in Table 6-1 on page 21. Refer to the rtl//test directory for source code for , the data (LSB first), then the parity (optional), and finally the STOP bit. The data buffer is , statistics for targeted devices are listed in Table 1-1 through Table 1-2 on page 8. Table 1-1 · CoreUARTapb
Actel
Original

vhdl code for 8-bit calculator

Abstract: vhdl ODD parity generator Bus. Odd parity over 8/16 bit TxData. Transmit Cell Available - used in SPHY mode and one-Clav , indication. Tells PHY device to drive data, after sampling this signal low. Odd parity over 8/16 bit RxData , even ports and Bit 1 for odd ports for Clav status; active high. Address of PHY device in MPHY , MPHY two Clav operation. In two-Clav operation, Bit 0 is for even ports and Bit 1 for odd ports for , ; MUC computes odd parity over data path and compares with received parity. Write Enable for Logical
Xilinx
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vhdl code for 4 bit even parity generator

Abstract: vhdl code for 9 bit parity generator time code. September 25, 2000 Deltatec LTC Bit Stream Generator Biphase Mark Encoder The LTC Bit Stream Generator retrieves 5 x 16 time code data bits from the register bank which are , described in Table 3. Customization of the core (8 bit µP interface for example) can be performed by , Longitudinal Time Code Generator September 25, 2000 Product Specification AllianceCORETM , under terms of the SignOnce IP License SMPTE/EBU Longitudinal Time Code time code generator Lock on
Xilinx
Original

vhdl code for 8 bit ODD parity generator

Abstract: vhdl code for 8-bit calculator on TxData Bus. Odd parity over 8/16 bit TxData. Transmit Cell Available - used in SPHY mode and , . Odd parity over 8/16 bit RxData. Receive Cell Available - used in SPHY mode and one-Clav operation , , Bit 0 is for even ports and Bit 1 for odd ports for Clav status; active high. Address of PHY device , even ports and Bit 1 for odd ports for Clav status; active high. Address of MPHY device, driven from , , Version1.0 8/16 bit UTOPIA operation SPHY operation supports Octet Level and Cell Level handshake MPHY
Xilinx
Original

vhdl code for 8 bit parity generator

Abstract: Design and Simulation of UART Serial Communication including : - 5,6,7 or 8-bit data transmission - Even/Odd or no parity bit generation and detection - Start , STOP 1 : 2 bit STOP The receiver always checks only for the first bit STOP. Active high. Enable parity , between the last word bit and the first STOP bit. Parity Control. Generates/checks an odd/even number of logic one bits in data word + parity bit. 1 : Even parity. 0 : Odd parity. Break Control. Active high , interrupt is generated for each received character containing a parity error. This bit is cleared once it
Logic Design Solutions
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UART 8251

Abstract: 8251 uart in vhdl code Control bit to define odd or even parity for both receive and transmit functions. When the parity_en control bit is set, a `1' on this bit indicates odd parity and `0' indicates even parity baud_val , · Parity (Odd, Even, None) · Baud Rate Control for Asynchronous Mode · Both Receive and Transmit , care parity_en Input Sync/Async Control bit to enable parity for both receive and transmit , transmit data buffer is not available for additional transmit data TXrdy 8-bit control bus used to
Actel
Original

design IP Uarts using verilog HDL

Abstract: uart vhdl code fpga Netlist One Year license for Even, odd, or no-parity bit generation and detection VHDL, Verilog source code called HDL Source serial-interface Single Design license for , One Year license where time of use is limited to 12 months. 5-, 6-, 7-, or 8-bit characters , for communications link fault isolation Break, parity, overrun, framing error simulation , . DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text
Digital Core Design
Original

verilog code 16 bit processor

Abstract: uart vhdl code fpga 5-, 6-, 7-, or 8-bit characters Even, odd, or no-parity bit generation and detection , time of use is limited to 12 months. Single Design license for VHDL, Verilog source code , 16 bit programmable baud generator MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD , programmable characteristics: serial-interface DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment
Digital Core Design
Original

16750 UART texas instruments

Abstract: vhdl code for fifo and transmitter 5-, 6-, 7-, or 8-bit characters Even, odd, or no-parity bit generation and detection , interrupts False start bit detection 16 bit programmable baud generator MODEM control , delivered IP Core VHDL, Verilog RTL synthesizable source code called HDL Source FPGA EDIF/NGO/NGD/QXP/VQM called Netlist Source code: VHDL Source Code or/and VERILOG Source Code or/and , parts of the code. · Baud generator · External RCLK source - enable - disable · External
Digital Core Design
Original

vhdl code for asynchronous fifo

Abstract: verilog hdl code for parity generator -, 6-, 7-, or 8-bit characters Even, odd, or no-parity bit generation and detection 1 , data set interrupts False start bit detection 16 bit programmable baud generator , for communications link fault isolation Break, parity, overrun, framing error simulation Two DMA , DCD ­ Digital Core Design. All Rights Reserved. DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test
Digital Core Design
Original

test bench verilog code for uart 16550

Abstract: verilog code for UART baud rate generator registers, with the same functionality serial-interface 5-, 6-, 7-, or 8-bit characters Even, odd, or no-parity bit generation and detection 1-, 1½-, or 2-stop bit generation , . CONFIGURATION DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted , appropriate constants in package file. There is no need to change any parts of the code. · Baud generator , Generator - The D16550 contains a programmable 16 bit baud generator that divides clock input by a divisor
Digital Core Design
Original
TL16C550A D16450 D16750 D16950 test bench verilog code for uart 16550 verilog code for UART baud rate generator test bench code for uart 16550 verilog code for baud rate generator vhdl code for 4 bit even parity generator address generator logic vhdl code D16X50

verilog code 16 bit LFSR

Abstract: vhdl code 16 bit LFSR SRLE16 clk X220_08_091100 Figure 8: 32-bit, 4-tap Parallel LFSR The code has been tested on the , work with current versions of Express, Exemplar, and Synplify. For both VHDL and Verilog code, the , pseudo-random noise (PN) code generator (XAPP211) and Gold code generators (XAPP217) commonly used in Code , detail. LFSR 1 Length N PN Code Out LFSR 2 Length N X220_01_010101 Figure 1: Gold Code Generator , generate are determined by the number and position of taps used to generate the parity feedback bit
Xilinx
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XAPP220 SRL16 verilog code 16 bit LFSR vhdl code 16 bit LFSR verilog code 8 bit LFSR vhdl code 8 bit LFSR simple LFSR 8 shift register by using D flip-flop

test bench verilog code for uart 16550

Abstract: test bench code for uart 16550 generator DELIVERABLES Even, odd, or no-parity bit generation and detection 1-, 1 , to 12 months. Single Design license for Source VHDL, Verilog source code called HDL , , RI, and DCD) Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or , LICENSING 5-, 6-, 7-, or 8-bit characters serial-interface Technology , is no need to change any parts of the code. · Baud generator - enable disable · FIFO
Digital Core Design
Original
verilog code for uart communication in fpga verilog hdl code for parity generator baud rate generator vhdl vhdl code for uart communication verilog code for uart communication uart vhdl code fpga

16650 uart

Abstract: uart 16650 timing serial-interface 5-, 6-, 7-, 8- or 9-bit characters Even, odd, or no-parity bit generation and , data Loop-back controls for communications link fault isolation Break, parity, overrun , code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL , use restrictions. VHDL, Verilog RTL synthesizable source code called HDL Source datao(7:0 , by holding CS low. Baud Generator - The D16950 contains a programmable 16 bit baud generator that
Digital Core Design
Original
16650 uart uart 16650 timing vhdl code for fifo and transmitter uart 16750 baud rate "flow control" verilog code for 8 bit shift register UART using VHDL OX16C950 D16754

vhdl code for 9 bit parity generator

Abstract: asynchronous fifo vhdl xilinx just one additional bit path between the transmitter and receiver for each 8 bits in the normal datapath. These extra bit paths can be used for any purpose, not just parity.) Data Funneling and , , the online code generator always creates code for a single chip. If the chip is receiving one channel , generator always creates code for a single chip, the same code might be applicable to more than one chip , SelectLink Verilog or VHDL source code. The modules are easily instantiated in the designer's top-level code
Xilinx
Original
XAPP263 vhdl code for 9 bit parity generator asynchronous fifo vhdl xilinx vhdl code switch layer 2 vhdl code for lvds receiver X263 X0Y17 X0Y19 X0Y20 X0Y21 X0Y23

vhdl code for 9 bit parity generator

Abstract: X26302 , this is just one additional bit path between the transmitter and receiver for each 8 bits in the normal data path. These extra bit paths can be used for any purpose, not just parity.) Data Funneling , SelectLink Verilog and VHDL source code generator is available at www.xilinx.com to dynamically generate , generator always creates code for a single chip. If the chip is receiving one channel only, then "Receiver , in a system with three FPGAs. The code generator automatically generates final code for all of the
Xilinx
Original
X26302 asynchronous fifo vhdl VHDL Bidirectional Bus XC2V1000-FG456 Signal Path Designer X0Y24 X0Y25 X0Y27 X0Y31 X111Y36 X111Y35

XAPP463

Abstract: written Figure 4. In the 512x36 organization, for example, the 36-bit data port width includes four parity bits , to parity on the 18K-bit block RAM. See Figure 4 for details on data mapping for and between each , 7936 Table 8: VHDL/Verilog RAM Initialization Attributes for Block RAM Attribute From To , parity bits. Figure 4 shows the expected bit format for each memory organization with parity bits-if , bits. Figure 4 shows the expected bit format for each memory organization with parity bits-if
Xilinx
Original
XAPP463 XC3S50 XC3S200 XC3S400 written RAMB16 vhdl code for bcd to seven segment display XC3S500E Seven Segment LED Display XC3S1000/L XC3S1000L

baud rate generator vhdl

Abstract: fifo generator xilinx spartan 57 Block RAMs · Parity; can be configured for odd or even Max FFs · Number of databits , byte-enable support Version of Core · Supports 8-bit bus interfaces opb_uartlite v1.00b Resources , integer (5 to 8) 8 integer Determines whether parity is used or not C_USE_PARITY Integer , parity is odd or even C_ODD_PARITY integer 1= odd parity, 0 = even parity. 1 integer , registers are organized as big-endian data. The bit and byte labeling for the big-endian data types is
Xilinx
Original
DS422 fifo generator xilinx spartan XILINX FIFO UART XILINX UART lite vhdl code for 8 bit ODD parity generator uart vhdl 2V100 DS209 CR202220

UART actel proasic3e VHDL

Abstract: 8251 uart vhdl ." PARITY_EN Input Control bit to enable parity for both receive and transmit functions. Parity is , parity for both receive and transmit functions. When the PARITY_EN control bit is set, a '1' on this bit indicates odd parity and a '0' indicates even parity. BAUD_VAL[12:0] Input 13-bit control bus used , the parity (optional), and finally the STOP bit. The data buffer is double-buffered in normal mode, so , . For the other families, the depth of the FIFO is 256. 8 v2.1 CoreUART v4.0 Handbook
Actel
Original
UART actel proasic3e VHDL 8251 uart vhdl UART 8251 8251 uart in vhdl code 8251 uart proasic3l rs232

vhdl code for 4 bit even parity generator

Abstract: vhdl code for 8 bit ODD parity generator clock speed · No dedicated clock frequency · 7 or 8 Bits Data · No/Odd/Even Parity , Transmit and receive data size: `0': use 7 bit data `1': use 8 bit data Parity enable: `0': no parity , of ones in a byte, including parity bit is even February 25, 2003 Optimized for 5 Fast , Actel Designer place and route tool · RTL Version o VHDL Source Code o Test Bench · All o , bit after a falling edge is detected low. If parity is enabled, it is checked and event failures are
Memec Design
Original
vhdl 8 bit parity generator code vhdl code for 8 bit parity generator
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