NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: number of bit positions in a single clock cycle. For example, an eight-bit barrel shifter could shift , Figure 4 is an 8-bit barrel shifter, implemented using one MULT18X18 MULT18X18 to move the data into and out of the barrel shifter. The 8-bit barrel shifter is preceded by two 8-bit 4 x 1 MUXs to move the , barrel shifter. This application note and accompanying Barrel 32 reference design are intended for , , multiplexers are used to place the bits correctly for proper storage. Thus, a barrel shifter is implemented by ... | Original |
4 pages, |
vhdl code for 16 bit barrel shifter MULT18X18 verilog code for 64 bit barrel shifter barrel shifter code vhdl 32 bit barrel shifter verilog code for 16 bit shifter 4 bit barrel shift register barrel shifter 32 bit barrel shifter vhdl 8-bit multiplier VERILOG 8 bit barrel shifter datasheet abstract |
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| Abstract: decoder. The first barrel shifter has a 10-bit output that can be easily coupled to an 8B/10B 8B/10B or 4B/5B decoder (both not included in the reference design). The second barrel shifter has a 16-bit output and is specifically designed for 8-bit protocols, such as SONET/SDH. Other barrel shifters can be designed by the , 10-Bit Barrel Shifter EN_10 16 16-Bit Barrel Shifter To user application DOUT_16 EN_16 , oldest. DOUT_10[9:0] Out 10-bit barrel shifter data output. DOUT_10 is synchronous to REFCLK. ... | Original |
14 pages, |
barrel shifter G703 TILE010 x8750 vhdl code for clock and data recovery dlc9 E1 pdh vhdl barrel shifter using verilog vhdl code for phase frequency detector prbs generator using vhdl prbs pattern generator using vhdl vhdl code for 16 prbs generator vhdl code for 4 bit barrel shifter XAPP875 XAPP875 abstract |
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| Abstract: DIN 10 FF SAM SAMV 4 10 REFCLK RST NI-DRU DOUT_10 10-Bit Barrel Shifter EN_10 16 16-Bit Barrel Shifter To user application DOUT_16 EN_16 X875_01_010809 Figure , decoder. The first barrel shifter has a 10-bit output that can be easily coupled to an 8B/10B 8B/10B or 4B/5B decoder (both not included in the reference design). The second barrel shifter has a 16-bit output and is specifically designed for 8-bit protocols, such as SONET/SDH. Other barrel shifters can be designed by the ... | Original |
14 pages, |
ML523 PLL 02A prbs pattern generator using vhdl TILE010 verilog code for 16 bit barrel shifter verilog disadvantages vhdl code for phase frequency detector G703 vhdl code for barrel shifter prbs generator using vhdl vhdl code for 16 prbs generator XAPP875 XAPP875 XAPP875 abstract |
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| Abstract: : 16-bit address and 16-bit data busses for each space (I, X, Y) Data Calculation Unit (DCU) 16 x 16-bit parallel Multiplier 40-bit Barrel Shifter Unit 40-bit Arithmetic and logic Unit Two 40-bit extended , maximum address registers for modulo addressing Program Control Unit (PCU) 16-bit Program Counter 3 , The D950-Core is a programmable 16-bit / single MAC DSP core used in combination with memories and custom or standard peripherals, implemented in the same silicon die for custom Application Specific DSP ... | Original |
23 pages, |
vhdl code of floating point unit G.729 chip G.711 D950-CORE processor control unit vhdl code ST18952 controler ARM7 ISA vhdl code mips code GDB950 CODE VHDL TO ISA BUS INTERFACE ieee floating point vhdl powerful D950-DSP D950-DSP D950-DSP abstract |
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| Abstract: a barrel shifter. FASICs currently account for the largest market segment and will retain this , handled directly on the DSP. A 36-bit barrel shifter as well as an exponent evaluation unit allow , Two 36-bit accumulators with shift/rotate function Zero overhead looping Support for division and , q q q q q q Two additional 36-bit accumulators Accumulator swap function 36-bit barrel , ] BARREL SHIFTER PL ALU/SHIFTER A0 E AOH AOL A1H A1L A1 E ACCUMULATORS COMPUTATION UNIT LC ... | Original |
4 pages, |
SPCE vhdl code for 4 bit barrel shifter verilog code for barrel shifter alu project based on verilog siemens spc 2 datasheet abstract |
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| Abstract: Datapath · · · · · 32-bit ALU Floating point disassembly/assembly 32-bit barrel shifter Count , includes a 32-bit ALU, a barrel shifter, a 24-element 32-bit wide register file, a test interface unit and , sizing from 8-,16- to 32-bit Write buffer HLD/HAK bus arbitration Easily customized for other on-chip , Reg 32-bit ALU Shifter Mux Stack Vector ADDRESS Mux Mux Instr. Reg Parser , extended bytecodes for embedded operations. The JEMCore improves Java execution efficiency by eliminating ... | Original |
4 pages, |
ROCKWELL ieee floating point vhdl java rockwell collins vhdl code for barrel shifter aJile Systems vhdl code for 4 bit barrel shifter java card 32 bit barrel shifter vhdl rockwell collins connector vhdl code for 8 bit barrel shifter ieee floating point alu in vhdl datasheet abstract |
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| Abstract: 56-BIT ACCUMULATORS 56-BIT BARREL SHIFTER JTAG 6 OnCETM MODD/IRQD MODC/IRQC MODB/IRQB , Division DSP56300 DSP56300 Architecture · Code Compatible with DSP56000 DSP56000 Architecture Migration path for , clock cycle Fully Pipelined 24 x 24 Parallel Multiplier-Accumulator · 56-bit Parallel Barrel Shifter Multibit shift instructions Bit-field insert/extract for efficient stream parsing Fast , MUX 56 PIPELINE REGISTERS PIPELINE REGISTERS BARREL SHIFTER ACCUMULATOR, ROUNDING, AND ... | Original |
33 pages, |
vhdl code for 8 bit barrel shifter 32 bit barrel shifter vhdl 56001a Digital Signal Processing DSP56000 DSP56300 DSP56301 MOTOROLA DSP56300 architecture 32 bit single cycle mips vhdl pga 132 packaging 16 bit single cycle mips vhdl DSP56300 abstract |
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| Abstract: synthesized with the design. Templates for the SIGNED_MULT_18X18 18X18 module are provided in VHDL and Verilog code , Embedded Multipliers in Spartan-3 FPGAs VHDL Instantiation Template - Component Declaration for , multipliers. For example, Figure 5 shows how a 22x16 multiplier could be implemented. The 22-bit value is decomposed into an 18-bit signed value and a 4-bit unsigned value from the LSBs. Two partial products are , by the 4-bit unsigned section. The second is a 34-bit signed product, formed by multiplying the ... | Original |
17 pages, |
verilog code for 16 bit multiplier binary multiplier Vhdl code 8 bit sequential multiplier VERILOG 4x4 barrel shifter block diagram 8x8 booth multiplier matrix multiplier Vhdl code Modified Booth Multipliers vhdl code for 8 bit barrel shifter 8 bit booth multiplier vhdl code MULT18X18S verilog code pipeline square root XAPP467 XAPP467 abstract |
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| Abstract: offset register controls a barrel shifter that extracts the ten-bit output word from a 19-bit wide piece , use an embedded 18 x 18 multiplier to implement most of the barrel shifter.[4] The files , to is used to generate the tenth bit of the barrel shifter. If it is a Virtex-II design and a free , for 4 x 3 and 16 x 9 aspect ratio 4:2:2 component digital video [1][2] · ANSI/SMPTE 244M for , the highest SDI bit rate. 4 www.xilinx.com 1-800-255-7778 XAPP288 XAPP288 (1.0) October 19, 2001 ... | Original |
11 pages, |
61179 32 bit barrel shifter vhdl 267M verilog code 5 bit LFSR verilog code 8 bit LFSR XAPP298 XAPP288 XAPP248 XAPP247 vhdl code for 16 bit barrel shifter 244M-1995 verilog code for barrel shifter vhdl code for 4 bit barrel shifter datasheet abstract |
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| Abstract: 16-bit barrel shifter 6.0 Demultiplexer 7.0 Data register 8.0 Parallel to serial shift register 9.0 , 3.0 Multiplexer The source code is - Philips CPLD Applications - 6-bit 4 to 1 multiplexer - , of commonly used digital functions 5.0 Barrel shifter The source is - 16 bit barrel , TO 14); END CASE; END PROCESS; END v1; The schematics for the barrel shifter are given in , Semiconductors Preliminary VHDL models of commonly used digital functions 7.0 4-bit Data Register ... | Original |
122 pages, |
32 bit barrel shifter vhdl 8 bit barrel shifter vhdl code ST10 ST11 ST12 ST13 ST14 ST15 traffic light controller vhdl vhdl code for 16 bit barrel shifter vhdl code for 16 BIT BINARY DIVIDER vhdl code for a 9 bit parity generator schematic counter traffic light datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| keeps 10-bits of previously processed data around for use - by the barrel shifter. This is offset value which can drive the barrel shifter. - The TRS encoder generates a 4-bit offset _in : - input register for the barrel shifter std_logic_vector(38 downto 0); signal : std_logic; - barrel shifter first level select bit signal bs_sel_2 : - barrel shifter second level select bits std_logic_vector(1 downto 0); signal bs www.datasheetarchive.com/download/58948463-996028ZC/xapp684.zip (multi_sdi_framer.vhd) |
Xilinx | 22/09/2004 | 2253.89 Kb | ZIP | xapp684.zip |
| keeps 10-bits of previously processed data around for use - by the barrel shifter. This is offset value which can drive the barrel shifter. - The TRS encoder generates a 4-bit offset std_logic_vector(4 downto 0); signal barrel_in : - input register for the prev_reg : - keeps 10 bits of previously data for barrel in : std_logic; - barrel shifter first level select bit signal bs_sel_2 www.datasheetarchive.com/download/91397821-996025ZC/xapp681.zip (hdsdi_framer.vhd) |
Xilinx | 09/01/2004 | 89.65 Kb | ZIP | xapp681.zip |
| barrel_shifter : std_logic_vector(width - 1 downto 0); begin for k in 0 to (width - 1) loop downto 0); begin for k in 0 to (width - 1) loop barrel_shifter_next(k + (conv_integer(shift_by)+1 - - - XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" - SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR - XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION - AS transpose_input ( inp : std_logic_vector) return std_logic_vector; - Byte Shifter for www.datasheetarchive.com/download/67289543-995991ZC/xapp562.zip (crc_functions_pkg.vhd) |
Xilinx | 22/01/2004 | 48.4 Kb | ZIP | xapp562.zip |
| _top : std_logic; - shift code for top level barrel shifter MUX signal sc_bot : - shift code for bottom level barrel shifter MUX std_logic_vector(11 downto 0 keeps 10-bits of previously processed data around for use - by the barrel shifter. This is offset value which can drive the barrel shifter. - The TRS encoder generates a 4-bit offset std_logic_vector(4 downto 0); signal barrel_in : - input register for the www.datasheetarchive.com/download/58948463-996028ZC/xapp684.zip (multi_sdi_framer_mult.vhd) |
Xilinx | 22/09/2004 | 2253.89 Kb | ZIP | xapp684.zip |
| shift codes for the - top and bottom level MUXes of the barrel shifter. sc_bot is 12-bit vector ); signal sc_top : std_logic; - shift code for top level barrel shifter MUX signal sc_bot : - shift code for bottom level barrel shifter MUX std_logic_vector(11 downto 0 keeps 10-bits of previously processed data around for use - by the barrel shifter. This is offset value which can drive the barrel shifter. - The TRS encoder generates a 4-bit offset www.datasheetarchive.com/download/91397821-996025ZC/xapp681.zip (hdsdi_framer_mult.vhd) |
Xilinx | 09/01/2004 | 89.65 Kb | ZIP | xapp681.zip |
| downto 0); - input reg for barrel shifter signal trs_out: std_ulogic_vector( 3 downto 0 barrel shifter extracts a 10-bit field from the 19-bit barrel_in - vector. The bits extracted - output barrel_in[18:9]. - - In this implementation, the nine LS bits of the barrel shifter (when the offset_reg value is 0). - - The barrel shifter's outputs are taken from bits [17 :9]. - - The MS bit of the barrel shifter is produced with a 10:1 MUX using a case - statement www.datasheetarchive.com/download/18522930-995943ZC/xapp247.zip (par_framer_mult.vhd) |
Xilinx | 03/12/2003 | 59.31 Kb | ZIP | xapp247.zip |
| -LCA Unified Libraries xapp026o.zip 23KB Multiplexers and Barrel Shifters in XC3000 XC3000 XC3000 XC3000 v.zip 32KB Multiplexers and Barrel Shifters in XC3000 XC3000 XC3000 XC3000 for a 4-port memory controller. Fits in an XC7236 XC7236 XC7236 XC7236. xapp044o RAM+ (XAPP131 XAPP131 XAPP131 XAPP131), implemented in VHDL and Verilog For All Platforms SW Release: All Category _xapp Contents of /pub/applications/xapp Application design files for XAPP Application Notes See /apps www.datasheetarchive.com/files/xilinx/docs/wcd00014/wcd014cc.htm |
Xilinx | 16/02/1999 | 13.54 Kb | HTM | wcd014cc.htm |
| and Barrel Shifters in XC3000 XC3000 XC3000 XC3000. V.1.01, Implemented in OrCAD 386+ V1.10 Unified Libraries xapp026v.zip 32KB Multiplexers and Barrel Shifters in XC3000 XC3000 XC3000 XC3000 files for a 4-port memory controller. Fits FIFOs Using the Virtex Block SelectRAM+ (XAPP131 XAPP131 XAPP131 XAPP131), implemented in VHDL and Verilog For RAM+ (XAPP131 XAPP131 XAPP131 XAPP131), implemented in VHDL and Verilog For All Platforms SW Release: All Category www.datasheetarchive.com/files/xilinx/docs/wcd0003c/wcd03cf6.htm |
Xilinx | 12/02/1999 | 9.35 Kb | HTM | wcd03cf6.htm |
| -LCA Unified Libraries xapp026o.zip 23KB Multiplexers and Barrel Shifters in XC3000 XC3000 XC3000 XC3000 v.zip 32KB Multiplexers and Barrel Shifters in XC3000 XC3000 XC3000 XC3000 for a 4-port memory controller. Fits in an XC7236 XC7236 XC7236 XC7236. xapp044o RAM+ (XAPP131 XAPP131 XAPP131 XAPP131), implemented in VHDL and Verilog For All Platforms SW Release: All Category _xapp Contents of /pub/applications/xapp Application design files for XAPP Application Notes See http www.datasheetarchive.com/files/xilinx/docs/wcd0003c/wcd03cf7.htm |
Xilinx | 16/02/1999 | 13.47 Kb | HTM | wcd03cf7.htm |
| file contains both the VHDL & Verilog code for the 64 bit version of the XAPP200 XAPP200 XAPP200 XAPP200 Reference file contains both the VHDL & Verilog code for the 16 bit version of the XAPP200 XAPP200 XAPP200 XAPP200 Reference .tar.Z 285 Kb Uploaded: 12-15-1999 VHDL code for XAPP134 XAPP134 XAPP134 XAPP134, SDRAM design for UNIX .zip 185 Kb Uploaded: 12-15-1999 VHDL code for XAPP134 XAPP134 XAPP134 XAPP134, SDRAM design which -25-2000 This file contains both the VHDL & Verilog code for XAPP200 XAPP200 XAPP200 XAPP200. These are the latest versions www.datasheetarchive.com/files/xilinx/docs/rp00020/rp0206e.htm |
Xilinx | 06/03/2000 | 39.36 Kb | HTM | rp0206e.htm |