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vhdl code for 16 prbs generator

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simulation for prbs generator in matlab

Abstract: block diagram prbs generator in matlab 16-bit pseudo random binary sequence (PRBS) generator which is initialized at beginning of a Data Field. The PRBS polynomial generator is: G(16) = X16 + X13 + X12 + X11 + X7 + X6 + X3 + X + 1. The sync byte of the incoming packet marks the beginning of Data Field, and the PRBS generator is loaded with , 2 for MW_ ATSC Modulator Core emission mask. Core Modifications Source code uses VHDL generics , , including the additional features for 16-VSB. It accepts a single, SMPTE 310 or DVB-ASI, MPEG-2 formatted
Xilinx
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vhdl code for 8 bit barrel shifter

Abstract: verilog code for barrel shifter specific PRBS pattern used in this application note for both the generator and the checker is based on the polynomial x15 + 1. The VHDL and Verilog code for both the generator and the checker can be found in the , binary sequence (PRBS) generator works at full speed on CLK_DT and can generate a PRBS 15 pattern. The , and works in parallel, while the PRBS generator is serial. The 10-bit output of the DRU is processed , Controllable via ChipScope Pro Analyzer Each of the four channels is equipped with: · A PRBS generator
Xilinx
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vhdl code for ofdm

Abstract: ofdm matlab simulation block for the pseudo random binary sequence (PRBS) generator is: 1 + x14 + x15. The sync byte of the first packet is bit-wise inverted from 47HEX to B8HEX, and the PRBS generator is loaded with the seed sequence "100101010000000". During the MPEG-2 sync bytes of the subsequent seven trasport packets the PRBS generator , for a range of puntured convolutional codes, based on a mother convolutional code of rate 1/2 with 64 , polynomials of the mother code are G1=171OCT for X output and G2=133 OCT for Y output. The two bit stream, X
Xilinx
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vhdl code for ofdm ofdm matlab simulation block vhdl code for 16 prbs generator prbs generator using vhdl vhdl code for pseudo random sequence generator vhdl code for block interleaver

verilog code for barrel shifter

Abstract: vhdl code for 8 bit barrel shifter the generator and the checker is based on the polynomial x15 + 1. The VHDL and Verilog code for both , CLK_DT PRBS Generator Ideal Deserializer HF_CLK (3.11 GHz) Simulation Only NI-DRU (Unit , pseudorandom binary sequence (PRBS) generator works at full speed on CLK_DT and can generate a PRBS 15 pattern , checker is synthesizable and works in parallel, while the PRBS generator is serial. The 10-bit output of , equipped with: · A PRBS generator continuously sending a PRBS 15 pattern. The user can force each of
Xilinx
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XAPP875 XAPP868 verilog code for barrel shifter vhdl code for 8 bit barrel shifter vhdl code for 4 bit barrel shifter vhdl code Pseudorandom Streams Generator vhdl code for loop filter of digital PLL DS202

vhdl code for ofdm

Abstract: vhdl code for ofdm transmitter sequence (PRBS) generator is: 1 + x14 + x15. The sync byte of the first packet is bit-wise inverted from 47HEX to B8HEX, and the PRBS generator is loaded with the seed sequence "100101010000000". During the MPEG-2 sync bytes of the subsequent seven trasport packets the PRBS generator continues, but its , the mother code are G1=171OCT for X output and G2=133 OCT for Y output. The two bit stream, X and Y , specified by clause 4.3.5 of ETSI EN 300 744 V1.5.1 (2004-11) for QPSK, 16-QAM or 64-QAM. It outputs I/Q
Xilinx
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vhdl code for ofdm transmitter OFDM Matlab code ofdm code in vhdl OFDM QPSK simulation VHDL PROGRAM for ofdm OFDM matlab program CODES

vhdl code for 16 prbs generator

Abstract: verilog code of prbs pattern generator , 2011 www.xilinx.com 6 Reference Design Table 4: Attribute Sets for PRBS Pattern Generator , Application Note: Xilinx FPGAs An Attribute-Programmable PRBS Generator and Checker XAPP884 , application note describes a PRBS generator/checker circuit where the generator polynomial, the parallelism , users who want to know how to use the PRBS generator and checker. The final section, PRBS Sequences , or checks it is indicated by the term LFSR. Table 1: PRBS Generator/Checker Attributes Attribute
Xilinx
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XC5VLX30-FF324-1 verilog code of prbs pattern generator VHDL CODE FOR 16 bit LFSR in PRBS verilog code 16 bit LFSR in PRBS prbs pattern generator using vhdl verilog prbs generator prbs using lfsr XC6SLX4-TQG144-2

vhdl code for loop filter of digital PLL

Abstract: vhdl code for All Digital PLL Verilog Code Structure CDR Code (Verilog) ChipScope Pro Tool Project Files (Verilog) Testbenches for the CDR (Verilog) VHDL Code Structure CDR Code (VHDL) ChipScope Pro Tool Project Files (VHDL) Testbenches for the CDR (VHDL) X868_08_121707 Figure 8: Reference Design Analysis Directory Code , speedsel_0 DCO 0 prbs0 PRBS Generator 0 CDR 0 rec_clk2m0 (K18) dt_out0 (AF19) CDR 1 rec_clk2m1 (AH15) dt_out1 (AG15) Common REFCLK: CLK_N (J16)/CLK_P (J17) DCO 1 PRBS Generator 1
Xilinx
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vhdl code for All Digital PLL vhdl code for phase frequency detector vhdl code for DCO E1 pdh vhdl vhdl code for loop filter of digital PLL spartan vhdl code for phase frequency detector for FPGA

vhdl code for 16 prbs generator

Abstract: vhdl code for 9 bit parity generator LCV LE LIU LOS M23 Mbps NRZ OOF PC PMON PRBS RDI RTL RX SONET SPE STS-1 TX VHDL , received as 16-bit sequences, each consisting of eight 1's, a 0, six code bits, and a trailing 0. If a , Generator transmits codes to the C-bit parity FEAC channel via the TXFRMR. The idle code is used to disable , detection is software programmable. Software searches for the PRBS pattern from the in-coming payload bits , encoded dual data rail. The Midbus allows for connection to a SONET framer. A 16-bit synchronous
Altera
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vhdl code for 9 bit parity generator free verilog code of prbs pattern generator vhdl code for 8 bit parity generator verilog code for pseudo random sequence generator in vhdl code for a 9 bit parity generator sonet testbench

VHDL CODE FOR 16 bit LFSR in PRBS

Abstract: vhdl code for 8 bit barrel shifter . The full VHDL source code for the PLDs in this application note is listed in Appendixes B and C. This , Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data , documented in this application note. Schematics and VHDL code are included in this document. Serial
Cypress Semiconductor
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vhdl code 8 bit LFSR vhdl code for 8 bit common bus vhdl code for pseudo random sequence generator in vhdl code to implement 8bit lfsr using maximum length sequence 8 bit barrel shifter vhdl code scrambler CY7B923/933

vhdl code scrambler

Abstract: prbs generator using vhdl . The full VHDL source code for the PLDs in this application note is listed in Appendices B and C. This , Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data , documented in this application note. Schematics and VHDL code are included in this document. Serial
Cypress Semiconductor
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vhdl code for 7 bit pseudo random sequence generator vhdl code for 16 bit Pseudorandom Streams Generation Using HOTLink vhdl code for nrz vhdl code 10 bit LFSR vhdl code for clock and data recovery

block diagram code hamming using vhdl

Abstract: hamming test bench "010101" configures the encoder for the (32,26) × (16,15) code. Table 3: Constituent Codes Supported by , example, with the (8,4) × (8,4) code, the user would provide valid data_in and assert data_en High for 16 , 802.16a standards · Optimized for Virtex®-II and Virtex-II Pro FPGAs, using structural VHDL and , process is illustrated in Figure 2 for an (8,4) × (8,4) product code, where the Dij represent input data , : Product Code Block for the (8,4)-by-(8,4) Case The core supports both extended Hamming and parity only
Xilinx
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block diagram code hamming using vhdl hamming test bench vhdl code hamming window vhdl code hamming hamming code FPGA block diagram code hamming DS211

iodelay

Abstract: vhdl code for 16 BIT BINARY DIVIDER stay close to the half-full condition. As the FIFO empties, the flag for hitting 6/16 is asserted, and , The FIFO marks of 3/16 and 13/16 are used in case the frequency drifts and for ensuring that the , Jittered Clock DCM CLKIN CLKFX REFCLK BUFG MUX FILL-LEVEL PRBS Generator DCM FIFO , oscillator. A PRBS generator is driven by the multiplied CLKFX output and writes into a standard FIFO. The , from the FIFO is then checked by a PRBS checker with the same polynomial as the generator. Once both
Xilinx
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XAPP872 iodelay vhdl code for 16 BIT BINARY DIVIDER vhdl code for frequency divider iodelay Virtex 5 vhdl code for FFT 32 point vhdl code for multiplexer 32 BIT BINARY UG190

vhdl HDB3

Abstract: PQFP208 footprint FPGA provides a PRBS generator, loopback capabilities, logic for alarm LEDs, and several timing , 3.9.5 VHDL CODE . 26 3.10 ALARMS , Display is controlled by the microprocessor. The ACTEL A1460A FPGA provides a PRBS data generator , 00H Select B8ZS line code for receiver Write XBAS Configuration Register 44H 3XH Select B8ZS, enable for ESF in transmitter (bits defined by `X' determine the FDL data rate & Zero Code
PMC-Sierra
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PM4344 PM6344 vhdl HDB3 PQFP208 footprint digital alarm clock vhdl code 74XXX139 alarm clock design of digital VHDL MLL41 TQUAD/PM6344 PMC-980328 PM4344/PM6344 PMC-951013

FSP250-60GTA

Abstract: fsp250-60gta power supply schematic placing orders for products or services. Printed on recycled paper ii Altera Corporation , information. For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For , exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also , the revision history for Chapter 1. Chapter(s) Date / Version 1 Altera Corporation July 2003
Altera
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FSP250-60GTA fsp250-60gta power supply schematic power supply fsp250-60gta fsp250-60 FSP250 manual FSP250-60gta manual P25-09565-00 RS-232 D-85757

verilog hdl code for encoder

Abstract: X9013 binary sequence (PRBS) generator whose output is XORed with the clear data stream on the transmitter side , packets remain 0x47. During the inverted sync byte interval (SYNC 1), the PRBS generator is loaded with a seed value of "100101010000000". After the seed is loaded, the PRBS generator runs continuously through , . Randomizer Disable Control: When asserted high, the output of the PRBS generator is not XORed with the data , packet, and low for 16 bytes. The Outer Coder block uses it to qualify on which clock cycles input data
Xilinx
Original
verilog hdl code for encoder X9013 digital FIR Filter verilog code polyphase QPSK using xilinx V50-4

vhdl code for 16 prbs generator

Abstract: verilog code for pseudo random sequence generator in randomizer is a pseudo random binary sequence (PRBS) generator whose output is XORed with the clear data , generator is loaded with a seed value of "100101010000000". After the seed is loaded, the PRBS generator , . Randomizer Disable Control: When asserted high, the output of the PRBS generator is not XORed with the data , . In DVB, this signal is high for the first 188 bytes of the packet, and low for 16 bytes. The Outer , Experience For the source code version, users should be familiar with Verilog HDL entry, synthesis
Xilinx
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qpsk modulation VHDL CODE EN-300-421 0x47 interleaver by vhdl Convolutional Puncturing vhdl

free verilog code of prbs pattern generator

Abstract: CRC-16 LCV LE LIU LOS M23 Mbps NRZ OOF PC PMON PRBS RDI RTL RX SONET SPE STS-1 TX VHDL , programmable. Software searches for the PRBS pattern from the in-coming unframed bit stream. When the number , Midbus allows for connection to a SONET framer. A 16-bit synchronous microprocessor interface (AIRbus , Input Line code violation for single rail signal Receive T3 Mapper Interface Signals rxsclk , placing orders for products or services. All rights reserved. ii Altera Corporation About this
Altera
Original
CRC-16 GR-499-CORE digital alarm clock vhdl code in modelsim HDLC verilog code

XC2VP20FF896

Abstract: vhdl code for lvds driver design. The PRBS generator and comma-count logic are identical. However, for 8B10B encoding and , first stage out of LUTs, a MUXF5 between those two LUTs, and a MUXF6 for the fifth bit. Figure 16 shows , _320M CNT5 CLK_320M 3 CLK_320M X756_16_101304 Figure 16: Block Diagram for 10:1 Serializer , technology is available. AC-Coupled Data Transmission For data transmission between two transceivers , transmission line. Choosing the correct value for the AC coupling depends on the maximum run length occurring
Xilinx
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XAPP756 XC2VP20 XAPP268 XAPP230 XC2VP20FF896 vhdl code for lvds driver MULT18X18S MULT18X18 UG024

verilog code of prbs pattern generator

Abstract: free verilog code of prbs pattern generator Guide [Ref 2] for details regarding the use of internal PCS clock dividers. PRBS Pattern Generation , LFSRs producing a PRBS pattern can be described by a polynomial. For example, the polynomial x15 + x14 , hardly any performance loss with an increase in the number of taps. The PRBS pattern generator designed , , 23, 29, and 31) as specified in ITU-T Recommendation O.150 for PRBS pattern generation [Ref 8]. The , ITU-T Recommendation O.150, Section 5.8 [Ref 8]. This is a recommended PRBS test pattern for 10
Xilinx
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verilog code 16 bit LFSR verilog code 8 bit LFSR in scrambler vhdl code 16 bit LFSR prbs pattern generator lfsr galois 64b/66b encoder XAPP713 8B/10B- PPC405 UG070

MZ80 sensor

Abstract: crt monitor circuit diagram intex 171 Distibuted RAM 400 0 16-Taps 8-Bits For example, a 16-bit shift register that leverages , . Figure 4 shows comparative examples of this for various 16-bit FIR filters. Distributed RAM also allows , . For more information on Xilinx devices, the CORE Generator tool, or CORE Solutions products, contact , . . . .1-5 XC4000-Series FPGAs: The Best Choice for Delivering Cores . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-5 Xilinx CORE Generator . . . . . .
Xilinx
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MZ80 sensor crt monitor circuit diagram intex 171 8086 microprocessor based project on weight AT89C51 opcode SL100 pin configuration generation of control signals in 89c51 micro XC4000-S PCI32 XC3000 XC4000 XC5000
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