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J2014001L401 GE Critical Power GP100, 3&934;-480, RS485 communications, add-on stand-alone shelf, configured for slot 3, hardware and shelf interconnect included visit GE Critical Power
J2014001L601 GE Critical Power Compact Power Line Shelves, GP100, 3Φ-480, dual, redundant, I2C shelf configured for 48Vdc output, configured for slot 1, hardware and shelf interconnect included visit GE Critical Power
J2014001L601A GE Critical Power Compact Power Line Shelves, GP100, 3Φ-480, dual, redundant, I2C shelf configured for 54Vdc output, configured for slot 1, hardware and shelf interconnect included visit GE Critical Power
CP841A_3C3R_S (150032047) GE Critical Power Galaxy Pulsar Edge Controller for Compact Power Line Applications with Security Features Update visit GE Critical Power
J2014003 GE Critical Power Compact Power Line Shelves, Dual I2C shelves for the CP3500 rectifier visit GE Critical Power
J2014001L402 GE Critical Power GP100, 3&934;-480, RS485 communications, controller slot, LAN, RJ45 terminations, configured for slot 3 visit GE Critical Power

vhdl code for 16 bit Pseudorandom Streams Generation

Catalog Datasheet MFG & Type PDF Document Tags

XAPP029

Abstract: adc controller vhdl code FIFOs using the Block SelectRAM+ memory in the Spartan-II FPGAs. Verilog and VHDL code is available for , and up/down counters are described, with lengths of 16 and 32 bits. Design files are available for all , on it. Additional VHDL files are available for direct use of this design. Specifically, the VHDL , supply current incrementally for an operating device. XAPP126 Data Generation and Configuration for , dedicated on-chip blocks of 4096 bit dual-port synchronous RAM, which are ideal for use in FIFO applications
Xilinx
Original
XAPP029 adc controller vhdl code verilog rtl code of Crossbar Switch Insight Spartan-II demo board vhdl code for pn sequence generator XAPP172 Q4-01 XAPP004 XAPP005 XC3000 XAPP007 XAPP008

VHDL CODE FOR 16 bit LFSR in PRBS

Abstract: vhdl code for 8 bit barrel shifter Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data , (CY7B923/CY7B933) is designed primarily for moving streams of 8-bit parallel bytes from one location to , . Scrambler PLD Internal Structure 7 Use HOTLink for 9- and 10-Bit Data pseudo-random data stream
Cypress Semiconductor
Original
VHDL CODE FOR 16 bit LFSR in PRBS vhdl code for 8 bit barrel shifter vhdl code 8 bit LFSR vhdl code for 9 bit parity generator vhdl code for 8 bit parity generator vhdl code for 16 prbs generator CY7B923/933

vhdl code scrambler

Abstract: prbs generator using vhdl Data Out Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code - , ; 13 Use HOTLink for 9- and 10-Bit Data Appendix B. Scrambler VHDL Source Code (continued) ELSE , primarily for operation with a transmission code known as 8B/10B. This code maps all possible 8-bit data , (CY7B923/CY7B933) is designed primarily for moving streams of 8-bit parallel bytes from one location to , 7 Use HOTLink for 9- and 10-Bit Data pseudo-random data stream. This capability (when enabled
Cypress Semiconductor
Original
vhdl code scrambler prbs generator using vhdl vhdl code for pseudo random sequence generator vhdl code for 4 bit barrel shifter vhdl code for 7 bit pseudo random sequence generator vhdl code for 16 bit Pseudorandom Streams Generation

lms algorithm using verilog code

Abstract: lms algorithm using vhdl code .14, 16 64-Bit PCI Target , . 80 C29116A 16-Bit Microprocessor , directly for an authorization code; the AMPP partner will generate this code based on your MAX+PLUS II PC , File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL instantiation templates Megafunction , .14, 16 64-Bit PCI Target
Altera
Original
lms algorithm using verilog code lms algorithm using vhdl code ATM machine working circuit diagram using vhdl verilog code for lms adaptive equalizer verilog code for lms adaptive equalizer for audio digital IIR Filter VHDL code

vhdl HDB3

Abstract: PQFP208 footprint . Figure 10 Backplane Loopbacks 3.9.5 VHDL Code The FPGA must be able to loopback data streams , 3.9.5 VHDL CODE . 26 3.10 ALARMS , provide a T1/E1 interface for the four duplex serial data streams. The TQUAD/EQUAD is a quadruple T1/E1 , 00H Select B8ZS line code for receiver Write XBAS Configuration Register 44H 3XH Select B8ZS, enable for ESF in transmitter (bits defined by `X' determine the FDL data rate & Zero Code
PMC-Sierra
Original
PM4344 PM6344 vhdl HDB3 PQFP208 footprint digital alarm clock vhdl code 74XXX139 alarm clock design of digital VHDL MLL41 TQUAD/PM6344 PMC-980328 PM4344/PM6344 PMC-951013

PRBS23

Abstract: PRBS31 of 10b'1111100000 for 10-bit symbols and 8b'11110000 for 8-bit symbols , for system clock activity. If the clock has ever toggled, the bit is 1. Returns true if the bit has , > Unlocks the SLD chain. Note to Table 14­10: (1) Transfers performed in 16- and 32-bit sizes are packed , cores instantiated in your SOPC Builder system, and for initial bring-up of your printed circuit board , , and Tools panes. f For further details on how to use the System Console GUI, refer to About
Altera
Original
QII53028-10 PRBS23 PRBS31 PRBS-15 verilog code of prbs pattern generator

47hc03

Abstract: PE-64931 .704-compatible transmit and receive interfaces for four 2048 kbit/s E1 data streams or four 1544kb/s T1 data streams. Two , (D/A) converter. A 4-bit (16 levels) D/A converter is updated eight times per period with programmed , the Data Sheet [1] operations section for details. An example of a pulse generation is shown in , of a DS-1 output waveform is presented in FIGURE 12 below. FIGURE 12. Transmit Pulse Generation for , -980474 ISSUE 1 TABLE 5. EOCTL/TOCTL WITH FREEDM-8 REFERENCE DESIGN Transmit XPLS Code (for meeting
PMC-Sierra
Original
PM6388 47hc03 PE-64931 C249-C252 E1 HDB3 A2142 P8009S-ND PMC-980474 PM6388/PM4388

free verilog code of prbs pattern generator

Abstract: CRC-16 .19 Generation & Detection of Pseudo- Random Bit Streams (PRBS , Detection of PseudoRandom Bit Streams (PRBS) Receive On the receive side, PRBS detection is software , Midbus allows for connection to a SONET framer. A 16-bit synchronous microprocessor interface (AIRbus , FEAC channel received from the RXFRMR. The FEAC codes are received as 16-bit sequences, each , asserts the corresponding bit in the FEAC interrupt status register. The RFEAC block receives idle code
Altera
Original
free verilog code of prbs pattern generator CRC-16 GR-499-CORE digital alarm clock vhdl code in modelsim HDLC verilog code

fpga frame buffer vhdl examples

Abstract: E1 pdh vhdl Adaptation Layer for Constant Bit Rate Services, Functionality and Specification", NY, NY, 1993. [6] ITU-T , Physical PLL Phase-Locked Loop PCM Pulse Coded Modulation PRBS Pseudorandom Bit Sequence , streams. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 9 , the actual start time for cell generation deviates from the scheduled start time for cell generation , can be used as long as the cell generation rate per queue is slower than once per frame. For
PMC-Sierra
Original
PM73121 fpga frame buffer vhdl examples E1 pdh vhdl TDM load cell fxs interface integrated circuit CRC-10 PM4341A PMC-1991575

FSP250-60GTA

Abstract: fsp250-60gta power supply schematic -48/STM-16 SONET/SDH SPI-4.2 SDI PCI Express 8-bit RapidIO and 1x/4x Serial RapidIO PCI , placing orders for products or services. Printed on recycled paper ii Altera Corporation , information. For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on this product, go to www.altera.com/mysupport. For , exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf. Also
Altera
Original
FSP250-60GTA fsp250-60gta power supply schematic power supply fsp250-60gta fsp250-60 FSP250 manual FSP250-60gta manual P25-09565-00 RS-232 D-85757

XILINX/HD-SDI over sd

Abstract: smpte 424m to itu 656 Audio/Video Connectivity Solutions for Virtex-II Pro and Virtex-4 FPGAs Reference Designs for , disclosing this Document and Intellectual Property (hereinafter "the Design") to you for use in the , are responsible for obtaining any rights you may require for your use or implementation of the Design , any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness , , FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL
Xilinx
Original
XAPP514 XAPP224 XILINX/HD-SDI over sd smpte 424m to itu 656 CTXIL103 smpte rp 198 3g hd sdi regenerator reclocker smpte 424m to smpte 274m AES18-1996 AES5-2003 AES3-2003 UG073

simple 32 bit LFSR using verilog

Abstract: verilog hdl code for traffic light control . . . . . . . . . . 3­22 16-Bit Versus 32-Bit CRC . . . . . . . . . . . . . . . . . . . . . . . . . , ) File Generation (For the Verilog HDL Testbench) . . . . . . . . . . . . . . . . 5­8 Testbench Time-Out , to 6.375 Gbps per lane Single or multiple lane support (up to 16 lanes) 8-, 16-, or 32-bit , priority packet Optional packet integrity protection using cyclic redundancy code (CRC-32 or CRC-16 , functional simulation models for use in Altera-supported VHDL and Verilog HDL simulators Support for
Altera
Original
simple 32 bit LFSR using verilog verilog hdl code for traffic light control verilog code 16 bit LFSR cyclic redundancy check verilog source 25.263 verilog code 10 bit LFSR in scrambler UG-0705-1

"Single-Port RAM"

Abstract: micro sd verilog MODEL and a Clock and Data Recovery (CDR) unit for flexible clocking. The transmit channel accepts an 8-bit , general-purpose use for the 16 macrocells in the logic block. Two of the remaining three product terms in the , example, a system that operates on a 32-bit data path that runs at 40 MHz can be implemented with 16-bit , Aware PLL Transmit FIFO for flexible variable phase clocking Differential CML serial input with , to: - Bit, byte, half-word, word, multi-word - COMMA or Full K28.5 detect - Single or
Cypress Semiconductor
Original
micro sd verilog MODEL

vhdl code for traffic light control

Abstract: vhdl code for crc16 using lfsr . . . . . . . . . . 3­23 16-Bit Versus 32-Bit CRC . . . . . . . . . . . . . . . . . . . . . . . . . , ) File Generation (For the Verilog HDL Testbench) . . . . . . . . . . . . . . . . 5­8 Testbench Time-Out , to 6.375 Gbps per lane Single or multiple lane support (up to 16 lanes) 8-, 16-, or 32-bit , priority packet Optional packet integrity protection using cyclic redundancy code (CRC-32 or CRC-16 , series Lane order reversal IP functional simulation models for use in Altera-supported VHDL
Altera
Original
vhdl code for traffic light control vhdl code for crc16 using lfsr verilog code 8 bit LFSR in scrambler SerialLite verilog code for traffic light control vhdl code 16 bit LFSR with VHDL simulation output

FRS transceiver

Abstract: micro sd verilog MODEL and a clock and data recovery (CDR) unit for flexible clocking. The transmit channel accepts an 8-bit , inputs. Of the 83 product terms, 80 are for general-purpose use for the 16 macrocells in the logic , achieve higher performance with fewer device resources. For example, a system that operates on a 32-bit data path that runs at 40 MHz can be implemented with 16-bit circuitry that runs internally at 80 MHz , dedicated Spread Aware PLL Transmit FIFO for flexible variable phase clocking Differential CML serial
Cypress Semiconductor
Original
CYP15G04K100V1-MGC FRS transceiver verilog code 5 bit LFSR CYP15G04K200V2-MGC CYP15G04K100V1-MGC/CYP15G04K200V2-MGC

XAPP1014

Abstract: smpte 424m to smpte 274m Audio/Video Connectivity Solutions for Virtex-5 FPGAs Reference Designs for the Broadcast , , release note, and/or specification (the "Documentation") to you solely for use in the development of , , OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR , FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOSS OF , History The following table shows the revision history for this document. Date Version Revision
Xilinx
Original
XAPP1014 3G-SDI serializer SONY service manual circuits dvb-c demultiplexer 425M ML571

wi fi antenna schematic

Abstract: CAPACITOR 10uf 50v E2-5 .704-compatible transmit and receive interfaces for four 2048 kbit/s E1 data streams or four 1544kb/s T1 data streams. Two , (D/A) converter. A 4-bit (16 levels) D/A converter is updated eight times per period with programmed , the Data Sheet [1] operations section for details. An example of a pulse generation is shown in , . Transmit Pulse Generation for DS-1 Mode In te rn a l 8 x c lo c k (S C L K ) TC LKO P o s itiv e P u , Transmit XPLS Code (for meeting ANSI DS-1/E1 template). Recommended Code Register Values with WIDEN = 1
PMC-Sierra
Original
wi fi antenna schematic CAPACITOR 10uf 50v E2-5 MC68340 PM4314 pc motherboard schematics smd m2

3g call flow

Abstract: XAPP1014 Audio/Video Connectivity Solutions for Virtex-5 FPGAs Reference Designs for the Broadcast , you solely for use in the development of designs to operate with Xilinx hardware devices. You may not , WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL , owners. Revision History The following table shows the revision history for this document. Date
Xilinx
Original
3g call flow vhdl code for multiplexing table dvb-t SMPTE 296M timing 720p30 hd-SDI deserializer LVDS 20k preset variable resistor vhdl code for multiplexing Tables in dvb-t

WAC-185-B-X

Abstract: WAC-185-B NOTE on page 176 for more information regarding Bellcore's SRTS patent , mode." for the R_UNDERRUN and R_RESUME field descriptions. · Under section 7.11 "Activating a New Queue on an Active Line" on page 171, changed from "CMD_REG_ATTN" to "CSD_REG_ATTN bit". 01/21/98 , ". · Deleted the first paragraph on page 65. · Replaced section 3.7.1 "SRTS for the Receive Side" starting on page 66 with section 3.7.1 "Generation of TL_CLK" starting on page 68. · Added section
PMC-Sierra
Original
WAC-185-B-X WAC-185-B WAC-021-C-X fairchild nomenclature 7812 p data EAC-030 PMC-980620

TRANSISTOR D400 data sheet download

Abstract: fireberd 6000 service manual section 3.7.1 "SRTS for the Receive Side" starting on page 66 with section 3.7.1 "Generation of TL_CLK , logic that Bellcore holds the patent on. Please refer to the NOTE on page 172 for more information , AVG_SUB_VALU fields for single DS0 no pointer mode. · Changed ItypE3 to ItypDS3 in DC Operating Conditions Table. · Changed the following timing parameters: · Interrupt Timing: PROC_INTR Tq(max) from 16 ns to , undershoot/ overshoot specification, and replaced with absolute maximum voltage range for TTL inputs. ·
PMC-Sierra
Original
TRANSISTOR D400 data sheet download fireberd 6000 service manual PM8318 pm5350 WAC-187-X DS2152
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