NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: code and a schematic symbol are created along with the netlist for the design. The CORE Generator , a name for the component. · Data Width: Select an input filter width from the pulldown menu. The , cascaded 2's complement input data Uses fast carry logic for high speed High performance and density , data and subtracts it from the data input to give a registered output that is one bit wider than the input. Signal names for the schematic symbol are shown in Figure 1 and described in Table 1. ... | Original |
2 pages, |
XC4000 ASSP29 32 bit carry adder vhdl code vhdl code for carry select adder vhdl code for gold code vhdl code for speech processing 32 bit carry select adder code vhdl code for sampling the data VHDL code for band pass Filter 32 bit carry select adder in vhdl low pass Filter VHDL code ASSP29 abstract |
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| Abstract: BitSync Framer INICORE created the structured VHDL CAN-Observer model for simulation and synthesis , / 07/99 Memec Design Services The iniCAN-Observer core is design for data link layer observer , for 1Mbit/s and 8MHz clk: tseg1 = 3 tseg2[2:0] in (tseg + 1) = number of TQ in the second bit , iniCAN-Observer data sheet For controlling the iniCAN core, there are two event inputs for starting and user , description rx_dlc[3:0] out The data length code. Values between 0 and 8 are valid and determine, how ... | Original |
7 pages, |
RXIDE observer datasheet abstract |
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| Abstract: center sampling for the data and stop bits. Three error detection signals are commonly used in UARTs. , This application note provides a functional description of VHDL and Verilog source code for a UART. , discussed. To obtain the VHDL (or Verilog) source code described in this document, go to section VHDL (or Verilog) Code Download, page 3 for instructions. Introduction The Universal Asynchronous Receiver , communication over serial communication links as RS232 RS232. The reference VHDL and Verilog code implements a UART ... | Original |
4 pages, |
verilog code parity verilog code for uart verilog code for shift register vhdl code for rs232 bit parity receiver vhdl code for rs232 interface vhdl code for uart parallel to serial conversion verilog design of UART by using verilog verilog code for uart communication interface of rs232 to UART in VHDL vhdl code for 8 bit register XAPP341 XAPP341 abstract |
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| Abstract: This application note provides a functional description of VHDL and Verilog source code for a UART. , To obtain the VHDL (or Verilog) source code described in this document, go to section "VHDL (or Verilog) Code Download" on page 3 for instructions. Introduction The Universal Asynchronous Receiver , communication over serial communication links as RS232 RS232. The reference VHDL and Verilog code implements a UART , the receiver and then the transmitter. The frame format for data transmitted/received by a UART is ... | Original |
3 pages, |
vhdl code for UART design vhdl code parity xc95144 rs232 XC95144 8 bit data bus using vhdl interface of rs232 to UART in VHDL 16 bit data bus using vhdl vhdl 8 bit register vhdl code for 8 bit shift register XAPP341 uart verilog code xc95144 uart XAPP341 abstract |
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| Abstract: This application note provides a functional description of VHDL and Verilog source code for a UART. , discussed. To obtain the VHDL (or Verilog) source code described in this document, go to section "VHDL (or Verilog) Code Download" on page 3 for instructions. Introduction The Universal Asynchronous Receiver , communication over serial communication links as RS232 RS232. The reference VHDL and Verilog code implements a UART , the receiver and then the transmitter. The frame format for data transmitted/received by a UART is ... | Original |
3 pages, |
vhdl code parity verilog code for uart xilinx vhdl rs232 code vhdl code download vhdl code for uart 16 bit register vhdl transmitter vhdl design of uart serial communication vhdl code for rs232 bit parity receiver uart vhdl vhdl code for 8 bit register xilinx uart verilog code XAPP341 XAPP341 abstract |
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| Abstract: and Verilog source code for a Manchester Encoder Decoder. The reasons to use Manchester code are discussed. The code can be compiled into either the Xilinx XC9572 XC9572 or XCR3064XL XCR3064XL CPLD. To obtain the VHDL (or , 6 for instructions. Introduction Manchester code is defined, and the advantages relative to , of Manchester code ranges from clock/2, occurring when the data pattern is alternating "1s" and "0s" , /boundary of a data cell. With a nonself clocking code, since the clock and data are distinct, there can be ... | Original |
6 pages, |
manchester coding vhdl code 16 bit microprocessor vhdl code for uart communication vhdl code for modulation manchester encoder xilinx generation circuit of manchester XAPP339 cyclic redundancy check verilog source xilinx uart verilog code manchester encoder vhdl code for clock and data recovery XAPP339 abstract |
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| Abstract: and Verilog source code for a Manchester Encoder Decoder. The reasons to use Manchester code are discussed. The code can be compiled into either the Xilinx XC9572 XC9572 or XCR3064XL XCR3064XL CPLD. To obtain the VHDL (or , 6 for instructions. Introduction Manchester code is defined, and the advantages relative to , of Manchester code ranges from clock/2, occurring when the data pattern is alternating "1s" and "0s" , /boundary of a data cell. With a nonself clocking code, since the clock and data are distinct, there can be ... | Original |
6 pages, |
verilog code for digital clock verilog manchester coding uart verilog code vhdl manchester encoder vhdl code for modulation manchester code verilog manchester coding digital clock vhdl code xilinx vhdl code for digital clock generation circuit of manchester line code manchester XAPP339 XAPP339 abstract |
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| Abstract: QuickBench The Visual Testbench Generator for Verilog and VHDL sAutomatic generation of , database paper spec DATA ERROR Expected Value Mismatch Verilog Module VHDL Entity simulator , "testbenches" that define how a design is verified". "For a 60,000 gate ASIC, the testbench has five times as much code as the RTL description of the design." - EETimes - Richard Goering, Editor s "One of the , Shelor, VHDL Consultant, March 1995 CHRONOLOGY® 4 QuickBench addresses the fact that testbench ... | Original |
27 pages, |
datasheet abstract |
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| Abstract: shows the bit timing: - sjw sampling point(s) + sjw sync + tseg1 tseg2 1 CAN bit , performed on the MC-ACT-XCANF using VHDL Test Benches. Simulation vectors used for verification are provided , place and route tool - RTL Version > VHDL Source Code Logic Symbol Controller Area Network (CAN) is a serial network that was originally developed for the automotive industry, and has become a , : - Test Bench Functional Description The XCAN core contains the complete data link layer ... | Original |
5 pages, |
APA450-BG456 AMBA BUS vhdl code AMBA APB bus protocol datasheet abstract |
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| Abstract: , des32.vhd, and des32_tb.vhd. The des.vhd file includes the logic for one channel: the data sampling delay , tap_ctrl_lut.v file includes the logic for one channel, the data sampling delay lines, and the output elastic , sampling and one 155 MHz clock for driving the data recovery state machines. Another 124.4 MHz clock is , the clocks than when using a DCM. Data Sampling Delay Lines The input data for each channel is , nets for all the channels. Figure 2 shows a LUT based data sampling delay line. X R(7) Y R ... | Original |
12 pages, |
XC2V1000 vhdl code 8 bit LFSR verilog code 8 bit LFSR testbench vhdl ram 16 x 4 PPC405 CLK180 vhdl code for clock and data recovery XAPP671 datasheet abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| : C, ASM, VHDL. Code Generation Tool Generation of a source code for each target node environment for the specification, simulation, and implementation of synchronous multi-rate DSP applications on multi-processor systems. Different tools allow for independent descriptions of the application . Features and Benefits Specification Tool A graphical interface for specifying the application and the code. Assignment and Routing Tools Data flow graph manually or automatically partitioned based on www.datasheetarchive.com/files/texas-instruments/sc/docs/dsps/softcoop/hspvirts.htm |
Texas Instruments | 05/06/1998 | 6.1 Kb | HTM | hspvirts.htm |
| loopback 600-ohm output driver VHDL code for serial interface To view the following documents ring/off-hook detection. In the lower-power mode, the TLV320AIC10 TLV320AIC10 TLV320AIC10 TLV320AIC10 converts data at a sampling rate of program internal registers without interference from the data conversion serial port, or without , such as the TMS320Cxx. The options include software reset, device power-down, separate control for ADC , as outlined in Appendix A. The TLV320AIC10 TLV320AIC10 TLV320AIC10 TLV320AIC10 is particularly suitable for a variety of applications www.datasheetarchive.com/files/texas-instruments/data/wwwti~1.com/sc/docs/products/analog/tl89f8~1.htm |
Texas Instruments | 31/01/2000 | 16.55 Kb | HTM | tl89f8~1.htm |
| loopback 600-ohm output driver VHDL code for serial interface To view the following documents ring/off-hook detection. In the lower-power mode, the TLV320AIC10 TLV320AIC10 TLV320AIC10 TLV320AIC10 converts data at a sampling rate of program internal registers without interference from the data conversion serial port, or without , such as the TMS320Cxx. The options include software reset, device power-down, separate control for ADC , as outlined in Appendix A. The TLV320AIC10 TLV320AIC10 TLV320AIC10 TLV320AIC10 is particularly suitable for a variety of applications www.datasheetarchive.com/files/texas-instruments/data/www.ti.com/sc/docs/products/analog/tlv320aic10.html |
Texas Instruments | 31/01/2000 | 16.55 Kb | HTML | tlv320aic10.html |
| sampling an 8-Mbit (.pdf 557,954 bytes) device based on the new process and will ship compatible 4 as fast, 12-volt programming for manufacturing cost-savings. The new FlashFile family provides a high-density, low-cost read/write storage solution well suited for code storage within networking applications, and for high-density data acquisition applications such as digital audio and digital photography flash or downloaded to DRAM, three levels of code protection are offered by the 28F008SC 28F008SC 28F008SC 28F008SC: absolute www.datasheetarchive.com/files/intel/products/design/news/cobra.htm |
Intel | 23/10/1996 | 6.73 Kb | HTM | cobra.htm |
| decodes commands for the core and the direction of the data bus buffer. Figure 1: XF8250 XF8250 XF8250 XF8250 Asynchronous controls the format of the data character. The contents of the LCR may be read, eliminating the need for , contact MDS directly. Recommended Design Experience For the source code versions, users should be Foundation, VHDL and Verilog. Symbols ViewLogic, Foundation Instantiation templates for VHDL and Verilog present in the CLB array. This is done to allow flexibility in using the cores with other logic. For www.datasheetarchive.com/download/55018419-977412ZC/rp069e2.zip (xf8250.pdf) |
Xilinx | 22/02/2000 | 3361.97 Kb | ZIP | rp069e2.zip |
| more information, contact Memec Design Services. Recommended Design Experience For the source code vectors for ViewLogic ViewSim, Testbench for VHDL and Verilog Symbols ViewLogic, Foundation Instantiation templates for VHDL and Verilog Evaluation Model None Reference designs & application notes Sample designs CLB array. This is done to allow flexibility in using the cores with other logic. For instance, if a Figure 1 and described below.Refer to the XF8250 XF8250 XF8250 XF8250 User's Guide for Figure 1: XF8256 XF8256 XF8256 XF8256 Multifunction www.datasheetarchive.com/download/55018419-977412ZC/rp069e2.zip (mds_xf8256.pdf) |
Xilinx | 22/02/2000 | 3361.97 Kb | ZIP | rp069e2.zip |
| the lot. For Military Products, that number is zero. ACCEPTABLE QUALITY LEVEL (AQL) A hypergometric sampling plan defined as the interpolated percent defective for which there is a 95% probability . Normally, the date code is based upon week of seal for the first sublot of the inspection lot counter) for improved design productivity. 2) (CAD tool library) Set of data needed to support the ASIC ENVIRONMENT (ACE) The graphical user interface delivery mechanism for submicron gate-array memory www.datasheetarchive.com/files/texas-instruments/sc/docs/military/liter/glossary/gloss.htm |
Texas Instruments | 04/02/1997 | 51.37 Kb | HTM | gloss.htm |
| for total cells and runt cells trans- mitted. Shift Register This is used for data on the UTOPIA side . Shift Register This module maintains a shift register for shifting data on the ATM side. It takes input transfer with PHY devices, including Switch, SAR and NIC circuits. The MUC facilitates data transfer from the ATM layer, reads them Figure 1: Data transfer between ATM layer device and UTOPIA received bytes and outputs this to the PHY device using TxPrty. It generates count enables for counting www.datasheetarchive.com/download/55018419-977412ZC/rp069e2.zip (utma.pdf) |
Xilinx | 22/02/2000 | 3361.97 Kb | ZIP | rp069e2.zip |
| data input for the IOB flip-flop. The input clock registers itself at the IOB flip-flop with the DCM established. The value K is a constant applied in the HDL code. FIFO and Data Storage Extension When the basic files for the top-level Simple ADS design AdsV2SmplNoFifoWave.do AdsV2SmplNoFifo_Dcm_Wave.do Adc5273Data Constraint Files for use with ISE tools /Verilog Verilog source code /Vhdl /AdcReceiver AdcReceiver.vhd Adc , or information "as is." By providing the design, code, or information as one possible implementation www.datasheetarchive.com/download/4786027-996049ZC/xapp774.zip (xapp774.pdf) |
Xilinx | 23/07/2004 | 1079.49 Kb | ZIP | xapp774.zip |
| data, lost profits, cost - or procurement of substitute goods or services, or for any OVERSAMP : integer := 4; - 4,5 or 10 times over sampling signal ila_data_rx : std - merchantability, non-infringement, or fitness - for a particular purpose. Xilinx does not warrant - that the functions contained in these designs will meet - your requirements, or that the operation of these designs - will be uninterrupted or error free, or that defects www.datasheetarchive.com/download/23037380-996044ZC/xapp759.zip (escon_pcs_nospoof.vhd) |
Xilinx | 26/04/2004 | 2752.08 Kb | ZIP | xapp759.zip |