NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: Customizable VHDL source code available, allowing generation of different netlist versions · Customized , of generics in the synthesizable VHDL source code of the core. Parameters allow the user to specify , Number of channel input bits - Number of channel output bits per channel input bit (allows emulation of , Generator (LFSR) definition parameters: LFSR size, LFSR feedback polynomial, LFSR seed (reset value , with Core Documentation User Manual Design File Formats EDIF netlist, XNF netlist, VHDL source ... | Original |
5 pages, |
FSM VHDL verilog code 8 bit LFSR application X9066 pseudo random generator verilog code 5 bit LFSR verilog code 32 bit LFSR vhdl code 10 bit LFSR verilog code 16 bit LFSR vhdl code 4 bit LFSR verilog code 8 bit LFSR vhdl code 8 bit LFSR vhdl code 16 bit LFSR S40-3 V50-6 S40-3 abstract |
|
|||
| Abstract: must know in advance when the first bit of the new fill code is required to be output from the LFSR , parameterizable. In the VHDL code, the number of taps, as well as, the tap points, and LFSR width are all , of period seven bits at time t = 0 (Table 1). If the 7-bit code were to be repeating within a , system level, a Gold Code generator is usually described by two polynomials that indicate the LFSR structure to be implemented. LFSR 1 Gold Code Out LFSR 2 x211_01_012400 Figure 1: Gold Code ... | Original |
8 pages, |
4 bit pn sequence generator verilog code 8 bit LFSR application SRL16E vhdl code 8 bit LFSR fpga cdma by vhdl examples pn sequence generator verilog code 5 bit LFSR vhdl code 16 bit LFSR simple 32 bit LFSR using verilog vhdl code PN code generator verilog code 32 bit LFSR datasheet abstract |
|
|||
| Abstract: : VHDL 32-bit CRC Serial Implementation VHDL code was written to implement a 32-bit serial CRC calculation. A 32-bit LFSR with clock enable is constructed by instantiating 32 D-type flip-flops and linking , summing checksum has the same probability of missing a bit error as an 8-bit checksum when the data , 32-Bit Error Checking Using the ispLSI 2128E 2128E ® and original data. CRCCs are very effective for , the checksum is internally consistent (i.e. multiple bit errors resulting in the same checksum). ... | Original |
2 pages, |
CRC-12 CRC-32 vhdl code 10 bit LFSR vhdl code for 1 bit error generator crc 16 LFSR 16 bit register vhdl CRC-16 simple LFSR CRC-16 ccitt 32-bit LFSR CRC-16 and CRC-32 CRC-16 and CRC-32 Ethernet 2128E 2128E abstract |
|
|||
| Abstract: : VHDL 32-bit CRC Serial Implementation VHDL code was written to implement a 32-bit serial CRC calculation. A 32-bit LFSR with clock enable is constructed by instantiating 32 D-type flip-flops and linking , summing checksum has the same probability of missing a bit error as an 8-bit checksum when the data , 32-Bit Error Checking Using the ispLSI 2128E 2128E ® and original data. CRCCs are very effective for , the checksum is internally consistent (i.e. multiple bit errors resulting in the same checksum). ... | Original |
2 pages, |
CRC-32 vhdl code for 8 bit shift register 2128E 32-bit LFSR vhdl code 12 bit LFSR CRC-12 CRC-16 CRC-16 and CRC-32 Ethernet 16 bit register vhdl simple 32 bit LFSR using vhdl vhdl code 16 bit LFSR vhdl code CRC 32 vhdl code for crc16 using lfsr 2128E abstract |
|
|||
| Abstract: SRLE16 SRLE16 clk X220_08_091100 Figure 8: 32-bit, 4-tap Parallel LFSR The code has been tested on the , shown in Figure 7. In the 32bit LFSR it will only use five SRL16s (Figure 8). Likewise a 64-bit LFSR , on the LUT that implements the SRL16E SRL16E. An example of a 16-bit LFSR implemented in VHDL and Verilog , : Multicycle Tap Access LFSR HDL Code The reference design was written in both VHDL and Verilog HDL. The , : Utilization Summary (Appendix A Code 16 bit length LFSR) Synopsys FPGA Express v3.4 Synplicity Synplify ... | Original |
10 pages, |
vhdl code 12 bit LFSR lfsr galois 32-bit shift register vhdl code gold sequence code vhdl code for 8 bit parity generator LFSR shift register by using D flip-flop SRL16 VHDL 32-bit pn sequence generator verilog code 32 bit LFSR vhdl code for 9 bit parity generator vhdl code 8 bit LFSR datasheet abstract |
|
|||
| Abstract: of period seven bits at time t = 0 (Table 1). If the 7-bit code were to be repeating within a , LFSR Terminology The basic functional block in Gold code generators are LFSRs. LFSRs sequence , generate the "parity" feedback bit. LFSR Implementation There are two implementation styles of LFSRs , (S-Type) LFSR. Tap Count 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 , Gold Code Out LFSR 2 x217_03_0060700 Figure 3: Gold Code Generator Gold Code Generators using ... | Original |
9 pages, |
PN generator circuit verilog code 5 bit LFSR polynomial 16bit pn sequence generator verilog hdl code for parity generator XAPP217 verilog code 8 bit LFSR lfsr galois GOLD CODE vhdl code PN code vhdl code for pn sequence generator gold sequence generator datasheet abstract |
|
|||
| Abstract: period seven bits at time t = 0 (Table 1). If the 7-bit code were to be repeating within a discrete , feedback bit. LFSR Implementation There are two implementation styles of LFSRs, Galois implementation , (S-Type) LFSR. Tap Count 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 , Gold Code Out LFSR 2 x217_03_0060700 Figure 3: Gold Code Generator Gold Code Generators using the LFSRs Implemented in Virtex Devices A 16-bit LFSR uses one slice in a Virtex device. A Virtex ... | Original |
8 pages, |
verilog code 16 bit LFSR gold codes generator vhdl code PN code generator gold sequence generator polynomial shift register coding SRL16 SRL16E verilog code 8 bit LFSR XILINX CROSS REFERENCE vhdl code 10 bit LFSR GOLD CODE datasheet abstract |
|
|||
| Abstract: A2 A3 X465_19_040503 Figure 8: SRLC16E SRLC16E Primitive Initialization in VHDL and Verilog Code A shift register can be initialized in VHDL or Verilog code for both synthesis and simulation. For , 17: 52-bit LFSR Gold Code Generator Gold code generators are used in CDMA systems to generate , document provides generic VHDL and Verilog submodules and reference code examples for implementing from , Q7 as the output, emulating an 8-bit shift register. Note that since the address lines control the ... | Original |
17 pages, |
vhdl code for pn sequence generator vhdl code 8 bit LFSR vhdl code for rs232 receiver using fpga verilog code 32 bit LFSR SRLC16E gold code generator vhdl code for n bit generic counter shift register by using D flip-flop verilog code 8 bit LFSR vhdl code for rs232 receiver fpga cdma by vhdl examples SRL16 XAPP465 SRL16 abstract |
|
|||
| Abstract: first bit of the new fill code is required to be output from the LFSR. The new serial fill sequence , : 41-stage, 2-tap LFSR with SRL16s in a Virtex-II Device HDL Code Verilog and VHDL code examples have , points and LFSR width are parameterizable. In the VHDL code, the number of taps, as well as, the tap , of period seven bits at time it = 0 (Table 1). If the 7-bit code were to be repeating within a , level, a Gold Code generator is usually described by two polynomials that indicate the LFSR structure ... | Original |
10 pages, |
verilog hdl code for parity generator fpga cdma by vhdl examples vhdl code PN code vhdl code gold sequence code gold code generator 4 bit pn sequence generator simple LFSR PN generator circuit vhdl code for 9 bit parity generator qpsk modulation VHDL CODE vhdl code 8 bit LFSR datasheet abstract |
|
|||
| Abstract: are fixed, however the tap points and LFSR width are parameterizable. In the VHDL code, the number of , of period seven bits at time t = 0 (Table 1). If the 7-bit code were to be repeating within a , that indicate the LFSR structure to be implemented. LFSR 1 Gold Code Out LFSR 2 , , the following HDL code (Table 3) will infer a 64-bit shift register using SRLs rather than FFs. Table 3: 64-Bit SRL Shift Register Example VHDL Verilog Always @(posedge clk) begin process (clk ... | Original |
10 pages, |
simple 32 bit LFSR using verilog simple 32 bit LFSR using vhdl SRL16 SRL16E vhdl code 10 bit LFSR XAPP211 vhdl code for pn sequence generator vhdl code 8 bit LFSR c code 4 bit LFSR pn sequence generator vhdl code gold sequence code LFSR datasheet abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| - and 5-bit universal LFSR counters, very efficient RAM-based 32-bit and 100-bit shift registers, and integration of a 16-Tap, 8-Bit Finite Impulse Response (FIR) filter macro with predefined coefficients (e : Maximum Logic Gates, Maximum Memory Bits, and Typical Gate Range. The methodology used to determine features are discussed, and examples show how to use them. Efficient Shift Registers, LFSR bits can be implemented most efficiently in XC4000E XC4000E XC4000E XC4000E Select-RAM. Using Linear Feedback Shift www.datasheetarchive.com/files/xilinx/weblinx/apps/fpga-v1.htm |
Xilinx | 25/09/1996 | 10.88 Kb | HTM | fpga-v1.htm |
| - - The following VHDL code implements a 511x8 FIFO in a Spartan . * * * * The following Verilog code implements a 511x8 FIFO in a Spartan-II* * device. The System VHDL or Verilog Nutritional Analysis easily generated. Linear Feedback Shift Registers (LFSRs) are used for both the read LFSRs is acceptable. They use very little logic, and are therefore much faster than a www.datasheetarchive.com/files/xilinx/docs/rp00007/rp007ae.htm |
Xilinx | 29/02/2000 | 26.1 Kb | HTM | rp007ae.htm |
| . Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each configured as a 16-bit shift register (SRL16 SRL16 SRL16 SRL16 macro). Hence, Xilinx devices implement efficient LFSRs Controller 100 KB VHDL, PC VHDL, UNIX Verilog, PC Verilog, UNIX 64-bit, PC 64-bit, UNIX 16-bit, PC www.datasheetarchive.com/files/xilinx/docs/rp00001/rp001ed.htm |
Xilinx | 19/03/2000 | 25.07 Kb | HTM | rp001ed.htm |
| CryptoBlaze: 8-Bit Security Microcontroller PicoBlaze Agenda What is CryptoBlaze? KryptoKit GF(2m customizable soft microcontroller PicoBlaze 49 baseline16-bit instructions 8 general-purpose 8-bit " correction PicoBlaze Example: GF(23) Multiply Example of 8 Bit Multiplication 57 * 83 = C1 addresses going out from there. Note that operands exit to the outside world as 8 bit bytes right above the intermediate result goes up to 9 bits, we need to EX-OR the reduction value with the leftmost 8 bits, to keep www.datasheetarchive.com/files/xilinx/files/cpld _modules/cryptoblaze.pps |
Xilinx | 08/03/2004 | 1209 Kb | PPS | cryptoblaze.pps |
| appropriate taps for maximum-length LFSR counters up to 168 bits. Configuring FPGAs Over a ) Compliant PCI Interface in XC3164A XC3164A XC3164A XC3164A (171 kb) 16-Tap, 8-Bit FIR Filter Application Note (175 kb) This application note describes the functionality and integration of a 16-Tap, 8-Bit . Contact Xilinx for DSP applications information via E-mail at dsp@xilinx.com . 16-Tap, 8-Bit integration of a 16-Tap, 8-Bit Finite Impulse Response (FIR) filter macro with predefined coefficients (e www.datasheetarchive.com/files/xilinx/weblinx/products/appsweb.htm |
Xilinx | 19/09/1996 | 24.83 Kb | HTM | appsweb.htm |
| # generators using LFSRs function lfsr(i : BIT_VECTOR) return BIT_VECTOR; - Gray counters function . - - Disclaimer : XILINX IS PROVIDING THIS DESIGN, CODE, OR - INFORMATION "AS IS" SOLELY FOR USE - PROVIDING THIS DESIGN, CODE, OR INFORMATION AS - ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE logic. - NOTE : assumes negative numbers require full 32 bits - Was in DWARE library, but Synplicity had a conflict with DWARE function bit_width (d : INTEGER) return NATURAL; - Functions to pad www.datasheetarchive.com/download/66124278-995866ZC/mfrd_source_code.zip (functions.vhd) |
Xilinx | 11/11/2004 | 958.87 Kb | ZIP | mfrd_source_code.zip |
| . - - - - The following VHDL code implements a 511x8 FIFO in a Spartan-II - - device. The inputs are a /13/99 - - - - Description : FIFO controller top level. - - Implements a 511x8 _logic_vector(8 downto 0) := "000000000"; signal write_addr: std_logic_vector(8 downto 0) := "000000000"; signal fcounter: std_logic_vector(8 downto 0) := "000000000"; signal read port ( I: IN std_logic; O: OUT std_logic); END component; component RAMB4_S8_S8 www.datasheetarchive.com/download/66187846-995901ZC/xapp175.zip (fifoctlr_cc.vhd) |
Xilinx | 13/12/1999 | 12.59 Kb | ZIP | xapp175.zip |
| . - - - - The following VHDL code implements a 511x8 FIFO in a Virtex - - device. The inputs are a /19/98 - - - - Description : FIFO controller top level. - - Implements a 511x8 _logic_vector(8 downto 0) := "000000000"; signal write_addr: std_logic_vector(8 downto 0) := "000000000"; signal fcounter: std_logic_vector(8 downto 0) := "000000000"; signal read port ( I: IN std_logic; O: OUT std_logic); END component; component RAMB4_S8_S8 port www.datasheetarchive.com/download/77571583-967559ZC/rp0276e.zip (fifoctlr_cc.vhd) |
Xilinx | 22/02/2000 | 72.35 Kb | ZIP | rp0276e.zip |
| . - - - - The following VHDL code implements a 511x8 FIFO in a Spartan-II - - device. The inputs are a /13/99 - - - - Description : FIFO controller top level. - - Implements a 511x8 _logic_vector(8 downto 0) := "000000000"; signal write_addr: std_logic_vector(8 downto 0) := "000000000"; signal fcounter: std_logic_vector(8 downto 0) := "000000000"; signal read port ( I: IN std_logic; O: OUT std_logic); END component; component RAMB4_S8_S8 www.datasheetarchive.com/download/47238106-995900ZC/xapp175.tar.z |
Xilinx | 13/12/1999 | 18.37 Kb | Z | xapp175.tar.z |
| . - - - - The following VHDL code implements a 511x8 FIFO in a Virtex - - device. The inputs are a /19/98 - - - - Description : FIFO controller top level. - - Implements a 511x8 _logic_vector(8 downto 0) := "000000000"; signal write_addr: std_logic_vector(8 downto 0) := "000000000"; signal fcounter: std_logic_vector(8 downto 0) := "000000000"; signal read port ( I: IN std_logic; O: OUT std_logic); END component; component RAMB4_S8_S8 port www.datasheetarchive.com/download/90081483-986258ZC/wcd013d0.zip (fifoctlr_cc.vhd) |
Xilinx | 12/02/1999 | 12.35 Kb | ZIP | wcd013d0.zip |