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vhdl code 16 bit processor

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Abstract: the library, simplifying the code for sequential elements (­v is used on a bit vector, 16 bits in , Description FPGA VHDL Description A block diagram of the packet processor FPGA is shown in Figure 2 , in a few pages of VHDL. Figure 3 gives the entire code for the packet multiplexer. The entity , can be routed to the output port. Referring to packet multiplexer A, input port A is the 16-bit , Appl i cat i o n N ot e A 64 MHz RISC Coprocessor Using the A1460 and VHDL Entry Warren Miller Actel
vhdl code for risc processor vhdl code for multiplexer vhdl code CRC 4 bit risc processor using vhdl vhdl code for multiplexer 2 to 1 16 bit risc processor using vhdl code A1460A 1I566 1I315 1I549
Abstract: General Purpose Input/Output Controller VME Slave Controller 24-bit address, 16-bit data bus VME Slave , address, 16-bit data VME slave controller with interrupts; 32-bit address, 32-bit data Gigabit Fibre , Interface (example is 4 channels, 16-bit data) POS-PHY Level 3 PHY interface POS-PHY Level 2 Link Layer , Module - Two 16-bit timers with 16-bit pre-scaler Interrupt Controller Serial Peripheral Interface (SPI , -, or 32- bit data-bus width Receive Data RAM Address RAM · Two 16-bit timer/counters PCI Actel
vhdl code for watchdog timer of ATM zilog 3570 z80 vhdl vhdl code for a 16*2 lcd vhdl code for rs232 receiver vhdl code for ethernet csma cd RS232
Abstract: XAPP058 and VHDL code for the XC95108. These files along with others mentioned are obtainable from the , contains the functionality described in the VHDL code. The VHDL design contains a UART receiver (entity , processor data bus in high impedance. In the VHDL design, the top level connectivity file (IRDNLD , interface control engine are defined in a package called "datatype". See the comments in the VHDL code , / PROGRAM operations (i.e. ERASE/PROGRAM/VERIFY, or BYPASS), you may need to modify the VHDL code to Xilinx
xilinx xc95108 jtag cable Schematic vhdl code for rs232 interface block diagram UART using VHDL vhdl code for uart communication vhdl code for rs232 receiver using cpld 4 bit microcontroller using vhdl XC9500 XC95108-10-PC84 XC95108-10PC84
Abstract: .14, 16 64-Bit PCI Target , . 80 C29116A 16-Bit Microprocessor , .14, 16 64-Bit PCI Target , , reference design ID Code: 73E2-1204 s s s s s s s s s s s 32-bit, 33-MHz PCI function Fully compliant , megafunction. 16 Altera Corporation Bus & Interface Figure 4. 32-Bit PCI Master/Target Megafunction Altera
lms algorithm using verilog code lms algorithm using vhdl code verilog code for lms adaptive equalizer digital IIR Filter VHDL code 8086 microprocessor based project qpsk demodulation VHDL CODE
Abstract: code. These BFL files are stimulus files for the Bus Functional Models located in the /hw/XilinxBFMinterface/pcores directory. The examples in xapp516.zip include BFL and VHDL test code to provide stimuli , in m4 eval macro to calculate two hex digits to create the 32-bit value. The 0x"eval(i*4, 16,2 , ) simulation of Xilinx Processor Intellectual Processor (PIP) cores. These BFMs allow the simulation of PIP cores which interface to the IBM CoreConnectTM Processor Local Bus (PLB) and On-chip Peripheral Bus Xilinx
XAPP515 XAPP516 0x000000F9 0x300000FF 0xABCDEF12 0000000F FF000000 00FF0000 0000FF00 000000FF
Abstract: data communication between the microprocessor and memory. The data bus from the processor is 16-bit , interface. This interface consists of the 16-bit processor data bus, u_data[15:0], the read/write control , high-speed performance. A complete VHDL design is available with this application note, see VHDL Code, page , represent powers of two are dedicated to parity bits. Table 1 illustrates how the 16-bit data word and parity bits are stored in memory. Table 1: Hamming Code Data and Parity Bits Bit Position 22 Xilinx
XAPP383 SECDED vhdl code SECDED vhdl code 16 bit microprocessor vhdl code hamming error correction code in vhdl verilog code hamming
Abstract: 16 Mbytes. Each chip has 8 databits and one bit for parity. When the Pentium processor wants to , described in VHDL and uses the Cypress Warp2® VHDL compiler. The VHDL code can be obtained from your local , Processor 100/133 MHz with a bus speed of 66 MHz · Memory device SDRAM 16 Mbytes - 66 MHz · Quad word , address latch is described in VHDL. This code can be obtained from your local Cypress FAE. WRITE: In , . This VHDL code can be obtained from your local Cypress FAE. Address Decoder Table 2. CS Decoding Cypress Semiconductor
asynchronous dram Cypress Applications Handbook vhdl code for sdram controller CY7C375
Abstract: described in VHDL and uses the Cypress Warp2® VHDL compiler. The VHDL code can be obtained from your local , Processor 100/133 MHz with a bus speed of 66 MHz · Memory device SDRAM 16 Mbytes - 66 MHz · Quad word , VHDL. This code can be obtained from your local Cypress FAE. WRITE: In this state the CAS command , chip has 8 databits and one bit for parity. When the Pentium processor wants to read/write a byte , decoding. The functional description of the Control FSM is described in VHDL. This VHDL code can be Cypress Semiconductor
pentium 4 opcode list
Abstract: Code · BC/RT/Monitor and RT-Only Configurations. · Single Clock Domain, Selectable for 10, 12, 16 , code, VHDL test bench, and supporting documentation, thus enabling designers to instantiate the , 7 uS uS 4 660.5 SOURCE CODE LANGUAGE VHDL SUPPORT DOCUMENTATION ACECore IP User , On-Chip Tri-State Buses. - Shared RAM, Up to 64K X 16 or 64K X 17 (with RAM parity) - 16-bit Address, 16-bit or 8-bit Data Path - "Zero Wait State" Interface (no hardware acknowledge) for Data Device
BU-69200 MT 6605 STANAG-3838 vhdl code manchester encoder vhdl code for manchester decoder MIL-STD-1553 vhdl MIL-STD-1553 1-800-DDC-5757 A5976
Abstract: Data Bus Byte Paths. Control/Status Bit [0] [1] [2] [3] Data Bits [7:0] [15:8] [23:16] [31:24 , · · · · · · · · · · · · · · · Rocket I/O Transceiver Processor Block Global Clock Networks , loopback test modes. Bit 1 is for serial loopback and bit 0 is for internal parallel loopback. Shuts down , REFCLK or REFCLK2. Deasserted is REFCLK. Asserted is REFCLK2. Receiver elastic buffer status. Bit 1 indicates if an overflow/underflow error has occurred when asserted High. Bit 0 indicates if the buffer is Xilinx
32x32 multiplier verilog code 4x4 unsigned multiplier VERILOG coding 12v relay interface with cpld in vhdl MULT18X18 80C31 instruction set vhdl code for 18x18 unSIGNED MULTIPLIER UG012 PCI64 DO-DI-PCI64-IP
Abstract: , VirtexTM, and VirtexTM-E devices · Decoder of convolutional codes · Customizes VHDL source code , post-synthesis verification supplied with the module · Core customization: - Convolutional code definition parameters: Code rate; Code generation vectors; Code constraint length - Number of input bits per symbol bit (specifies number of quantization levels for soft decoding) - Traceback decision depth - Radix , , VHDL source available extra Constraints File TOP_VITERBI_DEC_nl.ncf Verification VHDL testbench Xilinx
vhdl code for branch metric unit processor control unit vhdl code vhdl coding for hamming code branch metric hamming decoder vhdl code Radix selection unit I-10148 S40-3 V50-6
Abstract: higher. This application note shows how the 32-bit MicroBlazeTM processor can easily access these wide , Xilinx EDK SDRAM interface, enabling a 32-bit processor to access a 64-bit data bus. Introduction , from the processor. An access must first call the lower addressed 32-bit word followed by the address , processor in the FPGA can use its native 32-bit read and write operations as if it is accessing 32-bit memories. To access the 64-bit memory, the processor must issue a Low address (LS address bit = 0 Xilinx
XAPP729 PPC405 XC4VSX35-10FF668C SDD44 UCF virtex4 X729 vhdl sdram
Abstract: the PowerPC processor is clocked at 100 MHz. Bit transmit and receive operations are implemented , includes code examples in Verilog and VHDL. The PowerPC software reference design example is in C. The , Module GPIO Pin Connections Code Bit Number Description gpio_out[31] 0 LCD D0 gpio_out , processor overhead variations. As shown in "Appendix A: Simulation Examples", the eighth bit has a maximum , the start bit. Once the start bit is detected, the timer is read, and the processor reads the first Xilinx
verilog code for uart verilog code for uart communication UART using VHDL uart verilog code verilog code lcd interface of rs232 to UART in VHDL XAPP699 XAPP672
Abstract: codes. There is an extra 12 bit code that represents an endof-line (EOL) and finally any spare '0's in , code or a by Make-up code followed by a Termination code. The bit stream given in Figure 1 would , lines from the two 5-bit trees produces 5 outputs representing a code length of 2 to 6 bits. 2 , forks into two 16-bit shift registers, The longest valid fax codes are 13 bits long. By adding a , code is detected. 13-bit codes only exist for black pixel data and a following section describes the Xilinx
XC6200 XC6216 vhdl code for huffman decoding vhdl code for sr flipflop vhdl code for flip-flop vhdl code for 8 bit register XAPP085 XC6000DS XC6000
Abstract: 1995 1996 16-bit MPU 1997 1998 1999 32-bit CISC 32-bit RISC 32/16-bit MCU In-Stat , Objectives to develop a processor core providing 32-Bit MCU + DSP + DMA capabilities in the range of 10 , TEMIC Semiconductors MATRA MHS SPARCletTM 32 bit RISC microcontroller family Richard , Industrie TEMIC MATRA MHS Total WW High-End Embedded Processor Market 1999: $12,313 M 21 , Code generation Chain Improved SPARC Embedded Architecture Digital Signal Processing Support Temic Semiconductors
vhdl code 8 bit processor verilog code 16 bit CISC CPU verilog code for 32 bit risc processor vhdl code cisc processor vhdl code 32 bit risc code vhdl code 32 bit processor 90C7001 90C701 90C714 90C712 90C711
Abstract: FEATURES Three independent 16-bit counters Six programmable Counter modes Interrupt on , Software triggered strobe Source code: VHDL Source Code or/and VERILOG Source Code or/and , VHDL, Verilog source code called HDL Source Encrypted or plain text EDIF called Netlist , functionally identical and fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one , Element ­ 16 bit presettable synchronous down BIN/BCD counter. All trademarks mentioned in this Digital Core Design
D8254 82C54 vhdl code for 4 bit binary counter VHDL code for Real Time Clock binary multiplier Vhdl code binary multiplier Verilog code bcd verilog vhdl code for 8 bit common bus
Abstract: Peripherals: 10/100 Ethernet MAC AX1610 16-bit RISC Processor Xilinx Loarant LogiCORE AllianceCORE Interfaces , - End COMPONENT Declaration - The following code must appear in the VHDL architecture - , DVB-RCS compliant, 9 Mb/s data rate, switchable code rates and frame sizes Flexbus 4 Interface Core, 16 , Xilinx Xilinx Xilinx Xilinx LogiCORE LogiCORE LogiCORE LogiCORE 32 full duplex, CRC-16/32, 8/16-bit address insertion/deletion 16/32-bit frame seq, 8/16bit addr insert/delete, flag/zerop insert/detect Xilinx
Turbo decoder Xilinx verilog code for floating point adder dvb-RCS chip verilog code for FFT 32 point 65-bit vhdl code of 32bit floating point adder
Abstract: the upper column address on the DRAM address lines to select the upper byte of the 16-bit data lines , column address on the DRAM address lines to select the lower byte of the 16-bit data lines on the DRAM , -25MHz embedded processor · Use two 60 ns 16 Mbits DRAM (1M x 16) · Support random and page mode read/write , modification if implemented for another processor family. Figure 1. Fast Page Mode DRAM System RAS10 A[23:0] WE0 ASB UCAS0 SIZ[1:0] RWB CLKOUT MC68340 Processor LCAS0 MACH Memory Lattice Semiconductor
RAS20 decoder.vhd 180lt128 4 bit microprocessor using vhdl LC4256ZE vhdl code for 8-bit parity generator RD1014 LC4256ZE-5TN100C M4A3-128/64-55VC LSI5128VE-180LT128 LCMXO256E-5T100C
Abstract: Microprocessors, Controllers & Peripherals 10/100 Ethernet MAC AX1610 16-bit RISC Processor C165X MicroController , COMPONENT Declaration - The following code must appear in the VHDL architecture - body , distributed using the Xilinx CORE Generator. A core can take the form of synthesizable VHDL or Verilog code , LogiCORE 34% 81 XC2V250 X.25, POS, cable 32 full duplex, CRCmodems, frame 16/32, 8/16-bit address relay switches, insertion/deletion video confer. over ISDN 16/32-bit frame seq, 8/16-bit addr Xilinx
multiplier accumulator MAC code verilog xilinx logicore fifo generator 6.2 vhdl code 32bit LFSR vhdl code for FFT 256 point vhdl code direct digital synthesizer verilog code for distributed arithmetic XC2V1000 FG456-5 XC2V1000-5 XC2V1000-4 UG002
Abstract: SPARC V8 32-bit Processor LEON3 / LEON3-FT CompanionCore Data Sheet GAISLER Features Description · · · · · · · · · · · The LEON3 is a 32-bit processor based on the SPARC V8 , AHB I/F AMBA AHB Master (32-bit) Applications The LEON3 processor is designed for embedded , 2 x UART 16 x GPIO AHB / APB 32-bit AMBA AHB AHB CTRL Memory Controller with EDAC , VHDL source code or as a pre-synthesized netlist. The LEON3-FT core is available as a pre-synthesized Aeroflex Gaisler
LEON3FT M Meiko leon3 leon processor interrupt vhdl fpu coprocessor vhdl code for simple radix-2 IEEE-STD-754 IEEE-754
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