500 MILLION PARTS FROM 12000 MANUFACTURERS

Datasheet Archive - Datasheet Search Engine

 

vhdl code 16 bit processor

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: the library, simplifying the code for sequential elements (­v is used on a bit vector, 16 bits in , Description FPGA VHDL Description A block diagram of the packet processor FPGA is shown in Figure 2 , in a few pages of VHDL. Figure 3 gives the entire code for the packet multiplexer. The entity , can be routed to the output port. Referring to packet multiplexer A, input port A is the 16-bit , Appl i cat i o n N ot e A 64 MHz RISC Coprocessor Using the A1460 A1460 and VHDL Entry Warren Miller ... Actel
Original
datasheet

4 pages,
27.38 Kb

16 bit multiplexer vhdl A1460 full vhdl code for input output port vhdl code for data memory vhdl code for multiplexer 3 to 2 16 bit risc processor using vhdl code vhdl code for multiplexer 2 to 1 4 bit risc processor using vhdl vhdl code CRC vhdl code 16 bit processor vhdl code for multiplexer vhdl code for risc processor TEXT
datasheet frame
Abstract: General Purpose Input/Output Controller VME Slave Controller 24-bit address, 16-bit data bus VME Slave , address, 16-bit data VME slave controller with interrupts; 32-bit address, 32-bit data Gigabit Fibre , Interface (example is 4 channels, 16-bit data) POS-PHY Level 3 PHY interface POS-PHY Level 2 Link Layer , Module - Two 16-bit timers with 16-bit pre-scaler Interrupt Controller Serial Peripheral Interface (SPI , -, or 32- bit data-bus width Receive Data RAM Address RAM · Two 16-bit timer/counters PCI ... Actel
Original
datasheet

8 pages,
968.37 Kb

6809 cpu vhdl code 16 bit microprocessor vhdl code for 4 channel dma controller MIL-STD-1553B FPGA Z80 SCC vhdl code for rs232 interface APA075 Z80 PROCESSOR in aerospace A24D16 vhdl code 8 bit processor vhdl code for UART design 1553b VHDL vme vhdl VHDL rs232 driver vhdl code for ethernet csma cd vhdl code for rs232 receiver vhdl code for a 16*2 lcd z80 vhdl zilog 3570 vhdl code for watchdog timer of ATM TEXT
datasheet frame
Abstract: XAPP058 XAPP058 and VHDL code for the XC95108 XC95108. These files along with others mentioned are obtainable from the , contains the functionality described in the VHDL code. The VHDL design contains a UART receiver (entity , processor data bus in high impedance. In the VHDL design, the top level connectivity file (IRDNLD , interface control engine are defined in a package called "datatype". See the comments in the VHDL code , / PROGRAM operations (i.e. ERASE/PROGRAM/VERIFY, or BYPASS), you may need to modify the VHDL code to ... Xilinx
Original
datasheet

5 pages,
77.98 Kb

vhdl code for transceiver using UART DOWN COUNTER using 8051 uart vhdl XSVF microcontroller using vhdl rs232 VHDL xc9500 74x373 xilinx vhdl rs232 code simple microcontroller using vhdl XAPP058 UART using VHDL interface of rs232 to UART in VHDL infrared counter vhdl 4 bit microcontroller using vhdl vhdl code for rs232 receiver using cpld vhdl code for uart communication block diagram UART using VHDL vhdl code for rs232 interface xilinx xc95108 jtag cable Schematic vhdl code for rs232 receiver TEXT
datasheet frame
Abstract: .14, 16 64-Bit PCI Target , . 80 C29116A C29116A 16-Bit Microprocessor , .14, 16 64-Bit PCI Target , , reference design ID Code: 73E2-1204 73E2-1204 s s s s s s s s s s s 32-bit, 33-MHz PCI function Fully compliant , megafunction. 16 Altera Corporation Bus & Interface Figure 4. 32-Bit PCI Master/Target Megafunction ... Altera
Original
datasheet

224 pages,
1791.86 Kb

jpeg encoder vhdl code MCS-80 design kit verilog code for 2D linear convolution SICAN verilog DTMF decoder verilog code for lms VHDL CODE FOR PID CONTROLLERS ternary content addressable memory VHDL EFP10K10 qpsk demodulation VHDL CODE verilog code for fir filter using DA 8086 microprocessor based project digital IIR Filter VHDL code verilog code for lms adaptive equalizer lms algorithm using vhdl code lms algorithm using verilog code TEXT
datasheet frame
Abstract: code. These BFL files are stimulus files for the Bus Functional Models located in the /hw/XilinxBFMinterface/pcores directory. The examples in xapp516.zip include BFL and VHDL test code to provide stimuli , in m4 eval macro to calculate two hex digits to create the 32-bit value. The 0x"eval(i*4, 16,2 , ) simulation of Xilinx Processor Intellectual Processor (PIP) cores. These BFMs allow the simulation of PIP cores which interface to the IBM CoreConnectTM Processor Local Bus (PLB) and On-chip Peripheral Bus ... Xilinx
Original
datasheet

7 pages,
42.01 Kb

XAPP516 XAPP515 0xABCDEF12 0x300000FF 0x000000F9 TEXT
datasheet frame
Abstract: data communication between the microprocessor and memory. The data bus from the processor is 16-bit , interface. This interface consists of the 16-bit processor data bus, u_data[15:0], the read/write control , high-speed performance. A complete VHDL design is available with this application note, see VHDL Code, page , represent powers of two are dedicated to parity bits. Table 1 illustrates how the 16-bit data word and parity bits are stored in memory. Table 1: Hamming Code Data and Parity Bits Bit Position 22 ... Xilinx
Original
datasheet

4 pages,
34.77 Kb

XC2C128 7 bit hamming code hamming code hamming code in vhdl 4 bit Microprocessor VHDl code XAPP383 Error Detection hamming vhdl vhdl code 8 bit processor block diagram code hamming error detection code in vhdl verilog code hamming error correction code in vhdl vhdl code hamming vhdl code 16 bit processor vhdl code 16 bit microprocessor vhdl code SECDED SECDED TEXT
datasheet frame
Abstract: 16 Mbytes. Each chip has 8 databits and one bit for parity. When the Pentium processor wants to , described in VHDL and uses the Cypress Warp2® VHDL compiler. The VHDL code can be obtained from your local , Processor 100/133 MHz with a bus speed of 66 MHz · Memory device SDRAM 16 Mbytes - 66 MHz · Quad word , address latch is described in VHDL. This code can be obtained from your local Cypress FAE. WRITE: In , . This VHDL code can be obtained from your local Cypress FAE. Address Decoder Table 2. CS Decoding ... Cypress Semiconductor
Original
datasheet

8 pages,
198.54 Kb

vhdl code for sdram controller Cypress Applications Handbook asynchronous dram TEXT
datasheet frame
Abstract: described in VHDL and uses the Cypress Warp2® VHDL compiler. The VHDL code can be obtained from your local , Processor 100/133 MHz with a bus speed of 66 MHz · Memory device SDRAM 16 Mbytes - 66 MHz · Quad word , VHDL. This code can be obtained from your local Cypress FAE. WRITE: In this state the CAS command , chip has 8 databits and one bit for parity. When the Pentium processor wants to read/write a byte , decoding. The functional description of the Control FSM is described in VHDL. This VHDL code can be ... Cypress Semiconductor
Original
datasheet

8 pages,
192.21 Kb

pentium 4 opcode list TEXT
datasheet frame
Abstract: Code · BC/RT/Monitor and RT-Only Configurations. · Single Clock Domain, Selectable for 10, 12, 16 , code, VHDL test bench, and supporting documentation, thus enabling designers to instantiate the , 7 uS uS 4 660.5 SOURCE CODE LANGUAGE VHDL SUPPORT DOCUMENTATION ACECore IP User , On-Chip Tri-State Buses. - Shared RAM, Up to 64K X 16 or 64K X 17 (with RAM parity) - 16-bit Address, 16-bit or 8-bit Data Path - "Zero Wait State" Interface (no hardware acknowledge) for ... Data Device
Original
datasheet

4 pages,
371.28 Kb

16 word 8 bit ram using vhdl vhdl code for 4 bit ram Enhanced Mini-ACE 1553 VHDL MIL-STD-1553 vhdl vhdl code for manchester decoder vhdl code manchester encoder BU-69200 STANAG-3838 MT 6605 MIL-STD-1553 TEXT
datasheet frame
Abstract: Data Bus Byte Paths. Control/Status Bit [0] [1] [2] [3] Data Bits [7:0] [15:8] [23:16] [31:24 , · · · · · · · · · · · · · · · Rocket I/O Transceiver Processor Block Global Clock Networks , loopback test modes. Bit 1 is for serial loopback and bit 0 is for internal parallel loopback. Shuts down , REFCLK or REFCLK2. Deasserted is REFCLK. Asserted is REFCLK2. Receiver elastic buffer status. Bit 1 indicates if an overflow/underflow error has occurred when asserted High. Bit 0 indicates if the buffer is ... Xilinx
Original
datasheet

227 pages,
2068.17 Kb

national semiconductor catalog vhdl code for 18x18 unSIGNED MULTIPLIER adder xilinx vhdl pulse interval encoder 80C31 instruction set 12v relay interface with cpld in vhdl 32x32 multiplier verilog code 4x4 unsigned multiplier VERILOG coding TEXT
datasheet frame

Archived Files

Abstract Saved from Date Saved File Size Type Download
A fully customizable 8-bit soft microcontroller macros that provides 49 16-bit instructions 8 Filename.log Download assembled object code to EEPROM PicoBlaze Quick Start Training Making a Processor Start Training Program Memory Integration Binary code and processor can be integrated into a the same instruction set as FPGA version FGPA has 16 general-purpose 8-bit registers, CR-II uses 8
/datasheets/files/xilinx/files/cpld _modules/picoblaze.pps
Xilinx 08/03/2004 440.5 Kb PPS picoblaze.pps
XC3164A-2 XC3164A-2 FPGA 171 kb Summary 1/95 XC3000 XC3000 VIEW logic Verilog 16-Tap, 8-Bit ) VHDL (5 Mb) VHDL (3 Mb) Tactical (83 kb) Configuring FPGAs Over a Processor integration of a 16-Tap, 8-Bit Finite Impulse Response (FIR) filter macro with predefined coefficients (e.g. Digital Signal Processing (DSP) applications. Two case studies-a 16-tap, 8-bit fixed-point FIR filter and of the radix 2 butterfly. For 16-bit data and a 50 MHz system clock the computation time indicated is
/datasheets/files/xilinx/weblinx/apps/fpga.htm
Xilinx 05/02/1997 18.2 Kb HTM fpga.htm
on-chip processor. Currently, SGS-THOMSON offers 16-bit and 32-bit microcontroller cores, a 486DX 486DX core, and a 16-bit DSP core; other cores are in development. The cores, tools and models available , video conferencing systems and speech, sound, music and other multimedia functions. 16-bit MCU core The C16X-CORE C16X-CORE is a 16-bit processor core that combines the best features of the CISC and RISC requiring 16-bit, fixed-point operation, SGS-THOMSON's 40MIPS/25ns D950-CORE D950-CORE is suitable for
/datasheets/files/stmicroelectronics/stonline/press/news/220bp.htm
STMicroelectronics 06/02/1998 8.73 Kb HTM 220bp.htm
changed by reprogramming the on-chip processor. Currently, SGS-THOMSON offers 16-bit and 32-bit microcontroller cores, a 486DX 486DX core, and a 16-bit DSP core; other cores are in development. The cores, tools and other multimedia functions. 16-bit MCU core The C16X-CORE C16X-CORE is a 16-bit processor core that DSP. With around 90% of current DSP applications requiring 16-bit, fixed-point operation core that SGS-THOMSON uses in its ST10 range of 16-bit single-chip microcontrollers, which includes
/datasheets/files/stmicroelectronics/stonline/press/news/220bp-v1.htm
STMicroelectronics 14/06/1999 8.78 Kb HTM 220bp-v1.htm
Date Family Design 16 Tap, 8 Bit FIR Filter 170 KB Summary 11/94 XC4000 XC4000 VIEW speed in the FPGA design is set by the computation time of the radix 2 butterfly. For 16 bit data and a which, in single precision, processes 16-bit words. The Role of Distributed Arithmetic in . 16 Tap, 8 Bit FIR Filter Application Note   This application note describes the functionality and integration of a 16 Tap, 8 Bit Finite Impulse Response (FIR) filter macro with predefined coefficients (e.g.
/datasheets/files/xilinx/docs/wcd00002/wcd00208-v1.htm
Xilinx 16/02/1999 24.84 Kb HTM wcd00208-v1.htm
INSTRUCTION SET, JAVACARD ] AND NATIVE n 4-STAGE PIPELINE n 16 GENERAL PURPOSE 32-BIT REGISTERS, AND 10 Error Correction Code for single bit fail within a 32-bit word - 10 year data retention, 100,000 can only be executed in System mode. The CPU core has 16 32-bit general purpose registers, as complete Code Validation Tools chain including the VHDL Emulator, must be used for both the ST | SMARTCARD 32-BIT RISC MCU WITH 64
/datasheets/files/stmicroelectronics/stonline/books/ascii/docs/7351.htm
STMicroelectronics 19/10/2000 11.29 Kb HTM 7351.htm
No abstract text available
/download/40314210-995985ZC/xapp529_6_2.zip ()
Xilinx 26/03/2004 189.07 Kb ZIP xapp529_6_2.zip
configure an SRAM-based FPGA over a processor bus. It also illustrates the source code required to download and integration of a 16-Tap, 8-Bit Finite Impulse Response (FIR) filter macro with predefined information via E-mail at dsp@xilinx.com . 16-Tap, 8-Bit FIR Filter Application Note (175 kb) This application note describes the functionality and integration of a 16-Tap, 8-Bit Finite Impulse case studies-a 16-tap, 8-bit fixed-point FIR filter and a 24-bit Viterbi decoder-demonstrate the
/datasheets/files/xilinx/weblinx/products/appsweb.htm
Xilinx 19/09/1996 24.83 Kb HTM appsweb.htm
Summary 7/98 FPGA   16-Tap, 8-Bit FIR Filter 170 KB Summary 11/94 implementation-specific (place and route) techniques for optimizing a design for speed. 16-Tap, 8-Bit FIR Filter Application Note   This application note describes the functionality and integration of a 16-Tap, 8-Bit ) applications. Two case studies - a 16-tap, 8-bit fixed-point FIR filter and a 24-bit Viterbi decoder - butterfly. For 16-bit data and a 50 MHz system clock the computation time indicated is 320 ns. The number of
/datasheets/files/xilinx/docs/wcd00001/wcd00196.htm
Xilinx 17/07/1998 23.27 Kb HTM wcd00196.htm
16 bit counters, schmitt inputs, voltage translation and I/O translation at 50MHz = 6.8mA This power Quick Start Training Faster Designs with FREE CoolRunner Reference Designs Free VHDL design code XAPP328 XAPP328 VHDL 219 XC2C256 XC2C256 86 Microcontroller 8-bit Microcontroller XAPP387 XAPP387 VHDL & C 107 XC2C128 XC2C128 84 8-bit Microcontroller XAPP387 XAPP387 VHDL & C 212 Solution for All Designs Handheld, Portable Equipment * Estimated 128 macrocell device, Eight 16-bit
/datasheets/files/xilinx/files/cpld _modules/low_cost.pps
Xilinx 30/01/2004 4616 Kb PPS low_cost.pps