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CS47L90-CWZR Cirrus Logic PCM Codec visit Digikey
CS42888-DQZR Cirrus Logic PCM Codec, 1-Func, CMOS, PQFP64, LEAD FREE, MS-026, LQFP-64 visit Digikey
CS42888-DQZ Cirrus Logic PCM Codec, 1-Func, CMOS, PQFP64, LEAD FREE, MS-026, LQFP-64 visit Digikey
CS42888-CQZ Cirrus Logic PCM Codec, 1-Func, CMOS, PQFP64, LEAD FREE, MS-026, LQFP-64 visit Digikey
CS42888-CQZR Cirrus Logic PCM Codec, 1-Func, CMOS, PQFP64, LEAD FREE, MS-026, LQFP-64 visit Digikey
WM8778SEDS/V Cirrus Logic PCM Codec, 1-Func, CMOS, PDSO28, 10.20 X 5.30 MM, 1.75 MM HEIGHT, LEAD FREE, MO-150AH, SSOP-28 visit Digikey

verilog code voltage regulator

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Abstract: in Actel Libero IDE Model RTL Version ­ ­ · Verilog and VHDL Core Source Code Fully , parameter/generic), this output port can be connected to the VRPSM pin of the internal voltage regulator to , Device · Voltage, Current, and Temperature Monitoring Using a Microprocessor/Microcontroller and , Simulation: OVI-Compliant Verilog Simulators and Vital-Compliant VHDL Simulators Core Verification · Key Features Comprehensive VHDL and Verilog Testbenches · User Can Easily Modify User Actel
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verilog code for adc verilog code voltage regulator vhdl verilog code for amba apb bus 16bit microprocessor using vhdl simple ADC Verilog code vhdl code for Clock divider for FPGA 51700066PB-0/3
Abstract: component. It is a voltage regulator with an integrated PWI slave power controller. The EMU interfaces to , tracking and voltage adjustment .1-5 Typical CMU implementation , consumption to extend battery life. Power management utilized by the APC1 is based on the Adaptive Voltage Scaling (AVS), where the supply voltage of digital IC is adjusted to the minimum level required for , voltage, lowering supply voltage enables significant energy savings. An APC1-controlled advanced power National Semiconductor
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9297-APC1-D101 verilog code for apb SY751-DC-06002 APC1 Release Notes SY751-DA-03001 SY751-DC-06002 timing diagram of AMBA apb protocol
Abstract: 1.1.5 EMU The EMU is an off-chip voltage regulator with an integrated PWI slave power controller , .2-6 Software code module , utilized by the APC2 is based on the Adaptive Voltage Scaling (AVS), where the supply voltage of a , digital circuitries scales quadratically with operating voltage, lowering supply voltage enables significant energy savings. APC2 is capable of simultaneously controlling the voltage scaling of up to four National Semiconductor
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AN 10349 APC2 emu verilog code for ALU implementation 10349-APC2-D101
Abstract: Regulator 1.5 V Regulator Core FPGA Voltage USB Power Figure 2-2. Power Supply Block Diagram , connector J1 goes to a voltage regulator chip, U1. As soon as the external voltage is connected to the , pin 7 of U1, and the regulator begins to provide power at its output. The switching voltage , Verilog design for the CoreMP7 Evaluation Board. Appendix A ­ M7A3PE600 and M7A3P1000 FG484 Package , with Verilog. · You are familiar with PCs and the Windows operating system. CoreMP7 Development Kit Actel
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vhdl code for ethernet csma cd DTS090220U-P5P-SZ AM79C874VI ARM7TDMI-S instruction set DTS090220UP5P-SZ AA15 Fairchild RS-232
Abstract: Universal Serial Bus Interface Buffer PVDDREG Voltage Regulator PX1L Oscillator - Max Frequency , . OpusTM ­ Schematic and Layout NC VerilogTM ­ Verilog Simulator PearlTM ­ Static Path Verilog-XLTM ­ Verilog Simulator BuildGatesTM ­ Synthesis (Ambit) 4.46 3.3-s008 4.3-s095 3.3-s006 4.0-p003 Mentor Graphics® ModelSim® ­ Verilog and VHDL (VITAL) Simulator Leonardo SpectrumTM ­ Logic , PrimeTimeTM ­ Static Path VCSTM ­ Verilog Simulator Floorplan ManagerTM 01.01-SP1 01.08-SP1 01.08 Atmel
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ATL35 vhdl code for 8-bit adder hard disk serial ATA verilog code for DFT 8 bit risc microprocessor using vhdl vhdl code cisc processor verilog code pid controller 0802F
Abstract: specifications, and creates Verilog and/or VHDL code for both simulation and synthesis. Schematic , : defparam parameter_name = value; example: defparam width = 8; The following Verilog code shows how , proceeding Verilog code shows how parameter values can be changed during module instantiation. module , parameters. Parameters make Verilog code more readable, and allows changes (such as the reassignment of state , tied to ground (GND) or supply voltage (VCC). It is not recommended to leave these pads floating, as QuickLogic
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8 bit adder circuit turbo encoder circuit, VHDL code QL8x12B-0PL68C Verilog code of 1-bit full subtractor structural vhdl code for ripple counter verilog code for floating point adder VG0005
Abstract: Perl script for IntelHEX and Verilog MEM file format conversion, file concatenation, data extraction , Verilog MEM files. It can load several files at the same time. nvmrev nvmrev.bat Perl script for , . . . . . . . . . . . . . . . . . 34 11. Supply Voltage and Programming Voltage . . . . . . . . . . , Flash memory for permanent code or data storage. Instead, the device contains 4.5 kB of RAM, which serves as a unified CODE and XDATA RAM memory. The device contains 8 kB of NVM (OTP) memory for user Silicon Laboratories
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AN674 AN511
Abstract: JTAG Scan ARM Processor Voltage Regulator ASB/AHB System Controller EBI PLL Osc , number of elements that until recently were off-chip, notably oscillator/PLL, voltage regulator, reset , Transformation to Application-Specific System-on-Chip JTAG Scan ARM Processor Voltage Regulator , 's Mistral Emulation Platform The first step is to map the Verilog or VHDL code of the application-specific , modifications to the Verilog/VHDL code of the IP blocks, or by modifications to the device drivers or Atmel
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VHDL code for ADC and DAC SPI with FPGA FPGA based dma controller using vhdl ADC07 verilog code for parallel flash memory usb programmer xilinx free generating pwm verilog code
Abstract: functional model of the CoolRISC uP to the VHDL/Verilog simulated ASIC hardware. All signals of the uP are present and the time behavior of the co-simulated uP model is identical to that of a VHDL/Verilog coded , provides a functional model of the CoolRISC uP to the VHDL/Verilog simulated ASIC hardware. All signals of , /Verilog CoolRISC model. The HW/SW co-simulation tool is made of two parts: the first is connected to the , doing this the VHDL/Verilog database has to be completed with functions which are recognized by the -
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CoolRISC 816 abstract for UART simulation using VHDL Jaquet speed Jaquet vhdl code for march c algorithm DATE-2000
Abstract: script for IntelHEX and Verilog MEM file format conversion, file concatenation, data extraction, and IntelHEX checksum fixing. hexdiff hexdiff.bat Perl script for comparing IntelHEX and/or Verilog MEM , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 11. Supply Voltage and Programming Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11.1. Supply , permanent code or data storage. Instead, the device contains 4.5 kB of RAM, which serves as a unified CODE Silicon Laboratories
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Abstract: . Drawing showing the clock schematic block to enable 25MHz The following is an example Verilog code to , E-blocksTM CPLD board Document code: EB020-30-3 CPLD board datasheet EB020-00-3 Contents 1 , E-blocksTM CPLD board Document code: EB020-30-3 1. About this document This document concerns the E-blocks CPLD board, code EB020 version 3. The order code for this product is EB020. 1. Trademarks and , transferring hex code to a PICmicro microcontroller. C and assembly strategies This is available as a free Matrix Multimedia
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EPM7128 EPM128SLC84 LED Matrix PIC Board schematic CPLD 7000 SERIES matrix circuit VHDL code led flasher project
Abstract: lowest power CPLD available and the ideal target device for memory interface applications. The code for this design may be downloaded from the Xilinx web site, refer to section "HDL Code" on page 14 , increasing demands of portable and embedded devices. This market is driven by embedded code storage and bulk , Flash is a random access device appropriate for code storage applications. NAND technology organizes , . The WP# input provides protection when programming or erasing the device. The internal voltage Xilinx
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XAPP354 vhdl code for nand flash memory 8192Kx8 K9F4008W0A NAND flash memory XCR3032XLVQ44
Abstract: programming or erasing the device. The internal voltage regulator is reset when WP# is low, preventing any , available on the web is implemented in both VHDL and Verilog (see "HDL Code" on page 14 for more , requirements have been specified, the VHDL or Verilog source code can be generated. To generate VHDL source , power CPLD available and the ideal target device for memory interface applications. The code for this design may be downloaded from the Xilinx web site, refer to section HDL Code, page 14. This design fits Xilinx
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XCR3032XL XC2C32 xilinx mp3 vhdl decoder AMDFLASH amd nand flash ultranand Samsung Flash XAPP338
Abstract: -bit digital-toanalog converter, a 3.3- to 1.5-V voltage regulator, high-frequency PLLs and a DPLL. The special , , LeapFrog, SDF, Verifault, Verilog, Verilog HDL, Verilog-XL, and Veritime are trade marks of Cadence Design , numbers are preliminary). Nominal core voltage I/O voltage 1.5 V 1.3 V 1.1 V Typical gate , using Sunrise tools. SubChip design capabilities that support hierarchical design VHDL and Verilog , Every timing path through each GS40 family core and I/O macro is characterized at multiple voltage Texas Instruments
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ARM dual port SRAM compiler designware i2c NEC-V850 fastscan ARM946 ARM10 SRST143
Abstract: SOT89-3 Voltage Regulator Evaluation Board Userâ'™s Guide © 2009 Microchip Technology Inc , Technology Inc. SOT89-3 VOLTAGE REGULATOR EVALUATION BOARD USERâ'™S GUIDE Table of Contents Preface , . 5 1.2 What is the SOT89-3 Voltage Regulator Evaluation Board? . 5 1.3 What the SOT89-3 Voltage Regulator Evaluation Board kit includes . 6 Chapter 2 , . 18 © 2009 Microchip Technology Inc. DS51796A-page iii SOT89-3 Voltage Regulator Microchip Technology
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DS51796A DS51796A-
Abstract: TO220-3/TO263-3 Voltage Regulator Evaluation Board Userâ'™s Guide © 2009 Microchip , . DS51818A-page ii © 2009 Microchip Technology Inc. TO220-3/TO263-3 VOLTAGE REGULATOR EVALUATION BOARD , . 5 1.2 What is the TO220-3/TO263-3 Voltage Regulator Evaluation Board? . 5 1.3 What the TO220-3/TO263-3 Voltage Regulator Evaluation Board kit includes , . 16 © 2009 Microchip Technology Inc. DS51818A-page iii TO220-3/TO263-3 Voltage Regulator Microchip Technology
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DS51818A DS51818A-
Abstract: SOT23-3 Voltage Regulator Evaluation Board Userâ'™s Guide © 2008 Microchip Technology Inc , Technology Inc. SOT23-3 VOLTAGE REGULATOR EVALUATION BOARD USERâ'™S GUIDE Table of Contents Preface , . 5 1.2 What is the SOT23-3 Voltage Regulator Evaluation Board? . 5 1.3 What the SOT23-3 Voltage Regulator Evaluation Board kit includes? . 6 Chapter 2 , . 18 © 2008 Microchip Technology Inc. DS51785A-page iii SOT23-3 Voltage Regulator Microchip Technology
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DS51785A DS51785A-
Abstract: TO220-5 / TO263-5 Voltage Regulator Evaluation Board Userâ'™s Guide © 2009 Microchip , Microchip Technology Inc. TO220-5 / TO263-5 VOLTAGE REGULATOR EVALUATION BOARD USERâ'™S GUIDE Table of , . 11 1.2 What is the TO220-5 / TO263-5 Voltage Regulator Evaluation Board? . 11 1.3 What the TO220-5 / TO263-5 Voltage Regulator Evaluation Board kit includes , . TO220-5 / TO263-5 VOLTAGE REGULATOR EVALUATION BOARD USERâ'™S GUIDE Preface NOTICE TO CUSTOMERS All Microchip Technology
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DS22075 DS51817A DS51817A-
Abstract: Voltage Level Shifters Source Code This design example is implemented in Verilog HDL and successful , depends on its part number. An internal LDO voltage regulator provides the necessary 1.8-V internal voltage supply to the device (except in MAX IIG and MAX IIZ devices). The voltage regulator supports , MAX II CPLDs as Voltage Level Shifters Application Note 490 December 2007, version 1.0 Introduction This design example shows how to use Altera® MAX® II CPLDs to implement voltage level shifters Altera
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Level Shifters Altera MAX V CPLD Board Designs EPM1270 EPM2210 EPM240
Abstract: widths is encoded at one end and decoded at the other end. Voltage regulation-The output voltage in a voltage regulator system can be controlled to a desired level by varying the duty cycle. Power , outcome of the variation in average DC voltage and the current through the LED due to PWM. PWM Using , example source code and allocate the appropriate control and output lines to the GPIO lines of the MAX II , Width Modulation Using MAX II CPLDs Source Code Switch on the power to the demo board (using Altera
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Pulse Width Modulation verilog code to generate square wave EPM240G pulse code modulation applications AN-501-1
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