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EKS-LM3S1968-CD Texas Instruments Kit CD for EKS-LM3S1968 Evaluation Board with Code Composer Studio visit Texas Instruments
EKS-LM3S9B90-CD Texas Instruments Kit CD for EKS-LM3S9B90 Evaluation Kit with Code Composer Studio visit Texas Instruments
ICL7135CN Texas Instruments 4.5-Bits, 0.003 kSPS ADC, Muxed BCD Output, True Differential Input, 1 Ch. 28-PDIP 0 to 70 visit Texas Instruments
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TLC7135CDWRG4 Texas Instruments 4.5-Bits, 0.003 kSPS ADC, Muxed BCD Output, True Differential Input, 1 Ch. 28-SOIC visit Texas Instruments
TLC7135CDW Texas Instruments 4.5-Bits, 0.003 kSPS ADC, Muxed BCD Output, True Differential Input, 1 Ch. 28-SOIC 0 to 70 visit Texas Instruments Buy

verilog code for adc

Catalog Datasheet MFG & Type PDF Document Tags

verilog code for adc

Abstract: verilog code of 8 bit comparator optional. It may not be necessary if wire lengths are short. See "Appendix B - ADC Top Level Verilog Code - File ADCtop.v" on page 8 which shows an example of top-level Verilog code for the ADC 2.00 , to the Verilog code located in "Appendix A - ADC Verilog Implementation" on page 5 and and the , 1.1) 7 Virtex Analog to Digital Converter Appendix B - ADC Top Level Verilog Code - File , . This process continues for each bit of the DAC input. The DAC is one bit wider than the ADC output
Xilinx
Original

verilog code for eeprom i2c controller

Abstract: EP4CE22F17C6 will write Verilog HDL code for a simple 32-bit counter, add a phase-locked loop (PLL) megafunction as , Input 3.3V Table 3-9 Pin Assignments for ADC Signal Name ADC_CS_N ADC_SADDR ADC_SDAT ADC_SCLK , part is implemented in Verilog HDL code with SOPC builder. The source code is not available on the , name>.v Description Top level Verilog HDL file for Quartus II 2 .qpf Quartus , . 31 4.6 ADC
TerasIC Technologies
Original

EP4CE22f17

Abstract: EP4CE22F17C6 Verilog HDL code for a simple 32-bit counter, add a phase-locked loop (PLL) megafunction as the clock , Verilog HDL file The resulting empty file is ready for you to enter the Verilog HDL code. 4. Type the , 3.3V 3.3V 3.3V 3.3V Table 3-9 Pin Assignments for ADC Signal Name ADC_CS_N ADC_SADDR ADC_SDAT , hardware part is implemented in Verilog HDL code with SOPC builder. The source code is not available on the , .htm Description Top level Verilog HDL file for Quartus II Quartus II Project File Quartus II
TerasIC Technologies
Original

verilog code for adc

Abstract: parallel to serial conversion verilog .4 Appendix A. Logic Diagram, Description, and Verilog Code of the CPLD Program , , Description, and Verilog Code of the CPLD Program Figure A-1. Logic Diagram Using ADS8411/ADS8412 as , clock to the 15th clock. At the 16th clock, it falls to LOW and conversion starts. A.3 Verilog Code , Application Report SLAA199 ­ May 2004 Using ADS8411/ADS8412 as a Serial ADC Bhaskar Goswami , use a parallel ADC as a serial ADC by using a low-cost CPLD. This concept is tested with a Texas
Texas Instruments
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ADS8411 verilog code for adc parallel to serial conversion verilog EPM3032ATC44-10 ADS8412 CPLD military ADS8411/12

verilog code for adc

Abstract: adc controller vhdl code ADC data or PPE Filtered Data or PPE processed data is made available for the PDMA to transfer to , , and starts processing as soon as it detects a non-empty ADC. The PPE microcode is responsible for , channel for ADC data transfer 4. Processing of ADC data to extract ADC result Configuring Hardware , . 3 SmartFusion: Using ACE with PDMA Configuring PDMA Channel for ADC data transfer Setting up , Files for Application Note File/Folder Name Description SmartFusion_TOP.pdb Verilog Libero
Actel
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adc controller vhdl code adc vhdl adc verilog A2F500 adc vhdl source code verilog code for apb AC352

verilog code voltage regulator

Abstract: verilog code for adc in Actel Libero IDE Model RTL Version ­ ­ · Verilog and VHDL Core Source Code Fully , can be configured using toplevel parameters (Verilog) or generics (VHDL). For a detailed description , (Verilog and VHDL) March 2006 © 2006 Actel Corporation 1 See Actel's website for the latest version , Simulation: OVI-Compliant Verilog Simulators and Vital-Compliant VHDL Simulators Core Verification · Key Features Comprehensive VHDL and Verilog Testbenches · User Can Easily Modify User
Actel
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verilog code voltage regulator verilog code voltage regulator vhdl verilog code for amba apb bus 16bit microprocessor using vhdl simple ADC Verilog code vhdl code for Clock divider for FPGA 51700066PB-0/3

PR68A

Abstract: QSH-060-01-F-D-A sample rates. Please see the TI ADS6XXX-EVM Board User Guide and the ADS6425 ADC Data Sheet for further , conditions for these 16 test runs are shown. 5 Lattice Semiconductor Lattice TI ADC Demo User , Lattice Semiconductor Lattice TI ADC Demo User's Guide Figure 5. Graph of results for tests 13 , . Demo Reference Design Verilog Sample Code , -Permission: Lattice Semiconductor grants permission to use this code for use in synthesis for any Lattice
Lattice Semiconductor
Original
ADS644X PR68A QSH-060-01-F-D-A verilog code to generate sine wave PR69A verilog code for sine wave using FPGA vhdl code to generate sine wave ADS642X ADS6245EVM ADS6000
Abstract: Digital Converter (ADC) add-on suitable for most FPGA development kits. The OpenADC features a flexible , Connector for external clock input â¶â¶ Separate voltage regulators for ADC & LNA â¶â¶ Digilent Pmodâ , applications this will be acceptable, since the clock may only be used to generate the sample clock for the ADC. There will be many additional delays which will need to be compensated for in the ADC sample chain , for more detailed information about possible ADC output configurations. The ADC has a â'˜duty cycle NewAE Technology
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digital alarm clock vhdl code

Abstract: alarm clock design of digital VHDL Outputs Channel selection outputs. The ADC input mux channel selection for the current ADC conversion , wizard can be configured to generate either a VHDL or Verilog wrapper for System Monitor. 3. Click , for the System Monitor ADC. However, the System Monitor ADC requires a clock source in the range of , Introduction LogiCORE Facts The System Monitor provides an integrated solution for thermal management , through a JTAG interface enabling a powerful tool for debugging and testing during hardware development
Xilinx
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DS608 UG192 digital alarm clock vhdl code alarm clock design of digital VHDL alarm clock verilog hdl alarm clock design of digital verilog ADC Verilog Implementation xilinx vhdl code for digital clock

XAPP029

Abstract: adc controller vhdl code FIFOs using the Block SelectRAM+ memory in the Spartan-II FPGAs. Verilog and VHDL code is available for , Verilog or VHDL code. A hand-placed version of the design runs at 170 MHz in the -6 speed grade. XAPP132 , that developers will find helpful for both code creation and hardware development. Examples of hardware code (VHDL or Verilog) as well as "C" code are provided to augment the development of Handspring , The design strategies for loadable and non-loadable binary counters are significantly different. This
Xilinx
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XAPP029 verilog rtl code of Crossbar Switch Insight Spartan-II demo board vhdl code for pn sequence generator XAPP172 12-bit ADC interface vhdl code for FPGA Q4-01 XAPP004 XAPP005 XC3000 XAPP007 XAPP008

verilog code for adc

Abstract: block diagram of ct scanner Verilog code GENERAL DESCRIPTION The ADAS1128 is a 128-channel, current-to-digital, analog-todigital converter (ADC). It contains 128 low power, low noise, low input current integrators, simultaneous , 128-Channel, 24-Bit Current-to-Digital ADC ADAS1128 FEATURES 128-channel, low level , reduces external hardware. An SPI-compatible serial interface allows configuration of the ADC using the , × 10 mm, mini-BGA package. For more information on the ADAS1128, contact Analog Devices, Inc, at
Analog Devices
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OR127 block diagram of ct scanner sdi verilog code analog to digital converter verilog 080450 128-C AN127 D08045F-0-6/09

block diagram of ct scanner

Abstract: ADAS1128 board Reference design with reference layout FPGA Verilog code The ADAS1128 is a 128-channel, current-to-digital, analog-todigital converter (ADC). It contains 128 low power, low noise, low input current , 128-Channel, 24-Bit Current-to-Digital ADC ADAS1128 FEATURES GENERAL DESCRIPTION 128 , configuration of the ADC using the SDI input. The SDO output allows the user to daisy-chain several ADCs on a , believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use
Analog Devices
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Wire diagram of ct scanner digital to analog converter radiation ct scanner daisy chain verilog fpga radiation AN63 D08045F-0-9/10

ADAS1126

Abstract: block diagram of ct scanner board Reference design with reference layout FPGA Verilog code The ADAS1126 is a 32-channel, current-to-digital, analog-todigital converter (ADC). It contains 32 low power, low noise, low input current , 32-Channel, 24-Bit Current-to-Digital ADC ADAS1126 FEATURES GENERAL DESCRIPTION 32 , configuration of the ADC using the SDI input. The SDO output allows the user to daisy-chain several ADCs on a , is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of
Analog Devices
Original
D08786F-0-3/11

block diagram of ct scanner

Abstract: ADAS1126 board Reference design with reference layout FPGA Verilog code The ADAS1126 is a 32-channel, current-to-digital, analog-todigital converter (ADC). It contains 32 low power, low noise, low input current , 32-Channel, 24-Bit Current-to-Digital ADC ADAS1126 FEATURES GENERAL DESCRIPTION 32 , configuration of the ADC using the SDI input. The SDO output allows the user to daisy-chain several ADCs on a , . However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents
Analog Devices
Original
OR31 adas sensor x-ray sensor or31 AN16 AN31 D08786F-0-9/10

block diagram of ct scanner

Abstract: Wire diagram of ct scanner board Reference design with reference layout FPGA Verilog code The ADAS1127 is a 64-channel, current-to-digital, analog-todigital converter (ADC). It contains 64 low power, low noise, low input current , 64-Channel, 24-Bit Current-to-Digital ADC ADAS1127 FEATURES GENERAL DESCRIPTION 64 , configuration of the ADC using the SDI input. The SDO output allows the user to daisy-chain several ADCs on a , accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any
Analog Devices
Original
sdi converter 9106 AN32 D08785F-0-9/10

vhdl program for parallel to serial converter

Abstract: code: ◠VHDL Source Code or/and VERILOG Source Code or/and ◠Encrypted, or plain text EDIF â , available to conserve additional power. These modes make the D68HC11F1 IP Core especially attractive for , the exact configuration to meet usersâ'™ requirements. There is no need to pay extra for not used , — 17 priority levels ◠Dedicated vector for each interrupt ♦ Main16-bit timer/counter system â , ADC converter controller (option) ♦ EEPROMCTRL â'" External EEPROM controller (option) All
Digital Core Design
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vhdl program for parallel to serial converter D68HC11F D6802 D6803 D6809 DF6805 D68HC05

D6802

Abstract: MC68HC11KS2 select DELIVERABLES Source code: VHDL/VERILOG Source Code or/and Encrypted, or plain text EDIF , are two formats of delivered IP Core VHDL, Verilog RTL synthesizable source code called HDL Source , attractive for automotive and battery-driven applications. The D68HC11K has built in real time hardware on , extra for not used features and wasted silicon. It includes fully automated testbench with complete , Microcontroller Core can be used as direct replacement for any of the following HC11 Microcontrollers
Digital Core Design
Original
DF6811E MC68HC11KS2 generating pwm verilog code multi channel UART controller using VHDL verilog code for eeprom i2c controller verilog HDL program to generate PWM DF6808 D68HC08 D68HC11E D68HC11KW1 DF6811F

verilog program to generate PWM pulses

Abstract: 8-bit ADC interface vhdl complete code for FPGA : VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF VHDL & VERILOG test , delivered IP Core VHDL, Verilog RTL synthesizable source code called HDL Source FPGA EDIF/NGO/NGD/QXP , especially attractive for automotive and battery-driven applications. The D68HC11E has built in real time , need to pay extra for not used features and wasted silicon. It includes fully automated testbench with , sources 17 priority levels Dedicated vector for each interrupt Main16-bit timer/counter system 16
Digital Core Design
Original
verilog program to generate PWM pulses 8-bit ADC interface vhdl complete code for FPGA interface of ADC to UART in VHDL vhdl code for parallel to serial converter motorola 68hc11e verilog code for serial hardware multiplier 68HC11E DF6811K DF68XX

verilog code voltage regulator

Abstract: CORE8051 CoreAI. Fully RTL Version ­ Verilog and VHDL Core Source Code ­ · General Description , can be configured using toplevel parameters (Verilog) or generics (VHDL). For a detailed description , generics (VHDL), described in Table 4, for configuring the RTL code. All parameters and generics are , internal data FIFO for storing up to 256 ADC conversion results for later reading by a microprocessor, or , Fusion datasheet for further information.) Table 15 · ADC Control Register 1 (high-order) Bits
Actel
Original
CORE8051 scaler verilog code vhdl code for 16 BIT BINARY DIVIDER ADC rtl code microcontroller using vhdl APB VHDL code

verilog code for 4 bit ripple COUNTER

Abstract: 8-bit ADC interface vhdl complete code for FPGA Verilog netlist to the customer for post-layout simulation. Once design and post-layout simulation is , , lower power consumption relative to throughput, and greater flexibility and reliability. For code , required. The following table indicates the cells available for both Cadence Concept and Verilog systems , SOFTWARE DEVELOPMENT SUPPORT OKI provides software development support for assembly code development, C , trademarks, and Cadence and Verilog are registered trademarks of Cadence Design Systems, Inc. Design
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verilog code for 4 bit ripple COUNTER timer counters using jk flip flops D Flip Flops verilog code for 8 bit shift register vhdl code for 4 bit ripple COUNTER 16 BIT ALU design with verilog code
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