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verilog code for 8254 timer

Catalog Datasheet MFG & Type PDF Document Tags

USART 8251

Abstract: verilog code for 8254 timer Arbitration Unit Wait Control Unit Multi Protocol Serial Controller similar to 8530 Programmable Timer similar to 8254 PCI Target Controller with on-chip memory Peripheral / Memory Bus Interface CPU on-chip peripherals Programmable 16-bit Timer similar to 8254 Serial Controller Unit similar to 8251 Interrupt , Timer - 8254 Interrupt Controller - 8259 DMA Controller - 8237 Serial Controller - 8251 RS 232 Programmable Timer - 8254 Multi Protocol Serial Controller 8530 USART PCI
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8254 vhdl code

Abstract: 8259 Programmable Peripheral Interface such as Interrupt, DRAM, DMA, Timer and other Controls for the 80386 bus environment. The integrated , required for successful implementation: HDL RTL source code Sophisticated self-checking HDL Testbench , expanded Intel 8254 Interval Timer. One timer is used internally leaving 3 timers accessible to the , -Bit Programmable In- terval Timers o Intel 8254 compatible Programmable Wait State gene- The C82380 32 , peripheral set for 80386 based systems. Block Diagram rator o 0 to 15 Wait states Pipelined o 1 to 16
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8254 vhdl code 8259 Programmable Peripheral Interface intel 80386 block diagram intel 82380 8254 vhdl verilog code for 8254 timer

verilog code for 8254 timer

Abstract: 8254 vhdl Verilog RTL source code VHDL source code Synthesis script for Design Compiler CLK1 GATE1 TIMER/ COUNTER 1 Verilog & VHDL test vectors Reference technology netlist CONTROL MODES , O I N T E L L E C T U A L P R O P E R T Y M8254 PROGRAMMABLE INTERVAL TIMER OVERVIEW The M8254 contains three independent 16-bit timer/counters that can be programmed over a common 8-bit CPU interface. It can be used for timing external events, producing fixed delays or producing
Mentor Graphics
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vhdl code for 8 bit bcd COUNTER M82C206 PD-40003 003-FO

verilog code for 8254 timer

Abstract: 82c54 verilog code VHDL or Verilog · Applications Binary or BCD Counting Functionality based on the INTEL 8254 , HDL Source License · VHDL or Verilog RTL source code · Testbenches (self checking) · , C8254 Programmable Timer/Counter Megafunction Introduction The C8254 programmable interval timer/counter megafunction is a high-performance device, which is designed to solve the common timing , counter may operate in a different mode. All modes are software programmable. Six programmable timer
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82C54 82c54 verilog code 8254 intel microprocessor block diagram block diagram of intel 8254 chip 8254 intel microprocessor modes rtl decade counter vhdl code for 4 bit binary counter EP1C20-6 EP1S20-5 EP2S60-3

vhdl code for 8 bit bcd COUNTER

Abstract: verilog code for 8254 timer includes everything required for successful implementation: VHDL or Verilog RTL source code , Read/Write LSB only or MSB only or LSB first then MSB Programmable Timer/Counter Core Six , implements a high performance programmable interval timer/counter device, which is designed to solve the , for the desired delay. Shot o Rate Generator o Square Wave Mode o Software Triggered Strobe o , Applications The six programmable timer modes allow the C8254 to be used in applications requiring event
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16 bit counter with latch Programmable counter bcd mod 8 counter vhdl code for 4 bit counter APPLICATIONS OF mod 8 COUNTER Synchronous 8-Bit Binary Counters

8251 intel microcontroller architecture

Abstract: vhdl source code for 8086 microprocessor >.tdf), VHDL, Verilog HDL, or AHDL file Symbol File (.sym) for use in MAX+PLUS II , VHDL- or Verilog HDL-based design files that are optimized for the Altera FLEX 10K device family , RAM is used for program memory, application code can be loaded with a memory download mode , description of each AMPP megafunction, and a listing of corporate profiles and contact information for each , megafunctions. Some products listed in the AMPP partner profiles are available for non-Altera device
Altera
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8251 intel microcontroller architecture vhdl source code for 8086 microprocessor 8251 usart verilog coding for asynchronous decade counter verilog code for median filter 8251 uart vhdl

verilog code for 8254 timer

Abstract: 8 bit counter with latch · Documentation · VHDL or Verilog RTL source code · Testbenches (self checking) · Wrapper for pin , 8254 Applications The six programmable timer modes allow the C8254 to be used in applications , /Write LSB only or MSB only or LSB first then MSB Programmable Timer/Counter Core Six , implements a high performance programmable interval timer/counter device, which is designed to solve the , for the desired delay. Shot o Rate Generator o Square Wave Mode o Software Triggered Strobe o
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8 bit counter with latch verilog code for 16 bit common bus intel 8254 bcd verilog 3S1200E-4 2V80-6 4VLX15-12 5VLX30-3

mod 16 binary down counter

Abstract: bcd verilog functionality · Place & Route scripts · Constraints file · Documentation · VHDL or Verilog RTL source code , Command Read/Write LSB only or MSB only or LSB first then MSB Programmable Timer/Counter , One- Shot The C8254 megafunction implements a high performance programmable interval timer , requirements by programming one of the counters for the desired delay. Applications The six programmable timer modes allow the C8254 to be used in applications requiring event counters including: o Rate
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EP3C40-6 mod 16 binary down counter block diagram 3 element control EPM1270M-5 EP2S180-3

verilog code for 8254 timer

Abstract: verilog code for fixed point adder Communications 8254 Programmable Timer M8255 Programmable Peripheral Interface XF8255 Programmable Peripheral , ASIC core industry has been developing for over a decade. Today there exists a wealth of intellectual , , Areas of Expertise section, for each of our AllianceCORE partners. Our partners will be more than willing to discuss the possibility of producing a core specifically for your needs. Data Book Contents , system designers are beginning to look at using cores for their programmable logic designs. It is for
Xilinx
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verilog code for fixed point adder vhdl code for 8-bit BCD adder vhdl code for BCD to binary adder vhdl program for parallel to serial converter implementation of 16-tap fir filter using fpga verilog code for distributed arithmetic XC4000

8251a usart interface from z80

Abstract: 72065B in Library Compatible Device 8086 Z80 8237A 8251A 8254 8255A 8259A NEC Code V30MX 70008A 71037 71051 , , namely Verilog®, System HILO®, and V-SimTM. Simulation Verilog gate level m odels are provided for , for Verilog models is to use a hardw are m odeler simulation capability, where the actual stand-alone , Controller USART Interval Timer Peripheral Interface Interrupt Controller Floppy Disk Controller Real Time , preliminary specifications, package information, and operational data for the CB-C8 cell-based CMOS ASIC
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8251a usart interface from z80 72065B NEC V30MX Rambus ASIC Cell OPENCAD CMOS Block library nec floppy circuit 710XX TMXP-200 L427525

NEC 2561

Abstract: transistor f422 8254 NA71054 Interval Timer Features 8255A NA71055 Peripheral Interface 8259A , Datapath compiler available for multipliers, FIFOs, and register files NEC Code XXXA Programmable , simulation and testing of embedded cores and megamacros, full Verilog gate delay models are provided for , Controller 8237A Programmable DMA Controller 8251A USART 8254 Interval Timer 3-Wide, 1-2-3-Input AND-OR , Megafunctions The CB-C7, 3-volt cell-based product family is intended for low power portables and
NEC
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NEC 2561 transistor f422 transistor f423 nec 2561 equivalent transistor f422 equivalent transistor NEC D 882 p V30HL

NEC V30MX

Abstract: v 12719 simulation purposes. An alternative for Verilog models is to use a hardware modeler simulation capability , Sample of Megafunctions in Library Compatible Device NEC Code Description 16-bit Microprocessor , 8251A 71051 USART u Extensive macro library includes soft and hard megafunction blocks 8254 71054 Interval Timer 8255A 71055 Peripheral Interface 8259A 71059 Interrupt , contains preliminary specifications, package information, and operational data for the CB-C8 cell-based
NEC
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v 12719 8255a Max mode system in 8086 microprocessor 40673 71055 40673 cmos marking code C76

Digital IC CMOS 16x1 mux

Abstract: PART NUMBERING NEC IC DECODER Device 8088 8086 Z80 80C42 8237A S251A 8254 82S5A 8259A 4991A 72020 NEC Code V20HL(NA70108H) V30HL , simulation and testing of embedded cores and megamacros, full Verilog gate delay models are provided for all , -bit Microprocessor 765 Floppy Disk Controller 8237A Programmable DMA Controller 8251A USART 8254 Interval Timer 8255A , CB-C7,3-volt cell-based product family is intended for low power portables and battery-operated products , advantage is that the FT-type is well-suited for multiple designs built around a common embedded CPU
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Digital IC CMOS 16x1 mux PART NUMBERING NEC IC DECODER f34 function generator ic tba 810 NEC VOLTAGE COMPARATOR IC LIST F981 IC 00437T3 70108H 70116H NA80C42H NA8250

2-bit half adder

Abstract: microprocessors architecture of 8251 off quality CAE design libraries for QuickSim II, Verilog XL and VITAL CAE libraries optimized for , version · Support for `Thumb' instruction set · 30% improvement in code density over native ARM code · , macrofunctions are supplied as synthesizable RTL models for both VHDL and Verilog. In addition these , RAMs, as well as PLL and oscillators. These cells are optimised for easy synthesis, and are supported by high quality design kits for a range of industry standard CAE tools providing a low risk solution
Zarlink Semiconductor
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2-bit half adder microprocessors architecture of 8251 USART 8251 interfacing with 8051 microcontroller microprocessors interface 8086 to 8251 8255 interfacing with 8086 USART 6402 GSC200 DS4830 85C30

8251 usart architecture and interfacing

Abstract: microprocessors interface 8086 to 8251 quality CAE design libraries for QuickSim II, Verilog XL and VITAL CAE libraries optimized for synthesis , Hardware debug capabilities on TDMI version · Support for `Thumb' instruction set · 30% improvement in code , synthesizable RTL models for both VHDL and Verilog. In addition these macrofunctions are fully supported with , as PLL and oscillators. These cells are optimised for easy synthesis, and are supported by high quality design kits for a range of industry standard CAE tools providing a low risk solution and faster
Zarlink Semiconductor
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8251 usart architecture and interfacing

USART 6402

Abstract: verilog code for 8254 timer gates and tracks with sign o ff quality CAE design libraries for QuickSim II, Verilog XL and VITAL , SystemBuilder macrofunctions are supplied as synthesizable RTL models for both VHDL and Verilog. In addition , . These cells are optim ised for easy synthesis, and are supported by high quality design kits for a , delay for 2-input NAND with two loads (3.3V) BENEFITS â  Low power, 0.06nW /M Hz/gate at 2V , inputs and outputs - Comprehensive industry standard CAE tools â  Full set of I/O cells for
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advantages of master slave jk flip flop 82077SL IEEE1284 82365SL 79C90

microprocessors architecture of 8251

Abstract: USART 8251 interfacing with 8051 microcontroller of I/O cells for direct pad synthesis Accurate delay modelling for gates and tracks with sign off quality CAE design libraries for QuickSim II, Verilog XL and VITAL CAE libraries optimized for synthesis , , as well as PLL and oscillators. These cells are optimised for easy synthesis, and are supported by high quality design kits for a range of industry standard CAE tools providing a low risk solution and , 97ps gate delay for 2-input NAND with two loads (3.3V) Low power, 0.06µW/MHz/gate at 2V supply (NAND
Mitel Semiconductor
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Peripheral interface 8255 8255 interface with 8086 Peripheral ISO 8253-3 UART 8251 USART 8251 design 8086 4k ram 8k rom

2-bit half adder

Abstract: USART 8251 interfacing with 8051 microcontroller off quality CAE design libraries for QuickSim II, Verilog XL and VITAL CAE libraries optimized for , version · Support for `Thumb' instruction set · 30% improvement in code density over native ARM code · , macrofunctions are supplied as synthesizable RTL models for both VHDL and Verilog. In addition these , RAMs, as well as PLL and oscillators. These cells are optimised for easy synthesis, and are supported by high quality design kits for a range of industry standard CAE tools providing a low risk solution
Zarlink Semiconductor
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6402 uart 8253 usart programming DAC 8048 microprocessors architecture of 8253 82530 8086 interfacing with 8254 peripheral

free vHDL code of median filter

Abstract: free verilog code of median filter in MAX+PLUS II GDFs Include File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL , megafunction descriptions and partner profiles for each AMPP partner. The information in this catalog is current as of the print date, but megafunction specifications and availability are subject to change. For , applicable standards compliance, and a table with fitting and performance specifications. See page 11 for , Peripherals Telecommunications and Data Communications (Telecom & Datacom) DSP for Imaging DSP for
Altera
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free vHDL code of median filter free verilog code of median filter verilog code for UART with BIST capability verilog code for 2D linear convolution verilog code for 2D linear convolution filtering rx UART AHDL design

verilog code for 2D linear convolution

Abstract: verilog code for GPS correlator File (.inc) for use in MAX+PLUS II TDFs VHDL and Verilog HDL instantiation templates Megafunction , trademark laws. Altera Corporation acknowledges the trademarks of other organizations for their respective , . Verilog and Cadence are registered trademarks of Cadence Design Systems, Inc. SCVL, SCVL-S, MOR , for a particular purpose, or non-infringement of any patent, copyright, or their intellectual property rights. In the absence of written agreement to the contrary, Altera assumes no liability for Altera
Altera
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verilog code for GPS correlator vhdl code numeric controlled oscillator pipeline verilog code car parking 16 QAM modulation verilog code LED Dot Matrix vhdl code vhdl source code for 8085 microprocessor M-CAT-AMPP-02 EPF10K10 EPF10K20 EPF10K30 EPF10K40 EPF10K50
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