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LTC3816IFE#TRPBF Linear Technology LTC3816 - Single-Phase Wide VIN Range DC/DC Controller for Intel IMVP-6/IMVP-6.5 CPUs; Package: TSSOP; Pins: 38; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3734EUH#TR Linear Technology LTC3734 - Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3734EUH#PBF Linear Technology LTC3734 - Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3734EUH Linear Technology LTC3734 - Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3816EUHF#TRPBF Linear Technology LTC3816 - Single-Phase Wide VIN Range DC/DC Controller for Intel IMVP-6/IMVP-6.5 CPUs; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3816IUHF#TRPBF Linear Technology LTC3816 - Single-Phase Wide VIN Range DC/DC Controller for Intel IMVP-6/IMVP-6.5 CPUs; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3816EFE#PBF Linear Technology LTC3816 - Single-Phase Wide VIN Range DC/DC Controller for Intel IMVP-6/IMVP-6.5 CPUs; Package: TSSOP; Pins: 38; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3816EFE#TRPBF Linear Technology LTC3816 - Single-Phase Wide VIN Range DC/DC Controller for Intel IMVP-6/IMVP-6.5 CPUs; Package: TSSOP; Pins: 38; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3816IUHF#PBF Linear Technology LTC3816 - Single-Phase Wide VIN Range DC/DC Controller for Intel IMVP-6/IMVP-6.5 CPUs; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3816EUHF#PBF Linear Technology LTC3816 - Single-Phase Wide VIN Range DC/DC Controller for Intel IMVP-6/IMVP-6.5 CPUs; Package: QFN; Pins: 38; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3734EUH#TRPBF Linear Technology LTC3734 - Single-Phase, High Efficiency DC/DC Controller for Intel Mobile CPUs; Package: QFN; Pins: 32; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3816IFE#PBF Linear Technology LTC3816 - Single-Phase Wide VIN Range DC/DC Controller for Intel IMVP-6/IMVP-6.5 CPUs; Package: TSSOP; Pins: 38; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy

v20 single purpose processor

Catalog Datasheet MFG & Type PDF Document Tags

Infineon Tricore TC1797

Abstract: tc1797 Application Note, V2.0, October 2008 AP32120 TC1797 SENT Receiver with SPC support (CPU & PCP , last revision) V2.0 We Listen to Your Comments Any information within this document that you , : mcdocu.comments@infineon.com Application Note 3 V2.0, 2008-10 AP32120 SENT Receiver with SPC support Table of , .27 Application Note 4 V2.0, 2008-10 AP32120 SENT Receiver with SPC support Scope 1 Scope , . Have fun with Infineon's SENT receiver! 1 Single Edge Nibble Transmission (SENT) refers to the
Infineon Technologies
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Infineon Tricore TC1797 SAE J2716 protocol SAE-J2716 J2716 J2716 microcontroller Infineon Tricore TC1797 gpta

SAF-TC11IB-64D96E

Abstract: p3x btr User's Manual, V2.0, Sep. 2003 TC11IB System Units 32-Bit Single-Chip Microcontroller , health of the user or other persons may be endangered. User's Manual, V2.0, Sep. 2003 TC11IB , suspended BTP should be bit 19, not 18 V2.0 We Listen to Your Comments Any information within this , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 General Purpose Timer , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 2 TC11IB Processor Architecture
Infineon Technologies
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SAF-TC11IB-64D96E p3x btr Hitachi DSA00319 B.A. private examination 2011 diagrams hitachi ecu manual 1746 D-81541 IB-64D96E Q67121C2346 AP326111 AP3203011 2002-07/V1
Abstract: MicroBlaze processor. Design Implementation Design Tools The FSL V20 design is implemented in VHDL. XST , LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11f) DS449 December 18, 2012 Product Specification Introduction LogiCORE IP Facts The LogiCOREâ"¢ IP FSL V20 Fast Simplex Link (FSL) Bus is , interface is available on the Xilinx MicroBlazeâ"¢ processor. The interfaces are used to transfer data to and from the register file on the processor to hardware running on the FPGA. Core Specifics Xilinx
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vhdl synchronous bus

Abstract: LogiCORE IP Fast Simplex Link (FSL) V20 Bus (v2.11e) DS449 October 19, 2011 Product Specification Introduction The LogiCORETM IP FSL V20 Fast Simplex Link (FSL) Bus is a uni-directional point-to-point , implementing an interface to the FSL bus. The FSL interface is available on the Xilinx MicroBlazeTM processor. The interfaces are used to transfer data to and from the register file on the processor to hardware , October 19, 2011 Product Specification www.xilinx.com 1 LogiCORE IP Fast Simplex Link (FSL) V20
Xilinx
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vhdl synchronous bus

0202C

Abstract: ESPC merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in , . 2-2 Changes between RVCT v2.0 and RVCT v1.2 . 2-3 , This preface introduces the RealViewTM Compilation Tools v2.0 Essentials Guide and other user , this book This book provides an overview of the RealView Compilation Tools (RVCT) v2.0 tools and , this chapter for details of the differences between RVCT v2.0, RVCT v1.2, and the ARM Developer Suite
ARM
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0202C ESPC dyna image CODE16

TC1766

Abstract: LMB 1028 User's Manual, V2.0, July 2007 TC1766 32-Bit Single-Chip Microcontroller Volume 1 (of 2 , endangered. User's Manual, V2.0, July 2007 TC1766 32-Bit Single-Chip Microcontroller Volume 1 (of 2 , Units Revision History: V2.0, 2007-07 Previous Version: V1.1 2005-08 Page Subjects (major changes , V2.0, 2007-07 TC1766 System and Peripheral Units (Vol. 1 and 2) TC1766 User's Manual Volume 1 (of 2) System Units & Volume 2 (of 2) Peripheral Units Revision History: V2.0, 2007-07 6-9
Infineon Technologies
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LMB 1028 cpu 414-4H apn 2054 CERBERUS ocds phase looked loop MTI LTC 010

lmb 1021

Abstract: marking code INFINEON User's Manual, V2.0, Aug. 2007 TC116x 32-Bit Single-Chip Microcontroller Volume 1 (of 2 , endangered. User's Manual, V2.0, Aug. 2007 TC116x 32-Bit Single-Chip Microcontroller Volume 1 (of 2 , Units Revision History: V2.0, 2007-08 Previous Version: V1.2 2006-10 Page Subjects (major changes , SBCU_ID is added. User's Manual V2.0, 2007-08 TC116x System and Peripheral Units (Vol. 1 and 2 , : V2.0, 2007-08 7-16 DFlash address of the Load Page Buffer Command is updated. 7-40, 7-41
Infineon Technologies
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lmb 1021 marking code INFINEON CERBERUS INTF3000 tb 1060 f022 CNC DRIVES TC116

arm assembly language

Abstract: ESPC applications that run on a single processor. However, you can purchase additional licenses to extend the , application program. A hardware debug target might be a single processor, or a development board containing , this book. Change History Date Issue Change September 2003 A RVDS Release v2.0 , merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in , of the RealView Developer Suite v2.0 Components 2.1 2.2 2.3 Chapter 3 RealView Developer
ARM
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arm assembly language ETM10 L6238E

3310H transistor

Abstract: transistor sr52 Units User's Manual Revision History: 2001-02 Previous Version: Page V2.0 V1.0, 2000-11 , B-Step created for release purposes of the final version V2.0. 2) These versions for the A-Step , . . . . 1-19 General Purpose Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 General Purpose Timer Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 , Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 2 TC1775 Processor
Infineon Technologies
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3310H transistor transistor sr52 IN60 PACKAGE P48ab ltcc TMS 2370
Abstract: can be available in a single Virtex-II Pro device. Functional Description: Processor Block , 0 Virtex-II Proâ"¢ Platform FPGAs: Functional Description R DS083-2 (v2.0) June 13, 2002 , Manual and the PPC405 Processor Block Manual. Rocket I/Oâ"¢ Multi-Gigabit Transceiver CLB Multipliers and Block SelectRAM â'¢ Processor Block DCM Advance Product Specification Embedded Rocket I/Oâ"¢ Multi-Gigabit Transceiver (MGT) Processor block containing embedded IBM® PowerPCâ"¢ 405 Xilinx
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DS083-1 XAPP290
Abstract: . It has the following features: · 48-pin 7mm x 7mm QFP package · Single chip with integrated USB 2.0 PHY · Serial EEPROM port · Serial port · Two General Purpose Timers · Watchdog Timer · 16 bit Processor · Programmable Read and Write widths · Optimum hardware controlled transfer for speed and , V2.0 spec media, enhancing the access space up to 32GBytes. Device Interfaces · MultiMediaCard/ MMC 4.0 1/ 4/ 8 bit Data bus support · Secure Digital Card/ Secure Digital HS/ Secure Digital V2.0 cards OnSpec Electronic
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20MB/ 18MB/ 52MB/

VDD06

Abstract: TX39 RISC Processor Description Development Tool Support The TMP3912U is a single-chip, highly , processor core with the necessary support logic and peripherals functions needed to develop a complete PDA solution. This highly integrated solution supports the Microsoft® WindowsTM CE v2.0 operating system that , Single cycle multiply/accumulate (MAC) for integrated DSP functions such as V.34 compatible 28.8Kbps , for Windows CE v2.0 applications is available from Toshiba On-Chip Peripherals · Clock generator
Toshiba
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R3000A VDD06 TX39 MIPS R3000A RC2160997 RC32160997

Turbo decoder Xilinx

Abstract: CRC lte LTE UL Channel Decoder v2.0 XMP024 June 24, 2009 Product Brief Introduction The Xilinx® LTE , supported by the core: · Transport Block-based configuration on a channel basis to minimize processor , requirements while still minimizing processor interaction · Code Block Reassembly Calculation - Internal , the core · Fully optimized for speed and area · Fully synchronous design using a single , provide efficient use of the FPGA and offers a low bandwidth interface to an external processor to
Xilinx
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Turbo decoder Xilinx CRC lte xilinx lte TURBO decoder LTE uplink TB lte redundancy version

P-BGA-388-2

Abstract: 15D1H interrupt trigger levels Data Sheet 31 V2.0, 2002-12 TC11IB General Purpose Timer Units , .3, 2002-09 V2.0 Page 76 78 81,82 Subjects (major changes since last revision) SDRAM data input setup , and time critical code · Independent Peripheral Control Processor (PCP) for low level driver support , On-Chip Peripheral Units ­ Two Multifunctional General Purpose Timer Units (GPTU0 & GPTU1) with three , Debug Support (OCDS) Data Sheet 1 V2.0, 2002-12 TC11IB · · · · Power Management System Clock
Infineon Technologies
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P-BGA-388-2 15D1H

ubx-g5010

Abstract: UBX-G5000-BT UBX-G5010, UBX-G5000/UBX-G0010 u-blox 5 Single Chips and Chipsets for GPS and GALILEO , the single chip and chipset versions of the high performance u-blox 5 positioning engine , Integrated LNA USB V2.0 GPIO DDC (I2C compatible.) Main Power TCXO or Crystal Optional RTC , (UBX-G5010) 2 UARTs (UBX-G5000) 1 USB V2.0 Full Speed 12 Mbit/s 1 DDC (I2C compliant) 1 SPI , Limits -40°C to 85°C Single Package Chipset 515 m/s (1000 knots) UBX-G5010: 56 Pin
u-blox
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UBX-G0010 UBX-G5000-BT IC 7447 PIN CONNECTION DIAGRAM 7447 pin configuration ic 7447 pin configuration UBX-G0010-QT IC 7447 PIN CONFIGURATION FIGURE G5-X-06042-A1

XC7K325TFFG900

Abstract: XC7K325TFFG900-2 28 AXI Interface Based KC705 Embedded Kit MicroBlaze Processor Subsystem Data Sheet DS669 (v2.0) April 23, 2013 Product Specification Introduction The KC705 Embedded Kit MicroBlazeâ"¢ Processor , accesses processor functions directly. DS669 (v2.0) April 23, 2013 Product Specification , the KC705 MicroBlaze processor subsystem is shown in Figure 4. DS669 (v2.0) April 23, 2013 Product , ) are built around a MicroBlaze soft processor with various peripherals to enable embedded applications
Xilinx
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XC7K325TFFG900 XC7K325TFFG900-2 kintex7 XC7K325TFFG900 -2

memory stick pro duo pin

Abstract: Single chip with integrated USB 2.0 PHY · Serial EEPROM port · Serial port · Two General Purpose Timers · Watchdog Timer · 16 bit Processor · Programmable Read and Write widths · Optimum hardware , Supports CE-ATA · Support for SD V2.0 spec media, enhancing the access space up to 32GBytes. · OnSpec , MultiMediaCard/ MMC 4.0 1/ 4/ 8 bit Data bus support · Secure Digital Card/ Secure Digital HS/ Secure Digital V2.0 , products including liability or warranties relating to fitness for a particular purpose, merchantability
OnSpec Electronic
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memory stick pro duo pin
Abstract: 48-pin 16mm x 16mm QFP package Single chip with integrated USB 2.0 PHY Serial EEPROM port Serial port Two General Purpose Timers Watchdog Timer 16 bit Processor Programmable Read and Write widths , -bit media is 52MB/sec. Supports CE-ATA Support for SD V2.0 spec media, enhancing the access space up to , Digital HS/ Secure Digital V2.0 cards Memory Stick / Memory Stick PRO / Memory Stick HS / MS Duo Host , purpose, merchantability, or infringement or any patent, copyright or other intellectual property right OnSpec Electronic
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onspec

Abstract: · Single chip with integrated USB 2.0 PHY · Serial EEPROM port · Serial port · Two General Purpose Timers · Watchdog Timer · 16 bit Processor · Programmable Read and Write widths · Optimum , MMC 8-bit media is 52MB/sec. · Support for SD V2.0 spec media, enhancing the access space up to , / Secure Digital HS/ Secure Digital V2.0 cards · Memory Stick / Memory Stick PRO / Memory Stick HS / MS , purpose, merchantability, or infringement or any patent, copyright or other intellectual property right
OnSpec Electronic
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onspec 100MB

93CS66L

Abstract: LAD1 12v 8 pin relay PCI 9054 Data Book v2.0 © PLX , (PCI Master-to-Local Bus Access).3-9 vi PCI 9054 Data Book v2.0  , v2.0 © PLX Technology, Inc. All rights reserved. vii Contents 4.2.5.2.1. Continuous Burst Mode , Enables (J PCI 9054 Data Book v2.0 © PLX , Data Book v2.0 © PLX Technology, Inc. All rights reserved. ix Contents 7. Intelligent I/O (l20
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93CS66L LAD1 12v 8 pin relay PLX PCI9054 MC 9080 plx 9054 SD card V2.0 Physical Layer Spec 9054-SIL-DB-P1-2 USA/0899 LAD25 LAD24 LAD30 LAD23

memory stick pro duo pin

Abstract: nand flash memory reader 100-pin 16mm x 16mm QFP package Single chip with integrated USB 2.0 PHY Serial EEPROM port Serial port Two General Purpose Timers Watchdog Timer 16 bit Processor Programmable Read and Write widths , -bit media is 52MB/sec. Support for SD V2.0 spec media, enhancing the access space up to 32GBytes. OnSpec , Digital Card/ Secure Digital HS/ Secure Digital V2.0 cards Memory Stick / Memory Stick PRO / Memory Stick , products including liability or warranties relating to fitness for a particular purpose, merchantability
OnSpec Electronic
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nand flash memory reader CompactFlash, SmartMedia, Memory Stick, Secure Digital card controller

onspec

Abstract: memory stick pro duo pin package Single chip with integrated USB 2.0 PHY Serial EEPROM port Serial port Two General Purpose Timers Watchdog Timer 16 bit Processor Programmable Read and Write widths Optimum hardware controlled , SD V2.0 spec media, enhancing the access space up to 32GBytes. Device Interfaces · · · · · · , Card/ Secure Digital HS/ Secure Digital V2.0 cards Memory Stick / Memory Stick PRO / Memory Stick HS , products including liability or warranties relating to fitness for a particular purpose, merchantability
OnSpec Electronic
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XDS510

Abstract: CPUs Processors Composer Studio IDE v2.0 Install a copy of Code Composer Studio IDE v2.0 or above for each processor type , program. For demonstration purpose, debug sessions for all the six processor in the system are opened , processor. Locked Step Locked step is used to single step all processors that are not already running , a multiprocessor system with multiple CPUs on a single board or one or more multicore devices in , or cores. The multiple cores on a single device often even share a common block of memory, which
Texas Instruments
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XDS510 CPUs Processors Texas Instruments Code Composer Studio XDS510 jtag XDS560 circuit XDS510 ccs 3.3 SPRA822 XDS510/XDS560

XDS510

Abstract: CPUs Processors Composer Studio IDE v2.0 Install a copy of Code Composer Studio IDE v2.0 or above for each processor type , program. For demonstration purpose, debug sessions for all the six processor in the system are opened , processor. Locked Step Locked step is used to single step all processors that are not already running , For a multiprocessor system with multiple CPUs on a single board or one or more multicore devices in , or cores. The multiple cores on a single device often even share a common block of memory, which
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TMS320C5000 TMS320C5500 TMS320C6000 XDS560

RT9198-33pbr

Abstract: CSR BC04 HBH1X1M Bluetooth V2.0 + EDR Class 1 Module Data Book Bluetooth Module HBH1X1M Data Book www.hanamicron.co.kr Rev1.0 Apr. 2006 HBH1X1M Bluetooth V2.0 + EDR Class 1 Module Data Book List of , www.hanamicron.co.kr 2 page / 17 pages HBH1X1M Bluetooth V2.0 + EDR Class 1 Module Data Book 1. General , I2C PIO SPI 3.3V www.hanamicron.co.kr 3 page / 17 pages HBH1X1M Bluetooth V2.0 + EDR Class 1 Module Data Book 1.2 Features Fully Qualified Bluetooth v2.0 + EDR System Enhanced Data
Hana Micron
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BC04-ROM RT9198-33pbr CSR BC04 Bluetooth MODULE CLASS 1 long range bluetooth transmitter receiver schematic csr pskey RT9198-33PBR

TC1796 user manual

Abstract: ANA 658 22150 : V2.0, 2007-07 Previous Version: V1.0 2005-06 Page Subjects (major changes since last revision , V2.0, 2007-07 TC1796 System and Peripheral Units (Vol. 1 and 2) TC1796 User's Manual Volume 1 (of 2) System Units & Volume 2 (of 2) Peripheral Units Revision History: V2.0, 2007-07 6-4 , 's Manual Bit descriptions of CH0x/CH1x and HTRE0x/HTRE1x are updated. V2.0, 2007-07 TC1796 System , (of 2) Peripheral Units Revision History: V2.0, 2007-07 12-99 Address range for AEN21 is updated
Infineon Technologies
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TC1796 user manual ANA 658 22150 TC1796. System and Peripheral Units LTC1905 Infineon Tricore TC1796 4514H

hardware AES 256 controller

Abstract: AES 256 USB Serial port · Two General Purpose Timers · Watchdog Timer · 16 bit Processor · Internal RAM for , Encryption. It contains the following: · 48-pin 7mm x 7mm LQFP package · Single chip with integrated USB , Universal Serial Bus (USB) specification V2.0 and V1.1. Support for NAND SLC / NAND MLC Flash Widespread support for popular NAND SLC / NAND MLC flash media is available. The xSil 269B processor comes with a 4 , programmable clock speed is provided to set the clock speed based on the media's capabilities. The processor
OnSpec Electronic
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SHA-256 hardware AES 256 controller AES 256 USB AES SHA USB

mlc flash

Abstract: error correction code mlc LQFP package · Single chip with integrated USB 2.0 PHY · Serial EEPROM port · Supports NAND, NAND , time) · Firmware enhancements can be stored on On-board NAND · Serial port · Two General Purpose Timers · Watchdog Timer · 16 bit Processor · Internal RAM for supporting enhancements · ROM with BIOS , . USB Engine The xSil 259B meets the Universal Serial Bus (USB) specification V2.0 and V1.1. Support , available. The xSil 259B processor comes with a 4-Byte FEC Error correction algorithm that detects and
OnSpec Electronic
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mlc flash error correction code mlc USB NAND Flash NAND PHY nand error correction

XAPP1041

Abstract: 88E1111 PHY registers map PowerPC405 processor (with the PLBv46 Wrapper) and XAPP1041 (v2.0) September 24, 2008 www.xilinx.com , Clock 125 Mhz 125 Mhz MicroBlaze Processor Clock 125 MHz 125 MHz Clock XAPP1041 (v2.0 , Application Note: Embedded Processing R XAPP1041 (v2.0) September 24, 2008 Abstract , uses the Virtex®-5 FPGA with the built-in PowerPC® 440 processor. This system uses the embedded , the Virtex-4 FPGA with the built-in PowerPC 405 processor. This system uses the embedded PowerPC 405
Xilinx
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ML505 88E1111 PHY registers map Marvell PHY 88E1111 Datasheet Marvell PHY 88E1111 Xilinx Marvell PHY 88E1111 Xilinx spartan Marvell PHY 88E1111 alaska Marvell PHY 88E1111 alaska register map ML507 ML405 DS537 DS643 DS614
Abstract: 0 Virtex-II Proâ"¢ Platform FPGAs: Introduction and Overview R DS083-1 (v2.0) June 13 , transceiver blocks (based on Mindspeed's SkyRailâ"¢ technology) - Up to four IBM® PowerPC ® RISC processor , Processor Blocks Logic Cells(1) Slices XC2VP2 4 0 3,168 XC2VP4 4 1 XC2VP7 , -1 (v2.0) June 13, 2002 Advance Product Specification www.xilinx.com 1-800-255-7778 1 R , Five-stage data path pipeline Hardware multiply/divide unit Thirty-two 32-bit general purpose registers 16 Xilinx
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XC2VP30 XC2VP40 XC2VP50 XC2VP7-7FG456C DS083

alpine Full Speed

Abstract: D1369 - - 32-bit ARM7 processor with MMU 4K unified cache FPU (floating point unit) Graphics , Single, double, and extended precision (cont.) Functional Block Diagram COLOR LCD ROM , 256-entry 28-bit video palette - Single- and dual-scan panel LCDs (16-bit grayscale) s Serial CD , DATA BOOK v2.0 June 1997 CL-PS7500FE System-on-a-Chip for Internet Appliance 3 ADVANCE DATA BOOK v2.0 June 1997 CL-PS7500FE System-on-a-Chip for Internet Appliance TABLE OF
Cirrus Logic
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alpine Full Speed D1369 CS4333 3334 2114 ram LDR 3190 40-MH

verilog code for 32 bit risc processor

Abstract: 5421 synchronous counter (DSP) to the PCI bus using the PLX IOP 480 I/O processor. The information can be used to build a high , · · · · · performance based on the PLX 66MHz 32-bit PowerPC RISC Processor , .2 1.3 IOP 480 RISC PROCESSOR , . 5 IOP 480/C5409/21 AN v2.0 © 2000 PLX Technology, Inc. All rights reserved. i 1. INTRODUCTION 1.3 IOP 480 RISC Processor This application note describes the connection b etween the PLX
PLX Technology
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TMS320VC5421 TMS320VC5409 verilog code for 32 bit risc processor 5421 synchronous counter 5409 c5409 pci verilog code TMS320VC5409/21 TMS320VC5409/5421 SPRS098 C6202/2B/3/4 TMS320C6202/2B/3/4

CS5536AD

Abstract: AMD Geode CS5536 works with both the AMD GeodeTM LX and AMD GeodeTM GX processor families to create today's leading , performance The AMD Geode CS5536 companion device leverages a single, high-performance modular structure , (Direct Memory Access) functions · Flexible MFGPTs (Multi-Function General Purpose Timers) General , 2.0 standard. · Designed for use with the AMD Geode LX and GX processor families · 208 , GeodeLinkTM Control Processor ­ SUSP#/SUSPA# handshake with power management logic provides Sleep control of
Advanced Micro Devices
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CS5536AD AMD Geode CS5536 AMD Geode CS5536AD CS5536A CS5536AC amd nand flash 33360D

RGMII Layout Guide

Abstract: XQ5VLX110T 0 Virtex-5Q Family Overview DS174 (v2.0) March 22, 2010 0 Product Specification 0 , RISC architecture 7-stage pipeline 32 Kbyte instruction and data caches included Optimized processor , trademarks are the property of their respective owners. DS174 (v2.0) March 22, 2010 Product , Endpoint Transceivers(6) PowerPC Total Max Blocks for Ethernet Processor I/O User PCI MACs(5) (8 , configuration Bank 0. DS174 (v2.0) March 22, 2010 Product Specification www.xilinx.com 2 Virtex
Xilinx
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DSP48E RGMII Layout Guide XQ5VLX110T XQ5VSX50T 7846N XQ5VLX110T-1EF1136I bit slice processors UG197 UG193 UG191 UG200 UG195
Abstract: device works with both the AMD Geodeâ"¢ LX and AMD Geodeâ"¢ GX processor families to create todayâ'™s , maximized for performance The AMD Geode CS5536 companion device leverages a single, high-performance , channels â'" DMA (Direct Memory Access) functions â'¢ Flexible MFGPTs (Multi-Function General Purpose Timers) General features â'¢ Designed for use with the AMD Geode LX and GX processor families â , '" 32-bit 33/66MHz operation â'¢ GeodeLinkâ"¢ Control Processor â'" SUSP#/SUSPA# handshake with power Advanced Micro Devices
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33360C

ROE capacitor din 41 238

Abstract: la7232   System-on-a-chip solution â'" 32-bit ARM7 processor with MMU â'" 4K unified cache â'" FPU (floating point unit , '" Implements ANSI/IEEE Std 754-1985 â'" Single, double, and extended precision System-on-a Chip for Internet , -bit video palette â'" Single- and dual-scan panel LCDs (16-bit grayscale) â  Serial CD digital sound (32 , ADVANCE DATA BOOK v2.0 CL-PS7500FE System-on-a-Chip for Internet Appliance June 1997 ADVANCE DATA BOOK v2.0 This Material Copyrighted By Its Respective Manufacturer CL-PS7500FE System-on-a-Chip for
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ROE capacitor din 41 238 la7232 BD8156 rgb led 5050 LCOS panel 32-Bit Parallel-IN Serial-OUT Shift Register oper ARM7500
Abstract: '" â'" â'" â'" â'" â'" â'" â'" 32-bit ARM7 processor with MMU 4K unified cache FPU (floating , '" Implements ANSI/IEEE Std 754-1985 â'" Single, double, and extended precision (cont.) Version 2.0 , -bit video palette â'" Single- and dual-scan panel LCDs (16-bit grayscale) â  Serial CD digital sound , to 64 MHz ADVANCE DATA BOOK v2.0 June 1997 CL-PS7500FE 'CIRRUS LOGIC System-on-a-Chip fo r Internet Appliance ADVANCE DATA BOOK v2.0 June 1997 CL-PS7500FE System-on-a-Chip fo r -
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7500FE

WM9713G

Abstract: SLPB526495 Baseboard V2.0 V2.0 V2.0 V2.0 V2.0 V2.0 V2.0 Changes Creation of this document Minor clarifications Added , . 6 1.4.1 Marvell PXA320 Processor Based on Intel XScale Technology , . 7 2.1 PXA320 Processor , . 17 3.3.19 PXA320 Processor Bus , based on the Marvell Xscale® PXA320 processor and runs at up to 806 MHz. It serves as the main part
Toradex
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WM9713G SLPB526495 gsm based digital notice board using LCD GPIO61 PXA3xx jtag WM9713

ARM verilog code

Abstract: ARM1136 Release 1.2 January 2003 B Release 2.0 September 2003 C Release 2.0.1 for RVDS v2.0 , expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are , . 2-2 Changes between RVCT v2.1 and RVCT v2.0 . 2-3 Changes between RVCT v2.0 and RVCT v1.2 . 2-7 Creating an , this chapter for details of the differences between RVCT v2.1, RVCT v2.0, and RVCT v1.2. Chapter 3
ARM
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ARM verilog code ARM1136 0202D

DS401

Abstract: processor systems. The bus interconnect in the OPB V2.0 specification is a distributed multiplexer , 0 On-Chip Peripheral Bus V2.0 with OPB Arbiter (v1.10c) DS401 December 2, 2005 0 0 Product Specification Introduction LogiCORETM Facts The OPB_V20 On-Chip Peripheral Bus V2.0 with , drivers into a single bus. Core Specifics Supported Device Family QProTM-R VirtexTM-II, QPro , the OPB V2.0 specification except for DMA handshake signals · The OR structure can be
Xilinx
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CR209288 CR208644

SMR 53-7

Abstract: CL-CD180 processor by internal interrupts over a special bus dedicated to this purpose. Special internal-interrupt , LOGIC RAM RISC PROCESSOR FIRMWARE ROM TxD RxD MODEM Version 2.0 World Wide Web: http://www. cirrus , proprietary RISC processor architecture developed by Cirrus Logic specifically for data communication applications. This processor executes all instructions in one clock cycle, and uses a register-window , reliability. Theory of Operation The CL-CD1865 custom RISC processor is assisted by specialized peripheral
-
OCR Scan
CL-CD180 CL-CD1864 SMR 53-7 TTL LOGIC DATA BOOK vesuvius 74XX244 80X86

XQ2VP40-5FG676N

Abstract: XQ2VP40-5FF1152N 405 RISC processor blocks. Thirty-two 32-bit general purpose registers (GPRs) · , . Up to four Processor Blocks can be available in a single Virtex-II Pro device. On-Chip Memory , c 2 R DS136 (v2.0) December 20, 2007 QPro Virtex-II Pro 1.5V Platform FPGAs Complete , : DC and Switching Characteristics DS136-1 (v2.0) December 20, 2007 DS136-3 (v2.0) December 20 , Module 4: Pinout Information DS136-4 (v2.0) December 20, 2007 DS136-2 (v2.0) December 20, 2007 94
Xilinx
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FG676 FF1152 XQ2VP70-6EF1704I XQ2VP40-5FG676N XQ2VP40-5FF1152N xq2vp40 XQ2VP70 H337 EF1152 EF1704 FF1704

FFG668

Abstract: XC4VLX25-10FFG668CS2 ratio options between PPC405 and Processor Local Bus - DS112 (v2.0) January 23, 2007 Preliminary , ` 0 R Virtex-4 Family Overview DS112 (v2.0) January 23, 2007 0 0 Preliminary , only] IBM PowerPC RISC Processor Core [FX only] - · 1.5V to 3.3V I/O operation Built-in , grained I/O banking (configuration in one bank) PowerPC 405 (PPC405) Core Auxiliary Processor Unit , Members Configurable Logic Blocks (CLBs) (1) Block RAM PowerPC Max Max Processor Distributed
Xilinx
Original
FFG668 XC4VLX25-10FFG668CS2 Virtex4 XC4VFX60 Virtex 4 XC4VFX60 FFG676 FFG1517 DSP48

JMH330

Abstract: usb to sata converter circuit diagram ® AtomTM Z510 processor running at 1.1GHz. Robin Z530 offers a single PCI Express x1 lane, GLAN, HDA and up , Z530 533MHz 1GByte 4GByte V2.0 2.0mm 2.3. CPU and Chipset Robin with CPU Z530 Processor CPU Clock , Versions V2.0 V2.0 Changes Preliminary Release chapter LPC + note for LPC_CLK grammar changes chapter AC , chapter 5.3 New Disclaimer Pins B93 & B94 changed to 5V Rail 02-Jul-10 1.1 V2.0, V1.0 13-Jul-10 16-Sept-10 21-Sept-10 22-Sept-10 01-Feb-11 1.2 1.3 1.31 1.32 1.33 V2.0, V1.0 V2.0, V1.0 V2.0
Toradex
Original
JMH330 usb to sata converter circuit diagram rtl8111* Reference schematic circuit for sata ssd disk ddr2 ram slot pin detail 534 b34 diode 2002/95/EC

turbo encoder design using xilinx

Abstract: CRC24 LTE DL Channel Encoder v2.0 XMP023 April 24, 2009 Product Brief Introduction The Xilinx , speed and area · Fully synchronous design using a single clock · For use with the Xilinx , processor interface to reduce system-level overhead. Timing critical operations are performed by the FPGA , produces more than one code-block). Convolutional code applied to BCH and DCI data (single code block , www.xilinx.com 1 LTE DL Channel Encoder v2.0 Control and Broadcast Channel Processing X-Ref Target -
Xilinx
Original
turbo encoder design using xilinx CRC24 lte turbo encoder LTE DL Channel Encoder lte xilinx turbo convolution encoder

CL-CD180

Abstract: CL-CD1865 the processor by internal interrupts, over a special bus dedicated to this purpose. To reduce , INTERFACE RISC PROCESSOR FIRMWARE ROM 5 SERIAL INTERFACE 5 SERIAL INTERFACE 5 SERIAL , CL-CD1865 is based on a high-performance proprietary RISC processor architecture developed by Basis Communications specifically for data communication applications. This processor executes all instructions in one , processor is assisted by specialized peripheral logic. Serial data transmission and reception is handled
Basis Communications
Original
Design a 3-bit magnitude comparator by using basic CD96 CD1865 M68000 CL-CD1865-10QC-B diode D6E

CL-CD180

Abstract: CL-CD1865 INTERFACE 5 RAM SERIAL INTERFACE 5 SERIAL INTERFACE HOST BUS INTERFACE LOGIC RISC PROCESSOR FIRMWARE ROM 5 , CL-CD1865 is based on a high-performance proprietary RISC processor architecture developed by Cirrus Logic specifically for data communication applications. This processor executes all instructions in one clock cycle , performance, and maximum reliability. Theory of Operation The CL-CD1865 custom RISC processor is assisted , bit-level timing, bit-to-character assembly is done in firmware. Bits are passed to the processor by
Cirrus Logic
Original

core i3 addressing modes

Abstract: agl030 QN68 v2.0 IGLOO Low-Power Flash FPGAs ® with Flash*Freeze Technology Features and Benefits , Processor Support in IGLOO FPGAs · Segmented, Hierarchical Routing and Clock Structure · M1 IGLOO Devices-CortexTM-M1 Soft Processor Available with or without Debug Advanced I/O · 700 Mbps DDR, LVDS-Capable I/Os , 1.45 1.00 1.60 2.23 II v2.0 IGLOO Low-Power Flash FPGAs IGLOO Ordering , . v2.0 III IGLOO Low-Power Flash FPGAs Temperature Grade Offerings AGL015 AGL030
Actel
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core i3 addressing modes agl030 QN68 QN132 Actel igloo bank AGL400 FG144 AGL250 JESD8-12

AES-128

Abstract: FG256 v2.0 IGLOOe Low-Power Flash FPGAs ® with Flash*Freeze Technology Features and Benefits , , ×2, ×4, ×9, and ×18 organizations available) · True Dual-Port SRAM (except ×18) ARM Processor Support in IGLOOe FPGAs · M1 IGLOOe Devices-CortexTM-M1 Soft Processor Available with or without Debug , 289 529 961 1 1 1 1.6 2.23 2.23 v2.0 IGLOOe Low-Power Flash FPGAs , IGLOO V5 devices are marked accordingly. v2.0 III Temperature Grade Offerings AGLE600
Actel
Original
AES-128 FG256 FG484 ProASICPLUS Flash Family FPGAs v2.0 128-B

ARM processor securecore

Abstract: ARM SC100 SC100 advanced secure processor. This general purpose 32-bit processor offers high performance, very , architecture is characterized by a single data and address bus for instruction data. The SC100 processor , Features General · Based on the ARM® SC100 SecureCore 32-bit RISC Processor · Two Instruction , ® High-code-density 16-bit Instruction Set Von Neumann Load/Store Architecture ­ Single 32-bit Data Bus for , processor) 32K Bytes of ROM dedicated to Atmel's crypto Library Peripherals · One ISO 7816 Controller
Atmel
Original
ISO7816-2 ARM processor securecore ARM SC100 ARM processor pin configuration ARM SC100 Architecture AT91SC512384RCT AT91SC 512384RCT 6525AS

IN60 diode

Abstract: RENK Pt 100 sensor connection Peripheral Units User's Manual Revision History: 2001-02 Previous Version: Page V2.0 V1 , version for the B-Step created for release purposes of the final version V2.0. 2) These versions for , . . . . . . . . 1-14 General Purpose Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 General Purpose Timer Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16 , . . . . . 2-35 User's Manual I-1 V2.0, 2001-02 TC1775 Peripheral Units Table of
Infineon Technologies
Original
IN60 diode RENK Pt 100 sensor connection as15 G sr2 mod02 apqp MANUAL in60

XUartNs550

Abstract: RAMB16BWE project. There is a single C source file for the processor. · lcd_ref.c: C source file. Contains the , (v2.0) February 8, 2010 Author: Christophe Charpentier Summary The Simple MicroBlazeTM Microcontroller (SMM) is a small form factor 32-bit microcontroller based on the MicroBlaze processor that can be , property of their respective owners. XAPP1141 (v2.0) February 8, 2010 www.xilinx.com 1 , processor · 8KB of internal RAM/ROM · Software application is stored in BRAMs at configuration
Xilinx
Original
ML605 SP605 UG330 XUartNs550 RAMB16BWE RAM16BWER example ml605 uart 16450 RS232 UG081 UG534

verilog code for huffman coding

Abstract: huffman code generator in verilog · Single sample per clock cycle processing Sample data in, JPEG stream out No host processor , implementation. March 4, 2002 1 Motion JPEG Encoder Core V2.0 Host Processor (or) State Machine , Motion JPEG Encoder Core V2.0 March 4, 2002 Product Specification AllianceCORETM Facts TM , interface Host Processor: memory mapped interface capability Support for standard and abbreviated JPEG , Stream The highly integrated core does not require host processor intervention during the encoding
Xilinx
Original
verilog code for huffman coding huffman code generator in verilog huffman decoder verilog jpeg encoder vhdl code jpeg encoder verilog code for huffman encoding

memory stick pro duo pin

Abstract: nand flash memory reader General Purpose Timers Watchdog Timer 16 bit Processor Internal RAM for supporting enhancements ROM , -pin 16mm x 16mm QFP package Single chip with integrated USB 2.0 PHY Serial EEPROM port Supports up to 25 , MultiMediaCard/ MMC 4.0 1/ 4/ 8 bit Data bus support Secure Digital Card/ Secure Digital HS/ Secure Digital V2.0 , fitness for a particular purpose, merchantability, or infringement or any patent, copyright or other
OnSpec Electronic
Original
258B sd ram reader smartmedia usb Reader

ARM1176JZ

Abstract: X0010W B Release 2.0 September 2003 C Release 2.0.1 for RVDS v2.0 January 2004 D , limited to implied warranties of merchantability, or fitness for purpose, are excluded. This document is , . 1-7 Differences between RVCT v2.1 and RVCT v2.0 . A-2 Differences between RVCT v2.0 and RVCT v1.2 . A-6 Compatibility with , names. Denotes ARM processor signal names. Also used for terms in descriptive lists, where appropriate
ARM
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ARM1176JZ X0010W ARM968EJ-S TrustZone 0202F

e10g42bt

Abstract: NAS 1831 ? Customers will host more applications on a single, high-performing, virtualized server, driving more demand , When implemented within multi-core processor environments, the Intel® Ethernet Server Adapter X520-T2 , overall server performance. These technologies are Virtual Machine Device Queues (VMDq) and Single Root I , network planning: · Intel® Ethernet Server Adapter X520 Series for 10GbE SFP+ PCIe v2.0 (5 GT/s , Manager Compatible with x8 and x16 standard and low-profile PCI Express* slots Order Code Single unit
Intel
Original
10GBASE-T e10g42bt NAS 1831 connector RJ45 CAT-6 RJ-45 0810/SWU 318349-004US

MC74HC14D

Abstract: MC68681 PROGRAMMING EXAMPLE supports M68EZ328ADS v2.0: · Metrowerks Codewarrior · Single Step Development System · SLD Metrowerks , Motorola, Inc. M68EZ328ADS v2.0 Application Development System User's Manual Revision 1.0 , . 1-7 M68EZ328ADS v2.0 , . 2-8 Prepare the M68EZ328ADS v2.0 board . 2-8 Connecting M68EZ328ADS v2.0 to PC. 2-11 Installing
Motorola
Original
MC74HC14D MC68681 PROGRAMMING EXAMPLE MONITOR IBM E54 MC74HC14AD ST16C2552 LCD 14X2 EZADS20

LCD 14X2

Abstract: MC74HC14D following software debugger supports M68EZ328ADS v2.0: · Metrowerks Codewarrior · Single Step Development , single tone generator CHB-03E is provided on M68EZ328ADS v2.0. As shown in Figure 3-10, a simple , ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 Freescale Semiconductor, Inc. M68EZ328ADS v2.0 , . 1-7 M68EZ328ADS v2.0 , . 2-8 Prepare the M68EZ328ADS v2.0 board . 2-8
Motorola
Original
14x2 lcd B-30 B-31 D-40 SDS 202 transistor ADS7843

MC74HC14D

Abstract: MC74HC14AD ARCHIVED BY FREESCALE SEMICONDUCTOR, INC. 2005 Freescale Semiconductor, Inc. M68EZ328ADS v2.0 , . 1-7 M68EZ328ADS v2.0 , . 2-8 Prepare the M68EZ328ADS v2.0 board . 2-8 Connecting M68EZ328ADS v2.0 to PC. 2-11 Installing , . 3-24 Single Tone Generator
Motorola
Original
heart beat measuring device 68000 MC68681 PROGRAMMING EXAMPLE ADS7843 application 68000 motorola vme

XAPP463

Abstract: written particular purpose. XAPP463 (v2.0) March 1, 2005 www.xilinx.com 1 R Using Block RAM in , XAPP463 (v2.0) March 1, 2005 Summary For applications requiring large, on-chip memories, SpartanTM , 2 www.xilinx.com XAPP463 (v2.0) March 1, 2005 R Using Block RAM in Spartan-3 Generation , , microsequencers, program storage for embedded processor(s) The Xilinx CORE Generator system supports various , and applications for block RAM. XAPP463 (v2.0) March 1, 2005 www.xilinx.com 3 R Block
Xilinx
Original
XC3S50 XC3S200 XC3S400 written RAMB16 vhdl code for bcd to seven segment display XC3S500E Seven Segment LED Display vhdl code for 4 bit even parity generator XC3S1000/L XC3S1000L XC3S1500L

SPRA774

Abstract: DSK6711 Single processor. 7. Select the Startup GEL File(s) tab and click on the browse button. Browse to where , Studio v2.0 SPRA774 3 Testing Single Vector 3.1 Saving a Workspace With Files Connected , Studio v2.0 Harsh Sabikhi Code Composer Studio, Applications Engineering ABSTRACT This , Single Vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Output Screen of Single Vector Case . . .
Texas Instruments
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DSK6711 object counter project report to download

Msi 533 Motherboard

Abstract: intel 82580 designers others. MSI-X helps in load-balancing I/O interrupts across multiple processor cores, and Low Latency , interrupts to a specific processor core based on the application's address. Halogen-Free1 Working to , Ethernet server adapters for iSCSI allows administrators to use a single initiator, TCP/IP stack, and set , segmentation offload, Receive side coalescing (RSC), and checksum offload capabilities help reduce processor , the Intel® Xeon® processor 5500 series, which improves transmission reliablity and thus delivers an
Intel
Original
Msi 533 Motherboard intel 82580 designers E1G44HF I340-T4 intel 82580 board designers E1G44 0111/SWU 323205-003US

CSR BlueCore4

Abstract: BlueCore4-ROM _äìÉ`çêÉ»QJolj Device Features Single Chip Bluetooth® v2.0 System with EDR ! Fully Qualified Bluetooth v2.0 system ! Enhanced Data Rate (EDR) compliant with v2.0.E.2 of specification for , is a single chip radio and baseband IC for Bluetooth 2.4GHz systems including enhanced data rates , Bluetooth software stack it provides a fully compliant Bluetooth system to v2.0 of the specification for , fully compliant with the Bluetooth v2.0 Specification (all mandatory and optional features). To
Cambridge Silicon Radio
Original
CSR BlueCore4 BlueCore4-ROM BlueCore4 BlueCore4 at command BLUECORE4 CSR PS key BlueCore4 BC41B143A BC41B143A-

MC74HC14D

Abstract: MC68681 PROGRAMMING EXAMPLE single tone generator CHB-03E is provided on M68EZ328ADS v2.0. As shown in Figure 3-10, a simple , Freescale Semiconductor, Inc. Motorola, Inc. Freescale Semiconductor, Inc. M68EZ328ADS v2.0 , . 1-7 M68EZ328ADS v2.0 , . 2-8 Prepare the M68EZ328ADS v2.0 board . 2-8 Connecting M68EZ328ADS v2.0 to PC. 2-11 Installing
Motorola
Original
MC74HC125AD MC68681 PROGRAMMING baud CHB 402 manual transistor bra 94 MC74HC32AD RS232 8x8 controller circuit

SR3B261BD manual book

Abstract: telemecanique contactor catalogue . follow-up, management and coaching activities. (ASM's and SE's) The primary purpose for developing and , exception basis when 10 or more product catalog numbers are on a single request. CONFIDENTIAL. For use by , IAC INFOSOURCE 1.0 Sales Tools Telemecanique® and the OEM Market 1 Launch of Unity V2.0 , Unity V2.0 CONFIDENTIAL. For use by Schneider Electric personnel and channel partners only. 2 , Sales 48% Asia-Pacific Workforce 15,000 Sales 16% 3 Launch of Unity V2.0 A World Leader
Schneider Electric
Original
SR3B101BD SR3B261BD SR3B261BD manual book telemecanique contactor catalogue manual telemecanique altivar 31 telemecanique sr3b261bd manual SCHNEIDER PLC SR3B261BD SR2B121BD 100-240VAC SR2B121FU SR2B201BD SR2B201FU

stk 412 -410

Abstract: IC stk 412 410 multiple bits from one operand in a single instruction. User's Manual 2-4 V2.0, 2000-07 C167CS , User's Manual, V2.0, July 2000 C167CS Derivatives 16-Bit Single-Chip Microcontroller , endangered. User's Manual, V2.0, July 2000 C167CS Derivatives 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . C167CS Revision History: V2.0, 2000-07 , added C167CS Revision History: V2.0, 2000-07 (cont'd) Previous Version: Version 1.0
Infineon Technologies
Original
stk 412 -410 IC stk 412 410 STK 5333 c167cs-lm Bootstrap stk 412 -230 stk 142 150 T01CON T78CON

SiS5595

Abstract: A-PC06 PASSWORD SECURITY AND KEYBOARD POWER UP Preliminary V2.0 Nov. 2, 1998 i Silicon Integrated Systems , . 153 THE DATA ACQUISITION MODULE INTERNAL REGISTERS . 160 Preliminary V2.0 Nov. 2, 1998 , . 210 Preliminary V2.0 Nov. 2, 1998 iii Silicon Integrated Systems Corporation SiS5595 PCI , . 22 FIGURE 3.2-6 PROCESSOR POWER STATE DIAGRAM. 23 FIGURE , PURPOSE TIMER LOGIC . 28 FIGURE 3.2-11 GPIO LOGIC
Silicon Integrated Systems
Original
A-PC06 sis5600 motherboard electronic circuit diagram pc 100 sis530 8042 keyboard ps2 command SiS chipset of 2n3904 S5595

TMS320C5000

Abstract: RTDX GUI fixes have been implemented since Code Composer Studio v2.0, and this document will provide an overview , Triggering With Running Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . , respective owners. 1 SPRA812 1 Introduction Code Composer Studio v2.0 was one of Texas , integration and intensive testing went into the v2.0 release to make it the solid, robust product that it is , full support for a number of new and different digital signal processor (DSP) devices ­ both on the
Texas Instruments
Original
RTDX GUI C5402 C549 TMS320C541 TMS320C5510 C6211DSK

NS9360

Abstract: SPI AHB IP boot NS9360 32-bit NET+ARM Microprocessor High-performance ARM926EJ-S processor with rich set of , Features/Benefits Platforms and Services · High-performance ARM926EJ-S core · Up to 177 MHz processor , Processor · · · · · · · · · · · 103, 155, 177 MHz 5-stage pipeline Harvard , , VxWorks, etc. DSP instruction extensions: improved divide, single cycle multiply accumulate ARM , support Clock-gated processor for decreased power dissipation External System Bus Interface · ·
Digi International
Original
SPI AHB IP boot 272-P E2/1209

XAPP1026

Abstract: lwIP XPS LocalLink TEMAC in an Embedded Processor XAPP1026 (v2.0) June 15, 2009 www.xilinx.com 14 , : Siva Velusamy XAPP1026 (v2.0) June 15, 2009 Summary Lightweight IP (lwIP) is an open source , processor. This application note describes how to utilize the lwIP library to add networking capability to , property of their respective owners. XAPP1026 (v2.0) June 15, 2009 www.xilinx.com 1 R , Processor Frequency EMAC DMA ML505 MicroBlaze 125 MHz xps_ll_temac SDMA ML507
Xilinx
Original
XAPP1043 lwIP lwip130 marvell API guide rfc 1350 microblaze web server ML403 IDS11

E1G44HTBLK

Abstract: e1g44ht load-balancing I/O interrupts across multiple processor cores, and Low Latency Interrupts can provide certain , specific processor core based on the application's address. Support for iSCSI Intel® Ethernet server , iSCSI allows administrators to use a single initiator, TCP/IP stack, and set of management tools and , coalescing (RSC), and checksum offload capabilities help reduce processor utilization, increase throughput , ® processor 5500 series, which improves transmission reliablity and thus delivers an enterprise class iSCSI
Intel
Original
E1G44HTBLK e1g44ht bridgeless CRC-32 0110/SWU 323205-002US

SPARTAN-3A DSP 3400A

Abstract: AD7180 ] [optional] UG456 (v2.0) November 17, 2008 [optional] R R Xilinx is disclosing this user guide , MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL , Starter Kit www.xilinx.com UG456 (v2.0) November 17, 2008 Table of Contents Revision History . , -3A DSP FPGA Video Starter Kit UG456 (v2.0) November 17, 2008 www.xilinx.com 25 25 25 25 26 26 , 51 Spartan-3A DSP FPGA Video Starter Kit UG456 (v2.0) November 17, 2008 R Appendix A
Xilinx
Original
SPARTAN-3A DSP 3400A AD7180 schematic diagram vga to rca CH7301 SPARTAN camera link image sensor micron

c167cs-lm Bootstrap

Abstract: C166 multiple bits from one operand in a single instruction. User's Manual 2-4 V2.0, 2000-07 C167CS , User's Manual, V2.0, July 2000 C167CS Derivatives 16-Bit Single-Chip Microcontroller , endangered. User's Manual, V2.0, July 2000 C167CS Derivatives 16-Bit Single-Chip Microcontroller Microcontrollers N e v e r s t o p t h i n k i n g . C167CS Revision History: V2.0, 2000-07 , added C167CS Revision History: V2.0, 2000-07 (cont'd) Previous Version: Version 1.0
Infineon Technologies
Original
C166 C167 C167CS-4RM C167CS-LM C500

ARM920T

Abstract: ARM926EJ-S merchantability, or fitness for purpose, are excluded. This document is intended only to assist the reader in , Handling Processor Exceptions 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 , . About processor exceptions . 6-2 Determining the Processor State , 0203C Preface This preface introduces the RealView Compilation Tools v2.0 Developer Guide. It
ARM
Original
ARM920T

SiS chipset

Abstract: SIS5582 Dev ice ISA Device ISA Device Preliminary V2.0 April 15, 1997 ISA Dev ice PCI Dev i , the Pipelined Address Mode of Pentium CPU Support the Full 64-bit Pentium Processor data Bus Meet , Memory in Non-Cacheable Regions - Shadow RAM in Increments of 16 KBytes Preliminary V2.0 April 15 , for PCI to ISA Memory cycles Preliminary V2.0 April 15, 1997 3 Silicon Integrated Systems , V2.0 April 15, 1997 4 Silicon Integrated Systems Corporation SiS5581 SiS5582 Pentium PCI
Silicon Integrated Systems
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TI HA04 SiS 651 chipset of 74LS245 SiS chipset 386 8042 intel kbc intel 386 motherboard diagram S5581 S5582

IXF6400

Abstract: IXF6401 product brief IXF6402 Broadband Access Processor Product Overview www.intel.com/IXA Key Applications The IXF6402 is a fourth-generation 64-bit Broadband Access Processor capable of formatting and , packet encapsulation engine-all in a single, integrated package. The IXF6402 Broadband Access Processor can significantly benefit developers by helping: n Edge/access devices n Switches and , Processors n IXF6402 Broadband Access Processor n FLAME (Layer 2/3/4 Flexible Application Module
Intel
Original
IXF6400 IXF6401 PB-1010 USA/0600/4K/ASI/CR

SiS5598

Abstract: SiS chipset integrated single chip solution for Pentium PCI/ISA system. A portion of on-board DRAM is shared with the , PCI Bus ISA Bus ISA Dev ice ISA Device ISA Device Preliminary V2.0 April 15, 1997 , feature Support the Pipelined Address Mode of Pentium CPU Support the Full 64-bit Pentium Processor data , Preliminary V2.0 April 15, 1997 2 Silicon Integrated Systems Corporation SiS5597 SiS5598 Pentium PCI , Preliminary V2.0 April 15, 1997 3 Silicon Integrated Systems Corporation SiS5597 SiS5598 Pentium PCI
Silicon Integrated Systems
Original
SIS 5598 AMD 700 chipset bt815 HD03 P6 MOTHERBOARD SERVICE MANUAL intel 945 MAINBOARD pcb CIRCUIT diagram S5597 S5598

LVDS display 30 pin connector

Abstract: omnivision EVALUATION BOARD : Blackfin Processor Module powered by Analog Devices single core ADSP-BF533 processor; up to 600MHz, 32MB , Processor Module powered by Analog Devices single core ADSP-BF537 processor; up to 600MHz, 32MB RAM, 4MB , 36.5x31.5mm CM-BF537U: Blackfin Processor Module powered by Analog Devices single core ADSP-BF537 , size of 36.5x31.5mm TCM-BF537: Blackfin Processor Module powered by Analog Devices single core , new Blackfin Processor Module powered by Analog Devices single core ADSP-BF527 processor will be
BLUETECHNIX Mechatronische Systeme
Original
CM-BF533 LVDS display 30 pin connector omnivision EVALUATION BOARD ADSP-BF537 uclinux d type 50 pin connector ddr spi flash micron usb dac

16f877a microcontroller

Abstract: datasheet of 16F877A microcontroller bus available for interfacing to user electronics · Microchip 16F877A processor with 8K FLASH , handled automatically by the on-board FT245RL and its support circuitry V2.0 Page 1 of 14 June , code readers V2.0 Page 2 of 14 June 2006 GENERAL DESCRIPTION The DLP-245PB-G provides a , virtual com port. The architecture of the D2XX drivers consists of a Windows WDM V2.0 Page 3 of 14 , MPROG. V2.0 Page 4 of 14 June 2006 QUICK START GUIDE This guide requires the use of a
DLP Design
Original
16f877a microcontroller datasheet of 16F877A microcontroller interfacing of 16F877A microcontroller PID control, pic16f877a ARCHITECTURE OF 16F877A 16F877A microcontroller pin description DLP-USB245M-G 2N3904 PIC16F877A

8kx8 sram

Abstract: SiS 301 chipset integrated single chip solution for Pentium PCI/ISA system. A portion of on-board DRAM is shared with the , Device Preliminary V2.0 April 15, 1997 1 Silicon Integrated Systems Corporation SiS5597 , Pentium CPU Support the Full 64-bit Pentium Processor data Bus Meet PC97 Requirements Integrated Second , Systems Corporation · Preliminary V2.0 April 15, 1997 SiS5597 SiS5598 Pentium PCI/ISA Chipset · , Silicon Integrated Systems Corporation · · · · Preliminary V2.0 April 15, 1997 SiS5597
Silicon Integrated Systems
Original
8kx8 sram SiS 301 chipset Z11-Z1 rectangular led holders DRAM arbiter intel 945 MOTHERBOARD SERVICE MANUAL

Ethernet-MAC using vhdl

Abstract: sgmii Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User Guide UG074 (v2.0) May 12, 2009 R R , WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS , . Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com UG074 (v2.0) May 12, 2009 Revision , Revised sample code in "Interfacing to the Processor DCR," page 150. In Chapter 5: · Replaced Figure 5-2 , to the "Host Interface" section. UG074 (v2.0) May 12, 2009 www.xilinx.com Embedded Tri-Mode
Xilinx
Original
Ethernet-MAC using vhdl sgmii SGMII RGMII bridge RTL code for ethernet 1000BASE-X GT11

ARM processor

Abstract: teaklite single processor. However, you can purchase additional licenses to extend the RealView Debugger , v2.0 January 2004 B RVDS Release v2.1 Proprietary Notice Words and logos marked with , purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM , . 1-13 Differences 2.1 2.2 Changes between RVDS v2.1 and RVDS v2.0 , cross-references, and citations. Highlights interface elements, such as menu names. Denotes ARM processor signal
ARM
Original
0255B ARM processor teaklite AN98 ieee embedded system projects

atmel at45db642D

Abstract: ARM SC100 Features General · Based on the ARM® SC100TM SecurCoreTM 32-bit RISC Processor · Two , Set · Von Neumann Load/Store Architecture · Single 32-bit Data Bus for Instructions and Data · 3 , (up to 20MHz) · USB Interface (5 Endpoints) - USB V2.0 Full-speed (12Mbps), Suspend/Resume Modes , (Inter Chip) 0.8e Interface · Interface for External NAND Flash Memory · Single Wire Interface (Digital , ARM SC100 advanced secure processor. This general-purpose 32-bit processor offers high performance
Atmel
Original
AT91SC512384-8M atmel at45db642D AT45DB642D ATV4-91SC flash memory spi ARM SC100 7816

communication between cpu and iop

Abstract: low cost processor Three External PCI Bus Masters sI 2O Ready Messaging Unit with v2.0 Performance Extensions s , packages T E C H N O L O G Y ® I/O Processor The rapid spread of PCI in embedded designs has led to the creation of a new class of products, the I/O Processor (IOP). Design requirements driving the , performance, low cost processor, efficient memory management, flexible I/O device interface, high performance , -bit operation, at speeds up to 66MHz, and in 32-bit mode offers fly-by DMA with single cycle transfers between
PLX Technology
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communication between cpu and iop low cost processor PLX 480 Programmable interval timer chips 480-SIL-PB-0-1

6553a

Abstract: ATV4-91SC Features General · Based on the ARM® SC100TM SecurCoreTM 32-bit RISC Processor · Two , Set · Von Neumann Load/Store Architecture · Single 32-bit Data Bus for Instructions and Data · 3 , (up to 20MHz) · USB Interface (5 Endpoints) - USB V2.0 Full-speed (12Mbps), Suspend/Resume Modes , (Inter Chip) 0.8e Interface · Interface for External NAND Flash Memory · Single Wire Interface (Digital , advanced secure processor. This general-purpose 32-bit processor offers high performance, very low power
Atmel
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AT91SC512384-128M 6553a securcore

82546EB

Abstract: 82544GC incorporates two full Gigabit Ethernet MAC and PHY layer functions on a single, compact component. Packaged in , 1000BASE-LX (802.3z). In addition, the controller provides a single, direct Peripheral Component Interconnect (PCI) 2.2 and PCI-X 1.0a compliant bus that operates as a single multi-function device on the bus , a management processor. The SMBus port enables industry standards such as IPMI (Intelligent , packet descriptors in a single burst for efficient PCI-bandwidth usage. Two 64KB on-chip packet buffers
Intel
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82546EB 1000BASE-SX 82544GC intel DMA controller Unit 1000BASE-T 100BASE-TX 10BASE-T 133MH

NS9750

Abstract: Basic ARM9 block diagram NS9750 Powerful 32-bit ARM9 Microprocessor High performance 32-bit ARM9 processor with rich set , · Up to 200 MHz processor clock speed · 8 KB instruction and 4 KB data cache · On-chip 10/100 Mbit , Specifications 32-bit Arm926EJ-S RISC Processor Optimized 10/100 Ethernet MAC Serial Ports · · · · , as Linux, WinCE/Pocket PC, VxWorks, etc. DSP instruction extensions: improved divide, single , Active-matrix color TFT displays - Up to 24 bpp direct 8:8:8 RGB; 16 M colors - Single- and dual-panel color
Digi International
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Basic ARM9 block diagram 32-bit microprocessor harvard architecture block diagram VIA ARM926EJ-S 926EJ-S 388-P 10/100B
Abstract: . on all channels; up to 52 Mbits/sec. on a single channel using pro­ grammable sync; async rates up ,   PCI bus master data transfers; fully PCI 2.1 compliant â  ARM7TDMI processor with on-chip firmware , ) with dual-threshold control â  Interrupts allow host processor option to service any or all channels on a single interrupt â  Dual-queue buffer management system OVERVIEW The CL-CD4400 is a , . Each channel can operate at bit rates up to 8 Mbits/sec. (up to 52 Mbits/sec. data rate on a single -
OCR Scan
FCS-16 FCS-32

lfsr galois

Abstract: lfsr fibonacci warranties of merchantability or fitness for a particular purpose. XAPP661 (v2.0) June 25, 2003 , Application Note: Virtex-II Pro Family R XAPP661 (v2.0) June 25, 2003 RocketIO Transceiver , ) embedded in a single VirtexTM-II Pro FPGA. To build a system, an IBM CoreConnectTM infrastructure connects the PowerPCTM405 processor (PPC405) to external memory and other peripherals using the processor , . The processor reads the status and counter values from the XBERT through the PLB Interface, then
Xilinx
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XAPP662 lfsr galois lfsr fibonacci free verilog code of prbs pattern generator prbs pattern generator using analog verilog generating pwm verilog code verilog/lfsr fibonacci PCTM405
Abstract: /3.8/4.0/5.0 ns Fully synchronous register-to-register operation Single register "Flow-through" option , one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The , 10 8/15/02; v.2.0 Alliance Semiconductor P. 2 of 12 AS7C33256PFS32A AS7C33256PFS36A , on clock edges when ADSC is active or when CE0 and ADSP are active. Address strobe processor , , enables single register flow-through mode. Connect to VDD if unused or for pipelined operation. Snooze Alliance Semiconductor
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AS7C33256NTD32A/ AS7C33256NTD36A
Abstract: /3.8/4.0/5.0 ns Fully synchronous register-to-register operation Single register "Flow-through" option , one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The , 10 8/14/02; v.2.0 Alliance Semiconductor P. 2 of 12 AS7C33256PFS32A AS7C33256PFS36A , on clock edges when ADSC is active or when CE0 and ADSP are active. Address strobe processor , , enables single register flow-through mode. Connect to VDD if unused or for pipelined operation. Snooze Alliance Semiconductor
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basic architecture of ARM Processors

Abstract: programmer schematic arm licence to use this specification (ARM contract reference LEC-ELA-00081 V2.0). PLEASE READ THEM CAREFULLY , architecture 3.4.1 The generic ELF specification 3.4.2 ELF for the ARM architecture (processor supplement , public release. Document renumbered (formerly GENC-003535 v2.0). 10th October 2008 LS §3.9 , core registers The general purpose registers visible in the ARM architecture's programmer's model , ) BETWEEN YOU (AN INDIVIDUAL OR SINGLE ENTITY WHO IS RECEIVING THIS DOCUMENT DIRECTLY FROM ARM LIMITED
ARM
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basic architecture of ARM Processors programmer schematic arm ARM 9 processor arm9 architecture abi assembly language ARM1136J-S 0036B

82545EM

Abstract: 1000BASE-X PHY layer functions in a single, compact component. Packaged in a 21x21mm TFBGA, the Intel 82545EM , : management packets can be routed to or from a management processor. The SMBus port enables implementation of , prefetches up to 64 packet descriptors in a single burst for efficient PCI-bandwidth usage. A 64KB on-chip , processor, such as TCP/UDP/IP checksum calculations and TCP segmentation. Applications The Intel , up to 64 packet descriptors in a single burst Programmable host memory receive buffers (256B to 16KB
Intel
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NP2104 0302/OC/EW/PG/2
Abstract: and a PCI interface that maximizes the use of (SerDes) in a single, compact component. bursts , descriptors in a single burst for efficient and electrically compatible with the Intel® 82546GB , processor, such as TCP/UDP/IP checksum calculations and TCP segmentation. Applications The Intel , be routed to or from a management processor. The SMBus port enables implementation of LAN on , due to receive FIFO overrun Caches up to 64 packet descriptors in a single burst I Efficient Intel
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82545GM RC82545GM 0803/OC/WW/PDF

Intel IXA SDK Developers Workbench

Abstract: A8797-01 .19 Intel® Internet Exchange Architecture Software Developers Kit v2.0 for the IXP1200 Network Processor , Intel® Internet Exchange Architecture Software Developers Kit v2.0 for the IXP1200 Network Processor , ® IXA Software Developers Kit (SDK) v2.0 for the IXP1200 Network Processor Product Brief is available , Intel® WAN/LAN Access Switch Example Design for the Intel® IXP1200 Network Processor Application , fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other
Intel
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Intel IXA SDK Developers Workbench A8797-01 a8796 IXD4521 IXDP1200 IXF440

intel DMA controller Unit

Abstract: 82545EM PHY layer functions in a single, compact component. Packaged in a 21x21mm TFBGA, the Intel 82545EM , : management packets can be routed to or from a management processor. The SMBus port enables implementation of , prefetches up to 64 packet descriptors in a single burst for efficient PCI-bandwidth usage. A 64KB on-chip , processor, such as TCP/UDP/IP checksum calculations and TCP segmentation. Applications The Intel , up to 64 packet descriptors in a single burst Programmable host memory receive buffers (256B to 16KB
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Gigabit Ethernet MAC phy 0103/OC/TS/PDF

intel 82540EM

Abstract: 82540EM Controller integrates Gigabit Ethernet MAC and PHY layer functions in a single, compact component. Packaged , LAN: Management packets can be routed to or from a management processor. The SMBus port enables , Intel 82540EM Gigabit Ethernet Controller prefetches up to 64 packet descriptors in a single burst for , controller also offloads tasks from the host processor, such as TCP/UDP/IP checksum calculations and TCP , Caches up to 64 packet descriptors in a single burst Programmable host memory receive buffers (256B to
Intel
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82551QM 88551ER 82551ER intel 82540EM tfbga NP2103

9216D

Abstract: 16FADC GPT_X41, V2.0 14-5 V1.1, 2005-11 XC164CM Peripheral Units (Vol. 2 of 2) The General Purpose , . . . . . . 4-11 Pipeline Conflicts Using General Purpose Registers . . . . . . . . . . . . . 4-13 , . . . . . . . . . . . . 4-26 Use of General Purpose Registers . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1 The General Purpose Timer Units , . . 17-25 Single Event Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Infineon Technologies
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9216D 16FADC Quanta CT3 block diagram

UBX-G6010

Abstract: UBXG6010 '‰6 single chip GPS receiver, 56 Pin MLF(QFN) u-bloxâ'‰6 baseband processor, 100 pin CVBGA u-bloxâ'‰6 RF front-end IC, 24 pin MLF(QFN) Supplyâ'‰voltages Single voltage supply: 1.8â , u-bloxâ'‰6 single chips and chipsetsâ'‰ GPS UBX-G6010, UBX-G6000/G0010 Product description The UBX-G6010 and UBX-G6000/UBX-G0010 are the newest generation single chip and chipset GPS , RTC Optional RTC Crystal UART USB V2.0 GPIO DDC (l2C compatible) RF Input Matching
u-blox
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UBX-G6000-BA UBXG6010 UBX-G6000 UBX-G6010-SA UBX-G0010-QA G6-HW-09001-A2

NS9360B-0-I155

Abstract: NS9360B-0-C103 NET+ARM Processors · 32-bit, 177, 155, 103 MHz NET+ARM processor · 0.13 µm CMOS process · 10/100Base , -pit processor with rich set of peripherals > 177 MHz ARM9 core (ARM926EJ-S) > Harvard architecture with 8 kB/4 , General Purpose I/O (GPIO) pins > Highly configurable power management > Supported by the comprehensive , NS9360 is the third ARM9 processor in our award-winning family of NET+ARM 32-bit processors. It is , GPIO Hardware Specifications 32-BIT ARM926EJ-S RISC PROCESSOR · · · · · 103, 155, 177 MHz 5
Digi International
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NS9360B-0-C103 NS9360B-0-I155 NS9360B-0-C177 netarm 40 ARM926EJ-S jtag 13-EP C2/1106

SPARTAN-II xc2s200 pq208 block diagram

Abstract: fpga frame buffer vhdl examples 0 Spartan-II 2.5V FPGA Family: Functional Description R DS001-2 (v2.0) September 18, 2000 , . DS001-2 (v2.0) September 18, 2000 Preliminary Product Specification www.xilinx.com 1-800-255-7778 , the I/O banking rules. Module 2 of 4 2 www.xilinx.com 1-800-255-7778 DS001-2 (v2.0 , the external voltage source for correct operation. DS001-2 (v2.0) September 18, 2000 Preliminary , , organized in two similar slices; a single slice is shown in Figure 3. In addition to the four basic LCs
Xilinx
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SPARTAN-II xc2s200 pq208 block diagram fpga frame buffer vhdl examples DS001-1 DS001-3 DS001-4

E10G42BTDA

Abstract: X520-SR2 machines. SR-IOV allows for the partitioning of a PCI function into many virtual interfaces for the purpose , , for example, allows the bandwidth of a single port (function) to be partitioned into smaller slices , (TCO) by providing the ability to route LAN and SAN traffic over a single fabric. Support for Fiber , performance. PCIe v2.0 (5 GT/s) PCIe v2.0 (5 GT/s) support enables customers to take full advantage of 10 GbE by providing a maximum of 20 Gbps bi-directional throughput per port on a single dual port card
Intel
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E10G42BTDA X520-SR2 X520-DA2 E10G41BFLR intel ethernet E10G42BFSR 0609/TAR/OCG/PP/100 322217-001US

q965/q963 drivers

Abstract: GMA3000 Lighting (T&L) helps offload geometry processing-vertex shading, clipping and set up from the processor to the graphics engine. This allows the processor to perform more intensive calculations for , multitasking, delivers higher frame rates and lower processor utilization for high definition (HD) video , enables smooth playback of high definition videos while White Paper freeing up the processor for , (standard, enhanced or high-definition) plus multi-channel audio on a single cable. This interface
Intel
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q965/q963 drivers GMA3000 DVMT 4.0 Intel Q963 INTEL 965 intel hd graphics 2000 X3000

XC167-16

Abstract: free transistor equivalent book User's Manual, V2.0, April 2004 XC167-16 16-Bit Single-Chip Microcontroller with C166SV2 Core , may be endangered. User's Manual, V2.0, April 2004 XC167-16 16-Bit Single-Chip , t h i n k i n g . XC167 Volume 2 (of 2): Peripheral Units Revision History: V2.0 , . . . . . . . 3-35 [1] User's Manual I-1 V2.0, 2004-04 XC167-16 Derivatives Peripheral , . . . . . . . . . . . . . 4-11 [1] Pipeline Conflicts Using General Purpose Registers . . . . . . .
Infineon Technologies
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free transistor equivalent book transistor cross reference book 010B BOSCH CAN

81-BGA

Abstract: bluetooth module pin diagram Port Compatible with AMBA Peripheral Bus v2.0 interface Embedded 256KB(max) program ROM and 32KB SRAM , : Single 3.3V(typical) Power consumption: 30mA(maximum) for normal mode of operation; [TBD]µA for standby , MX99L801 is based on the ARM7TDMI processor. All blocks are connected to the processor through AMBA bus , without real-time software control to reduce the processor MIPS requirements. Bluetooth Voice Codec The , compliant, with one for HCI and the other reserved for system debugging. General Purpose I/Os 16
Macronix International
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81-BGA bluetooth module pin diagram IEEE1149 PM0923 CA95131

XC2VP100

Abstract: XC2VP70 0 R Virtex-II ProTM Platform FPGAs: Introduction and Overview 0 0 DS083-1 (v2.0) June 13 , (based on Mindspeed's SkyRailTM technology) - Up to four IBM® PowerPC ® RISC processor blocks Based on , Transceiver Blocks 4 4 8 8 8 0 or 12(2) 0 or 16(2) PowerPC Processor Blocks 0 1 1 2 2 2 2 2 2 4 18 X 18 , without notice. DS083-1 (v2.0) June 13, 2002 Advance Product Specification www.xilinx.com , multiply/divide unit Thirty-two 32-bit general purpose registers 16 KB two-way set-associative instruction
Xilinx
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XC2VP20 XC2VP70 XC2VP100 XC2VP125 FF1696 DS083-4

parallax infrared sensor

Abstract: human body temperature detection sensor mlx90614 sensors that feature a single pin serial interface for connection to most microcontrollers. The MLX90614 , Multiple modules can be connected to a single I/O pin for serial networking Module can act as a stand , ) v2.0 11/18/2008 Page 1 of 8 Connections and Pin Definitions The BASIC Stamp 2 is used as the example processor in this documentation. The MLX90614 module mounts into a socket terminal or breadboard , (#28040-28042) v2.0 11/18/2008 Page 2 of 8 How MLX90614 Infrared Thermometer Modules Work Using a
Parallax
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parallax infrared sensor human body temperature detection sensor mlx90614 temperature sensor interface with basic stamp mlx90614esf-acf parallax 28042 Thermopile Sensor Circuit SX20AC/SS-G
Abstract: 0 R CoolRunner XPLA3 CPLD DS012 (v2.0) January 10, 2005 0 14 Features â'¢ â , 3.6V) industrial grade 5V tolerant I/O pins Input register set up time of 2.5 ns Single pass logic , owners. All specifications are subject to change without notice. DS012 (v2.0) January 10, 2005 , macrocell for speed critical logic. If wider than a single P-Term logic is required at a macrocell, 47 , (v2.0) January 10, 2005 Preliminary Product Specification R CoolRunner XPLA3 CPLD MC1 MC2 Xilinx
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XCR3032XL XCR3064XL XCR3512XL XC9500XL XCR3384XL TQ144

ARM SC100 7816

Abstract: ISO7816-2 purpose 32-bit processor offers high performance, very low power consumption, and additional features to , processor. It uses a Von Neumann Load/store architecture, this architecture is characterized by a single , Features General · Based on the ARM® SC100TM SecureCoreTM 32-bit RISC Processor · Two , ® High-code-density 16-bit Instruction Set Von Neumann Load/Store Architecture ­ Single 32-bit Data Bus for , With or Without Autoerase 24K Bytes of RAM (2K Bytes shared with AdvX TM crypto processor) 32K Bytes
Atmel
Original
192192CT-USB 6556a inter chip usb AT91SC192192CT-USB ISO7816 ISO7816-3
Abstract: P4080 Multicore Processor in 45 nm technology, is designed to deliver The QorIQ P4080 multicore processor, the high-performance, next-generation networking first product offered in the QorIQ P4 , QorIQ P4080 processor is designed for in the under 30-watt power category. It combined control and , I-Cache Security Fuse Processor Power Management 1024 KB CoreNet Platform Cache Power , processor is well suited for applications Advanced virtualization technology brings a that are highly Freescale Semiconductor
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P4080/P4040/P4081 P4081 P4040 QP4080FS

hpc36003v20

Abstract: hpc16003u20 manipulation, and high speed computation. The HPC devices are complete microcomputers on a single chip. Ali , single byte â'" 16x16 multiply and 32 x 16 divide â'" Eight vectored interrupt sources â'" Four 16 , registers â  52 general purpose I/O lines (memory mapped) â  8k bytes of ROM, 256 bytes of RAM on chip â , B10, B11, B12 and B15 are general purpose Outputs only in this mode. Port B may also be configured via , ) B15: RD Read Output Port I is an 8-bit input port that can be read as general purpose inputs and Is
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hpc36003v20 hpc16003u20 HPC36003V-20 HPC16003V20 HPC46003VF30 HPC36003V30 HPC16083/HPC26083/HPC36083/HPC46083/ 16003/H PC26003/H PC36003/ PC46003 HPC16083

sdio hub

Abstract: , there is a high dependence on the types of modules used and the SPI capability of both the processor , no need to take into account special timing or handshake mechanisms. SDIO v2.0 also calls for the , board. Thus this leads to one evaluation board with a fixed processor but almost infinite possibilities , used by their design teams or for sale. Nevertheless, due to the slower change in processor and main , interfaces on their main processor to support all the different SDIO modules that they would like to have on
Cypress Semiconductor
Original
sdio hub

canton AS 85 SC service manual

Abstract: TRW CAP single chip All system timing internal logic ROM RAM and I O are provided on the chip to produce a cost , when using 20 0 MHz clock 134 ns at 30 0 MHz High code efficiency most instructions are single byte , -bit timer counters with pulse width modulated outputs Four input capture registers 52 general purpose I O , -bit input port that can be used as general purpose digital inputs Port P is a 4-bit output port that can be used as general purpose data or selected to be controlled by timers 4 through 7 in order to
National Semiconductor
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HPC16064 HPC46004 canton AS 85 SC service manual TRW CAP canton AS 105 SC service manual canton AS 65 SC service manual canton AS 60 SC service manual Deutsch relay socket se HPC46064

pc to pc communication using zigbee

Abstract: Raisonance RLink hardware 25) PRO stack ­ Added support for the STM32F10xxx V2.0 firmware library ­ Added STM32F103x HAL APIs , EmberZNet 3.3.1 (software version: 3.3 build 25) PRO stack, for the STM32F10xxx V2.0 firmware library and , applications which show how a single device (sink node) collects data from 2 sensor devices Light and switch , instances of STR71x-9x USB virtual COM. Issue analysis: The PC is able to recognize only a single , uploading the firmware into the SN260 processor. In this case, the utility em2xx_load.exe can be directly
STMicroelectronics
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pc to pc communication using zigbee Raisonance RLink hardware STM32F103RBT6 STM32F103x STM32F10* USB STM32 firmware library RN0017 SNDEV-260 STM32F10 STM32F103

PS key BlueCore4

Abstract: WT11A FEATURES OVERVIEW · Fully Qualified Bluetooth system v2.0 + EDR, CE and FCC · Class 1, range up , is a single chip Bluetooth solution which implements the Bluetooth radio transceiver and also an on , purpose memory required by the Bluetooth stack. 12 2.2.2 Crystal The crystal oscillates at 26MHz , processor PIO4 UART_RTS RXD PIO7 Test interface TX RTS Another device CTS RX UART , the USB section of the Bluetooth v2.0 + EDR specification or alternatively can appear as a set of
Bluegiga Technologies
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WT11A BlueCore BCCMD Commands wt11 development board schematic WT11 BlueGiga pskey_pcm_config32 WT11-A

schematic diagram of fingerprint sensor

Abstract: MF1 plus 80 Microsystems for Biometrics FingerTIPTM FTF 1100 MF1 V2.0 CMOS Chip and System Data Book 3.3 , incurred. Components used in life-support devices or systems must be expressly authorized for such purpose , Description of the SPI Interface 21 4.2.1 EPP/SPI Infineon Technologies 21 3/38 FTF 1100 MF1 V2.0 , Infineon Technologies 4/38 FTF 1100 MF1 V2.0 databook 3.3 (05.00) FingerTIPTM 1 Introduction , design for precautionary measures and attributes. Infineon Technologies 5/38 FTF 1100 MF1 V2.0
Infineon Technologies
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schematic diagram of fingerprint sensor MF1 plus 80 schematic diagram of fingerprint module capacitive fingerprint sensor specification infineon spp at commands interfacing diagram of fingerprint sensor

CSR BLUECORE4 rfcomm firmware

Abstract: OVERVIEW â'¢ Fully Qualified Bluetooth system v2.0 + EDR, CE and FCC â'¢ Class 1, range up to 300 , 26 MHz Crystal WT11 Figure 3: Block Diagram of WT11 2.2.1 BlueCore04 BlueCore4 is a single , buffers used to hold voice/data for each active connection and the general purpose memory required by the , PIO5 UART_CTS Host CTS processor PIO4 UART_RTS RXD PIO7 Test interface TX , implemented can behave as specified in the USB section of the Bluetooth v2.0 + EDR specification or
RF Solutions
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CSR BLUECORE4 rfcomm firmware

ftf1100mf1

Abstract: sensor shield v2.0 Draft Copy for Review Microsystems for Biometrics FingerTIPTM FTF 1100 MF1 V2.0 CMOS Chip and , systems must be expressly authorized for such purpose! Critical components 1) of Infineon Technologies AG , Description of the SPI Interface 4.2.1 EPP/SPI 21 21 22 22 4/38 FTF 1100 MF1 V2.0 databook 3.3 (05.00 , LITERATURE INDEX 38 39 Infineon Technologies 5/38 FTF 1100 MF1 V2.0 databook 3.3 (05.00 , design for precautionary measures and attributes. Infineon Technologies 6/38 FTF 1100 MF1 V2.0
Infineon Technologies
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ftf1100mf1 sensor shield v2.0 fingerprint sensor pcb with circuit schematic diagram of biometric fingerprint resistance fingerprint sensor infineon package databook

C161JI-32FF

Abstract: C161JC-32FF multiple bits from one operand in a single instruction. User's Manual 2-4 V2.0, 2001-01 C161CS , . C161CS/JC/JI Revision History: V2.0, 2001-01 Previous Version: Version 1.0, 1999-05 , Revision History: V2.0, 2001-01 (cont'd) Previous Version: Version 1.0, 1999-05 Page , 's Manual I-1 1-1 1-3 1-5 1-8 V2.0, 2001-01 C161CS/JC/JI Derivatives Table of Contents , . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-1 Single Chip Mode . . . . . . . . . . . .
Infineon Technologies
Original
C161JI-32FF C161JC-32FF C161CS-32FF C161JI-16FF C161J XX55H C161CS-32F/-16F C161JC-32F/-16F C161JI-32F/-16F TXD0-TXD10
Abstract: 06 - 60 www.trinamic.com TMC429+TMC26x-EVAL Board V2.0 / Manual (V2.00 / 2011-AUG-02) Table of , Board V2.0 / Manual (V2.00 / 2011-AUG-02) 1 Life support policy TRINAMIC Motion Control GmbH & Co , TMC429+TMC26x-EVAL Board V2.0 / Manual (V2.00 / 2011-AUG-02) 4 2 Features This evaluation board is for , GmbH & Co. KG TMC429+TMC26x-EVAL Board V2.0 / Manual (V2.00 / 2011-AUG-02) 3 Mechanical and , V2.0 / Manual (V2.00 / 2011-AUG-02) 6 4 Connectors & Keys The TMC429 evaluation board v.1.1 is Trinamic Motion Control
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TMC26 TMC424 2010-NOV-05 2011-MAR-17 TMC260/261/260 2011-MAI-02

XC2300

Abstract: Infineon* XC2300 bootloader Revision History: V2.0, 2007-12 Previous Version(s): V1.0, 2007-06 (XC2000) V0.1, 2007-03, Draft version , document) to: mcdocu.comments@infineon.com User's Manual V2.0, 2007-12 XC2300 Derivatives , 13-1 [1] 14 The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . 22-7 [2] User's Manual L-1 V2.0, 2007-12 XC2300 Derivatives , . . . . . . . . . . . . . . . . . . . . . . 3-18 [1] User's Manual L-2 V2.0, 2007-12
Infineon Technologies
Original
Infineon* XC2300 bootloader C167 Bootstrap SYSCON external RAM C16x Family Instruction Set Manual can bootloader brushless DC motor speed bosch jtag RBUF01SRH RBUF01SRL B158-H9134-X-X-7600

SERVICE MANUAL oki 32 lcd tv

Abstract: 1DC2A HPC devices are complete microcomputers on a single chip. All system timing, internal logic, ROM, RAM , MHz â'" High code efficiencyâ'"most instructions are single byte â'" 16 x 16 multiply and 32 x 16 , purpose I/O lines (memory mapped) â  16k bytes of ROM, 512 bytes of RAM on-chip â  ROMIess version , , B12 and B15 are general purpose outputs only in this mode. Port B may also be configured via a 16 , -bit input port that can be read as general purpose inputs and is also used for the following functions
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OCR Scan
SERVICE MANUAL oki 32 lcd tv 1DC2A hlx crystal USER MANUAL oki 32 lcd tv SERVICE MANUAL oki 23 lcd tv HPC46004V20 PC16064/26064/36064/46064/16004/26004/ D-8080
Abstract: . 71 -2- Publication Release Date: March 11, 2010 Revision: V2.0 14.6 Slave Select Pin , . 137 -3- Publication Release Date: March 11, 2010 Revision: V2.0 N78E059A/N78E055A Data , : V2.0 2. FEATURES  Fully static design 8-bit CMOS microcontroller.  Wide supply voltage of , and 64k bytes Data Memory address space.  Maximum five 8-bit general purpose I/O ports pin-to-pin , with Idle mode and Power Down mode. -5- Publication Release Date: March 11, 2010 Revision: V2.0 nuvoTon
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XC2786-96F

Abstract: XC2700 Revision History: V2.0, 2007-12 Previous Version(s): V1.0, 2007-06 (XC2000) V0.1, 2007-03, Draft version , document) to: mcdocu.comments@infineon.com User's Manual V2.0, 2007-12 XC2700 Derivatives , 13-1 [1] 14 The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . 22-7 [2] User's Manual L-1 V2.0, 2007-12 XC2700 Derivatives , . . . . . . . . . . . . . . . . . . . . . . 3-18 [1] User's Manual L-2 V2.0, 2007-12
Infineon Technologies
Original
XC2786-96F stk 1414 audio amplifier circuit diagram EEPROM 25xxx easy programmer EEPROM 25xxx ic stk 015 E80CH B158-H9136-X-X-7600

xilinx tri mode ethernet TRANSMITTER signal

Abstract: ML505 Video Over IP User Guide UG463 (v2.0) January 20, 2009 R R Disclaimer: Xilinx is , MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL , Guide Revision www.xilinx.com UG463 (v2.0) January 20, 2009 Table of Contents Preface , Video Over IP User Guide UG463 (v2.0) January 20, 2009 Common Registers Definitions . . . . . . . . , Guide UG463 (v2.0) January 20, 2009 www.xilinx.com 4 Offset 0x02: Status Register 2 . . . . .
Xilinx
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xilinx tri mode ethernet TRANSMITTER signal vhdl pid DVB T transport stream processor w20DF w2C65 xilinx vhdl rs232 code

TDFS4500

Abstract: 37C665 (CL-PS7500FE processor clock) OD1 (general purpose open drain I/O) 9 10 IOCLK (CL-PS7500FE I/O system clock OD0 , purpose other than demonstrating functional operation of the CL-PS7500FE. The information contained in , . The company that developed the ARM710 processor core in the CL-PS7500FE. The number of bit transitions , a single location in the exact sequence in which it was written. A type of non-volatile memory. Fast , Europe. Actually stands for Phase Alternation by Line. Single In-Line Memory Module. SIMMs are available
Cirrus Logic
Original
TDFS4500 37C665 La2 D22 PAL 010a peppa 8-LED bar

MHDR1X5

Abstract: JTAG header 7x2 : Blackfin Processor Module powered by Analog Devices single core ADSP-BF533 processor; up to 600MHz, 32MB , Processor Module powered by Analog Devices single core ADSP-BF537 processor; up to 600MHz, 32MB RAM, 4MB , 36.5x31.5mm CM-BF537U: Blackfin Processor Module powered by Analog Devices single core ADSP-BF537 , size of 36.5x31.5mm TCM-BF537: Blackfin Processor Module powered by Analog Devices single core , new Blackfin Processor Module powered by Analog Devices single core ADSP-BF527 processor will be
BLUETECHNIX Mechatronische Systeme
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CM-BF561 MHDR1X5 JTAG header 7x2 JTAG header 7x2 datasheet JTAG header 7x2 datasheet Connector MT48LC16M16a2bg-75it
Abstract: . 72 -2- Publication Release Date: March 11, 2011 Revision: V2.0 14.7 Mode Fault Detection , . 135 -3- Publication Release Date: March 11, 2011 Revision: V2.0 N78E366A Data Sheet 1 , 11, 2011 Revision: V2.0 2. FEATURES  Fully static design 8-bit CMOS microcontroller. ï , and 64k bytes Data Memory address space.  Maximum five 8-bit general purpose I/O ports pin-to-pin , Date: March 11, 2011 Revision: V2.0 N78E366A Data Sheet  Much lower power consumption than nuvoTon
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Abstract: -Bit Performance XC2000 Family / Base Line Userâ'™s Manual V2.0 2009-03 M ic r o co n t ro l l e r s , -Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Base Line Userâ'™s Manual V2.0 , Revision History: V2.0, 2009-03 Previous Version(s): V1.2, 2008-09 (V1.1 skipped) V1.0, 2008-06 Page , configuration table corrected Userâ'™s Manual V2.0, 2009-03 XC2200M Derivatives XC2000 Family / Base Line XC2200M Revision History: V2.0, 2009-03 16-32f, 16-59f GPT timer registers reworked Infineon Technologies
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16/32-B 14REL B158-H9251-G2-X-7600

AB38R

Abstract: tag l9 225 400 0 R Virtex-II ProTM Platform FPGAs: Introduction and Overview 0 0 DS083-1 (v2.0) June 13 , (based on Mindspeed's SkyRailTM technology) - Up to four IBM® PowerPC ® RISC processor blocks Based on , Transceiver Blocks 4 4 8 8 8 0 or 12(2) 0 or 16(2) PowerPC Processor Blocks 0 1 1 2 2 2 2 2 2 4 18 X 18 , without notice. DS083-1 (v2.0) June 13, 2002 Advance Product Specification www.xilinx.com , multiply/divide unit Thirty-two 32-bit general purpose registers 16 KB two-way set-associative instruction
Xilinx
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AB38R tag l9 225 400 BF957

010B

Abstract: C166SV2 (Pre-release) V2.1, 2003-06 V2.0, 2003-03 V1.1, 2002-02 (Draft Manual) V1.0, 2001-04 (Draft Manual) Page , . . . . . . . . . . . . . 4-11 [1] Pipeline Conflicts Using General Purpose Registers . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . 4-26 [1] Use of General Purpose Registers . . . . . . . , Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . 14-1 [2] Timer Block GPT1 . . . . . , [2] Single Event Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-27
Infineon Technologies
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XC161 J1850 sae 1850 vpw

CSR 8510

Abstract: CSR 8510 hardware ! 4.2V tolerant LED driver Single Chip Bluetooth® v1.2 System Production Information Data Sheet for April 2006 General Description Applications BlueCore3-Audio Flash is a single chip , ! Synthesiser ! Physical Interfaces Full speed USB v1.1 (v2.0 compatible) interface , Analogue Single ended receiver input PIO[0]/RXEN A1 Bi-directional with programmable strength
Cambridge Silicon Radio
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BC31A223A CSR 8510 CSR 8510 hardware MDR771F CSR BLUECORE VIRTUAL MACHINE AUTHENTICATION COPROCESSOR 2.0C CSR 8510 bluetooth BC31A223B BC31A223A-

r20 ah16

Abstract: chassis m28 Processor NOR Flash Dual DVB-CI/one CableCARDTM interface MP@ML Dual Channel or MP@HL Single , STD2000 ® Single-Chip Worldwide iDTV Processor DATABRIEF SD/HD Digital Video ID Video , Rev. 2 January 2006 1/11 STD2000 Dual Channel Video Input Processor Analog Video Inputs , Detection Dual Channel High Definition Video Processor Image Processing 24, 25, 30, 50, 60 to , ) Dual Transport Stream Processor Dual Transport Stream Demux DES, DVB and Multi2
STMicroelectronics
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r20 ah16 chassis m28 ac3 downmix decoder AG13 ak27 diode ag26 32K-D

ak25

Abstract: General Purpose IOs ● Low-power mode and wake-up controller Gamma 2D Graphic Processor â , STD2000 ® Single-Chip Worldwide iDTV Processor SD Analog Video HD Video Display , Generator Digital Audio Out DDR SDRAM â  Dual-Channel High Definition Video Processor ● Up ,   Dual DVB-CI and CableCARDâ"¢ interface â  MP@ML Dual Channel or MP@HL Single Channel MPEG-2 Video , without notice. STD2000 Dual Channel Video Input Processor â  Analog Video Inputs ● CVBS, Y
STMicroelectronics
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ak25

xc-2200

Abstract: brushless motor 6236 driver Revision History: V2.0, 2007-12 Previous Version(s): V1.0, 2007-06 (XC2000) V0.1, 2007-03, Draft version , document) to: mcdocu.comments@infineon.com User's Manual V2.0, 2007-12 XC2200 Derivatives , 13-1 [1] 14 The General Purpose Timer Units . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . 22-8 [2] User's Manual L-1 V2.0, 2007-12 XC2200 Derivatives , . . . . . . . . . . . . . . . . . . . . . . 3-18 [1] User's Manual L-2 V2.0, 2007-12
Infineon Technologies
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xc-2200 brushless motor 6236 driver RPR MAC vhdl code infineon can bootloader XC2285-56F EQUIVALENT EBC 6531 B158-H9132-X-X-7600

fft_v5te

Abstract: ARM968EJ-S A Non-Confidential RVDS v2.0 Release January 2004 B Non-Confidential RVDS v2 , purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM , .1 . B-8 Changes between RVDS v2.1 and RVDS v2.0 . B , . Denotes ARM processor signal names. Also used for terms in descriptive lists, where appropriate , directory. Also, many of the examples used in the documentation are contained in a single examples
ARM
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fft_v5te pxa270 user guide PXA270 SC1200 ZSP400 pxa270 reload memory 0255F

QN108

Abstract: CORE8051 Version Advance v0.7 (January 2007) Changes in Current Version (v2.0) In the "Package I/Os: Single , v2.0 ® Actel Fusion Family of Mixed-Signal FPGAs Features and Benefits In-System , Controller (MMC) Low Power Consumption · Single 3.3 V Power Supply with On-Chip 1.5 V Regulator · Sleep , Overview (AFS600) Package I/Os: Single-/Double-Ended (Analog) Fusion Devices AFS090 AFS600 , FG484 and FG256. II v2.0 Actel Fusion Family Mixed-Signal FPGAs Product Ordering Codes
Actel
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QN108 CORE8051 ACTEL FUSION AFS1500
Abstract: Controller XE166 Family / Base Line Userâ'™s Manual V2.0 2009-03 M ic r o co n t ro l l e r s , 16-Bit Single-Chip Real Time Signal Controller XE166 Family / Base Line Userâ'™s Manual V2.0 , XC2200M Revision History: V2.0, 2009-03 Previous Version(s): V1.2, 2008-09 (V1.1 skipped) V1 , Manual V2.0, 2009-03 XE167xM/XE164xM/XE162xM Derivatives XE166 Family / Base Line XC2200M Revision History: V2.0, 2009-03 16-32f, 16-59f GPT timer registers reworked, interrupt control Infineon Technologies
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XE167 M/XE164 M/XE162 B158-H9256-G2-X-7600

chassis m28

Abstract: GFX E6 STD2000 ® Single-Chip Worldwide iDTV Processor DATABRIEF SD/HD Digital Video ID Video , MIPS 16K - I, 32K-D te le so Ob - ct u Dual-Channel High Definition Video Processor , Dual DVB-CI/one CableCARDTM interface MP@ML Dual Channel or MP@HL Single Channel MPEG-2 Video , Processor Digital Video Inputs D1/HD Digital video input (CCIR 601-656 / SMPTE 274M, SMPTE 296M , 32-bit RISC ST40 CPU (266 MHz, 480MIPs) Dual Channel High Definition Video Processor
STMicroelectronics
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GFX E6 Encoder e27 AG29 transport Stream demux ae31 ATSC-A54

XAPP864

Abstract: verilog hdl code for triple modular redundancy XAPP864 (v2.0) April 1, 2010 Summary Xilinx® devices are designed to have an inherently low susceptibility to single event upsets (SEUs). This application note provides a substantial discussion of , and other countries. All other trademarks are the property of their respective owners. XAPP864 (v2.0 , 18.06 57.02 Device XAPP864 (v2.0) April 1, 2010 www.xilinx.com 2 Risk Assessment and , only changes (flips) a single configuration bit. Multi-bit upsets (MBUs) due to a single ionizing
Xilinx
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verilog hdl code for triple modular redundancy xilinx uart verilog code for spartan 3a frame_ecc UG-116 uart verilog testbench RAM SEU

RAS 1210 SUN HOLD

Abstract: sun hold ras 1210 ISA Bus ISA Device ISA D ev ice ISA Device Preliminary V2.0 December 9, 1996 ISA , Address Mode of Pentium CPU Supports the Full 64-bit Pentium Processor data Bus Supports 32-bit PCI , Preliminary V2.0 December 9, 1996 2 Silicon Integrated Systems Corporation SiS5571 Pentium PCI/ISA , Prefetch Buffer(CTPFF) with 8 QW Deep Built-in one 32-bit General Purpose Register Integrated PCI-to-ISA , two 8237 Associated Registers Built-in Two 8259A Interrupt Controllers Preliminary V2.0 December 9
Silicon Integrated Systems
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RAS 1210 SUN HOLD sun hold ras 1210 magnetic switch diagram push botton t85 ha6 IRQ1-15 HA2311 S5571 75/66/60/50MH 256K/512K/1M/2M/4M/16M

Automotive ECU IC

Abstract: -Bit Performance XC2000 Family / Base Line Userâ'™s Manual V2.0 2009-03 M ic r o co n t ro l l e r s , -Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Base Line Userâ'™s Manual V2.0 , Revision History: V2.0, 2009-03 Previous Version(s): V1.2, 2008-09 (V1.1 skipped) V1.0, 2008-06 Page , V2.0, 2009-03 XC27x5X Derivatives XC2000 Family / Base Line XC2200M Revision History: V2.0 , : mcdocu.comments@infineon.com Userâ'™s Manual 5 V2.0, 2009-03 XC27x5X Derivatives XC2000 Family / Base Line
Infineon Technologies
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Automotive ECU IC B158-H9254-G2-X-7600

digital storage oscilloscope

Abstract: TDS6124C Measurements System Includes: Dual Processor System (2.8 GHz Pentium 4 and 583 MHz PowerPC), High , systems offer multiple trigger types only on a single event (A Event), with delayed trigger (B Event , diagrams at data rates to beyond 6.25 Gb/s. Software clock recovery to 10 Gb/s. TDSJIT3 v2.0 Jitter , oscilloscopes: Fast, PCI bus speed communication between the data acquisition processor and the Microsoft , or less Delta Time Accuracy 635 fsRMS over
Tektronix
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TDS6000 TDS6154C TDS6124C TDS6804B TDS6604B digital storage oscilloscope Tektronix 336 HDB3 matlab TDS6000C

example ml605

Abstract: XAPP1052 Performance Demonstration Reference Design for the Xilinx Endpoint PCI Express® Solutions XAPP1052 (v2.0 , transferred to a peripheral device over the PCI Express link. A system DMA would reside off the processor bus , the data, the BMD relieves the processor and allows other processing activities to occur while the , countries. All other trademarks are the property of their respective owners. XAPP1052 (v2.0) November 18 , . XAPP1052 (v2.0) November 18, 2009 www.xilinx.com 2 Exploring the DMA Performance Demo Hierarchy
Xilinx
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asus motherboard virtex-6 ML605 user guide FPGA based dma controller using vhdl ML605 UCF FILE xapp1052 document ML555

xpressrom

Abstract: ADC12138 . The WebPAD SP3GX01 system is based on the Geode GXLV processor and the Geode CS5530 I/O companion , miscellaneous system specifications. Geode GXLV Processor/CS5530 Based Design Together these devices provide , Interface q 40 general purpose I/Os q Programmable serial UART q 1 16-bit idle timer q 3 16-bit timer , technology based virtual audio support q AC97 V2.0 compliant codec support q National Semiconductor LM4546 , TI PCI1211 PC Card Controller q Support for single Type II PC card q Supports PCMCIA and CardBus
National Semiconductor
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xpressrom ADC12138 CS9210 ac97 Microphone mtbf COP8SGE7

VFPv3

Abstract: LEB128 licence to use this specification (ARM contract reference LEC-ELA-00081 V2.0). PLEASE READ THEM CAREFULLY , core registers The general purpose registers visible in the ARM architecture's programmer's model , ) BETWEEN YOU (AN INDIVIDUAL OR SINGLE ENTITY WHO IS RECEIVING THIS DOCUMENT DIRECTLY FROM ARM LIMITED , software or hardware; applications, operating system or driver software; RISC architecture; processor , Specification solely for the purpose of developing, having developed, manufacturing, having manufactured
-
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ARM946E-S VFPv3 LEB128 VFPv3 instruction set VFPv3 NEON ARM coprocessor ARM FPA ARM1156
Abstract: -Bit Performance XC2000 Family / Base Line Userâ'™s Manual V2.0 2009-03 M ic r o co n t ro l l e r s , -Bit Single-Chip Microcontroller with 32-Bit Performance XC2000 Family / Base Line Userâ'™s Manual V2.0 , Revision History: V2.0, 2009-03 Previous Version(s): V1.2, 2008-09 (V1.1 skipped) V1.0, 2008-06 Page , V2.0, 2009-03 XC2300A Derivatives XC2000 Family / Base Line XC2200M Revision History: V2.0 , : mcdocu.comments@infineon.com Userâ'™s Manual 5 V2.0, 2009-03 XC2300A Derivatives XC2000 Family / Base Line Infineon Technologies
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B158-H9252-G2-X-7600

vhdl code for lvds driver

Abstract: dual lvds vhdl 0 R VirtexTM-E 1.8 V Field Programmable Gate Arrays 0 0 DS022-2 (v2.0) April 2, 2001 , subject to change without notice. DS022-2 (v2.0) April 2, 2001 Preliminary Product Specification , www.xilinx.com 1-800-255-7778 DS022-2 (v2.0) April 2, 2001 Preliminary Product Specification R , shows a more detailed view of a single slice. In addition to the four basic LCs, the Virtex-E CLB , applications such as Digital Signal Processing. DS022-2 (v2.0) April 2, 2001 Preliminary Product
Xilinx
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vhdl code for lvds driver dual lvds vhdl IQ GENERATOR CODE WITH VHDL TSHCKO32 FG860 XCV1000E XCV2000E XCV400E XCV600E

TT 2222 Horizontal Output Transistor pins out

Abstract: transistor tt 2222 0 VirtexTM-E 1.8 V Extended Memory Field Programmable Gate Arrays R DS025-2 (v2.0 , . DS025-2 (v2.0) November 16, 2001 www.xilinx.com 1-800-255-7778 Module 2 of 4 1 VirtexTM-E , combined within a given bank. www.xilinx.com 1-800-255-7778 DS025-2 (v2.0) November 16, 2001 R , the I/O pins in the bank assume this role. DS025-2 (v2.0) November 16, 2001 Within a bank , similar slices, as shown in Figure 4. Figure 5 shows a more detailed view of a single slice
Xilinx
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XCV405E TT 2222 Horizontal Output Transistor pins out transistor tt 2222 TT 2222 Horizontal Output voltage TT 2222 verilog pci zip X13307 DS025-1 DS025-3 DS025-4

UL41

Abstract: ARM cortex A9 neon SIMD Non-Confidential Release 2.0.1 for RVDS v2.0 January 2004 D Non-Confidential Release 2.1 for RVDS v2 , purpose, are excluded. This document is intended only to assist the reader in the use of the product. ARM , .1 and RVCT v2.0 . Differences between RVCT v2.0 and RVCT v1 , . Denotes ARM processor signal names. Also used for terms in descriptive lists, where appropriate , , you can access them from one of the following: · a single PDF file: install_directory
ARM
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UL41 ARM cortex A9 neon SIMD ARM cortex A9 neon ARM cpu ARMv6 ARMv7 0202H
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