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SN74LS245N3 Texas Instruments Octal bus transceivers 20-PDIP 0 to 70
SN74LS245DBRE4 Texas Instruments Octal bus transceivers 20-SSOP 0 to 70
SN74LS245NSRG4 Texas Instruments LS SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO20, GREEN, PLASTIC, SOP-20
SN74LS245NSRE4 Texas Instruments Octal bus transceivers 20-SO 0 to 70
SN74LS245DBRG4 Texas Instruments Octal bus transceivers 20-SSOP 0 to 70
SN74LS245DWG4 Texas Instruments Octal bus transceivers 20-SOIC 0 to 70

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uses of 74ls245 to speed up buses

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: software permits you to specify up to 127 additional ports of 8 I/O modules each. Total capacity can thus , - both now, and in the future. Using up to a 24-slot STD card cage, you can add a large menu of widely , addition to the 16 modules controlled by the VSC-31 card. Software, in turn, permits specification of up to , VSC card allows you to control and monitor key functions in all phases of your operation. This is , Relatively slower data speed. (However, high quantities of data are not commonly required for industrial -
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gordos relays ziatech Gunther - Reed Relays intel 74LS244 8031 Intel Microprocessor grigsby VSC-311 RM-65 BP002
Abstract: interlaced input and interlaced or non interlaced output; programmable sync polarity Supports up to 4MB of , supports up to 4MB of memory without an external decoder. T1/T2 Control/Interface This functional block , keying and up to 16.7 million displayable colors. VideoView is the new standard for high quality, cost , , RGB Camera, or one of two frame buffer images. It can then be output to a VGA monitor, TV monitor , which can be connected to either AT bus signals or MCA bus signals. The function of the pins is -
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live video mixer circuit diagram vga camera pinout S0Q28 MDQ19-MDQ18 philips 107 crt monitor vga connector trident micro 65BSC
Abstract: set ting bit 6 of the TXCR register to 0. The external hybrid circuit uses two operational , PLCC. The 68 pin package allows the controller to access external ROM of up to 32K bytes and exter nal RAM of up to 16K bytes. This allows users to customize their own software, and provides a means for , to compensate for a far end DTE being up to 2.3% over speed. The transmitter Async/Sync always , The SCI 1054 is a complete2400 bps, 5V only modem IC including a Sendfax capability up to 9600 bps -
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SC11054CN ibm t30 laptop schematic diagram 74LS04FC sc11011 SC22201 QPSK qam trans Modulator block diagram SC11054 SC11011 SC11021 SC11061 SC11074 SC11075
Abstract: the'S700's ou tput structure, this part dike the 'S730/1/4i can drive highly capacitative loads, of say up to , e outputs to rescue designs w ith overloaded buses, S c h m itt-trig g e r inputs to likew ise , dynamic-MOS address buses, and so forth. Today the dem ands are to re duce com p o n e n t costs and system , " part. The approach is to look for com m on configurations o f pairs of 8 -b it parts, and im plem ent , levels of integration, due either to their parallel data structure or to the electrical properties of -
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S730T 63S081 74S161 ELS546 LS547 OSRAM ICM 10
Abstract: bit 6 of the TXCR register to 0. The external hybrid circu it uses two operational amplifiers, one in , interfaced directly to an IBM PC bus, but use of a 74LS245 buffer is suggested. The only external parts may , or 11-bit) characters to compensate for a far end DTE being up to 23% over speed. The transmitter , transmitter consisting of - Async to Sync converter - Scrambler - Data encoder - 75% square root o f raised , bit is deleted. The output of the async/ sync converter is applied to the scrambler. The scrambler is -
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SC11026CN dar PLUS transformer sc11026 QPSK telephone modem schematic Pulse Transformer - PPT JIS F 7805 tolerance SC11006 SCU026 28-PIN SC11026 11026C
Abstract: phase coherence. The output of the FSK modulator is applied to the appropriate filter when the low speed , Async to sync converter - Scrambler - Data encoder - 75% square root of raised cosine pulse shaper - , timing recovery circuit (sampling clock of 600 Hz) - FSK demodulator - Sync to Async converter · 8 , of 2400/1200 Hz ± 0.01% derived from the master clock oscillator. To compensate for the input and , output data rate, a stop bit is deleted. The output of the async/sync convertor is applied to the -
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scr FIR 3D 41 intel 8096 instruction set free of intel 8096 microcontroller 8250B uart Quadrature Hybrid SC22102-1 VL7C224A VL7C225 VL7C235 VL7C245 VL7C225/235/245 LB02J-
Abstract: controller to access external ROM of up to 32K bytes and exter­ nal RAM of up to 16K bytes. This allows , The SCI 1054 is a complete 2400 bps, 5V only modem IC including a Sendfax capability up to 9600 bps , ): ⡠Full transmitter consisting of - Async to Sync converter - Scrambler - Data encoder - 75 , . The output of the async/ sync converter is applied to the scrambler. The scrambler is a 17 , quad/dibit that is applied to the QAM /QPSK modulator. The pur­ pose of the scrambler is to random -
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82c50b SC11054CV RS-232 SC11091 DB25P RS-232C 74LS04
Abstract: expansion bus use this line to speed up accesses. It requires a 3300 pull-up resistor. 52 IOCHRDY I Active , be used to force a refresh cycle from an I/O device. An external pull up of 6200 is required. 9 , emulation of lower speed IO channels to maintain compatibility with AT or PC/XT IO adapters and memory cards , support correct AT bus timing â  1MB to 16MB of DRAM memory support â  A complete PC AT requires only , compatible integrated solution. The flexible architecture of the CHIPSet allows it to be used in any ¡APX386 -
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82C301 82A304 82A305 P82C301 P82C302 intel 82C301 CS8232 CS8232-16 82c306 t435 crystal Q0Q12S5 82C302 82A303
Abstract: 82C480 provides up to 2 times the performance of the IBM 8514/A hardware. Projected performance for major , monitor with a resolution of up to 2560x2048 and supporting video rates of up to 300 MHz Line Draw Line , frequency is selected to match the speed of the RAMs used: MCLK VRAM Speed 25 MHz 150 ns 32 MHz 120 ns , Video Clock Select. If BLANK/=0 (blank active), used to select one of up to eight frequencies using , support for up to 16 million colors (Autoconfigurable for 6-bit or 8-bit RAMDACs) Resolutions supported -
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82B484 31DF DIODE IBM motherboard schematics 478 LM339 APPLICATIONS 15-13 pin vga cable connection ibm 478 motherboard Hsync Vsync VGA 8514/A-COMPATIBLE 160-P LM339 3L6IL244
Abstract: hybrid must be turned off by set ting bit 6 of the TXCR register to 0. The external hybrid circuit uses , The SC11026 includes: Full transmitter consisting of - Async to Sync converter - Scrambler - Data , clock of 600 Hz) - FSK demodulator - Tone detector - Sync to Async converter 8-bit analog to digital , output of the async/ sync converter is applied to the scrambler. The scrambler is a 17-bit shift regis , applied to the Q A M /Q PSK modulator. The pur pose of the scrambler is to random ize data so that the -
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79L05 VR 120 varistor reco relay microtran t9311 Lm324 as high pass filter GL 7805 SC11026CV SC11026CQ SC11039 78L05 MF/35V 79L05
Abstract: applied to the appro­ priate filter when the low speed mode of the operation is selected. The filter , to compensate for a far end DTE being up to 2.3% over speed. The transmitter Async/Sync always , * It is up to the user to make sure that the expected tone falls within the passband of the filter. If , C 11024 MODEM The SC11026 includes: ⡠Full transm itter consisting of - Async to Sync converter , the first fou r/tw o stages of the shift register form the q u ad /d ib it that is applied to the Q -
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Abstract: ROMless version of the SC I 1019 & 20. It isavailable in a 68 pin PLCC and operates with up to 32k , to compensate for a far end DTE being up to 2.3% over speed. The transmitter Async/Sync always , storage of configuration settings and phone numbers. B L O C K DIAGRAM NO TE: NU M BERS N EXT TO , consisting of - Async to Sync converter - Scram bler - Data encoder - 75% sq u a re root o f raised , filters - Baud tim ing recovery circuit (sam pling clock of 600 Hz) - FSK demodulator - Sync to Async -
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SC11024 SC11022 SC11024CV 11024CN MAB-MA10 MA12-MA13
Abstract: FSK modulator is applied to the appro priate filter when the low speed mode of the operation is , consisting of - Async to Sync converter - Scrambler - Data encoder -75% square root of raised cosine pulse , timing recovery circuit (sampling clock of 600 Hz) - FSK demodulator - Sync to Async converter 8 , output of the async/ sync converter is applied to the scrambler. The scrambler is a 17-bit shift regis , exclusive OR'd with the input data. The resultant data is applied to the D input of the shift register -
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SC11006CV sc11006cn SC11019CN carrier recovery PSK 1800 Hz EM-188 ic lm324 st make SC11019 SC11006CN 16C450 MA8-MA10
Abstract: -T Transceiver. Transmit Packet Format Each Packet to be transmitted consists of a four byte header and up , up the rest of the system. Bytes 1 and 2, called the Next Packet Pointer, point to the location , bus cycle to support 16-bit, 12Mhz ISA bus architecture. s Uses Fewer Support Chips - Lower Systems Cost - Higher Reliability s Manages 64K bytes of Local Packet Buffer. - Connects to RAS/CAS , Transmit and Receive Error Handling. - Automatic Padding of transmit packets to 64 bytes minimum packet Seeq Technology
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80C04A 80C04 10BASE5 10BASE2 DRAM 4464 tms 4464 4464 dram 74LS45 NQ80C04A 10BASE-T MD400121/B
Abstract: bit 6 of the TXCR register to 0. The external hybrid circuit uses two operational amplifiers, one in , consisting of - Async to Sync converter - Scrambler - Data encoder - 75% square root of raised cosine pulse , filters - Baud timing recovery circuit (sampling clock of 600 Hz) - FSK dem odulator - Sync to Async , stop b it is deleted. The output of the async/ sync converter is applied to the scrambler. The , quad/dibit that is applied to the QAM/QPSK modulator. The pur pose of the scrambler is to random ize -
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dts master audio DL 1200 SC11020CV SC11021CV 74LS04W temperature controller using 8096 PARADE Lot Code SC11020 RS232 AD0-A07
Abstract: in the active window to get the pop up menu.The title bar of the active window indicates the , included to provide statutory protection in the event of unauthorized or unintentional public disclosure , in Innoveda's Internet notification system called Innovate to receive notification of late-breaking , message to: innovate@innoveda.com Include the words subscribe eProduct Designer in the body of the e-mail , launched, click here to invoke it. Once you set up your project, eProduct Designer automatically creates Innoveda
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CI 74LS00 CI 74LS148
Abstract: off by set ting bit 6 of the TXCR register to 0. The external hybrid circuit uses two operational , that easily con nects to the SC22201 (128 by 8) EE memory for perm anent storage of configuration , includes: Full transm itter consisting of - Async to Sync converter - Scrambler - Data encoder - 75% sq u , of 2400/1200 Hz ±0.01% derived from the master clockoscillator. To compensate for the input and , stages of the shift register form the q u ad /d ib it that is applied to the QAM/QPSK modulator. The pur -
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11024C 2764 z SC110
Abstract: to the appro priate filter w hen the low speed m ode of the operation is selected. The filter section , off by set ting bit 6 of the TXCR register to 0. The external hybrid circuit uses two operational , to compensate for a far end DTE being up to 2.3% over speed. The transmitter Async/Sync always , easily connects to the SC22201 (128 by 8) EE m em ory for perm anent storage of configuration settings , 1024 indudes: Full transm itter consisting of - Async to Sync converter - Scrambler - Data encoder - -
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7805 sct processor AT550 74LS04N SC11020CN ibm microprocessor g5 system 390 connecting diagram for ic 74LS30 B242010 F/35V
Abstract: . The 68-pin version is capable of addressing up CONNECTION DIAGRAMS U " KDV [ T SOUT . S vcci ¡7 , WR IOO SHE D fiEMgQio d o p i n g 7T3 s sc to 24k bytes of external memory. This MAC is similar to, and pin compatible with, th e S C llO ll. The major differences are the addition of , Three of the four I / O pins on the specified models of the internal ROMed MAC are programmed to set the , control of GIO (page 16). The internal ROM uses these pins as follows: 101 102 103 Serial E2PROM D1 -
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STR 11006 intel 8096 ADF70 NYP196-18 electrical characteristics of 8096 24201Q SC11023 44-PIN DB-25
Abstract: 6 · Any interlaced or non-interlaced monitor with a resolution of up to 2560x2048 and supporting video rates of up to 300 MHz LINE DRAW Line draw functions (straight lines only) are handled in , to match the speed of the RAMs used: MCLK 25 MHz 32 MHz 40 MHz 88 NCLK In High , High High High Video Clock Select. If BLANK/=0 (blank active), used to select one of up to eight , , or disclosure by the Government is subject to restrictions set forth in subparagraph (c)(1)(ii) of -
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BSS0001 ramdac 8514 BT475 d04 diode Marking s4 S3 TRIO jumper S3 TRIO 64 82C480/ CHIPS/230 CHIPS/250 CHIPS/280 CHIPS/450
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