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PC16550DN/NOPB Texas Instruments Universal Asynchronous Receiver/Transmitter with FIFOs 40-PDIP 0 to 70 visit Texas Instruments Buy
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PC16550DN Texas Instruments Universal Asynchronous Receiver/Transmitter with FIFOs 40-PDIP 0 to 70 visit Texas Instruments

uart+16550

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 0 OPB 16550 UART (v1.00d) DS430 December 2, 2005 0 Product Specification 0 Introduction LogiCORETM Facts This document provides the specification for the OPB 16550 UART (Universal Asynchronous Receiver/Transmitter) Intellectual Property (IP). Core Specifics The OPB 16550 UART , the OPB 16550 UART Point Design implementation are highlighted and explained in Specification , register compatible with all standard 16450 and 16550 UARTs Design File Formats Product Xilinx
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PC16550D uart16550 16550 uart national 16550 uart UART-16550 16550 Cr2026 CR202609
Abstract: 0 XPS 16550 UART (v3.00a) DS577 September 16, 2009 0 Product Specification 0 Introduction LogiCORETM Facts This document provides the specification for the XPS 16550 UART (Universal , Version of Core The XPS 16550 UART described in this document has been incorporating features , specification. Differences between the National Semiconductor PC16550D and the XPS 16550 UART are highlighted , standard 16450 and 16550 UARTs Special Features N/A Implements all standard serial interface Xilinx
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XC6SLX16-CSG324 XC6SLX16CSG324 uart 16550 S3ADSP3400 uart fpga PLBV46
Abstract: 0 XPS 16550 UART (v1.00a) DS577 April 20, 2007 0 Product Specification 0 Introduction LogiCORETM Facts This document provides the specification for the XPS 16550 UART (Universal Asynchronous Receiver/Transmitter) Intellectual Property (IP). The XPS 16550 UART described in , Semiconductor PC16550D and the XPS 16550 UART are highlighted in Specification Exceptions section. Core , with all standard 16450 and 16550 UARTs · Implements all standard serial interface protocols Xilinx
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XPS 16550 UART v1.00a 0x1008 16450 UART National Semiconductor PC16550D UART 16550 uart timing XC4VLX40-FF1148 128-B
Abstract: 0 PLB 16550 UART (v1.00c) DS431 (v1.0.1) November 25, 2003 0 0 Product Overview , www.xilinx.com 1-800-255-7778 1 PLB 16550 UART (v1.00c) UART Background The PLB 16550 performs , characters received from a modem or microprocessor peripheral. The PLB 16550 is capable of transmitting and , 16550 can transmit and receive independently. The device can be configured and it's status monitored via the internal register set. The PLB 16550 is capable of signaling receiver, transmitter and modem National Semiconductor
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UART using VHDL National Semiconductor 16550 UART baud rate generator vhdl
Abstract: LogiCORE IP AXI UART 16550 (v1.01a) DS748 July 25, 2012 Product Specification Introduction The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to the AMBA® (Advance , AXI UART 16550 described in this document incorporates features described in the National , National Semiconductor PC16550D and the AXI UART 16550 data sheet are highlighted in the Specification , 16450 and 16550 UARTs Supports default core configuration for 9600 baud, 8 bits data length, 1 stop bit Xilinx
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HOLDING XC7K410TFFG676-3 TM-7000
Abstract: INDUSTRY STANDARD 16550 UART Author: PY 1.0 INTRODUCTION This application note describes the major differences between Exar's XR16L580 and the industry standard 16550 UART (referred to as "16550" in this , -TQFP) · The XR16L580 and 16550 are both available in the 48-pin TQFP package. Additionally, the 16550 can , pin-to-pin compatible with the industry standard 16550, but some legacy signals are not available ("No , Power-Save feature is perfect for battery operated designs. These two pins are `No Connects' in the 16550 Exar
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XR16L580IM TL16C550CPT TL16C550CPFB intel 16550 op134 DAN139 48-TQFP
Abstract: LogiCORE IP AXI UART 16550 (v1.01a) DS748 June 22, 2011 Product Specification Introduction LogiCORE IP Facts Table The AXI Universal Asynchronous Receiver Transmitter (UART) 16550 connects to , Interfaces AXI4-Lite Resources2, 3, 4 Block RAMs LUTs The AXI UART 16550 described in this , PC16550D and the AXI UART 16550 data sheet are highlighted in the Specification Exceptions section , and 16550 UARTs Design Entry Tools · Supports default core configuration for 9600 baud, 8 Xilinx
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AMBA AXI4 XC6VLX75T-FF784 uart vhdl fpga XC7V855T V6 6D XC7K410T
Abstract: CONTROLLERS FEATURES s UART 16550 16550 I/O 24 24 Speed (MHz) 33 20 Fully Static Z180TM , /Generator 16550 Compatible MIMIC Interface ­ 16 mA MIMIC Output Drive Capability Notes , enhanced Z8S180 microprocessor, a 16550 MIMIC with increased MIMIC drive capability for direct connection , be maintained with the Z80189's ability to mimic the 16550 UART chip. The Z80180 core is the intelligent controller between the data pump and 16550 MIMIC interface when used in internal applications ZiLOG
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Z8L189 IBM PC Connection circuit diagram Z180 S180 MIMIC COM PORT Z80189/Z8L189 100-P
Abstract: following wording: "UARTs for the 16550 are enabled by" to "FIFOs for the 16550 are enabled by." In the , RC32365 provides 1 UART which is designed to be compatible wit h both the 16450 and the 16550. The 16550 is identical to the 16450 except that the 16550 provides a 16 byte FIFO on both receive and transmit sid es. FIFOs for the 16550 are enabled by setting bit 0 of the Buffer Control Register, BCR[0]. , the board design ­ Polled mode. The RC32365 UART behaves in compliance with the 16550 specifications Integrated Device Technology
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16550 initialization C32365 DMA11S
Abstract: operation and is backward compatible with the 16550 and 16450 The operational modes are UART Sharp-IR IrDA , the 16550 UART the PC87108 provides a special fallback mechanism that automatically switches the device to 16550 compatibility mode when the standard baud generator divisor registers are accessed The , Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Fully compatible with 16550 and , to 16550 compatibility mode IrDA modes pipelining Selectable 16 or 32 level FIFOs Multiple optical National Semiconductor
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C1996 INFRARED REMOTE CONTROL decoder of 16450 UART
Abstract: Eureka Technology EP600 UART Product Summary FEATURES · Functionally compatible with 16550. · Supports Character (16450) and FIFO (16550) mode operations. · Designed optimized for ASIC and PLD implementations. · Synchronous design with edge triggered flip-flops based on system clock input. · 16-byte FIFO for transmitter and receiver reduces the number of interrupt to the CPU. · Holding , character mode (16450) and FIFO mode (16550) of operations. Default operation is character mode so that Eureka Technology
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uart 16450 timing design of UART 16450 EP600 programming
Abstract: compatible with the 16550 and 16450. The operational modes are: UART, Sharp-IR, IrOA 1.0 SIR, IrDA 1.1 MIR , can be selected as the base address. In order to support existing legacy software using the 16550 UART, the PC87108 provides a special fallback mechanism that automatically switches the device to 16550 , Fully compatible with 16550 and 16450 devices Enhanced UART mode Sharp-IR with selectable internal or , deferral Automatic fallback to 16550 compatibility mode IrDA modes pipelining Selectable 16 or 32 level -
OCR Scan
IR5L
Abstract: a few simple steps. The PCI DUAL RS232 TWIN 9 card is fully Plug and Play compatible! THE 16550 UART 16550 UARTs provide a 16 byte input and 16 byte output FIFO hardware buffer for each serial port , ensures maximum performance! n n n 2 RS232 Serial Ports. Optional parallel printer port. 16550 , , Windows 3.1 & DOS. n Fully PCI 2.1 compliant. ORDER DESCRIPTION PCI DUAL RS232 TWIN 9(16550 UART -
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CC-257
Abstract: sharing, advanced UART support and serial diagnostic utilities. Communications Chip: 16550 (16650 , OMG-COMM232-PCI includes the 16550 UART, providing a 16 byte FIFO to keep your datacom applications running , DOS and Windows 3.1x/95/NT Communications ß 16550 Buffered UART std/16650 or 16750 Buffered UART Omega Engineering
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16650 uart RS-232 95/98/M OMG-COMM232-PCI-SS OMG-COMM232-PCI-SX
Abstract: . The OMG-ULTRACOMM422-PCI includes the 16550 UART, providing D4 IEEE-488 CONTROLLERS AND , Designed to Maximize DOS and Windows 3.1x/95/98/NT Communications ß 16550 Buffered UART std/Full , Communications Chip: 16550 Number of Ports: four RS-485/422 Max. Data Rate: 460.8K bps Max. Data Distance: up Omega Engineering
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RS-422/485 RS-485 RS422/485 DB-37
Abstract: the 16550. The 16550 is identical to the 16450 except that the 16550 provides a 16 byte FIFO on both receive and transmit sides. UARTs for the 16550 are enabled by setting bit 0 of the Buffer Control , UARTs behave in compliance with the 16550 specifications in the interrupt driven mode. 5&5& 'HVLJQ , 16550 to enable the 16 bytes of FIFOs to be filled (transmit) or emptied (receive) in a single execution , the next byte to the UART or the FIFO. The 16550 specifications state that LSR[5] can be guaranteed to Integrated Device Technology
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s334 ejtag RC32334/RC32332 RC32332
Abstract: memory spaces, a PCMCIA slave interface with a UART block that emulates the UART 16550, and a fully , Support Includes: -HDLC -UART -UART 16550 Emulation -BISYNC -Totally Transparent Mode - , Modes - Support for Direct Access by PCMCIA Host to 68000 Bus for Fast Data Transfers · 16550 Emulation Block - Complete H/W and S/W Emulation of the 16550 UART - DMA Support for the 68000 Side of the 16550 Emulation Controller · Low Power Control - On Chip PLL Can Be Used with 32-KHz Crystal Motorola
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MC68356 MC68302 DSP56002 motorola 68000 architecture Motorola 56002 designing with the MC68008 motorola 68000 pin diagram motorola 68000 block diagram MC68356/D CPM68000
Abstract: designed to be compatible with both the 16450 and the 16550. The 16550 is identical to the 16450 except that the 16550 provides a 16 byte FIFO on both receive and transmit sides. UARTs for the 16550 are , design x Polled mode. The RC32334 UARTs behave in compliance with the 16550 specifications in , RZIOD+ GQD HW\% FIFOs were introduced in the 16550 to enable the 16 bytes of FIFOs to be filled , 16550 specifications state that LSR[5] can be guaranteed to be 1 when the Transmit Holding Register -
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Abstract: Features 16450/16550 Compatible 16 byte transmit FIFO IPCUART-APB-APB 16450/16550 Compatible UART Core 16 byte receive FIFO Modem control Programmable baud rate gene- rator Prioritized interrupt system Line status and error checking (parity and framing errors) 2 Direct Memory Access Modes Loopback Mode The IPC-UART-APB is a 16450/16550 compatible Universal Asynchronous Receiver/Transmitter (UART). The IPC-UART-APB contains a baud rate generator that can be configured to Cast
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16550 uart timing diagram uart verilog testbench AMBA APB UART datasheet of 16450 UART UART testbench of a transmitter in verilog
Abstract: the 16550. The 16550 is identical to the 16450 except that the 16550 provides a 16 byte FIFO on both receive and transmit sides. UARTs for the 16550 are enabled by setting bit 0 of the Buffer Control , UARTs behave in compliance with the 16550 specifications in the interrupt driven mode. RC32334 , introduced in the 16550 to enable the 16 bytes of FIFOs to be filled (transmit) or emptied (receive) in a , the software to write the next byte to the UART or the FIFO. The 16550 specifications state that LSR[5 Integrated Device Technology
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16550 16 byte buffer IDT RC32334 Users Manual
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