PD98501 VR4120A S14767E IEEE802 PD98501N7-F6 S14828EJ5V0DS00 S14828EJ5V0DS - Datasheet Archive

 

Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

 

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT µPD98501 PD98501 NETWORK CONTROLLER The µPD98501 PD98501 is a high performance controller which can perform the protocol conversion between IP packets and ATM cells, which is especially suitable for ADSL modem. It includes high performance MIPS based 64-bit RISC processor VR4120A VR4120A CPU core, ATM cell processor, Ethernet controller, USB controller block, UTOPIA2 interface and SDRAM interface. Detailed function descriptions are provided in the following user's manual. Be sure to read the manual before designing. µPD98501 PD98501 User's Manual: S14767E S14767E FEATURES · Includes high performance MIPS based 64-bit RISC processor VR4120A VR4120A · Can perform RTOS and network middleware (M/W) on the chip · Includes interface for PROM and flash ROM used for storing boot program · Includes 32-bit RISC controller, as ATM cell processor · Software SAR processing by RISC controller affords flexibility for specification update · Supports CBR/VBR/UBR service classes · Includes 2-channel 10/100 Mbps Ethernet controllers compliant to IEEE802 IEEE802.3, IEEE802 IEEE802.3u and IEEE802 IEEE802.3x · Can directly connect external Ethernet PHY device through 3.3-V MII interface · Includes USB full speed function controller compliant to USB specification 1.1 · Supports operation conforming to the USB Communication Device Class Specification · Can directly connect 64M-bit and 128M-bit SDRAM as external memory · Includes 8-bit 33 MHz UTOPIA level 2 interface compliant to ATM Forum af-phy-0039 · Includes boundary scan function (JTAG) compliant to IEEE 1149.1 · Includes Micro Wire interface · Includes 2-channel general purpose timers · Using advanced CMOS technology · Power supply voltage: 3.3 V (I/O), 2.5 V (Core) · Package 352-pin T-BGA ORDERING INFORMATION Part Number µPD98501N7-F6 PD98501N7-F6 Package 352-pin tape BGA (heat spreader type) (35 × 35) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14828EJ5V0DS00 S14828EJ5V0DS00 (5th edition) Date Published August 2002 NS CP (K) Printed in Japan The mark shows major revised points. © 2000 µPD98501 PD98501 BLOCK DIAGRAM µPD98501 PD98501 USB VR4120A VR4120A RISC Processor Core Full-speed USB Controller PROM / Flash SDRAM Ethernet Controller #1, #2 System Controller IBUS 3.3-V MII 33-MHz UTOPIA-2 ATM Cell Processor PHY Management JTAG 2 JTAG Controller Clock Control Unit Data Sheet S14828EJ5V0DS S14828EJ5V0DS RS-232C/Micro Wire Parallel Port µPD98501 PD98501 PIN CONFIGURATION (Bottom View) · 352-pin tape BGA (head spreader type) (35 × 35) µPD98501N7-F6 PD98501N7-F6 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A Data Sheet S14828EJ5V0DS S14828EJ5V0DS 3 µPD98501 PD98501 Pin Name Pin No. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 4 Pin Name IC-Open IVDD GND PUAGND GND EVDD EVDD IC-PUpR IC-Open IVDD IVDD EVDD UDRD1 IVDD UDRAD3 UDRAD0 UDTE_B UDTAD3 GND UDTD5 UDTCLK UMRST_B UDTD0 UMINT_B UMAD11 UMAD11 UMMD IC-PDn IC-Open IC-Open PUDVD PUDGND PUSTBY GND EVDD IC-Open GND UDRSC UDRD5 UDRD2 GND UDRAD2 IVDD UDTSC UDTAD2 UDTAD0 EVDD UDTD2 UDTD1 UMSL_B UMWR_B UMAD9 UMAD8 Pin No. C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 Pin Name SCLK CLKSL IC-PDn PUMD_B PUAVD IC-PDn IC-PDn USBDP IC-PDnR IVDD UDRCLV UDRD6 UDRD3 UDRD0 UDRCLK GND UDTAD4 UDTAD1 UDTD7 UDTD4 IVDD UMRDY_B UMRD_B EVDD UMAD7 GND PSAVD PSDGND GND IC-PDn USBCLK IC-PDn IC-Open USBDM IC-PDnR GND UDRE_B UDRD7 UDRD4 UDRAD4 UDRAD1 UDTCLV EVDD IVDD UDTD6 UDTD3 GND GND UMAD10 UMAD10 UMAD6 UMAD5 UMAD3 Pin No. E01 E02 E03 E04 E23 E24 E25 E26 F01 F02 F03 F04 F23 F24 F25 F26 G01 G02 G03 G04 G23 G24 G25 G26 H01 H02 H03 H04 H23 H24 H25 H26 J01 J02 J03 J04 J23 J24 J25 J26 K01 K02 K03 K04 K23 K24 K25 K26 L01 L02 L03 L04 Pin Name EVDD PSDVD PSAGND GND IVDD UMAD4 UMAD2 EVDD SRMCS_B SRMOE_B PSTBY PSMD_B UMAD1 UMAD0 IC-PUpR IC-PUpR SMD30 SMD30 SMD31 SMD31 IVDD GND IC-PUpR IC-PUpR IC-PUpR IC-PUpR SMD27 SMD27 GND SMD28 SMD28 SMD29 SMD29 IC-PUpR IC-PUpR UMD7 GND IVDD GND SMD25 SMD25 SMD26 SMD26 IVDD UMD6 UMD5 UMD4 SMD22 SMD22 SMD23 SMD23 EVDD SMD24 SMD24 UMD3 EVDD UMD2 UMD1 SMD18 SMD18 SMD19 SMD19 SMD20 SMD20 SMD21 SMD21 Data Sheet S14828EJ5V0DS S14828EJ5V0DS Pin No. L23 L24 L25 L26 M01 M02 M03 M04 M23 M24 M25 M26 N01 N02 N03 N04 N23 N24 N25 N26 P01 P02 P03 P04 P23 P24 P25 P26 R01 R02 R03 R04 R23 R24 R25 R26 T01 T02 T03 T04 T23 T24 T25 T26 U01 U02 U03 U04 U23 U24 U25 U26 Pin Name UMD0 IC-PUp GND IVDD SMD16 SMD16 SMD17 SMD17 IVDD GND IC-PUpR IC-PUpR IC-PUpR IC-PUpR SMA19 SMA19 SMA20 SMA20 GND EVDD IC-PUpR IC-PUpR IC-PUpR IC-PUpR SMA18 SMA18 SMA17 SMA17 SMA16 SMA16 SMA15 SMA15 MI2TD1 MI2TD0 IVDD GND SMA14 SMA14 EVDD SMA13 SMA13 SMA12 SMA12 MI2TCLK MI2COL MI2TD3 MI2TD2 SMA11 SMA11 IVDD GND SMA10 SMA10 MI2TER MI2CRS IVDD GND SMA9 SMA8 SMA7 EVDD MI2TE MI2RCLK EVDD MI2RER Pin No. V01 V02 V03 V04 V23 V24 V25 V26 W01 W02 W03 W04 W23 W24 W25 W26 Y01 Y02 Y03 Y04 Y23 Y24 Y25 Y26 AA01 AA02 AA03 AA04 AA23 AA24 AA25 AA26 AB01 AB02 AB03 AB04 AB23 AB24 AB25 AB26 AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 Pin Name SMA6 SMA5 IVDD GND MI2RD1 MI2RD0 MI2MD MI2RDV SMA4 SMA3 GND SMA2 IVDD MI2MCLK MI2RD3 MI2RD2 SMA1 EVDD SMA0 SDCKE1 GND IC-PDnR IC-PDnR GND IVDD GND SDCLK1 SDCS_B EVDD MITD1 MITD0 IVDD SDRAS_B SDCAS_B EVDD SDCLK0 GND MICRS MITD3 MITD2 SDWE_B SDCKE0 SMD15 SMD15 SMD10 SMD10 SMD6 EVDD SMD1 EXNMI_B POM5 POM2 POM0 URSDI µPD98501 PD98501 Pin No. AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 Pin Name EVDD IC-Open EVDD GND IC-PUpR JRSTB_B JDO IC-PDn ROMSEL0 MIRD2 GND MITER MITCLK MICOL GND SMD11 SMD11 SMD14 SMD14 SMD8 GND SMD4 IVDD EXINT_B POM7 Pin No. AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE01 AE02 AE03 AE04 AE05 AE06 Pin Name IVDD URCLK URDSR_B/MWDO URRTS_B/MWDI IVDD IC-Open IC-PDn IC-Open IC-Open JMS EVDD ROMSEL1 MIMCLK MIRD0 MIMD MIRER IVDD IVDD GND EVDD SMD9 SMD3 SMD2 Pin No. AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF01 AF02 AF03 Pin Name GND ENDCEN POM6 POM3 GND URDCD_B/MWCS URDTR_B GND IC-Open IC-PUpR IC-PUpR BIG IVDD JCK IC-PDn IC-PDn MIRD3 IVDD MIRCLK MITE GND SMD13 SMD13 SMD12 SMD12 Pin No. AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 Pin Name SMD5 SMD7 SMD0 RST_B EVDD POM4 POM1 IVDD URCTS_B/MWSK URSDO IC-PDn IC-Open IC-Open IVDD IC-PUpR GND JDI SSEL IC-PDn GND MIRD1 GND MIRDV Special pin name description: IC-PDn: Pull Down IC-PDnR: Pull Down with Resistor IC-PUp: Pull Up IC-PUpR: Pull Up with Resistor Remark In this document, XXX_B stands for active low pin. Data Sheet S14828EJ5V0DS S14828EJ5V0DS 5 µPD98501 PD98501 CONTENTS 1. PIN FUNCTIONS. 7 1.1 Power Supply . 7 1.2 System PLL Power Supply. 7 1.3 USB PLL Power Supply . 7 1.4 System Control Interface. 8 1.5 Memory Interface . 8 1.6 ATM Interface . 9 1.7 Ethernet Interface. 10 1.8 USB Interface. 11 1.9 UART/Micro Wire Interface. 11 1.10 Parallel Port Interface . 11 1.11 Boundary Scan Interface. 11 1.12 I.C. - Open . 12 1.13 I.C. - Pull Down . 12 1.14 I.C. - Pull Down with Resistor . 12 1.15 I.C. - Pull Up . 12 1.16 I.C. - Pull Up with Resistor . 12 2. ELECTRICAL SPECIFICATIONS. 13 3. PACKAGE DRAWING . 41 4. RECOMMENDED SOLDERING CONDITIONS. 42 6 Data Sheet S14828EJ5V0DS S14828EJ5V0DS µPD98501 PD98501 1. PIN FUNCTIONS Symbol of I/O column indicates following status in this section. I :Input O :Output I/O :Bidirection I/OZ :Bidirection (Include Hi-Z state) I/OD :Bidirection (Open drain output) OZ :Output (Include Hi-Z state) OD :Output (Open drain) 1.1 Power Supply Pin Name Pin No. I/O Active Level Function GND A03, A05, AB23, AC16, AC23, AD01, AE02, AE07, AE14, AF01, AF19, AF23, C16, C26, D10, D21, D22, E04, G04, H02, H26, P26, T03, T26, W03, Y23, Y26, A19, AA02, AD05, AE11, AF25, B07, B10, B14, D03, J02, L25, M04, N03, V04 GND (0 V) IVDD A02, A10, A14, AA01, AA26, AD14, AE24, AF11, B16, D18, E23, J01, J23, L26, M03, P25, V03, A11, AD07, AD10, AD26, AE01, AE19, AF17, C10, C21, G03, T02, T25, W23 Internal logic core power supply (+2.5 V) EVDD A07, A12, AA23, AB03, AC06, AC13, AC15, AD20, AE03, AF08, B08, B20, C24, E01, E26, K24, N04, R02, U04, U25, Y02, A06, D17, K03 External (I/O) power supply (+3.3 V) 1.2 System PLL Power Supply Pin Name Pin No. I/O Active Level Function PSAGND E03 Analog ground (0 V) PSAVD D01 Analog power supply (+2.5 V) PSDGND D02 Digital ground (0 V) PSDVD E02 Digital power supply (+2.5 V) 1.3 USB PLL Power Supply Pin Name Pin No. I/O Active Level Function PUAGND A04 Analog ground (0 V) PUAVD C05 Analog power supply (+2.5 V) PUDGND B05 Digital ground (0 V) PUDVD B04 Digital power supply (+2.5 V) Data Sheet S14828EJ5V0DS S14828EJ5V0DS 7 µPD98501 PD98501 1.4 System Control Interface Pin Name Pin No. I/O Active Level Function SCLK C01 I System clock (33 MHz) CLKSL C02 I Clock select (L: 100 MHz/H: 66 MHz) for VR4120A VR4120A and SDRAM PSMD_B F04 I L System PLL mode control input (L: normal, H: through) Note PSTBY F03 I H System PLL standby mode control input (L: active, H: standby) PUMD_B C04 I L USB PLL mode control (L: normal, H: through) Note PUSTBY B06 I H USB PLL standby mode control (L: active, H: standby) BIG AE18 I H VR4120A VR4120A big endian mode ENDCEN AE08 I EXINT_B AD08 I L External interrupt EXNMI_B AC08 I L External non-maskable interrupt RST_B AF07 I L System reset ROMSEL0, ROMSEL1 AC21, AD21 I ROM access bus width (ROMSEL1/0 = L/L: 32-bit, L/H: 16-bit, H/L: 8-bit) SSEL AF21 I UART/Micro Wire Select (L: UART, H: Micro Wire) Endian conversion enable Note PSMD_B and PUMD_B pins shall be connected to GND. 1.5 Memory Interface Pin Name Pin No. I/O Active Level Function SDCLK0, SDCLK1 AB04, AA03 O SDCKE0, SDCKE1 AC02, Y04 O H SDRAM clock enable SDCS_B AA04 O L SDRAM chip select SDRAS_B AB01 O L SDRAM row address strobe SDCAS_B AB02 O L SDRAM column address strobe SDWE_B AC01 O L SDRAM/PROM/FLASH write enable SRMCS_B F01 O L PROM/FLASH chip select SRMOE_B F02 O L PROM/FLASH output enable SMA0 - SMA20 SMA20 Y03, Y01, W04, W02, W01, V02, V01, U03, U02, U01, T04, T01, R04, R03, R01, P04, P03, P02, P01, N01, N02 O Memory address SMD0-SMD31 SMD0-SMD31 AF06, AC07, AE06, AE05, AD06, AF04, AC05, AF05, AD04, AE04, AC04, AD02, AF03, AF02, AD03, AC03, M01, M02, L01, L02, L03, L04, K01, K02, K04, J03, J04, H01, H03, H04, G01, G02 I/O Memory data 8 Data Sheet S14828EJ5V0DS S14828EJ5V0DS SDRAM clock µPD98501 PD98501 1.6 ATM Interface (1) UTOPIA management interface Pin Name Pin No. I/O Active Level Function UMMD A26 O Management mode select UMINT_B A24 I L Interrupt from PHY UMRD_B C23 O L Management read enable UMRDY_B C22 I L Management data ready UMRST_B A22 O L PHY reset UMSL_B B23 O L PHY select UMWR_B B24 O L Management write enable UMAD0 - UMAD11 UMAD11 F24, F23, E25, D26, E24, D25, D24, C25, B26, B25, D23, A25 O PHY address UMD0 - UMD7 L23, K26, K25, K23, J26, J25, J24, H25 I/O Management data (2) UTOPIA data interface Pin Name Pin No. I/O Active Level Function UDRCLK C15 O UDRCLV C11 I H Receive cell available UDRE_B D11 O L Receive enable UDRSC B11 I H Receive cell start UDRAD0 - UDRAD4 A16, D15, B15, A15, D14 O Receive PHY address UDRD0 - UDRD7 C14, A13, B13, C13, D13, B12, C12, D12 I Receive data UDTCLK A21 O Transmit clock UDTCLV D16 I H Transmit Cell Available UDTE_B A17 O L Transmit enable UDTSC B17 O H Transmit Cell start position UDTAD0 - UDTAD4 B19, C18, B18, A18, C17 O Transmit PHY address UDTD0 - UDTD7 A23, B22, B21, D20, C20, A20, D19, C19 O Transmit data Data Sheet S14828EJ5V0DS S14828EJ5V0DS Receive clock 9 µPD98501 PD98501 1.7 Ethernet Interface (1) Ethernet interface (Channel 1) Pin Name Pin No. I/O Active Level Function MIRCLK AE25 I MII - Receive clock (2.5 MHz/25 MHz) MIMCLK AD22 O MII - Management clock MIMD AD24 I/O MII ­ Management data MICOL AC26 I MII - Collision MICRS AB24 I MII - Carrier sense MIRDV AF26 I MII - Receive data valid MIRER AD25 I MII - Receive error MIRD0 - MIRD3 AD23, AF24, AC22, AE23 I MII - Receive data MITCLK AC25 I MII - Transmit clock (2.5 MHz/25 MHz) MITE AE26 O MII - Transmit enable MITER AC24 O MII - Transmit error MITD0 - MITD3 AA25, AA24, AB26, AB25 O MII - Transmit data (2) Ethernet interface (Channel 2) Pin Name Pin No. I/O Active Level Function MI2RCLK U24 I MII - Receive clock (2.5 MHz/25 MHz) MI2MCLK W24 O MII - Management clock MI2MD V25 I/O MII - Management data MI2COL R24 I MII - Collision MI2CRS T24 I MII - Carrier sense MI2RDV V26 I MII - Receive data valid MI2RER U26 I MII - Receive error MI2RD0 - MI2RD3 V24, V23, W26, W25 I MII - Receive data MI2TCLK R23 I MII - Transmit clock (2.5 MHz/25 MHz) MI2TE U23 O MII - Transmit enable MI2TER T23 O MII - Transmit error MI2TD0 - MI2TD3 P24, P23, R26, R25 O MII - Transmit data 10 Data Sheet S14828EJ5V0DS S14828EJ5V0DS µPD98501 PD98501 1.8 USB Interface Pin Name Pin No. I/O Active Level Function USBCLK D05 I External USB clock (12 MHz) USBDM D08 I/O USB data (-) USBDP C08 I/O USB data (+) 1.9 UART/Micro Wire Interface Pin Name Pin No. I/O Active Level Function URCLK AD11 I UART external clock (18.432 MHz) URSDO AF13 O UART serial data output URSDI AC12 I UART serial data input URDTR_B AE13 O L UART data terminal ready URRTS_B AD13 O L UART data request to send /MWDI I URCTS_B AF12 Micro Wire data in I /MWSK L O URDCD_B AE12 Micro Wire sampling clock out I /MWCS L O URDSR_B AD12 UART data carrier detect Micro Wire chip select I /MWDO UART clear to send L O UART data set ready Micro Wire data out Remark For the function multiplexed pins (AD13, AF12, AE12, AD12), function is determined as follows. SSEL = L: UART operation mode SSEL = H: Micro Wire operation mode 1.10 Parallel Port Interface Pin Name POM0 - POM7 Pin No. I/O AC11, AF10, AC10, AE10, AF09, AC09, AE09, AD09 Active Level O Function Parallel port signal output 1.11 Boundary Scan Interface Pin Name Pin No. I/O Active Level Function JCK AE20 I B-SCAN clock JDI AF20 I B-SCAN input-data JDO AC19 OZ B-SCAN output-data JMS AD19 I B-SCAN mode select JRSTB_B AC18 I Data Sheet S14828EJ5V0DS S14828EJ5V0DS L B-SCAN reset 11 µPD98501 PD98501 1.12 I.C. - Open Pin Name IC-Open Pin No. I/O A09, B09, A01, B02, D07, B03, AC14, AD15, AD17, AD18, AE15, AF15, AF16 Active Level O Function Leave open 1.13 I.C. - Pull Down Pin Name IC-PDn Pin No. I/O AF22, C03, B01, D04, C06, D06, C07, AE21, AC20, AD16, AE22, AF14 Active Level I Function Connect to GND 1.14 I.C. - Pull Down with Resistor Pin Name IC-PDnR Pin No. I/O C09, D09, Y24, Y25 Active Level I/O Function Connect to GND via pulldown resistor 1.15 I.C. - Pull Up Pin Name IC-PUp Pin No. I/O L24 Active Level I Function Connect to EVDD 1.16 I.C. - Pull Up with Resistor Pin Name IC-PUpR 12 Pin No. I/O A08, H24, H23, G26, G25, G24, G23, F26, F25, N26, N25, N24, N23, M26, M25, M23, M24, AC17, AE16, AE17, AF18 I/O Data Sheet S14828EJ5V0DS S14828EJ5V0DS Active Level Function Connect to EVDD via pull-up resistor µPD98501 PD98501 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Parameter Symbol Conditions Ratings Unit Storage temperature -0.5 to +3.6 V I/O buffer -0.5 to +4.6 V VI1/VO1 LVTTL-level pin -0.5 to +4.6 V USB I/O buffer -0.5 to +4.6 V IO1 LVTTL-level pin, IOL = 9 mA 30 mA IO2 Output current Internal logic core VI2/VO2 Input/output voltage IVDD EVDD Supply voltage USB I/O buffer, IOL = 18 mA 55 mA -60 to +150 °C Tstg Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Conditions Parameter Low level input voltage MIN. TYP. MAX. Unit IVDD 2.35 2.5 2.65 V EVDD Supply voltage Symbol Conditions 3.15 3.3 3.45 V 0.8 V 0.8 V VIL1 LVTTL-level pin VIL2 USB I/O/ buffer, refer to (9) USB Interface Parameter (Single-end operation) VIH1 LVTTL-level pin 2.0 V VIH2 USB I/O/ buffer, refer to (9) USB Interface Parameter (Single-end operation) 2.0 V USB differential input voltage VIDF USB I/O buffer, refer to (9) USB Interface Parameter (Differential operation) 0.2 V Operating ambient temperature TA High level input voltage 0 0 Data Sheet S14828EJ5V0DS S14828EJ5V0DS 70 °C 13 µPD98501 PD98501 DC Characteristics (IVDD = 2.5 ± 0.15 V, EVDD = 3.3 ± 0.15 V, TA = 0 to +70 °C) Parameter MAX. Unit IIDD 1100 mA EIDD Supply current Symbol Conditions MIN. TYP. 200 mA Input leakage current ILI VI = EVDD or GND ±10 µA Off state output current IOZ VO = EVDD or GND ±10 µA Low level output voltage VOL1 LVTTL-level pin, IOL = 9 mA 0.4 V VOL2 USB I/O buffer, refer to (9) USB Interface Parameter 0.3 V VOH1 LVTTL-level pin, IOH= 9mA 2.4 VOH2 USB I/O buffer, refer to (9) USB Interface Parameter 2.8 High level output voltage V EVDD V Capacitance (TA = 25°C, VDD = 0 V) ° MAX. Unit Input Capacitance Parameter CI fC = 1 MHz, 4 8 pF Output Capacitance CO Unmeasured pins returned to 0 V 4 8 pF I/O Capacitance CIO 4 8 pF 14 Symbol Conditions Data Sheet S14828EJ5V0DS S14828EJ5V0DS MIN. TYP. µPD98501 PD98501 Pin Classifications Input pins Category Number of Pins Application Pins LVTTL-level pin VI1, VIL1/VIH1 BIG, CLKSL, ENDCEN, EXINT_B, EXNMI_B, JCK, JDI, JMS, JRSTB_B, MI2COL, MI2CRS, MI2MD, MI2RCLK, MI2RD[3:0], MI2RDV, MI2RER, MI2TCLK, MICOL, MICRS, MIMD, MIRCLK, MIRD[3:0], MIRDV, MIRER, MITCLK, MWDI, PSMD_B, PSTBY, PUMD_B, PUSTBY, ROMSEL[1:0], RST_B, SCLK, SMD[31:0], SSEL, UDRCLV, UDRD[7:0], UDRSC, UDTCLV, UMD[7:0], UMINT_B, UMRDY_B, URCLK, URCTS_B, URDCD_B, URDSR_B, URSDI, USBCLK 100 USB I/O buffer VI2, VIL2/VIH2, VIDF USBDP, USBDM 2 Output pins Category Number of Pins Application Pins LVTTL-level pin IO1 VO1, VOL1/VOH1 JDO, MI2MCLK, MI2MD, MI2TD[3:0], MI2TE, MI2TER, MIMCLK, MIMD, MITD[3:0], MITE, MITER, MWCS, MWDO, MWSK, POM[7:0], SDCAS_B, SDCKE0, SDCKE1, SDCLK0, SDCLK1, SDCS_B, SDRAS_B, SDWE_B, SMA[20:0], SMD[31:0], SRMCS_B, SRMOE_B, UDRAD[4:0], UDRCLK, UDRE_B, UDTAD[4:0], UDTCLK, UDTD[7:0], UDTE_B, UDTSC, UMAD[11:0], UMD[7:0], UMMD, UMRD_B, UMRST_B, UMSL_B, UMWR_B, URDTR_B, URRTS_B, URSDO 142 USB I/O buffer IO2 VO2, VOL2/VOH2 USBDP, USBDM 2 AC Characteristics (IVDD = 2.5 ± 0.15 V, EVDD = 3.3 ± 0.15 V, TA = 0 to +70 °C) (1) AC Test Waveform Input signal 0.5EVDD Test points 0.5EVDD Ouput signal 0.5EVDD Test points 0.5EVDD Data Sheet S14828EJ5V0DS S14828EJ5V0DS 15 µPD98501 PD98501 (2) Clock parameter Clock Cycle Clock High Width Clock Low Width (2)-1 Clock input Parameter Symbol Conditions MIN. MAX. Unit SCLK input cycle tCYSCK 30.0 40.0 ns SCLK input high level width tWHSCK 0.4 × tCYSCK 0.6 × tCYSCK ns SCLK input low level width tWLSCK 0.4 × tCYSCK 0.6 × tCYSCK ns MITCLK input cycle tCYMTK 40.0 400.0 ns MITCLK input high level width tWHMTK 0.4 × tCYMTK 0.6 × tCYMTK ns MITCLK input low level width tWLMTK 0.4 × tCYMTK 0.6 × tCYMTK ns MIRCLK input cycle tCYMRK 40.0 400.0 ns MIRCLK input high level width tWHMRK 0.4 × tCYMRK 0.6 × tCYMRK ns MIRCLK input low level width tWLMRK 0.4 × tCYMRK 0.6 × tCYMRK ns MI2TCLK input cycle tCY2TK 40.0 400.0 ns MI2TCLK input high level width tWH2TK 0.4 × tCY2TK 0.6 × tCY2TK ns MI2TCLK input low level width tWL2TK 0.4 × tCY2TK 0.6 × tCY2TK ns MI2RCLK input cycle tCY2RK 40.0 400.0 ns MI2RCLK input high level width tWH2RK 0.4 × tCY2RK 0.6 × tCY2RK ns MI2RCLK input low level width tWL2RK 0.4 × tCY2RK 0.6 × tCY2RK ns USBCLK input cycle tCYUBK 83.1 84.6 ns USBCLK input high level width tWHUBK 0.4 × tCYUBK 0.6 × tCYUBK ns USBCLK input low level width tWLUBK 0.4 × tCYUBK 0.6 × tCYUBK ns JCK input cycle tCYJCK 100.0 1000.0 ns JCK input high level width tWHJCK 0.4 × tCYJCK 0.6 × tCYJCK ns JCK input low level width tWLJCK 0.4 × tCYJCK 0.6 × tCYJCK ns 16 Data Sheet S14828EJ5V0DS S14828EJ5V0DS µPD98501 PD98501 (2)-2 Clock output Parameter Symbol Conditions MIN. MAX. Unit SDCLK0 output cycle tCYSK0 Load 10 pF 10.0 15.0 ns SDCLK0 output high level width tWHSK0 Load 10 pF 0.4 × tCYSK0 0.6 × tCYSK0 ns SDCLK0 output low level width tWLSK0 Load 10 pF 0.4 × tCYSK0 0.6 × tCYSK0 ns SDCLK1 output cycle tCYSK1 Load 10 pF 10.0 15.0 ns SDCLK1 output high level width tWHSK1 Load 10 pF 0.4 × tCYSK1 0.6 × tCYSK1 ns SDCLK1 output low level width tWLSK1 Load 10 pF 0.4 × tCYSK1 0.6 × tCYSK1 ns UDTCLK output cycle tCYUTK Load 50 pF 30.0 ns UDTCLK output high level width tWHUTK Load 50 pF 0.4 × tCYUTK ns UDTCLK output low level width tWLUTK Load 50 pF 0.4 × tCYUTK ns UDRCLK output cycle tCYURK Load 50 pF 30.0 ns UDRCLK output high level width tWHURK Load 50 pF 0.4 × tCYURK ns UDRCLK output low level width tWLURK Load 50 pF 0.4 × tCYURK ns MIMCLK output cycle tCYMCK Load 50 pF 420.0 ns MIMCLK output high level width tWHMCK Load 50 pF 0.4 × tCYMCK ns MIMCLK output low level width tWLMCK Load 50 pF 0.4 × tCYMCK ns MI2MCLK output cycle tCYM2K Load 50 pF 420.0 ns MI2MCLK output high level width tWHM2K Load 50 pF 0.4 × tCYM2K ns MI2MCLK output low level width tWLM2K Load 50 pF 0.4 × tCYM2K ns Data Sheet S14828EJ5V0DS S14828EJ5V0DS 17 µPD98501 PD98501 (3) Reset, PLL parameter IVDD, EVDD PSTBY (System PLL), PUSTBY (USB PLL) tWHPSY, tWHUSY SCLK (System clock) External OSC Unstable Period Internal PLL OSC tWLPLK, tWLULK Stable Period RST_B (System Reset) tWLRSB Parameter Symbol Conditions MIN. MAX. Unit RST_B input low level width tWLRSB 6.0 × tCYSCK ns PSTBY hold high level width tWHPSY 1 µs PSTBY lookup time tWLPLK 1000 µs PUSTBY hold high level width tWHUSY 1 µs PUSTBY lookup time tWLULK 1000 µs Load 50 pF Load 50 pF (4) Interrupt interface parameter tWLEIT, tWLENM EXINT_B EXNMI_B (input) Parameter Symbol Conditions MIN. MAX. Unit EXINT_B input low level width tWLEIN 4.0 × tCYSK0 ns EXNMI_B input low level width tWLENM 4.0 × tCYSK0 ns 18 Data Sheet S14828EJ5V0DS S14828EJ5V0DS µPD98501 PD98501 (5) SDRAM interface parameter SDCLK0 (output) tDSE0SK0 tDSE0SK0 SDCKE0 (output) tDSCSSK0 tDSCSSK0 tDSRASK0 tDSRASK0 tDSCASK0 tDSCASK0 tDSW ESK0 tDSW ESK0 tDSMASK0 tDSMASK0 SDCS_B (output) SDRAS_B (output) SDCAS_B (output) SDWE_B (output) SMA[20:0] (output) tDSMDSK0 SMD[31:0] (output) tDSMDSK0 tDSMDSK0 Hi-Z Hi-Z tASMDSK0 tFSMDSK0 tSSMDSK0 tHSMDSK0 SMD[31:0] (input) Hi-Z Parameter Hi-Z Symbol Conditions MIN. MAX. Unit SDCKE0 output delay from SDCLK0 tDSE0SK0 Load 30 pF 1.0 7.5 ns SDCS_B output delay from SDCLK0 tDSCSSK0 Load 30 pF 1.0 7.5 ns SDRAS_B output delay from SDCLK0 tDSRASK0 Load 30 pF 1.0 7.5 ns SDCAS_B output delay from SDCLK0 tDSCASK0 Load 30 pF 1.0 7.5 ns SDWE_B output delay from SDCLK0 tDSWESK0 Load 50 pF 1.0 7.5 ns SMA[20:0] output delay from SDCLK0 tDSMASK0 Load 50 pF 1.0 7.5 ns SMD[31:0] output floating to active delay from SDCLK0 tASMDSK0 Load 50 pF 1.0 SMD[31:0] output delay from SDCLK0 tDSMDSK0 Load 50 pF 1.0 SMD[31:0] output active to floating delay from SDCLK0 tFSMDSK0 Load 50 pF SMD[31:0] input setup to SDCLK0 tSSMDSK0 4.0 ns SMD[31:0] input hold from SDCLK0 tHSMDSK0 1.0 ns Data Sheet S14828EJ5V0DS S14828EJ5V0DS ns 7.5 ns 7.5 ns 19 µPD98501 PD98501 SDCLK1 (output) tDSE1SK1 tDSE0SK1 SDCKE1 (output) tDSCSSK1 tDSCSSK1 tDSRASK1 tDSRASK1 tDSCASK1 tDSCASK1 tDSWESK1 tDSWESK1 tDSMASK1 tDSMASK1 SDCS_B (output) SDRAS_B (output) SDCAS_B (output) SDWE_B (output) SMA[20:0] (output) tDSMDSK1 SMD[31:0] (output) tDSMDSK1 tDSMDSK1 Hi-Z Hi-Z tASMDSK1 tFSMDSK1 tSSMDSK1 tHSMDSK1 SMD[31:0] (input) Hi-Z Parameter Hi-Z Symbol Conditions MIN. MAX. Unit SDCKE1 output delay from SDCLK1 tDSE1SK1 Load 30 pF 1.0 7.5 ns SDCS_B output delay from SDCLK1 tDSCSSK1 Load 30 pF 1.0 7.5 ns SDRAS_B output delay from SDCLK1 tDSRASK1 Load 30 pF 1.0 7.5 ns SDCAS_B output delay from SDCLK1 tDSCASK1 Load 30 pF 1.0 7.5 ns SDWE_B output delay from SDCLK1 tDSWESK1 Load 50 pF 1.0 7.5 ns SMA[20:0] output delay from SDCLK1 tDSMASK1 Load 50 pF 1.0 7.5 ns SMD[31:0] output floating to active delay from SDCLK1 tASMDSK1 Load 50 pF 1.0 SMD[31:0] output delay from SDCLK1 tDSMDSK1 Load 50 pF 1.0 SMD[31:0] output active to floating delay from SDCLK1 tFSMDSK1 Load 50 pF SMD[31:0] input setup to SDCLK1 tSSMDSK1 4.0 ns SMD[31:0] input hold from SDCLK1 tHSMDSK1 1.0 ns 20 Data Sheet S14828EJ5V0DS S14828EJ5V0DS ns 7.5 ns 7.5 ns µPD98501 PD98501 (6) Flash ROM interface parameter T0 T1 T2 T3 FAT (=4) T4 T5 T6 SDCLK (internal) tSSMAROE tHSMAROE SMA[20:0] (output) tSRCSROE tHRCSROE SRMCS_B (output) tHSWEROE tSSWEROE SDWE_B (output) tWLROE tWHROE SRMOE_B (output) tSSMDROE SMD[31:0] (input) tHSMDROE Hi-Z Parameter Hi-Z Symbol Condition MIN. MAX. Unit SMA[20:0] setup to SRMOE_B tSSMAROE Load 50 pF 5.0 × tCYSK0 - 8.0 ns SMA[20:0] hold from SRMOE_B tHSMAROE Load 50 pF 1.0 × tCYSK0 - 8.0 ns SRMCS_B setup to SRMOE_B tSRCSROE Load 50 pF 5.0 × tCYSK0 - 8.0 ns SRMCS_B hold from SRMOE_B tHRCSROE Load 50 pF SDWE_B setup time to SRMOE_B tSSWEROE Load 50 pF 2.0 × tCYSK0 - 8.0 ns SDWE_B hold time from SRMOE_B tHSWEROE Load 50 pF 4.0 × tCYSK0 - 8.0 ns SRMOE_B low level pulse width tWLROE Load 50 pF 5.0 × tCYSK0 - 8.0 ns SRMOE_B high level pulse width tWHROE Load 50 pF 1.0 × tCYSK0 - 8.0 ns SMD[31:0] setup to SRMOE_B tSSMDROE 10.0 ns SMD[31:0] hold from SRMOE_B tHSMDROE 0 ns Data Sheet S14828EJ5V0DS S14828EJ5V0DS 5.0 ns 21 µPD98501 PD98501 T0 T1 T2 T3 FAT (=4) T4 T5 T6 SDCLK (internal) tSSMASWE tHSMASWE SMA[20:0] (output) tSRCSSWE tHRCSSWE SRMCS_B (output) tWHSWE tWLSWE SDWE_B (output) tSROESWE tHROESWE SRMOE_B (output) tSSMDSWE SMD[31:0] (output) tHSMDSWE Hi-Z Hi-Z tASMDSWE Parameter Symbol tFSMDSWE Condition MIN. MAX. Unit SMA[20:0] setup to SDWE_B Load 50 pF 4.0 × tCYSK0 - 8.0 ns SMA[20:0] hold from SDWE_B tHSMASWE Load 50 pF 2.0 × tCYSK0 - 8.0 ns SRMCS_B setup to SDWE_B tSRCSSWE Load 50 pF 4.0 × tCYSK0 - 8.0 ns SRMCS_B hold from SDWE_B tHRCSSWE Load 50 pF 1.0 × tCYSK0 - 8.0 ns SRMOE_B setup time to SDWE_B tSROESWE Load 50 pF 4.0 × tCYSK0 - 8.0 ns SRMOE_B hold time from SDWE_B tHROESWE Load 50 pF 2.0 × tCYSK0 - 8.0 ns SDWE_B low level pulse width tWLSWE Load 50 pF 3.0 × tCYSK0 - 8.0 ns SDWE_B high level pulse width tWHSWE Load 50 pF 7.0 × tCYSK0 - 8.0 ns SMD[31:0] setup to SDWE_B tSSMDSWE Load 50 pF 4.0 × tCYSK0 - 8.0 ns SMD[31:0] hold from SDWE_B tHSMDSWE Load 50 pF SMD[31:0] output floating to active delay from SDWE_B tASMDSWE Load 50 pF SMD[31:0] output active to floating delay from SDWE_B 22 tSSMASWE tFSMDSWE Load 50 pF 1.0 × tCYSK0 + 8.0 4.0 × tCYSK0 - 8.0 Data Sheet S14828EJ5V0DS S14828EJ5V0DS ns ns 1.0 × tCYSK0 + 8.0 ns µPD98501 PD98501 (7) ATM interface parameter (7)-1 UTOPIA2 interface UDTCLK (output) tSUTLUTK tHUTLUTK UDTCLV (input) tDUTAUTK UDTAD[4:0] (output) tDUTDUTK UDTD[7:0] (output) tDUTEUTK UDTE_B (output) tDUTSUTK UDTSC (output) Parameter Symbol Conditions MIN. MAX. Unit UDTCLV setup time to UDTCLK tSUTLUTK 8.0 ns UDTCLV hold time from UDTCLK tHUTLUTK 1.0 ns UDTAD[4:0] output delay from UDTCLK tDUTAUTK Load 50 pF 1.0 15.0 ns UDTD[7:0] output delay from UDTCLK tDUTDUTK Load 50 pF 1.0 15.0 ns UDTE_B output delay from UDTCLK tDUTEUTK Load 50 pF 1.0 15.0 ns UDTSC output delay from UDTCLK tDUTSUTK Load 50 pF 1.0 15.0 ns Data Sheet S14828EJ5V0DS S14828EJ5V0DS 23 µPD98501 PD98501 UDRCLK (output) tSURLURK tHURLURK UDRCLV (input) tDURAURK UDRAD[4:0] (output) tSURDURK tHURDURK UDRD[7:0] (input) tDUREURK UDRE_B (output) tSURSURK tHURSURK UDRSC (input) Parameter Symbol Conditions MIN. MAX. Unit UDRCLV setup time to UDRCLK 8.0 ns UDRCLV hold time from UDRCLK tHURLURK 1.0 ns UDRAD[4:0] output delay from UDRCLK tDURAURK UDRD[7:0] setup to from UDRCLK tSURDURK 8.0 ns UDRD[7:0] hold time from UDRCLK tHURDURK 1.0 ns UDRE_B output delay from UDRCLK tDUREURK UDRSC setup time to UDRCLK tSURSURK 8.0 ns UDRSC hold time from UDRCLK 24 tSURLURK tHURSURK 1.0 ns Load 50 pF Load 50 pF Data Sheet S14828EJ5V0DS S14828EJ5V0DS 1.0 1.0 15.0 15.0 ns ns µPD98501 PD98501 (7)-2 UTOPIA management interface tWLURT UMRST_B (output) tWLUIT UMINT_B (input) Parameter Symbol Conditions MIN. MAX. Unit UMRST_B low level pulse width tWLURT 3.0 × tCYSCK ns UMINT_B low level pulse width tWLUIT 3.0 × tCYSCK ns Data Sheet S14828EJ5V0DS S14828EJ5V0DS 25 µPD98501 PD98501 tSUMAURD tHUMAURD UMAD[11:0] (output) tSUSLURD tHUSLURD tSUW RURD tHUWRURD UMSL_B (output) UMWR_B (output) tW LURD UMRD_B (output) tSURYURD tHURYURD UMRDY_B (input) tSUMDURD tHUMDURD Hi-Z UMD[7:0] (input) Parameter Symbol Conditions Hi-Z MIN. MAX. Unit UMAD[11:0] setup to UMRD_B tSUMAURD Load 50 pF 10 ns UMAD[11:0] hold from UMRD_B tHUMAURD Load 50 pF 4 ns UMSL_B setup to UMRD_B tSUSLURD Load 50 pF 5 ns UMSL_B hold from UMRD_B tHUSLURD Load 50 pF 0 ns UMWR_B setup to UMRD_B tSUWRURD Load 50 pF 5 ns UMWR_B hold from UMRD_B tHUWRURD Load 50 pF 0 ns UMRD_B low level pulse width tWLURD Load 50 pF 50 ns UMRDY_B setup to UMRD_B tSURYURD 25 ns UMRDY_B hold from UMRD_B tHURYURD 10 ns UMD[7:0] setup to UMRD_B tSUMDURD 15 ns UMD[7:0] hold from UMRD_B tHUMDURD 15 ns 26 Data Sheet S14828EJ5V0DS S14828EJ5V0DS µPD98501 PD98501 tSUMADSR tHUMADSR UMAD[11:0] (output) tSUSLDSR tHUSLDSR tSRWDSR tHRW DSR UMSL_B (output) UMWR_B (as R/W : output) tW LDSR UMRD_B (as DS : output) tSDAKDSR tHDAKDSR UMRDY_B (as DACK : input) tSUMDDSR Hi-Z UMD[7:0] (input) Parameter tHUMDDSR Symbol Conditions Hi-Z MIN. MAX. Unit UMAD[11:0] setup to DS tSUMADSR Load 50 pF 10 ns UMAD[11:0] hold from DS tHUMADSR Load 50 pF 4 ns UMSL_B setup to DS tSUSLDSR Load 50 pF 5 ns UMSL_B hold from DS tHUSLDSR Load 50 pF 0 ns R/W setup to DS tSRWDSR Load 50 pF 5 ns R/W hold from DS tHRWDSR Load 50 pF 0 ns DS low level pulse width tWLDSR Load 50 pF 50 ns DACK setup to DS tSDAKDSR 25 ns DACK hold from DS tHDAKDSR 10 ns UMD[7:0] setup to DS tSUMDDSR 15 ns UMD[7:0] hold from DS tHUMDDSR 15 ns Data Sheet S14828EJ5V0DS S14828EJ5V0DS 27 µPD98501 PD98501 tSUMAUW R tHUMAUW R UMAD[11:0] (output) tSUSLUW R tHUSLUW R UMSL_B (output) tW LUWR UMWR_B (output) tSURDUW R tHURDUW R UMRD_B (output) tSURYUW R tHURYUW R UMRDY_B (input) tSUMDUW R UMD[7:0] (output) tHUMDUW R Hi-Z Hi-Z tAUMDUW R Parameter Symbol Conditions tFUMDUW R MIN. MAX. Unit UMAD[11:0] setup to UMWR_B tSUMAUWR Load 50 pF 10 ns UMAD[11:0] hold from UMWR_B tHUMAUWR Load 50 pF 4 ns UMSL_B setup to UMWR_B tSUSLUWR Load 50 pF 5 ns UMSL_B hold from UMWR_B tHUSLUWR Load 50 pF 0 ns UMRD_B setup to UMWR_B tSURDUWR Load 50 pF 5 ns UMRD_B hold from UMWR_B tHURDUWR Load 50 pF 0 ns UMWR_B low level pulse width tWLUWR Load 50 pF 50 ns UMRDY_B setup to UMWR_B tSURYUWR 25 ns UMRDY_B hold from UMWR_B tHURYUWR 10 ns UMD[7:0] setup to UMWR_B tSUMDUWR 15 ns UMD[7:0] hold from UMWR_B tHUMDUWR 4 ns UMD[7:0] active time to UMWR_B tAUMDUWR Load 50 pF 15 ns UMD[7:0] floating time from UMWR_B tFUMDUWR Load 50 pF 4 ns 28 Data Sheet S14828EJ5V0DS S14828EJ5V0DS µPD98501 PD98501 tSUMADSW UMAD[11:0] (output) tHUMADSW tSUSLDSW tSRWDSW UMSL_B (output) tHUSLDSW tHRWDSW UMWR_B (as R/W : output) tWLDSW UMRD_B (as DS : output) tSDAKDSW tHDAKDSW UMRDY_B (as DACK : input) tSUMDDSW UMD[7:0] (output) tHUMDDSW Hi-Z Hi-Z tAUMDDSW Conditions tFUMDDSW Parameter Symbol UMAD[11:0] setup to DS tSUMADSW Load 50 pF 10 ns UMAD[11:0] hold from DS tHUMADSW Load 50 pF 4 ns UMSL_B setup to DS tSUSLDSW Load 50 pF 5 ns UMSL_B hold from DS tHUSLDSW Load 50 pF 0 ns R/W setup to DS tSRWDSW Load 50 pF 5 ns R/W hold from DS tHRWDSW Load 50 pF 0 ns DS low level pulse width tWLDSW Load 50 pF 50 ns DACK setup to DS tSDAKDSW 25 ns DACK hold from DS tHDAKDSW 10 ns UMD[7:0] setup to DS tSUMDDSW 15 ns UMD[7:0] hold from DS tHUMDDSW 4 ns UMD[7:0] active time to DS tAUMDDSW Load 50 pF 15 ns UMD[7:0] floating time from DS tFUMDDSW Load 50 pF 4 ns Data Sheet S14828EJ5V0DS S14828EJ5V0DS MIN. MAX. Unit 29 µPD98501 PD98501 (8) Ethernet interface parameter (8)-1 Ethernet 1 MITCLK (input) tDMTEMTK tDMTEMTK MITE (output) tDMTDMTK tDMTDMTK MITD[3:0] (output) tDMTRMTK tDMTRMTK MITER (output) Parameter MITE output delay from MITCLK Symbol tDMTEMTK Conditions Load 50 pF MIN. MAX. Unit 0 20 Note ns Note ns ns MITD[3:0] output delay from MITCLK tDMTDMTK Load 50 pF 0 20 MITER output delay from MITCLK tDMTRMTK Load 50 pF 0 20 Note Note In MII Spec., Maximum output delay is specified as 25 ns 30 Data Sheet S14828EJ5V0DS S14828EJ5V0DS µPD98501 PD98501 MIRCLK (input) tSMRVMRK tHMRVMRK MIRDV (input) tSMRDMRK tHMRDMRK MIRD[3:0] (input) tSMRRMRK tHMRRMRK MIRER (input) Parameter Symbol Conditions MIN. MAX. Unit MIRDV setup time to MIRCLK tSMRVMRK 10 ns MIRDV hold time from MIRCLK tHMRVMRK 10 ns MIRD[3:0] setup time to MIRCLK tSMRDMRK 10 ns MIRD[3:0] hold time from MIRCLK tHMRDMRK 10 ns MIRER setup time to MIRCLK tSMRRMRK 10 ns MIRER hold time from MIRCLK tHMRRMRK 10 ns tWHMCL MICOL (input) tWHMCS MICRS (input) Parameter Symbol Conditions MIN. MAX. Unit MICOL high level pulse width tWHMCL 2.0 × tCYMTK ns MICRS high level pulse width tWHMCS 2.0 × tCYMTK ns Data Sheet S14828EJ5V0DS S14828EJ5V0DS 31 µPD98501 PD98501 MIMCLK (output) tSMMDMCK tHMMDMCK MIMD (input) tAMMDMCK tDMMDMCK tFMMDMCK MIMD (output) Parameter Symbol Condition MIN. MAX. Unit MIMD setup to MIMCLK tSMMDMCK 20 ns MIMD hold from MIMCLK tHMMDMCK 0 ns MIMD active delay from MIMCLK tAMMDMCK Load 50 pF 10 ns MIMD output delay from MIMCLK tDMMDMCK Load 50 pF 10 MIMD floating delay from MIMCLK tFMMDMCK Load 50 pF 10 32 Data Sheet S14828EJ5V0DS S14828EJ5V0DS 20 ns ns µPD98501 PD98501 (8)-2 Ethernet 2 MI2TCLK (input) tD2TE2TK tD2TE2TK tD2TD2TK tD2TD2TK MI2TE (output) MI2TD[3:0] (output) tD2TR2TK tD2TR2TK MI2TER (output) Parameter Symbol Conditions MIN. MAX. Unit Note ns MI2TE output delay from MI2TCLK tD2TE2TK Load 50 pF 0 20 MI2TD[3:0] output delay from MI2TCLK tD2TD2TK Load 50 pF 0 20 Note ns 0 Note ns MI2TER output delay from MI2TCLK tD2TR2TK Load 50 pF 20 Note In MII Spec., Maximum output delay is specified as 25 ns Data Sheet S14828EJ5V0DS S14828EJ5V0DS 33 µPD98501 PD98501 MI2RCLK (input) tS2RV2RK tH2RV2RK MI2RDV (input) tS2RD2RK tH2RD2RK MI2RD[3:0] (input) tS2RR2RK tH2RR2RK MI2RER (input) Parameter Symbol Conditions MIN. MAX. Unit MI2RDV setup time to MI2RCLK tS2RV2RK 10 ns MI2RDV hold time from MI2RCLK tH2RV2RK 10 ns MI2RD[3:0] setup time to MI2RCLK tS2RD2RK 10 ns MI2RD[3:0] hold time from MI2RCLK tH2RD2RK 10 ns MI2RER setup time to MI2RCLK tS2RR2RK 10 ns MI2RER hold time from MI2RCLK tH2RR2RK 10 ns tWH2CL MI2COL (input) tWH2CS MI2CRS (input) Parameter Symbol Conditions MIN. MAX. Unit MI2COL high level pulse width tWH2CL 2.0 × tCY2TK ns MI2CRS high level pulse width tWH2CS 2.0 × tCY2TK ns 34 Data Sheet S14828EJ5V0DS S14828EJ5V0DS µPD98501 PD98501 MI2MCLK (output) tS2MD2CK tH2MD2CK MI2MD (input) tA2MD2CK tD2MD2CK tF2MD2CK MI2MD (output) Parameter Symbol Condition MIN. MAX. Unit MI2MD setup to MI2MCLK tS2MD2CK 20 ns MI2MD hold from MI2MCLK tH2MD2CK 0 ns MI2MD active delay from MI2MCLK tA2MD2CK Load 50 pF 10 ns MI2MD output delay from MI2MCLK tD2MD2CK Load 50 pF 10 MI2MD floating delay from MI2MCLK tF2MD2CK Load 50 pF 10 Data Sheet S14828EJ5V0DS S14828EJ5V0DS 20 ns ns 35 µPD98501 PD98501 (9) USB interface parameter External Circuitry The USB line I/O signals (refer to chapter 1.8 USB interface) need 4 external resistors to adjust the output impedance (R1 and R2 = 22 each), to code the full speed USB mode (R3 = 1.5 k) and to protect the output driver of the USBDM pin (R4 = 51 k). The following figure shows a typical connection diagram. R3 µ PD98501 PD98501 EVDD = 3.3 V R1 USBDP to USB Connector USBDM R2 GND R4 Parameter: USBDM, USBDP Rise time Fall time 90% 90% CL Differential Data Lines 10% 10% CL tF tR tPERIOD = 1/tDRATE Crossover points Differential Data Lines n × tPERIOD + tDJ1 Next transitions Paired transitions n × tPERIOD + tDJ2 tPERIOD = 1/tDRATE Differential Data Lines Crossover points n × tPERIOD + tDEOP 36 Crossover points extended tEOPT, tEOPR Data Sheet S14828EJ5V0DS S14828EJ5V0DS µPD98501 PD98501 tPERIOD = 1/tDRATE VIL Differential Data Lines tFST tPERIOD = 1/tDRATE Differential Data Lines tJR1 tJR2 Next transitions n x tPERIOD + tJR1 Paired transitions (n+1) x tPERIOD + tJR2 Parameter Symbol Condition MIN. MAX. Unit Rise time tR Load 50 pF 1.0 20.0 ns Fall time tF Load 50 pF 1.0 20.0 ns Differential rise and fall time matching tFRFM tR/tF 90.0 111.1 % Full-speed data rate tDRATE 11.97 12.13 Mbps ns Source jitter total (including frequency tolerance): To next transition tDJ1 -3.5 +3.5 For paired transitions tDJ2 -4.0 +4.0 tDEOP -2.0 +5.0 Source jitter for differential transition to SE0 transition Receiver jitter: ns ns To next transition tJR1 -18.5 +18.5 For paired transitions tJR2 -9.0 +9.0 Source SE0 interval of EOP tEOPT 160.0 175.0 Receiver SE0 interval of EOP tEOPR 82.0 Width of SE0 interval during differential transition tFST Data Sheet S14828EJ5V0DS S14828EJ5V0DS ns ns 14.0 ns 37 µPD98501 PD98501 (10) Parallel port interface parameter SDCLK0 tDPOM POM[7:0] (output) Parameter Symbol POM[7:0] output delay tDPOM Conditions MIN. Unit 0.0 Load 50 pF MAX. 8.0 ns (11) UART interface parameter T BAUDOUT (internal) tWLUDO URSDO (output) START DATA(5-8) PARITY STOP START PARITY STOP tWLUDI URSDI (input) Remark START DATA(5-8) START The BAUDOUT is equal to the 16X of transmisson baud rate (1/T = 16 × Baud Rate). Customize Baud Rates can be achieved by selecting proper divisor values for MSB and LSB of baud rate generator. Parameter Symbol Conditions MIN. MAX. Unit 18.432 MHz URCLK input frequency fCYUCK URSDO low level width tWLUDO 16 × T ns URSDI low level width tWLUDI 16 × T ns 38 Data Sheet S14828EJ5V0DS S14828EJ5V0DS µPD98501 PD98501 (12) Micro Wire interface parameter tWHWSK tWLWSK tCYWSK URCTS_B (as MWSK : output) tSWSKWCS tSWCSWSK tHWCSWSK URDCD_B (as MWCS :output) tAWDOWSK tDWDOWSK tDWDOWSK tFWDOWSK URDSR_B (as MWDO : output) URRTS_B (Read) tSWDIWSK Hi-Z (as MWDI : input) URRTS_B (Status) tHWDIWSK Hi-Z tAWDIWSK tFWDIWSK Hi-Z Hi-Z (as MWDI : input) Parameter Symbol Conditions MIN. MAX. Unit MWSK clock cycle tCYWSK Load 50 pF 400 × tCYSK0 ns MWSK high time tWHWSK Load 50 pF 190 × tCYSK0 ns MWSK low time tWLWSK Load 50 pF 190 × tCYSK0 ns MWSK setup to MWSK tSWSKWCS Load 50 pF 90 × tCYSK0 ns MWCS setup to MWSK tSWCSWSK Load 50 pF 90 × tCYSK0 ns MWCS hold from MWSK tHWCSWSK Load 50 pF 90 × tCYSK0 ns MWDO output active to floating delay from MWSK tAWDOWSK Load 50 pF 190 × tCYSK0 ns MWDO output delay from MWSK tDWDOWSK Load 50 pF 190 × tCYSK0 ns MWDO output floating to active delay from MWSK tFWDOWSK Load 50 pF 190 × tCYSK0 ns MWDI setup to MWSK tSWDIWSK 10 × tCYSK0 ns MWDI hold from MWSK tHWDIWSK 10 × tCYSK0 ns MWCS to status time from MWSK tAWDIWSK 100 × tCYSK0 ns MWCS to MWDO in 3-state tFWDIWSK 40 × tCYSK0 ns Data Sheet S14828EJ5V0DS S14828EJ5V0DS 39 µPD98501 PD98501 (13) JTAG boundary-scan JCK (input) tSJMS tHJMS tSJDI tHJDI JMS (input) JDI (input) tDJDO tDJDO JDO (output) tWLJRT JRST_B (input) Parameter Symbol Conditions MIN. MAX. Unit JMS Setup Time tSJMS 15 ns JMS Hold Time tHJMS 15 ns JDI Setup Time tSJDI 15 ns JDI Hold Time tHJDI 15 ns JDO Output Delay tDJDO JRSTB_B Low Pulse Width tWLJRT 40 Load 50 pF 25 5 × tCYJCK Data Sheet S14828EJ5V0DS S14828EJ5V0DS ns ns µPD98501 PD98501 3. PACKAGE DRAWING 352-PIN 352-PIN TAPE BGA (HEAT SPREADER TYPE) (35x35) A B A1 A 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Q R S T B W A2 D AE AC AA W U R N L J G E C A AF AD AB Y V Y P M K H F D B X C Index area Y J H A S G B K F S E M M M ITEM S A B P L S MILLIMETERS N 34.60±0.15 34.60±0.15 D E F G 35.00±0.20 1.625 1.27 (T.P.) 0.60±0.10 0.80 +0.20 -0.10 J 1.40 +0.30 -0.20 K (Z) 23.00 MAX. 23.00 MAX. H detail of B part 35.00±0.20 A1 A2 B C detail of A part A 0.15 L 0.75±0.15 M 0.30 N P Q 0.25 MIN. 0.10 3.0 R S T W 2.0 2.0 3.0 20.19 X Y Z 20.19 C0.4 0.20 S352N7-127-F6-2 S352N7-127-F6-2 Data Sheet S14828EJ5V0DS S14828EJ5V0DS 41 µPD98501 PD98501 4. RECOMMENDED SOLDERING CONDITIONS The µPD98501 PD98501 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 4-1. Surface Mounting Type Soldering Conditions µPD98501N7-F6 PD98501N7-F6: 352-pin tape BGA (heat spreader type) (35 × 35) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher), Count: three times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) IR35-107-3 IR35-107-3 VPS Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher), Count: three times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) VP15-107-3 VP15-107-3 Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together. 42 Data Sheet S14828EJ5V0DS S14828EJ5V0DS µPD98501 PD98501 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Data Sheet S14828EJ5V0DS S14828EJ5V0DS 43 µPD98501 PD98501 VR4120A VR4120A is a trademark of NEC Corporation. Micro Wire is a trademark of National Semiconductor Corp. Ethernet is a trademark of Xerox Corp. MIPS is a trademark of MIPS Technologies, Inc. · The information in this document is current as of August, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. · No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. · NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. · Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. · While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. · NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4