S11409EJ2V0UMJ1 PD98408 S12313E CIRCUIT-----------------------58 PE-67588 - Datasheet Archive

 

Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

 

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": 8. 9. 10. 11. 12. Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. USER'S MANUAL µ © NEC Corporation 1997 Document NO: S11409EJ2V0UMJ1 S11409EJ2V0UMJ1(2nd edition) Date Published: October 2000 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. II The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. · The information in this document is current as of February, 1997. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. · No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. · NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. · Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. · While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. · NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4 III PREFACE Readers This manual should be read by users in order to understand the µPD98408 PD98408 functions for designing application systems. Purpose This manual is intended to describe the hardware functions of the µPD98408 PD98408 to the user. Organization This manual consists of the following sections: Overview · Pin Functions · Functional Overview · Registers · JTAG boundary scan · The Example of Application · How to read This manual assumes that readers possess basic knowledge on electric/electronic circuit, logic circuit, and microcomputers. To find out about the functions of the µPD98408 PD98408, please read in the order of the table of contents. If you want to know about the electrical characteristics of the µPD98408 PD98408, please refer to the supplementary data sheet. Legends Data weight Active low Note Caution Remark Numerical expression : : : : : : Upper digit is left and lower is right. ×××_B (after the name of pin or signal, _B) Explanation for Note in the text. Description that should be carefully read Complementary explanation for the text Binary . ×××× or ××××B Decimal. ×××× Hexadecimal. ××××H Related documents The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such. - Data Sheet: S12313E S12313E IV CONTENTS CHAPTER 1 OVERVIEW 1.1 FEATURES- 1 1.2 ORDERING INFORMATION- 1 1.3 SAMPLE SYSTEM CONFIGURATION (APPLICATION)- 2 1.4 BLOCK DIAGRAM- 3 1.5 PIN CONFIGURATION- 4 1.6 PIN CONFIGURATION (Top View) - 5 CHAPTER 2 PIN FUNCTIONS 2.1 PIN FUNCTIONS - 7 2.2 RECOMENDED CONNECTION FOR UNUSED PINS-16 PINS-16 2.3 PIN CONDITIONS WHILE RESET-17 RESET-17 CHAPTER 3 FUNCTION OVERVIEW 3.1 PMD SUBLAYER -18 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 Equalizer Comparator Clock and Data Recovery Latch Driver Tx Selector Rx Selector 3.2 TC SUBLAYER -20 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 LOS Detection NRZI Encoding and Decoding Command-Byte Insertion and Detection 4B5B Block Encoding and Decoding Cell Scrambling and Descrambling HEC Generation and Verification Idle/Unassigned Cell Detection 3.3 ATM LAYER (UTOPIA) INTERFACE-24 INTERFACE-24 3.3.1 Transmit Interface 3.3.2 Receive Interface 3.3.3 FIFO Block 3.4 LOOP-BACK MODE -26 3.4.1 3.4.2 3.4.3 3.4.4 PMD Loop-Back 1 PMD Loop-Back 2 ATM Layer Loop-Back Transmit Data Select Function at Loop-Back 3.5 CPU INTERFACE-29 INTERFACE-29 3.5.1 Write Cycle 3.5.2 Read Cycle 3.6 PSEUDO ERROR GENERATION FUNCTION -32 V 3.7 ERROR/FAILURE DETECTION FUNCTIONS-32 FUNCTIONS-32 3.7.1 LOS (Loss of Signal) Detection Function 3.7.2 HEC Error/4B5B Code Error Detection Function 3.7.3 Transmit FIFO/Receive FIFO Overflow Detection Function 3.8 X_8 COMMAND CODE TRANSMIT/RECEIVE FUNCTION-34 FUNCTION-34 3.8.1 X_8 Command Code Transmit Function 3.8.2 X_8 Command Code Receive Function 3.9 TEST SIGNAL GENERATION FUNCTION -35 3.10 PMD-ONLY MODE -35 3.11 INTERRUPT PROCESSING -36 CHAPTER 4 REGISTERS 4.1 REGISTER MAP -39 4.2 REGISTER FUNCTIONS -41 4.2.1 Scrambler/Descrambler ON/OFF Setting Register(SCRR) - 41 4.2.2 Command Register (CMR)- 42 4.2.3 PHY Interrupt Source Register (PICR) - 43 4.2.4 PHY Interrupt Mask Register (PIMR) - 44 4.2.5 Discarded Cell Counter (DCCOU)- 45 4.2.6 LOS Information Register (LOSERR) - 45 4.2.7 LOS Interrupt Mask Register (LOSMSK) - 46 4.2.8 PMD Loop-Back 1 Setting Register (LBPMDT)- 46 4.2.9 PMD Loop-Back 2 Setting Register (LBPMDU) - 47 4.2.10 ATM Loop-Back Setting Register (LBATM)- 47 4.2.11 FIFO Overflow Registers (FIFOOVT/FIFOOVR) - 48 4.2.12 FIFO Overflow Interrupt Mask Registers (FOVTMSK/FOVRMSK) - 49 4.2.13 PHY Address Register (PHYADD)- 50 4.2.14 Test Pattern Generation Function Select Register (TSTMOD) - 51 4.2.15 PMD Standby Register (PMDSTBY) - 52 4.2.16 Idle Cell Discard Specification Register (DMODE1) - 53 4.2.17 Idle Cell Discard Condition Setting Register (DMODE2) - 53 4.2.18 Discarded Cell Counter Overflow Information Register (DCINFO) - 54 4.2.19 Discarded Cell Counter Overflow Interrupt Mask Register Information Register (DCMASK) - 54 4.2.20 Self Test 1 (Internal HEC Error) Register (SELFTST1) - 55 4.2.21 Self Test 2 (Internal 4B5B Code Error) Register (SELFTST2) - 55 4.2.22 X_8 Transmission Enable Register (X8_IN)- 56 CHAPTER 5 JTAG BOUNDARY SCAN 5.1 FEATURES-57 FEATURES-57 5.2 INTERNAL CONFIGURATION OF BOUNDARY SCAN CIRCUIT-58 CIRCUIT-58 5.2.1 5.2.2 5.2.3 5.2.4 Instruction register TAP controller Bypass register Boundary scan register 5.3 PIN FUNCTION -59 VI 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 JCK pin JMS pin JDI pin JDO pin JRST_B pin 5.4 OPERATION DESCRIPTION-60 DESCRIPTION-60 5.4.1 TAP controller 5.4.2 TAP controller state 5.5 TAP CONTROLLER OPERATION -65 5.6 INITIALIZING TAP CONTROLLER -68 5.7 INSTRUCTION REGISTER -68 5.7.1 BYPASS Instruction 5.7.2 EXTEST instruction 5.7.3 Boundary scan data bit definition CHAPTER 6 THE EXAMPLE OF APPLICATION 6.1 CONNECTION WITH PE-67588 PE-67588 MAGNETICS -72 6.2 CONNECTION WITH TLA-6M102 TLA-6M102 MAGNETICS -74 6.3 BOARD LAYOUT -76 Note: NEASCOT and NEASCOT-T20 NEASCOT-T20 are trademarks of NEC Corporation. VII CHAPTER 1 OVERVIEW TM The NEASCOT-T20 NEASCOT-T20 is an LSI chip for the 25.6Mbps ATM physical layer. The chip provides the TC sub-layer functions and PMD sub-layer functions. The chip supports UTOPIA Level 2 as an interface from/to an ATM/AAL layer LSI chip. 1.1 FEATURES · 25.6-Mbps ATM PHY (PMD & TC) functions for six ports · Conforms to ATM Forum PHY Interface spec. (af-phy-0040.000 November 1995) · UTOPIA Level2 V1.0(af-phy-0039.000 June 1995: MAX.8bit / 40MHz) Interface · 3 sell transmit / receive FIFOs per each port · PMD sublayer functions a) Internal clock recovery b) Internal equalizer · TC sublayer functions a) b) c) d) e) NRZI encoder/decoder Command byte insertion/detection 4B/5B encoder/decoder Scrambler/descrambler HEC generation/verification · CPU interface: Intel / Motorola selectable · STP and UTP (categories 3, 4, 5) supported · Loop-back function: Loop-back at the PMD sublayer and ATM layer interfaces · OAM functions: Detection of Loss of Signal, detection of HEC error and 4B/5B code error · Test function: JTAG (IEEE 1149.1) compatible · Supply voltage: 3.3 V ±5% 1.2 ORDERING INFORMATION Part Number µPD98408GD-LML PD98408GD-LML Package 208-pin plastic QFP (FINE PITCH) ( 28mm) 1 1.3 SAMPLE SYSTEM CONFIGURATION (APPLICATION) ATM switching hub #5 µPD98408 PD98408 . . UTOPIA Level 2 #0 UTOPIA Level 2 NIC µPD98408 PD98408 SONET-IF Backbone network ATM-SW UTOPIA Level 2 NIC UTOPIA Level 2 NIC 25-Mbps ATM Interface using UTP (Category 3) CPU Typical System Design 2 Magnetics UTP/STP (cat.3/4/5) Magnetics Receiver Transmit clock (32 MHz) PMD Transmitter PMD loopback 1 Equalizer PMD loopback 2 Clock/data recovery µ PD98408 PD98408 NRZI encoder NRZI decoder CPU bus CPU interface 4B/5B encoder (command byte insertion) 4B/5B decoder (command byte detection) TC Scrambler Descrambler HEC generation HEC verification ATM layer loopback Idle/unassigned cell detector TEST interface JTAG interface Transmit FIFO Receive FIFO Transmit data UTOPIA Level 2 Receive data 1.4 BLOCK DIAGRAM UTOPIA interface Block Diagram 3 1.5 PIN CONFIGURATION 3.3V POWER SUPPLY RDIP0 RDIN0 RxSOC RxENB_B RxADDR0 - RxADDR4 RxCLAV TxDATA0 - TxDATA7 JDI/TCLK0 JDO/RDATA0 ATM Layer Interface 8 TxSOC TxENB_B TxADDR0 - TxADDR4 5 TxCLAV µPD98408 PD98408 TM (NEASCOT - T20 ) DATA0 - DATA7 . 8 6 CPU Interface DS_B/RD_B DTACK_B/RDY_B INT_B TCLOCK SOUT BUSMODE SIN/TDATA5 . ADDR0 - ADDR5 SEL_B RW_B/WR_B IC/RCLK5 IC/TDATA0 IC/RDATA4 IC/RDATA5 IC/TDATA1 IC/TDATA2 IC/TDATA3 IC/TDATA4 PMDONLY 5 TxCLK JCK/TCLK1 JMS/TCLK2 JRST_B/TCLK3 Interface for External TC 8 RxCLK RDIP5 RDIN5 TDOP5 TDON5 IC/TCLK4 IC/TCLK5 RECCLK/RDATA1 IC/RDATA3 IC/RDADA2 IC/RCLK0 DGND RxDATA0 - RxDATA7 TDOP0 TDON0 RESET_B . UTP Interface AGND AGND AGND AGND AGND AGND AGND . DVDD . AVDD AVDD AVDD AVDD AVDD AVDD . . TIMING TRANSMIT RESET CLOCK MARKER (32 MHz) Pin Configuration 4 1.6 PIN CONFIGURATION (Top View) ( 28mm) 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 AGND TDOP5 TDON5 AGND AVDD AVDD AGND RDIP4 RDIN4 AVDD AGND TDOP4 TDON4 AGND AVDD AVDD AGND RDIP3 RDIN3 AVDD AGND TDOP3 TDON3 AGND AVDD AVDD AGND RDIP2 RDIN2 AVDD AGND TDOP2 TDON2 AGND AVDD AVDD AGND RDIP1 RDIN1 AVDD AGND TDOP1 TDON1 AGND AVDD AVDD AGND RDIP0 RDIN0 AVDD AGND AVDD 208-pin plastic QFP (FINE PITCH) AVDD TDOP0 TDON0 AGND AGND AVDD AGND AVDD AGND AVDD AGND IC IC DVDD DGND BUSMODE DS_B/RD_B RW_B/WR_B SEL_B DTACK_B/RDY_B INT_B DGND ADDR0 ADDR1 ADDR2 DGND DVDD ADDR3 ADDR4 ADDR5 DGND DATA0 DATA1 DGND DATA2 DATA3 DVDD DATA4 DATA5 DGND DATA6 DATA7 DGND CG TxENB_B TxCLAV DVDD TxSOC TxADDR0 TxADDR1 DGND DGND 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 DVDD SOUT RESET_B DGND TCLOCK DGND RxDATA7 RxDATA6 DVDD RxDATA5 RxDATA4 DGND RxDATA3 RxDATA2 DGND RxDATA1 RxDATA0 DVDD RxCLK DGND RxADDR4 RxADDR3 DGNG RxADDR2 RxADDR1 DVDD DGND RxADDR0 RxSOC DGND RxCLAV RxENB_B IC DVDD TxDATA7 TxDATA6 DGND TxDATA5 TxDATA4 DGND TxDATA3 TxDATA2 DVDD TxDATA1 TxDATA0 DGND TxCLK DGND TxADDR4 TxADDR3 TxADDR2 DVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 µPD98408GD-LML PD98408GD-LML AVDD RDIN5 RDIP5 AGND IC IC AGND AVDD AGND AVDD AGND AVDD AGND IC IC DVDD DGND PMDONLY IC/RCLK0 IC/RCLK1 IC/RCLK2 DGND IC/RCLK3 IC/RCLK4 IC/RCLK5 DGND DVDD JDI/TCLK0 JCK/TCLK1 JMS/TCLK2 DGND JRST_B/TCLK3 IC/TCLK4 IC/TCLK5 DVDD JDO/RDATA0 RECCLK/RDATA1 IC/RDATA2 DGND IC/RDATA3 IC/RDATA4 IC/RDATA5 DGND IC/TDATA0 IC/TDATA1 IC/TDATA2 DVDD IC/TDATA3 IC/DATA4 SIN/TDATA5 DGND DGND 5 Pin Name ADDR0-ADDR5 AGND AVDD BUSMODE CG DATA0-DATA7 DGND DS_B/RD_B DTACK_B/RDY_B DVDD IC IC/RCLK0C/RCLK5 IC/RDATA2-5 IC/TCLK4, IC/TCLK5 IC/TDATA0-4 INT_B JCK/TCLK1 JDI/TCLK0 : : : : : Address Analog Ground Analog Supply Voltage Bus Mode Connect GND : : : : : : : Data Digital Ground Data Strove/Read Data Acknowledge/Ready Digital Supply Voltage Internal Connect Internal Connect/Receive Clock : Internal Connect/Receive Data RxADDR0RxADDR4 RxCLAV RxCLK RxDATA0RxDATA7 RxENB_B RxSOC SEL_B SIN/TDATA5 SOUT TCLOCK TDON0-TDON5 : Receive Cell Available : Receive Data Clock : Receive Data : Receive Enable : Receive Start Address of ATM Cell : Selector : Signal In/Transmit Data : Signal Out : Transmit Clock : Internal Connect/Transmit Clock : Internal Connect/Transmit Data TDOP0-TDOP5 TxADDR0-4 : Transmit Data Output Negative : Transmit Data Output Positive : Transmit Address : Interrupt : JTAG Test Clock/Transmit Clock : JTAG Test Data Input/ TxCLAV TxCLK : Transmit Cell Available : Transmit Data Clock TxDATA0- : Transmit Data Transmit Clock TxDATA7 : JTAG Test Data Output/ TxENB_B Receive Data TxSOC JMS/TCLK2 : JTAG Test Mode Select/ Transmit Clock JRST_B/TCLK3 : JTAG Test Reset/Transmit Clock PMDONLY : PMD Only RDIN0-RDIN5 : Receive Data Input Negative RDIP0-RDIP5 : Receive Data Input Positive RECCLK/RDATA1 : Recovery Clock/Receive Data RESET_B : Reset RW_B/WR_B : Read Write/Write JDO/RDATA0 : Receive Address : Transmit Enable : Transmit Start Address of ATM Cell 6 CHAPTER 2 PIN FUNCTIONS 2.1 PIN FUNCTIONS (1) POWER SUPPLY Pin name Pin No. I/O Function AVDD 1, 8, 10, 12, 147, 149, 151, 156, 157, 159, 163, 164, 169, 173, 174, 179, 183, 184, 189, 193, 194, 199, 203, 204 - +3.3-volt power input for analog section DVDD 16, 27, 35, 47, 53, 61, 70, 78, 86, 95, 104, 110, 120, 130, 143 - +3.3-volt power input for digital section AGND 4, 7, 9, 11, 148, 150, 152, 153, 158, 162, 165, 168, 172, 175, 178, 182, 185, 188, 192, 195, 198, 202, 205, 208,13,146 - Ground input for analog section DGND 17, 22, 26, 31, 39, 43, 51, 52, 56, 58, 64, 67, 72, 75, 79, 82, 89, 92, 98, 100, 105, 106, 114, 117, 123, 126, 131, 135, 142 - Ground input for digital section As for the way of VDD and GND connection , refer to chapter 6. 7 (2) CABLE INTERFACE Pin name Pin No. I/O RDIP0 161 I Function Receive data input from port #0 (Balanced analog signal input) RDIN0 160 I Receive data input from port #0 (Balanced analog signal input) TDOP0 155 O Transmit data output to port #0 (Balanced analog signal output) TDON0 154 O Transmit data output to port #0 (Balanced analog signal output) RDIP1 171 I Receive data input from port #1 (Balanced analog signal input) RDIN1 170 I Receive data input from port #1 (Balanced analog signal input) TDOP1 167 O Transmit data output to port #1 (Balanced analog signal output) TDON1 166 O Transmit data output to port #1 (Balanced analog signal output) RDIP2 181 I Receive data input from port #2 (Balanced analog signal input) RDIN2 180 I Receive data input from port #2 (Balanced analog signal input) TDOP2 177 O Transmit data output to port #2 (Balanced analog signal output) TDON2 176 O Transmit data output to port #2 (Balanced analog signal output) RDIP3 191 I Receive data input from port #3 (Balanced analog signal input) RDIN3 190 I Receive data input from port #3 (Balanced analog signal input) TDOP3 187 O Transmit data output to port #3 (Balanced analog signal output) TDON3 186 O Transmit data output to port #3 (Balanced analog signal output) RDIP4 201 I Receive data input from port #4 (Balanced analog signal input) RDIN4 200 I Receive data input from port #4 (Balanced analog signal input) TDOP4 197 O Transmit data output to port #4 (Balanced analog signal output) TDON4 196 O Transmit data output to port #4 8 (Balanced analog signal output) RDIP5 3 I Receive data input from port #5 (Balanced analog signal input) RDIN5 2 I Receive data input from port #5 (Balanced analog signal input) TDOP5 207 O Transmit data output to port #5 (Balanced analog signal output) TDON5 206 O Transmit data output to port #5 (Balanced analog signal output) 9 3)UTOPIA INTERFACE Pin name Pin No. I/O Function RXDATA0 RXDATA7 69, 68, 66, 65, 63, 62, 60, 59 O (3-state output) These pins constitute an 8-bit data bus that outputs the receive data to an ATM layer device. The data is output at the rising edge of RXCLK. RXCLK 71 I This pin supplies clock signals for the receive data to an ATM layer device. RXSOC 81 O (3-state output) This pin outputs a receive cell start position signal. The signal informs an ATM layer device the position of the first byte of a receive cell. At the first byte, RXSOC is set to 1. RXENB_B 84 I This pin inputs a output enable signal for RXDATA0RXDATA7 and RXSOC. When the signal is set to 0, the outputs from RXDATA0-RXDATA7 and RXSOC are enable. RXADDR0 RXADDR4 80, 77, 76, 74, 73 I These pins input signals indicating the address of µPD98408 PD98408. RXCLAV 83 O (3-state output) TXDATA0 TXDATA7 97, 96, 94, 93, 91, 90, 88, 87 I These pins constitute an 8-bit data bus that inputs the transmit data from an ATM layer device. The data is input at the rising edge of TXCLK. TXCLK 99 I This pin supplies clock signals for the transmit data from an ATM layer device. TXSOC 109 I This pin inputs a transmit cell start position signal. The signal indicates the position of the first byte of a transmit cell input from an ATM layer device. At the first byte, TXSOC is set to 1. TXENB_B 112 I This pin inputs a transmission enable signal. The signal indicates whether an ATM layer device outputs valid transmit data to TXDATA0 to TXDATA7. When valid data is output, the signal is set to 0. Otherwise, the signal is set to 1. TXADDR0 TXADDR4 108, 107, 103, 102, 101 I These pins input signals indicating the address of µPD98408 PD98408. Used to transmit data. TXCLAV 111 O (3-state output) This pin outputs receive cell available signal. When µPD98408 PD98408 has a complete output cells, asserts RXCLAV high to indicate for transfer to ATM layer device. This pin outputs transmit cell available signal. When µPD98408 PD98408 can accept receive cells, asserts TXCLAV high to indicate to ATM layer device. 10 4)CPU INTERFACE Pin name Pin No. I/O BUSMODE 141 I DATA0 - DATA7 125, 124, 122, 121, 119, 118, 116, 115 I/O ADDR0-ADDR5 134, 133, 132, 129, 128, 127 I These pins set the address (6 bits) of an internal register. SEL_B 138 I DS_B/RD_B 140 I This pin enables or disables register access. When set to 0, access is enabled. · When BUSMODE is set to 0, the input of this pin functions as a data strobe (DS_B) signal of the Motorola-compatible interface. In a read cycle: DS_B, when set to 0, enables read data. In a write cycle: DS_B, when set to 0, functions as a write data strobe signal. RW_B/WR_B 139 I Function This pin selects the operating mode of the CPU interface. 0: style (Motorola compatible) 1: style (Intel compatible) These pins transfer data (8 bits) between the CPU and internal registers. DATA7 corresponds to the most significant bit. · When BUSMODE is set to 1, the input of this pin functions as a read instruction of the Intel-compatible interface. RD_B, when set to 0, functions as a read instruction. · When BUSMODE is set to 0, the input of this pin functions as a read/write control (RW_B) signal of the Motorolacompatible interface. 0: Write cycle 1: Read cycle · When BUSMODE is set to 1, the input of this pin functions as a write instruction of the Intel-compatible interface. WR_B, when set to 0, functions as a write instruction. DTACK_B /RDY_B 137 O · When BUSMODE is set to 0, the output of this pin functions as an acknowledge signal (DTACK_B) of the Motorola-compatible interface. The signal indicates whether data transmission on the data bus has been completed. Once data transmission has been completed, DTACK_B is driven to 0. · When BUSMODE is set to 1, the output of this pin functions as a ready signal (RDY_B) of the Intelcompatible interface. The signal indicates whether data transmission on the data bus has been completed. Once data transmission has been completed, RDY_B is driven to 0. INT_B 136 O The output of this pin informs the CPU that an interrupt source has been detected. 11 5)OTHER PINS Pin name Pin No. I/O JDI/TCLK0 28 I Function This pin has two functions. The status of the PMDONLY pin determines the current function of the pin. · When the PMDONLY pin is set to 0: (JDI) This pin functions as a JTAG test data input. · When the PMDONLY pin is set to 1: (TCLK0) This pin functions as a transmit clock input for the PMD transmission block (port #0). JDO/RDATA0 36 O This pin has two functions. The status of the PMDONLY pin determines the current function of the pin. · When the PMDONLY pin is set to 0: (JDO) This pin functions as a JTAG test data output. · When the PMDONLY pin is set to 1: (RDATA0) This pin functions as a receive data output from the PMD reception block (port #0). JCK/TCLK1 29 I This pin has two functions. The status of the PMDONLY pin determines the current function of the pin. · When the PMDONLY pin is set to 0: (JCK) This pin functions as a clock input for the JTAG test. · When the PMDONLY pin is set to 1: (TCLK1) This pin functions as a transmit clock input for the PMD transmission block (port #1). JMS/TCLK2 30 I This pin has two functions. The status of the PMDONLY pin determines the current function of the pin. · When the PMDONLY pin is set to 0: (JMS) This pin functions as a JTAG test mode input. · When the PMDONLY pin is set to 1: (TCLK3) This pin functions as a transmit clock input for the PMD transmission block (port #2). JRST_B /TCLK3 32 I This pin has two functions. The status of the PMDONLY pin determines the current function of the pin. · When the PMDONLY pin is set to 0: (JRST_B) This pin inputs the JTAG test reset signal. · When the PMDONLY pin is set to 1: (TCLK3) This pin functions as a transmit clock input for the PMD transmission block (port #3). 12 IC/TCLK4 33 I This pin has two functions. The status of the PMDONLY pin (with pull-down determines the current function of the pin. resistor) · When the PMDONLY pin is set to 0: (IC) This pin should be left open. · When the PMDONLY pin is set to 1: (TCLK4) This pin functions as a transmit clock input for the PMD transmission block (port #4). IC/TCLK5 34 I This pin has two functions. The status of the PMDONLY pin (with pull-down determines the current function of the pin. resistor) · When the PMDONLY pin is set to 0: (IC) This pin should be left open. · When the PMDONLY pin is set to 1: (TCLK5) This pin functions as a transmit clock input for the PMD transmission block (port #5). RECCLK 37 O /RDATA1 This pin has two functions. The status of the PMDONLY pin determines the current function of the pin. · When the PMDONLY pin is set to 0: (RECCLK) This pin functions as a recovery clock output from the receive data. The pin outputs the recovery clock of port #0. · When the PMDONLY pin is set to 1: (RDATA1) This pin functions as a receive data output from the PMD reception block (port #1). IC/RDATA3 40 O This pin has two functions. The status of the PMDONLY pin determines the current function of the pin. · When the PMDONLY pin is set to 0: (IC) This pin should be left open. · When the PMDONLY pin is set to 1: (RDATA3) This pin functions as a receive data output from the PMD reception block (port #3). IC/RDATA2 38 O This pin has two functions. The status of the PMDONLY pin determines the current function of the pin. · When the PMDONLY pin is set to 0: (IC) This pin should be left open. · When the PMDONLY pin is set to 1: (RDATA2) This pin functions as a receive data output from the PMD reception block (port #2). 13 IC/RCLK0 RCLK5 19, 20, 21, 23, 24, 25 I/O (with pull-down resistor) These pins have two functions. The status of the PMDONLY pin determines the current function of the pin. · When the PMDONLY pin is set to 0: (IC) These pins should be left open. · When the PMDONLY pin is set to 1: (RCLK0-5) These pins functions as a receive clock output from the PMD reception block (ports #0 to #5). IC/TDATA0 44 I (with pull-down resistor) This pin has two functions. The status of the PMDONLY pin determines the current function of the pin. · When the PMDONLY pin is set to 0: (IC) This pin should be left open. · When the PMDONLY pin is set to 1: (TDATA0) This pin functions as a transmit data input for the PMD transmission block (port #0). IC/RDATA4 41 O This pin has two functions. The status of the PMDONLY pin determines the current function of the pin. · When the PMDONLY pin is set to 0: (IC) This pin should be left open. · When the PMDONLY pin is set to 1: (RDATA4) This pin functions as a receive data output from the PMD reception block (port #4). IC/RDATA5 42 O This pin has two functions. The status of the PMDONLY pin determines the current function of the pin. · When the PMDONLY pin is set to 0: (IC) This pin should be left open. · When the PMDONLY pin is set to 1: (RDATA5) This pin functions as a receive data output from the PMD reception block (port #5). IC/TDATA1 45 I (with pull-down resistor) This pin has two functions. The status of the PMDONLY pin determines the current function of the pin. · When the PMDONLY pin is set to 0: (IC) This pin should be left open. · When the PMDONLY pin is set to 1: (TDATA1) This pin functions as a transmit data input for the PMD transmission block (port #1). 14 IC/TDATA2 46 I This pin has two functions. The status of the PMDONLY pin (with pull-down determines the current function of the pin. resistor) · When the PMDONLY pin is set to 0: (IC) This pin should be left open. · When the PMDONLY pin is set to 1: (TDATA2) This pin functions as a transmit data input for the PMD transmission block (port #2). IC/TDATA3 48 I This pin has two functions. The status of the PMDONLY pin (with pull-down determines the current function of the pin. resistor) · When the PMDONLY pin is set to 0: (IC) This pin should be left open. · When the PMDONLY pin is set to 1: (TDATA3) This pin functions as a transmit data input for the PMD transmission block (port #3). IC/TDATA4 49 I This pin has two functions. The status of the PMDONLY pin (with pull-down determines the current function of the pin. resistor) · When the PMDONLY pin is set to 0: (IC) This pin should be left open. · When the PMDONLY pin is set to 1: (TDATA4) This pin functions as a transmit data input for the PMD transmission block (port #4). SIN/TDATA5 50 I This pin has two functions. The status of the PMDONLY pin (with pull-down determines the current function of the pin. resistor) · When the PMDONLY pin is set to 0: (SIN) This pin functions as the X_8 command transmission timing input. · When the PMDONLY pin is set to 1: (TDATA5) This pin functions as a transmit data input for the PMD transmission block (port #5). SOUT 54 O This pin functions as the X_8 command reception timing output. This pin specifies whether this chip is operated as PMD + TC I or as PMD. (with pull-down 0: The chip is operating as PMD + TC. resistor) 1: The chip is operating as PMD. PMDONLY 18 TCLOCK 57 I This pin supplies a transmit clock (32 MHz). RESET_B 55 I This pin inputs the signal to reset the entire chip. IC 5, 6, 14, - These pins should be left open. I This pin should be connected to DGND. 15, 85, 144,145 CG 113 15 2.2 RECOMENDED CONNECTION FOR UNUSED PINS Pin Name Input/Output Recommended connection for unused pins RDIP0-RDIP5 Input pull-up through 1k the resistor RDIN0-RDIN5 Input pull-down through 1k the resistor TDOP0-TDOP5 Output open TDON0-TDON5 Output open JDI/TCLK0 Input pull-up through resistor JDO/RDATA0 Output open JCK/TCLK1 Input pull-up through resistor JMS/TCLK2 Input pull-up through resistor JRST_B/TCLK3 Input pull-down through resistor IC/TCLK4 Input (with pull-down resistor) open IC/TCLK5 Input (with pulll-down resistor) open RECCLK/RDATA1 Output open IC/RDATA3 Output open IC/RDATA2 Output open IC/RCLK0-5 Output/Input (with pull-down resistor) open IC/TDATA0 Input (with pull-down resistor) open IC/RDATA4 Output open IC/RDATA5 Output open IC/TDATA1 Input (with pull-down resistor) open IC/TDATA2 Input (with pull-down resistor) open IC/TDATA3 Input (with pull-down resistor) open IC/TDATA4 Input (with pull-down resistor) open SIN/TDATA5 Input (with pull-down resistor) open SOUT Output open PMDONLY Input (with pull-down resistor) open 16 2.3 PIN CONDITIONS WHILE RESET During reset, the state of output pins is as follows. Pin Name Input/Output Pin conditions while reset TDOP0-TDOP5 Output Unknown TDON0-TDON5 Output Unknown RXDATA0-RXDATA7 Output (3-state) Hi-Z RXSOC Output (3-state) Hi-Z RXCLAV Output (3-state) Hi-Z TXCLAV Output (3-state) Hi-Z DATA0-DATA7 Input/Output Hi-Z DTACK_B/RDY_B Output High INT_B Output High JDO/RDATA0 Output Unknown RECCLK/RDATA1 Output Unknown SOUT Output Low 17 CHAPTER 3 FUNCTION OVERVIEW 3.1 PMD SUBLAYER PMD Sublayer 0 PMD loop-back 2 instruction PMD loop-back 1 instruction RDIP_0 RDIN_0 Equalizer Clock & Data Recovery Comparator Receive data Receive clock Rx selector UTP I/F TC SUBLAYER Loop-back data TDOP_0 TDON_0 Latch Driver Transmit data Transmit clock Tx selector . . . . PMD Sublayer 5 PMD Sublayer Block Diagram 18 3.1.1 Equalizer This block equalizes a UTP cable. 3.1.2 Comparator This block receives the equalized data and checks whether the data is high or low. 3.1.3 Clock and Data Recovery This block reproduces the clock and data from the input receive data. When the circuit is in idle status (no command and valid data should be send), but µPD98408 PD98408 is sending dummy data, which are scrambled and 4B5B block encoded. And the reverse equipment in idle status is sending dummy data, too, according to ATM Forum (af-phy0040.000). The clock and data recovery can start working. After the receive side detect X_X and X_4 commands, µPD98408 PD98408 begins to receive cell as valid data. 3.1.4 Latch This block latches the transmit data from the TC sublayer to the transmit clock. 3.1.5 Driver This block drives a transmit transformer with differential output. 3.1.6 Tx Selector This block functions as a selector of the transmission side. It is used for the reception loopback test. At the test, this selector inputs the output of the clock and data recovery block to the driver block. 3.1.7 Rx Selector This block functions as a selector of the reception side. It is used for the transmission loopback test. At the test, this selector selects Loop-back data as input to the clock and data recovery block. 19 3.2 3.2.1 TC SUBLAYER LOS Detection If the receive data signal is left unchanged in the receive section, this status is judged to be a loss of signal, and an alarm is raised. According to the condition of detection and cancellation, see 3.7.1 LOS detection function. 3.2.2 NRZI Encoding and Decoding The transmission section converts NRZ codes into NRZI codes. The reception section converts the NRZI codes back to NRZ codes. H H H L L L H H H L L L NRZ NRZI DECODE H L H H H H L NRZI ENCODE H L L L L NRZI NRZ Code and NRZI Code 20 3.2.3 Command-Byte Insertion and Detection In 25.6Mbps ATM Interface, command bytes are defined for cell boundary detection and timing signal insertion. (1) X_X is inserted into the top of cell for cell boundary detection. And it means reset of receive side. (2) X_4 is inserted into the top of cell for cell boundary detection. But it doesn't mean descranbling reset of receive side. (3) X_8 is used to add desired timing information to the transmit data. This command byte is inserted into the transmit data according to the timing signal input from the SIN pin. The command byte is used, for example, to insert an 8-kHz timing signal for voice. While cells are not being transmitted, invalid data is transmitted. Command byte X_8 is also inserted into the invalid data. SYNC_EVENT ATM Cell Cell N-1 Cell N Cell X_4 X_8 X_4 X_X 53 octet N+1 Cell N+2 Example of Cell Delineation and Sync_Event Using Commands 3.2.4 4B5B Block Encoding and Decoding The transmission section divides the 8-bit transmit data into two parts, the high-order 4 bits and the low-order 4 bits, converting each part into a 5-bit symbol as indicated in Table 1. The reception section converts the received 5-bit symbol back into 4-bit data. Data Symbol Data Symbol Data Symbol Data Symbol 0000 10101 0001 01001 0010 01010 0011 01011 0100 00111 0101 01101 0110 01110 0111 01111 1000 10010 1001 11001 1010 11010 1011 11011 1100 10111 1101 11101 1110 11110 1111 11111 ESC (X) 00010 Conversion Table: 4-Bit Command/Data to 5-Bit Symbol 21 3.2.5 Cell Scrambling and Descrambling The transmission section encodes the transmit data into a suitable distribution across the frequency spectrum in order to avoid electromagnetic interference (EMI). The scrambler/descrambler uses a 10bit pseudo random number generator (PRNG) based on the generator polynomial shown below: G(X) = X 10 7 +X +1 + 1 2 3 4 5 6 7 8 9 10 X X X X X X X X X X + 0 D Key dx d0 + 1 D + 2 D + = unscrambled data bit D3 (msb) d1 D x = scrambled data bit + = exclusive or d2 d3 Block Diagram of Pseudo Random Number Generator µPD98408 PD98408 scramble ATM cells (53 bytes). But it does not scramble command bytes. The descrambler decodes the data by EXCLUSIVE ORing the scrambled data and the random number used for scrambling the data. The data can be decoded only when identical random numbers are used in scrambling and descrambling. The PRNG is periodically reset to match the pseudo random numbers used for encode and decode. The transmission side resets the scrambler PRNG at the beginning of a cell and adds command byte X_X to the cell. The reception side resets the descrambler PRNG at the beginning of the cell if the command byte detector detects X_X. µPD98408 PD98408 automatically sends X_X command at intervals according to the internal timer for the scrambler reset. If there is a period during which no available cells are transmitted, the chip resets the scrambler at the beginning of the next available cell transmission. The operation of the scrambler/descrambler can be stopped by setting registers. 22 3.2.6 HEC Generation and Verification The transmission section executes a CRC operation for the header of a transmit cell and generates HEC. (1) The following polynomial, having each bit of the 4-byte (32-bit) header except the HEC field 8 31 30 29 in ATM cell as coefficients, is multiplied by X : H(X) = a X + a X + a X + . + 31 30 29 a X+a . 1 0 8 2 (2) The result is divided by this generator polynomial: G(X) = X + X + X + 1 (operation of modulo-2). (3) Then, 55(H) is subtracted (exclusive OR) from the remainder of the division. This result is written into the HEC field (last byte of the ATM cell header area). The reception section executes a CRC operation for the header of a receive cell and verifies the HEC field. (1) 55(H) is subtracted (exclusive OR) from the following polynomial, having each bit of the 539 38 byte (40-bit) header including the HEC field as coefficients: H(X) = a X + a X + 39 38 37 a X + . + a X + a . 37 1 0 8 2 (2) The result is divided by this generator polynomial: G(X) = X + X + X + 1 (operation of modulo-2). (3) If the remainder is 0, there is no header error. If the remainder is not 0, a header error exists. According to the header error cell, the following two processing can be chosen by the setting of the HECERM bit of command register (CMR). HECERM=0 Discard the header error cell HECERM=1 Transmit the cell to the ATM layer device with the defective header 3.2.7 Idle/Unassigned Cell Detection The reception section detects an idle or unassigned cell and discards the cell according to the cell discard judgment condition setting register (DMODE2) settings. Mode 1: The cell is discarded when VPI is set to 0 (GFC not set to 0) and when VCI is set to 0. Mode 2: The cell is discarded when VPI is set to 0 (GFC set to 0) and when VCI is set to 0. Mode 3: An idle or unassigned cell is not discarded. 23 3.3 ATM LAYER (UTOPIA) INTERFACE The ATM layer interface of the µPD98408 PD98408 conforms to UTOPIA level 2 Specification Version 1.0, as specified by the ATM Forum. The ATM layer interface is used to transfer data between the µPD98408 PD98408 and ATM layer device. UTOPIA level 2 supports a multi-PHY interface, which features multiple PHY ports. In this case, it transmits data while choosing PHY port using address, TxADDR and RxADDR. The PHY port used to transmit or receive data is determined by means of polling by the ATM layer device. 3.3.1 Transmit Interface The ATM layer device sets the address of each PHY port in TXADDR during cell transmission in order to check the TXCLAV status of the port. The PHY port whose address is set in TXADDR drives TXCLAV active at the next clock cycle when it is ready to receive a cell from the ATM layer device. Otherwise, it drives TXCLAV inactive. The ATM layer device selects one of the PHY ports that are ready to receive cells and sets the port address in TXADDR immediately before TXENB_B is negated. When TXENB_B is negated, the ATM layer device starts cell transmission to the PHY port. Then, the ATM layer device begins the next polling to determine another PHY port to which a cell can be transmitted. selection polling polling: 1 2 3 4 5 6 polling 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TXCLK TXADDR 1F N+2 1F N-3 1F N-2 1F N-1 1F N+3 N+1 1F N N+3 N-3 TXCLAV 1F N+2 N-2 1F N N-1 N+3 1F N+1 1F N+1 1F N+3 N+1 N+1 TXENB_B TXDATA P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 H1 H2 H3 H4 TXSOC cell transmission to: PHY N PHY N+3 Polling and Selection Phases at Transmit Interface 24 3.3.2 Receive Interface The ATM layer device sets the address of each PHY port in RXADDR during cell transmission in order to check the RXCLAV status of the PHY port. The PHY port whose address is set in RXADDR drives RXCLAV active at the next clock cycle when it has a cell to be output to the ATM layer device. Otherwise, it drives RXCLAV inactive. The ATM layer device selects one of the PHY ports that can output a cell and sets the port address in RXADDR immediately before RXENB_B is negated. When RXENB_B is negated, the PHY port starts cell transmission to the ATM layer device. Then, the ATM layer device begins the next polling to determine another PHY port to output a cell. selection polling polling polling: 1 2 3 4 5 6 8 7 9 10 11 12 13 14 15 16 17 18 19 20 RXCLK RXADDR RXCLAV N+2 1F N-3 1F N-2 1F N-1 1F N+3 1F N+1 1F N-1 1F N+3 N+3 N-3 N+2 N-2 1F N+1 1F N-1 1F N+3 N-1 N+1 N+1 N-1 N-1 RXENB_B RXDATA P35 P36 P37 P38 P39 P40 P41 P42 P43 P44 P45 P46 P47 P48 H1 H2 H3 H4 RXSOC cell transmission from: PHY N PHY N+3 Polling and Selection Phases at Receive Interface 25 3.3.3 FIFO Block The FIFO block adjusts the timing of the µPD98408 PD98408 and ATM layer device. The transmission and reception sections each have a FIFO block having a depth of three cells per port. (1) FIFO of the transmission section This block has an ATM layer device and a buffer function for signaling rate conversion from the data of the ATM Layer device into internal data for the µPD98408 PD98408. When the writing of a third cell starts in the FIFO of the transmission section, TXCLAV is negated to indicate that the FIFO is full. If an overflow occurs, it is reported to the CPU. (2) FIFO of the reception section This block has a buffer function for signaling rate conversion from µPD98408 PD98408 internal data into ATM layer device data. If this FIFO contains no other cells to be transmitted when transmission to UTOPIA starts, RXCLAV is negated to indicate that this block is empty. If an overflow occurs, it is reported to the CPU. Note: When compelling discarding the data which is stored in transmit and receive FIFO, reset the LSI. The data can not be discarded, depending on ENn7 bit in the PHY address (PHYADD) register. 3.4 LOOP-BACK MODE 3.4.1 PMD Loop-Back 1 TRANSMITTER LATCH PMD BLOCK UTOPIA BUS UTP TC BLOCK RX CLOCK EQUALIZER RECEIVER SELECTOR RECOVERY UTOPIA INTERFACE The transmit data is returned to the reception section of the PMD sublayer. PMD Loop-Back 1 26 3.4.2 PMD Loop-Back 2 TRANSMITTER TX SELECTOR CLOCK RECOVERY LATCH PMD BLOCK UTOPIA BUS UTP RECEIVER TC BLOCK EQUALIZER UTOPIA INTERFACE The receive data is returned to the transmission section of the PMD sublayer. PMD Loop-Back 2 3.4.3 ATM Layer Loop-Back RECEIVE FIFO PARALLEL TO SERIAL UTOPIA BUS SERIAL TO SELECTOR PARALLEL UTOPIA INTERFACE TC SUBLAYER UTP PMD SUBLAYER The transmit data is returned to the reception section of the ATM layer interface. TRANSMIT FIFO ATM Layer Loop-Back 27 3.4.4 Transmit Data Select Function at Loop-Back The data to be transmitted to the circuit executing PMD loop-back 1 or ATM layer loop-back can be selected from the following: · Normal cell data (same data as the loop-back data) · Recurring data 01010101. · All-zero data The CMR register (address = 00H) selects identical circuit transmit data at loop-back for all of the six circuits. The circuit transmit data selection at loop-back is valid only when PMD loopback 1 or ATM layer loop-back is executed. Otherwise, the normal cell data is output, irrespective of the setting of the CMR register. 28 3.5 CPU INTERFACE The CPU interface provides an interface to the bus of the processor used to control the µPD98408 PD98408. The µPD98408 PD98408 supports two interfaces: one compatible with Motorola processors and the other compatible with Intel processors. The current CPU interface is determined by the status of the BUSMODE pin at a hardware reset. BUSMODE=`1' : style (Intel-compatible) BUSMODE=`0' : style (Motorola-compatible) "DS_B, RW_B, DTACK_B" type interface (Motorola 68K, Intel i960 compatible) "RD_B, WR_B, RDY_B" type interface (Intel compatible) Management Entity (uP) 6 8 1 1 1 ADDR[5.0] DATA[7.0] 1 1 RDY_B INT_B SEL_B WR_B RD_B 6 PHY Layer Management Entity (uP) 8 1 1 1 1 1 BUSMODE=`1' ADDR[5.0] DATA[7.0] SEL_B RW_B DS_B PHY Layer DTACK_B INT_B BUSMODE=`0' CPU Interface 29 3.5.1 Write Cycle In the ATM layer, a write cycle is executed when: An address is driven onto ADDR; the data to be written is brought onto DATA, and a suitable strobe signal is asserted. In the PHY layer, the completion of transmission is reported when RDY_B (DTACK_B) is driven and asserted within a predetermined period. If not selected, DATA enter the high-impedance state. If BUSMODE is set to 1, data is strobed when WR_B is asserted while RD_B is high. If BUSMODE is set to 0, data is strobed when DS_B is asserted and while RW_B is set to 0. Figure 14 shows the write timings. ADDR SEL_B BUSMODE = `0' BUSMODE = `1' DATA WR_B RD_B RDY_B DS_B RW_B DTACK_B Single Data Byte Write Transfer 30 3.5.2 Read Cycle In the ATM layer, a read cycle is executed when: An address is driven onto ADDR, and SEL_B and a suitable strobe signal are asserted. In the PHY layer, RDY_B (DTACK_B) is driven within a predetermined period and the requested data is brought onto DATA. Then, RDY_B (DTACK_B) is asserted to report that transmission has been completed. If not selected, DATA enter the high-impedance state. If BUSMODE is set to 1, data is strobed when RD_B is asserted while WR_B is high. If BUSMODE is set to 0, data is strobed when DS_B is asserted and when RW_B is set to 1. Figure 15 shows the read timings. ADDR SEL_B BUSMODE = `1' RD_B BUSMODE = `0' DATA DS_B WR_B RDY_B RW_B DTACK_B Single Data Byte Read Transfer 31 3.6 PSEUDO ERROR GENERATION FUNCTION The µPD98408 PD98408 has a pseudo error generation function for generating an HEC error and 4B5B code error on the transmission side. When this function is combined with PMD loop-back 1, selftest of the error cell reception function can be executed. A HEC or 4B5B code error is generated according to the register settings. While the registers are being set, errors are continuously inserted. As well as the HEC error, 4B5B code errors are inserted into valid cells only. Errors are inserted only when cells are transmitted. 3.7 ERROR/FAILURE DETECTION FUNCTIONS The µPD98408 PD98408 features the following error/failure detection functions: · LOS (loss of signal) detection function · HEC error detection function · 4B5B code error detection function · Transmit FIFO overflow detection function · Receive FIFO overflow detection function · Function for counting the number of cells discarded on the reception side · Overflow detection function for the counter used to count the number of cells discarded on the reception side When any of the following is detected, an interrupt to the CPU can be generated: · LOS (loss of signal) · Transmit FIFO overflow · Receive FIFO overflow · Overflow of the discarded cell counter of the reception side 32 3.7.1 LOS (Loss of Signal) Detection Function µPD98408 PD98408 detect LOS occurrence in two kinds of following way. When meeting either condition (1) or (2), the bit of the LOS information register (LOSERR) shows 1 and the interrupt into the CPU generate. (The interrupt can be masked per port) (1) when the receive signal doesn't change for about 11µsec (346 clocks at 32MHz TCLOCK) or longer (2) when 4B5B code error happens for about 224µsec (7168 clocks at 32MHz TCLOCK) And the condition of LOS status is clear, when 4B5B code error doesn't happen for about 224µsec. Note: Immediately after reset, µPD98408 PD98408 becomes LOS occurrence status at all the ports. And µPD98408 PD98408 becomes LOS clear status for about 224µsec at least. µ After port connection, the host CPU have to read LOS information register (LOSERR) and confirm LOS clear status (the LSn bit=0). Then, the host CPU should cancel a interrupt mask by the LOS occurrence. 3.7.2 HEC Error/4B5B Code Error Detection Function Cells are checked for an HEC or 4B5B code error. If such an error is detected, the corresponding cell is discarded, and the discarded cell counter is incremented. A single counter is used to count the total number of HEC and 4B5B code errors. The discarded cell counter is incremented when a cell is discarded due to an error, but not when an idle cell is discarded. If the registers are set so as not to discard a cell in the event of an HEC error, the discarded cell counter is not incremented if an HEC error is detected. The 4B5B code error is detected only within valid cell data and only after command byte X_X or X_4 has been detected. Any 4B5B code error occurring outside the valid cell data is ignored. If a command code other than X_X, X_4, or X_8 is received within cell data, the fact is regarded as a 4B5B code error, such that the discarded cell counter is incremented. When a cell consisting of fewer than 53 bytes is received, the discarded cell counter is not incremented. If the discarded cell counter overflows, an interrupt to the CPU is generated. Meanwhile, the counter is held at the maximum value. 33 3.7.3 Transmit FIFO/Receive FIFO Overflow Detection Function If the transmit FIFO or receive FIFO overflows, the overflow is reported to the CPU as an interrupt. The cell causing the overflow is discarded. The discarded cell counter is not incremented when a cell is discarded due to the FIFO overflow. 3.8 X_8 COMMAND CODE TRANSMIT/RECEIVE FUNCTION 3.8.1 X_8 Command Code Transmit Function Command code X_8 is sent when a pulse signal is input to the SIN pin. At pulse signal input, command code X_8 is sent to the circuit which is enabled for X_8 transmission by register setting. The pulse input to the SIN pin should have a pulse width of at least eleven 32-MHz transmit clocks (TCLK pin). 3.8.2 X_8 Command Code Receive Function When command code X_8 is received, a pulse signal is output to the SOUT pin. The pulse output to the SOUT pin is executed for only one of the six circuits. The single circuit for which the X_8 receive timing signal is output can be selected by setting registers. The pulse width of the pulse signal output to SOUT is fifteen 32-MHz receive clocks, obtained after clock recovery. 34 3.9 TEST SIGNAL GENERATION FUNCTION The µPD98408 PD98408 has a test signal generation function for the transmit pulse mask test and transmit jitter test. The following five test signals are supported: · Recurring signal 010101. · Recurring signal 00110011. · Recurring signal 000111000111. · Recurring signal 0000111100001111. · Recurring signal 00000111110000011111. The desired test signal is selected by setting registers. 3.10 PMD-ONLY MODE The µPD98408 PD98408 can be set to operate as pure PMD device, disabling the TC function (PMD-only mode). When this function is used, the chip functions as a six-port PMD chip. This function is enabled by setting the PMDONLY pin to 1. In PMD-only mode, only PMD blocks functions. The CPU interface and UTOPIA interface are not working. The JTAG interface cannot be used, either. 35 3.11 INTERRUPT PROCESSING The µPD98408 PD98408 has an interrupt output pin INT_B. By using this pin as an interrupt, the µPD98408 PD98408 reports detection of an error and occurrence of a counter overflow to the host. The INT_B signal becomes active if one of the bits of the PHY interrupt cause register (PICR) is set to "1". When the host detects that INT_B has become active, it first reads the PICR register and identifies the interrupt cause. If the cause is LOS, FOVRT, FOVRR or DCCOU, the host also reads the corresponding LOSERR, FIFOOVT, FIFOOVR and DCINFO registers to check the cause of the interrupt. The following figure shows the relationship of the registers to the interrupt cause. The user can mask each interrupt cause. 3.11.1 Interrupt processing If an interrupt is generated and one of the bits of the PICR register is set, INT_B becomes active. Even if the cause of the event no longer exists, the bit status of the register is maintained until the host reads the register, and the INT_B signal remains active. If the host reads the register when the cause of the interrupt no longer exists, the bit of the interrupt cause register is reset and the INT_B signal becomes inactive. In the example in the following figure, the LOS bit of the PICR register is set and the INT_B signal becomes active because LOS is detected. The host reads the PICR and the LOSERR register once. However, the LOS status still persists at this time, the LOS bit of the PICR register is not cleared, and the INT_B signal does not become inactive, either. Although a recovery is later made from the LOS status and the cause of the interrupt no longer exists, the current statuses of the LOS bit and INT_B signal are maintained because the host read the LOSERR register under reset condition. When the host reads the LOSERR register the second time, the LOS status no longer exists. Consequently, the LOS bit of PICR register is reset and the INT_B signal becomes inactive at the same time. Cautions: Each cause bit may be set due to reception of an undefined frame immediately after power application to the µPD98408 PD98408. After power application, therefore, clear all the interrupt cause registers to 0 by using LSI hardware reset. 36 Interrupt Cause Register Bit and INT_B Signal Detection Event(LOS Detection) Undetection 1 LOS bit of PICR 0 H INT_B L Read PICR by host Read LOSERR by host Reset condition: Register read by the host when interrupt cause no longer exists 37 Relationship between Interrupt Cause Registers PHY Interrupt Cause register (PICR) Interrupt cause detail register - INT_B becomes active if one of the bits of this register is set to "1". Mask Register - The user can mask the occurrence of an interrupt from each interrupt cause by using the mask register. - When each bit of Interrupt Cause Detail Registers (DCINFO, FIFOOVT, FIFOOVR and LOSERR) is cleared "0", the bit of this register is cleared and INT_B become inactive. PICR register - - - DCC FOV FOV LOS OU RR RT - PIMR register LOS=1: LOS detection of each port LOSERR register LOSMSK register - If at least one bit of this register is set to "1", the LOS bit of PICR register is set. - The condition of the bits cleared is register read by the host when interrupt cause no longer exists FOVRT=1: Occurrence transmit FIFO overflow of each port FIFOOVT register FOVTMSK register - If at least one bit of this register is set to "1", the FOVRT bit of PICR register is set. - When read by host, the bits are cleared. FOVRR=1: Occurrence receive FIFO overflow of each port FIFOOVR register FOVRMSK register - If at least one bit of this register is set to "1", the FOVRT bit of PICR register is set. - When read by host, the bits are cleared. DCINFO=1: Occurrence discard cell counter overflow of each port DCINFO register DCMASK register - If at least one bit of this register is set to "1", the DCCOU bit of PICR register is set. - When read by host, the bits are cleared. 38 CHAPTER 4 REGISTERS 4.1 REGISTER MAP (00H TO 3FH) Address Register name 00H SCRR 01H R/W Default value Scrambler/descrambler (ON/OFF setting) R/W 00H CMR Command register R/W 00H 02H PICR PHY interrupt source register R 00H 03H PIMR PHY interrupt mask register R/W 1FH R 00H R 00H 04H to 09H Function DCCOU0-5 Discarded cell counter 0AH LOSERR LOS information register 0BH LOSMSK LOS interrupt mask register R/W 3FH 0CH LBPMDT Loop-back setting register (PMD loop-back 1: TC side) R/W 00H 0DH LBPMDU Loop-back setting register (PMD loop-back 2: UTP side) R/W 00H 0EH LBATM Loop-back setting register (ATM loop-back) R/W 00H 0FH FIFOOVT FIFO overflow information register (transmit) R 00H 10H FIFOOVR FIFO overflow information register (receive) R 00H 11H FOVTMSK FIFO overflow interrupt mask register (transmit) R/W 3FH 12H FOVRMSK FIFO overflow interrupt mask register (receive) R/W 3FH 13H to 18H PHYADD0-5 PHY address and enable register R/W 00H 19H to 1EH TSTMOD0-5 Test pattern mode setting register R/W 00H 23H PMDSTBY PMD standby setting register R/W 00H 26H DMODE1 Cell discard specification register R/W 00H 27H DMODE2 Cell discard judgment condition setting register R/W 00H 29H DCINFO Discarded cell counter overflow information register R 00H 2AH DCMASK Discarded cell counter overflow interrupt mask register R/W 3FH 2BH SELFTST1 Self test 1 register (HEC error occurred) R/W 00H 2CH SELFTST2 Self test 2 register (4B5B code error occurred) R/W 00H R/W 00H - - 2DH X8_IN 2EH to 3FH - X_8 input enable setting register Reserved area 39 (Rules) 1) Notational conventions for writing port numbers The port numbers start from zero. The six internal ports are represented as the 0th, 1st, 2nd, 3rd, 4th, and 5th ports. (Description of notation) 7 00H 6 5 4 3 2 1 0 - - S5 S4 S3 S2 S1 S0 Unused bit (Don't care for reading. Always zero for writing) Register address 40 4.2 REGISTER FUNCTIONS 4.2.1 Scrambler/Descrambler ON/OFF Setting Register (SCRR: Default 00H) (a) Each bit specifies whether the scrambler/descrambler is enabled for the corresponding port. 7 00H R/W 6 - - 5 4 SCR5 SCR4 3 2 1 0 SCR3 SCR2 SCR1 SCR0 SCRn Default 0 (*) 0 Scrambler/descrambler enabled 1 Scrambler/descrambler disabled * SCRn: Bit corresponding to the port #n (n = 0 to 5) 41 4.2.2 Command Register (CMR: Default 00H) (a) The bits specify the following functions (common to all six ports). 7 01H R/W 6 - 5 X8OUT2 4 X8OUT1 3 X8OUT0 LBSEL1 HECERM 2 1 0 LBSEL0 HECGEN HECERM Default 0 0 1 HECGEN HEC error cell discarded HEC error cell transferred Default 0 0 HEC generated 1 HEC not generated (X8OUT2, X8OUT1, X8OUT0) : Sets the port for which X8 receive timing signal is output. (Default (0, 0, 0) (0, 0, 0) Outputs the X8 signal of the 0th port. (0, 0, 1) Outputs the X8 signal of the 1st port. (0, 1, 0) Outputs the X8 signal of the 2nd port. (0, 1, 1) Outputs the X8 signal of the 3rd port. (1, 0, 0) Outputs the X8 signal of the 4th port. (1, 0, 1) Outputs the X8 signal of the 5th port. Others Outputs the X8 signal of the 0th port. (LBSEL1, LBSEL0) : Selects the transmit data at PMD loop-back1 and ATM loop-back. (Default (0, 0) (0, 0) Transmit data from the TC section (0, 1) Recurring data 010101. (1, 0) Stop mode (recurring data 00000.) (1, 1) Disabled Note: HECGEN and HECERM are the setting bits which is common to all the ports. 42 4.2.3 PHY Interrupt Source Register (PICR: Default 00H) (a) Holds an interrupt flag. The DCCOU bit is set to 1 if any bit of the ECINFO register (address 29H) is set to 1. The DCCOU bit is not cleared when the PICR register is read. This bit is automatically set to zero when the bits of the ECINFO register are read and cleared to zero. The FOVRT bit is set to 1 if any bit of the FIFOOVT register (address 0FH) is set to 1. The FOVRT bit is not cleared when the PICR register is read. This bit is automatically set to zero when the bits of the FIFOOVT register are read and cleared to zero. The FOVRR bit is set to 1 if any bit of the FIFOOVR register (address 10H) is set to 1. The FOVRR bit is not cleared when the PICR register is read. This bit is automatically set to zero when the bits of the FIFOOVR register are read and cleared to zero. The LOS bit is set to 1 if any bit of the LOSERR register (address 0AH) is set to 1. The LOS bit is not cleared when the PICR register is read. This bit is automatically set to zero when the bits of the LOSERR register are read and cleared to zero. Reading the LOSERR register during the port LOS state does not cause the bits of the LOSERR register to be cleared to zero, nor the LOS bit of this register to be set to zero. The INT_B pin is driven active (0) when the flag of at least one bit is set. And INT_B pin is driven inactive (1) when the all flag are clear. About the interrupt proceeding detail, see 3.11. An interrupt source itself can be read, with any of the interrupt source mask settings described in 4.2.4. 7 5 - 02H R 6 - - DCCOU 4 3 2 DCCOU FOVRR FOVRT 1 0 LOS - Default 0 0 No discarded cell counter overflow 1 Discarded cell counter overflow occurred FOVRT, FOVRR Default 0 (*) 0 No FIFO overflow 1 FIFO overflow occurred * FOVRT: Transmission side, FOVRR: Reception side LOS Default 0 0 No LOS 1 LOS occurred 43 4.2.4 PHY Interrupt Mask Register (PIMR: Default 1FH) (a) This register mask an interrupt caused by any bit of the PICR register is set to 1. Even while this register is set to mask the interrupt, the interrupt source, as described in Section 4.2.3 (PICR), can be read. 7 6 5 4 03H R/W - - - DCCOU 0 3 2 Default 1 Discarded cell counter overflow interrupt not masked Discarded cell counter overflow interrupt masked DCCOU FOVRR FOVRT 1 LOS 0 1 (*) 1 (*) FOVRT, FOVRR Default 1 0 FIFO overflow interrupt not masked 1 FIFO overflow interrupt masked LOS Default 1 0 LOS interrupt not masked 1 LOS interrupt masked (*) FOVRT: Transmission side, FOVRR: Reception side (*) Don't write "0" 44 4.2.5 Discarded Cell Counter (DCCOU: Default 00H) (a) Holds the accumulated number (0 to 255) of cells that have been discarded due to an error (HEC error, 4B5B error) in each port. When read, the counter is reset to 00H. Upon the occurrence of an overflow, the counter is tied to FFH until it is read. Upon the occurrence of an overflow, the overflowed port number is shown the DCINFOn bits of Discard Cell Counter Information register (DCINFO) and an interrupt to the CPU can be generated at the same time. 7 6 5 4 04H DCCOU07 DCCOU07 DCCOU06 DCCOU06 DCCOU05 DCCOU05 R 3 MSB DCCOU04 DCCOU04 2 1 DCOU03 DCOU03 D CCOU02 CCOU02 DCCOU01 DCCOU01 0 port #0 DCCOU00 DCCOU00 LSB · · · · 7 6 5 4 3 09H DCCOU57 DCCOU57 DCCOU56 DCCOU56 DCCOU55 DCCOU55 DCOU54 DCOU54 R 2 MSB DCOU53 DCOU53 1 DCCOU52 DCCOU52 0 DCCOU51 DCCOU51 DCCOU50 DCCOU50 port #5 LSB 4.2.6 LOS Information Register (LOSERR: Default 00H) (a) Holds the loss of signal (LOS) status of each port. An interrupt can be generated at the same timing as LOS generation. The register is reset to 00H when it is read. Even if the LOS status is cleared, the register is not reset to zero before being read. While the port is in the LOS status, the register is not reset to zero even when it is read. 7 0AH R 6 5 - - LS5 4 3 2 1 0 LS4 LS3 LS2 LS1 LS0 LSn Default 0 (*) 0 No LOS 1 LOS occurred * LSn: Bit corresponding to the port #n (n = 0 to 5) 45 4.2.7 LOS Interrupt Mask Register (LOSMSK: Default 3FH) (a) This register mask an interrupt caused by LOS (loss of signal) occurring in each port. Even while this register is set to mask the interrupt, the interrupt source, as described in Section 4.2.6 (LOSERR), can be read. 7 0BH R/W 6 - 5 - 4 3 2 1 0 LSMK5 LSMK4 LSMK3 LSMK2 LSMK1 LSMK0 LSMKn Default 1 (*1) 0 LOS interrupt not masked 1 LOS interrupt masked * LSMKn: Bit corresponding to the port #n (n = 0 to 5) 4.2.8 PMD Loop-Back 1 Setting Register (LBPMDT: Default 00H) (a) Sets PMD loop-back 1 for each port. When loop-back 1 is set, the transmit data which input from UTOPIA bus can be returned to the receive side of UTOPIA bus (source loop-back). 7 0CH R/W 6 5 - - PMLBT5 4 3 2 PMLBT4 PMLBT3 1 0 PMLBT2 PMLBT1 PMLBTn PMLBT0 Default 0 (*) 0 PMD loop-back 1 disabled 1 PMD loop-back 1 enabled * PMLBTn: Bit corresponding the port #n (n = 0 to 5) 46 4.2.9 PMD Loop-Back 2 Setting Register (LBPMDU: Default 00H) (a) Sets PMD loop-back 2 for each port. When loop-back 2 is set, the receive data from a port can be returned to the transmit side of a port (remote loop-back). 7 0DH R/W 6 - 5 - 4 3 2 PMLBU5 PMLBU4 PMLBU3 1 0 PMLBU2 PMLBU1 PMLBU0 PMLBUn Default 0 (*) 0 PMD loop-back disabled 1 PMD loop-back enabled * PMLBUn: Bit corresponding the port #n (n = 0 to 5) 4.2.10 ATM Loop-Back Setting Register (LBATM: Default 00H) (a) Sets ATM layer loop-back for each port. When ATM loop-back is set, the transmit data which input from UTOPIA bus can be returned to the receive side of UTOPIA bus. In case of PMD loop-back 1, the switchback point is PMD sub-layer. In case of ATM loop-back, the point is UTOPIA interface. 7 0EH - 6 - 5 4 3 2 1 ATMLB5 ATMLB4 ATMLB3 ATMLB2 ATMLB1 0 ATMLB0 R/W ATMLBn Default 0 (*) 0 ATM layer loop-back disabled 1 ATM layer loop-back enabled * ATMLBn: Bit corresponding the port #n (n = 0 to 5) 47 4.2.11 FIFO Overflow Registers (FIFOOVT/FIFOOVR: Default 00H) (a) The two registers hold the FIFO overflow status of the transmission and receive sides of a port separately. When read, the register is reset to 00H. The FIFO overflow can cause an interrupt. FIFOOVT register 7 0FH R 6 5 4 3 2 1 0 - - FOT5 FOT4 FOT3 FOT2 FOT1 FOT0 FOTn Default 0 (*) 0 No overflow 1 Overflow occurred * FOTn: Bit corresponding to the port #n (n = 0 to 5) FIFOOVR register 7 10H R 6 5 - - FOR5 4 3 FOR4 FOR3 2 1 FOR2 FOR1 FORn 0 FOR0 Default 0 (*) 0 No overflow 1 Overflow occurred * FORn: Bit corresponding to the port #n (n = 0 to 5) 48 4.2.12 FIFO Overflow Interrupt Mask Registers (FOVTMSK/FOVRMSK: Default 3FH) (a) These registers mask an interrupt caused by an FIFO overflow occurring in each port, separately for the transmission and reception sides. Even while this register is set to mask the interrupt, the interrupt source, as described in Section 4.2.11 (FIFOOVT/FIFOOVR), can be read. FOVTMSK register 7 11H R/W 6 - - 5 4 3 FOTM5 FOTM4 FOTM3 2 1 0 FOTM2 FOTM1 FOTM0 FOTMn Default 1 (*) 0 Overflow interrupt not masked 1 Overflow interrupt masked * FOTMn: Bit corresponding to the port #n (n = 0 to 5) FOVRMSK register 7 12H R/W 6 - - 5 4 3 2 1 0 FORM5 FORM4 FORM3 FORM2 FORM1 FORM0 FORMn Default 1 (*) 0 Overflow interrupt not masked 1 Overflow interrupt masked * FORMn: Bit corresponding to the port #n (n = 0 to 5) 49 4.2.13 PHY Address Register (PHYADD: Default 00H) (a) Holds the PHY address of each port for UTOPIA. Note: While PHY address disable, both PMD-sublayer and TC-sublayer of the port are working. So, the error detection function works for receive data which are input from PMD port. If the µPD98408 PD98408 detects an error, the discard cell counter is counted up. But no receive data is transferred to UTOPIA interface. And the µPD98408 PD98408 sends dummy data scrambled and 4B5B block encoded to the PMD port. 7 6 5 13H EN07 - - R/W 4 3 2 1 0 MSB PHA04 PHA04 PHA03 PHA03 PHA02 PHA02 PHA01 PHA01 PHA00 PHA00 port #0 LSB 7 6 5 18H EN57 - - R/W 4 3 2 1 MSB PHA54 PHA54 PHA53 PHA53 PHA52 PHA52 0 PHA51 PHA51 PHA50 PHA50 port #5 LSB PHY address for UTOPIA ENn7 Default 0 0 Address disabled 1 Address enabled 50 4.2.14 Test Pattern Generation Function Select Register (TSTMOD: Default 00H) (a) Selects the test pattern generation mode for each port. When TSn0 (n = 0 to 5) is set, the test pattern is sent to PMD without being scrambled or converted into NRZI. 7 5 4 3 2 1 0 - 19H R/W 6 - - - TS03 TS02 TS01 TS00 port #0 7 1EH R/W 6 5 4 3 2 1 0 - - - - TS53 TS52 TS51 TS00 TS50 port #5 Default 0 0 1 * Decoded value (TS03,TS02, TS01) (0, 0, 0) 0 (0, 0, 1) 1 (0, 1, 0) 2 (0, 1, 1) 3 (1, 0, 0) 4 (1, 0, 1) 5 (1, 1, 0) 6 (1, 1, 1) 7 Test mode disabled Test mode enabled Decoded value (*) 0 1 2 3 4 5 6 7 TS00: Waveform test 1 enabled(1)/disabled(0) TS11: Waveform test 2 enabled(1)/disabled(0) TS12: Waveform test 3 enabled(1)/disabled(0) TS13: Waveform test 4 enabled(1)/disabled(0) TS14: Waveform test 5 enabled(1)/disabled(0) NA NA NA ·Waveform test1: Recurring signal 010101. ·Waveform test2: Recurring signal 00110011. ·Waveform test3: Recurring signal 000111000111. ·Waveform test4: Recurring signal 0000111100001111. ·Waveform test5: Recurring signal 00000111110000011111. 51 4.2.15 PMD Standby Register (PMDSTBY: Default 00H) (a) Sets PMD standby for each port (power down mode). 7 23H R/W 6 5 - - PMDSTB5 4 3 2 1 0 PMDSTB4 PMDSTB3 PMDSTB2 PMDSTB1 PMDSTB0 PMDSTBn Default 0 (*) 0 Normal 1 Standby * PMDSTBn: Bit corresponding to the port #n (n = 0 to 5) Note: While PMD standby, both PMD-sublayer and TC-sublayer of the port are not available. So, the error detection function is not available. Also no receive data is transferred to UTOPIA interface. The µPD98408 PD98408 does not drive transmit data to the PMD port. The PMD port becomes Hi-Z status. 52 4.2.16 Idle Cell Discard Specification Register (DMODE1: Default 00H) (a) Selects whether to discard an idle cell in each port. DMODE2 (Section 4.2.17) specifies the conditions under which cells are discarded. 7 26H R/W 6 5 - - DMOD15 DMOD15 4 3 DMOD14 DMOD14 2 1 DMOD13 DMOD13 DMOD12 DMOD12 0 DMOD11 DMOD11 DMOD1n DMOD10 DMOD10 Default 0 (*) 0 Cell discarded 1 Cell not discarded * DMOD1n: Bit corresponding to the port #n (n = 0 to 5) 4.2.17 Idle Cell Discard Condition Setting Register (DMODE2: Default 00H) (a) Sets the conditions used for judging an idle cell for each port. 7 27H R/W 6 5 - - DMOD25 DMOD25 4 3 DMOD24 DMOD24 2 DMOD23 DMOD23 DMOD2n 1 DMOD22 DMOD22 0 DMOD21 DMOD21 DMOD20 DMOD20 Default 0 (*) 0 VPI=0 (GFC: don't care), VCI=0 1 VPI=0 (GFC=0), VCI=0 * DMOD2n: Bit corresponding to the port #n (n = 0 to 5) 53 4.2.18 Discarded Cell Counter Overflow Information Register (DCINFO: Default 00H) (a) Holds the discarded cell counter overflow status for each port. The register is set to 1 when an overflow occurs. The register is reset when it is read. The overflow can cause an interrupt. 7 5 4 - 29H R 6 3 - DCINFO5 DCINFO4 2 1 DCINFO3 DCINFO2 DCINFOn 0 DCINFO1 DCINFO0 Default 0 (*) 0 No overflow 1 Overflow occurred * DCINFOn: Bit corresponding to the port #n (n = 0 to 5) 4.2.19 Discarded Cell Counter Overflow Interrupt Mask Register Information Register (DCMASK: Default 3FH) (a) Masks an interrupt caused by an overflow of the discarded cell counter for each port. Even while this register is set to mask the interrupt, the interrupt source, as described in Section 4.2.18 (DCINFO), can be read. 7 2AH R/W 6 - - 5 4 3 DCMASK5 DCMASK4 DCMASK3 2 1 DCMASK2 DCMASK1 0 DCMASK0 DCMASKn Default 1 (*) 0 Overflow interrupt not masked 1 Overflow interrupt masked * DCMASKn: Bit corresponding to the port #n (n = 0 to 5) 54 4.2.20 Self Test 1 (Internal HEC Error) Register (SELFTST1: Default 00H) (a) Sets HEC error self generation mode for each port. 7 2BH R/W 6 5 4 - - HECER5 3 2 HECER2 HECER4 HECER3 1 0 HECER1 HECER0 HECERn Default 0 (*) 0 HEC error self generation mode disabled 1 HEC error self generation mode enabled * HECERn: Bit corresponding to the port #n (n = 0 to 5) 4.2.21 Self Test 2 (Internal 4B5B Code Error) Register (SELFTST2: Default 00H) (a) Sets 4B5B code error self generation mode for each port. 7 2CH R/W 6 5 - - 4B5BER5 4 3 4B5BER4 4B5BER3 2 4B5BER2 1 0 4B5BER1 4B5BER0 4B5BERn Default 0 (*) 0 4B5B code error self generation mode disabled 1 4B5B code error self generation mode enabled * 4B5BERn: Bit corresponding to the port #n (n = 0 to 5) 55 4.2.22 X_8 Transmission Enable Register (X8_IN: Default 00H) (a) Enables or disables X_8 command signal transmission for each port. The X_8 command is transmitted for a port enabled with this register, at the input timing received from the SIN pin. 7 2DH R/W 6 5 4 3 2 - - X8INEN5 X8INEN4 X8INEN3 X8INEN2 X8INENn 1 X8INEN1 0 X8INEN0 Default 0 (*) 0 X_8 transmission disabled 1 X_8 transmission enabled * X8INENn: Bit corresponding to the port #n (n = 0 to 5) 56 CHAPTER 5 JTAG BOUNDARY SCAN (This function can be supported on request.) The µPD98408 PD98408 has a JTAG boundary scan circuit. 5.1 · · · · FEATURES Conforms to IEEE 1149.1 JTAG Boundary Scan Standard. Three registers dedicated to boundary scan · Instruction register · Bypass register · Boundary scan register Two instructions supported · BYPASS instruction · EXTEST instruction Five pins dedicated to boundary scan · JCK (JTAG Clock) · JMS (JTAG Mode Select) · JDI (JTAG Data Input) · JDO (JTAG Data Output) · JRST_B (JTAG Reset) 57 5.2 Internal Configuration of Boundary Scan Circuit The following figure shows the block diagram of the internal JTAG boundary scan circuit of the µPD98408 PD98408. Block Diagram of Boundary Scan Circuit Boundary scan register Bypass register MUX Output buffer JDO JDI Instruction decoder Instruction register JMS JCK TAP controller JRST_B 5.2.1 Instruction register The instruction register consists of a 2-bit shift register and writes instruction data from the JDI pin. The register and instruction are selected by this instruction data. 5.2.2 TAP (Test Access Port) controller The TAP controller changes operating state by latching the signal of the JMS pin at the rising edge of the clock input to the JCK pin. 5.2.3 Bypass register The bypass register consists of a 1-bit shift register connected between the JDI and JDO pins when the TAP controller is in Shift-DR state. If this register is selected while the TAP controller is in Shift-DR state, data is shifted to the JDO pin at the rising edge of the clock input to the JCK pin. When this register is selected, the operation of the JTAG boundary circuit does not influence on the operation of the µPD98408 PD98408. 5.2.4 Boundary scan register The boundary scan register is located between an external pin of the µPD98408 PD98408 and internal logic circuit. When this register is selected, data is latched or loaded by the instruction of the TAP controller. If this register is selected while the TAP controller is in Shift-DR state, data is output to the JDO pin starting from the LSB at the falling edge of the clock input to the JCK pin. 58 5.3 PIN FUNCTION 5.3.1 JCK (JTAG Clock) pin The JCK pin is used to supply a clock signal to the JTAG boundary scan circuit (such as the bypass register, instruction register, and TAP controller). This clock signal is isolated so as not to be supplied to the other internal circuits of the µPD98408 PD98408. 5.3.2 JMS (JTAG Mode Select) pin Input to the JMS signal is latched at the rising edge of the clock input to the JCK pin and defines the operation of the TAP controller. 5.3.3 JDI (JTAG Data Input) pin The JDI pin is an input pin that inputs data to the JTAG boundary scan circuit register. 5.3.4 JDO (JTAG Data Output) pin The JDO pin is an output pin that outputs data from the JTAG boundary scan circuit. This pin changes its output at the falling edge of the clock input to the JCK pin. This pin is a three-state output pin and is controlled by the TAP controller. 5.3.5 JRST_B (JTAG Reset) pin This pin asynchronously initializes the TAP controller. This reset signal sets the µPD98408 PD98408 in the normal operation mode and the boundary register in non-operation state. 59 5.4 OPERATION DESCRIPTION 5.4.1 TAP controller The TAP controller is a circuit having 16 states synchronized with changes of the JMS and JCK pins. Its operation is specified by IEEE Standard 1149.1. 5.4.2 TAP controller state The following figure shows the state transition of the TAP controller. The state of the TAP controller is determined depending on the state of the JMS pin signal input at the rising edge of the clock input to the JCK pin. The operations of the instruction register, boundary scan register, and bypass register change at the rising or falling edge of the clock input to the JCK pin. State Transition of TAP Controller (1) Test-Logic-Reset H L H (2) Run-Test/Idle (3) Select-DR-Scan L H (4) Select-IR-Scan L H H L H (5) Capture-DR (11) Capture-IR L L (6) Shift-DR (12) Shift-IR L H L H H (7) Exit1-DR L L (8) Pause-DR H H (13) Exit1-IR (14) Pause-IR L L H L L (9) Exit2-DR (15) Exit2-IR H H (10) Update-DR H (16) Update-IR L H L Remarks 1. "H" and "L" of the arrows indicating state transition in the above figure indicate the state of the JMS pin at the rising edge of the clock input to the JCK pin. 2. Numbers in ( ) in the above figure correspond to the explanation below. 60 Operation Timing in Controller State JCK Controller state Enters state Starts in state at rising edge of JCK pin Starts in state at rising edge of JCK pin (1) Test-Logic-Reset The boundary scan circuit performs no operation on the µPD98408 PD98408. Therefore, it does not affect the system logic of the µPD98408 PD98408. Because the bypass instruction is stored to the instruction register and executed on initialization. The TAP controller enters the Test-Logic-Reset state if the JMS pin holds the high level for the duration of at least five rising edges of the JCK pin signal, regardless of the current state of the controller. The TAP controller holds this state for the duration in which the JMS pin signal high. If the TAP controller must be in the Test-Logic-Reset state, the controller returns to the original Test-Logic-Reset state even if a low-level signal is input once to the JMS pin by mistake (due to, for example, the influence of the external interface), if the JMS pin signal holds its high level status for the duration of three rising edges of the JCK pin signal. The operation of the test logic does not influence the logic operation of the µPD98408 PD98408 due to the above error. When the TAP controller exits from the Test-Logic-Reset state, the controller enters the RunTest/Idle state. In this state, no operation is performed because the current instruction is set by the operation of the bypass register. The logic operation of the JTAG boundary scan circuit is inactive even in the Select-DR-Scan and Select-IR-Scan states. (2) Run-Test/Idle The TAP controller is in this state during scan operation (in Select-DR-Scan or Select-IR-Scan state). Once the controller has entered this state and if the JMS pin signal holds the low level, the controller remains in this state. The controller enters the Select-DR-Scan state if the JMS pin signal holds high level at one rising edge of the JCK pin signal. All the test data registers (boundary register and bypass register) selected by the current instruction hold the previous status (Idle). While the TAP controller is in this state, the instruction does not change. (3) Select-DR-Scan This is a temporary boundary scan state. The boundary scan register and bypass register selected by the current instruction hold the previous state. If the JMS signal is held low at the rising edge of the JCK pin signal while the TAP controller is in this state, the controller enters the Capture-DR state, and scan sequence to the selected registers is started. If the JMS signal is held high at the rising edge of the JCK pin signal, the TAP controller enters the Select-IR-Scan state. While the controller is in this state, the instruction does not change. 61 (4) Select-IR-Scan This is a temporary boundary scan state. The boundary scan register and bypass register selected by the current instruction hold the previous state. If the JMS signal is held low at the rising edge of the JCK pin signal while the TAP controller is in this state, the controller enters the Capture-IR state, and scan sequence to the selected registers is started. If the JMS signal is held high at the rising edge of the JCK pin signal, the TAP controller enters the Test-Logic-Reset state. While the controller is in this state, the instruction does not change. (5) Capture-DR In this controller state, data is loaded to the boundary scan register selected by the current instruction in parallel at the rising edge of the JCK pin signal (in this case, data is input from the input pin of each device to the corresponding boundary scan register). While the TAP controller is in this state, the instruction does not change. If the TAP controller is in this state at the rising edge of the JCK pin signal, the controller enters the following state: · · If the JMS pin signal is held high If the JMS pin signal is held low : : Exit1-DR state Shift-DR state (6) Shift-DR In this controller state, JDI and JDO are connected (at either of the boundary scan register of bypass register) by the current instruction. The shift data is shifted one state at a time toward the serial output direction at each rising edge of the JCK pin signal. The boundary scan register or bypass register selected by the current instruction holds the previous status without change if the controller is not on the serial bus (not in the Shift-DR state). While the controller is in this state, the instruction does not cha