PD98404 NEASCOT-P30TM S11821EJ5V0UM00 S11821EJ5V0UM NEASCOT-P30 NEASCOT-S40C - Datasheet Archive

 

µPD98404 (NEASCOT-P30TM) ADVANCED ATM SONET FRAMER Document No. S11821EJ5V0UM00 (5th edition) Date Published January 2003

 

User's Manual µPD98404 PD98404 (NEASCOT-P30TM NEASCOT-P30TM) ADVANCED ATM SONET FRAMER Document No. S11821EJ5V0UM00 S11821EJ5V0UM00 (5th edition) Date Published January 2003 NS CP(K) 1996 Printed in Japan [MEMO] 2 User's Manual S11821EJ5V0UM S11821EJ5V0UM NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. User's Manual S11821EJ5V0UM S11821EJ5V0UM 3 NEASCOT-P30 NEASCOT-P30, NEASCOT-S40C NEASCOT-S40C, and NEASCOT-X15 NEASCOT-X15 are trademarks of NEC Electronics Corporation. · The information in this document is current as of January, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. · No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. · NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. · Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. · While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. · NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 4 User's Manual S11821EJ5V0UM S11821EJ5V0UM MAJOR REVISIONS IN THIS EDITION Page Contents CHAPTER 1 GENERAL 1.3 System Configuration Example p.15 Change of device used in the figure. CHAPTER 2 PIN FUNCTION 2.2.1 PMD interface p.22 Addition of description to PMDALM pin. 2.2.6 Power supply and ground p.27 Change of description to pins. p.52 p.55 CHAPTER 3 FUNCTIONAL OUTLINE Addition of description to Table 3-10. Addition of Caution 2 to Table 3-13. p.63 p.73 p.74 CHAPTER 4 INTERFACES Change of description in Table 4-2. Addition of description to 4.2.1 (1). Change of Figure 4-18. p.150 CHAPTER 7 BOARD LAYOUT Change of description in Table 7-1. p.156 p.157 CHAPTER 8 CONSTRAINTS Addition of 8.2.3 Abnormal operation in ALP mode. Addition of 8.2.4 Fixed receiver circuit status in RPLP mode. The mark shows major revised points. User's Manual S11821EJ5V0UM S11821EJ5V0UM 5 PREFACE Readers of this manual This manual is intended for user engineers who wish to design and develop an application system using the µPD98404 PD98404. Purpose This manual introduces the hardware functions of the µPD98404 PD98404 in the following organization. Organization This manual consists of the following chapters. · · Pin function · Functional outline · Interfaces · Registers · JTAG boundary scan · Board layout · How to Read This Manual General Constraints It is assumed that the readers of this manual have a general knowledge of electricity, logic circuits, and microcomputers. For the overall functions of the µPD98404 PD98404 Read this manual in the order of Table of Contents. For the electrical characteristics of the µPD98404 PD98404 Refer to the Data Sheet separately available. The data bit string of SONET/SDH is transmitted by the µPD98404 PD98404 via the PMD interface, starting from the MSB. In this manual, the bits in the overhead of the SONET/SDH framer are referred to using the following two types of bit names: (1) First bit through eighth bit These bit names are mainly used to indicate a bit string in the overhead byte in the SONET/SDH frame and indicate in the order in which the bits are output from the PMD interface. 6 User's Manual S11821EJ5V0UM S11821EJ5V0UM (2) D7 bit through D0 bit These bit names are mainly used to indicate the bits of an internal register of the µPD98404 PD98404 and are equivalent to the D7 through D0 pins of the external management interface. · Indication of bits in internal register Transmission sequence from PMD interface 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit D7 D6 D5 D4 D3 D2 D1 D0 Register Conventions Data significance : Left: high-order digit, Right: low-order digit Active low : ×××_B (_B after pin or signal name) Address of memory map: Top: High-order, bottom: low-order Note : Explanation of items marked with Note in the text Caution : Important information Remark : Supplement Numeric notation : Binary . ×××× or ××××B Decimal number . ×××× Hexadecimal number . ××××H Related documents Some of the related documents listed below are preliminary versions but are not so specified here. · Brochure : S11631E S11631E · Data sheet : S11822E S11822E User's Manual S11821EJ5V0UM S11821EJ5V0UM 7 TABLE OF CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 Features . 13 Ordering Information . 14 System Configuration Example . 15 Block Diagram . 16 Pin Configuration . 17 CHAPTER 2 2.1 2.2 GENERAL . 13 PIN FUNCTION . 18 Pin Configuration . 18 Pin Function. 21 2.2.1 PMD interface.21 2.2.2 ATM layer interface .24 2.2.3 Management interface.25 2.2.4 Internal test pin.27 2.2.6 2.3 JTAG boundary scan.26 2.2.5 Power supply and ground.27 Processing of Unused Pins. 28 CHAPTER 3 3.1 3.2 3.3 FUNCTIONAL OUTLINE. 29 Transmission Function. 31 Reception Function. 34 OAM Information Control Function . 41 3.3.1 3.4 3.5 3.6 3.7 3.8 Transmission OAM control .41 3.3.2 Reception OAM Control.45 Frame Overhead Insert/Drop Function . 50 Alarm Report Pins (PHYALM[2:0], PMDALM). 51 Pseudo Error Frame Transmission Function . 53 Register Function. 54 Loopback Function . 55 CHAPTER 4 4.1 INTERFACES . 57 ATM Layer Interface . 57 4.1.1 Mode .59 4.1.3 Single PHY octet level handshake mode .60 4.1.4 Single PHY cell level handshake mode.63 4.1.5 4.2 Signals.57 4.1.2 Multi-PHY mode (TCLV/RCLV 3-state) .67 PMD Interface . 73 4.2.1 4.3 8 Serial interface mode .73 4.2.2 Parallel interface mode.78 Management Interface . 79 User's Manual S11821EJ5V0UM S11821EJ5V0UM 4.3.1 Read operation. 80 4.3.2 Write operation. 82 4.3.3 Interrupt processing . 84 CHAPTER 5 5.1 5.2 Register Map. 88 Register Function . 91 CHAPTER 6 6.1 6.2 REGISTERS. 88 JTAG BOUNDARY SCAN . 137 Features . 137 Internal Configuration of Boundary Scan Circuit . 138 6.2.1 6.2.2 TAP (Test Access Port) controller. 138 6.2.3 Bypass register . 138 6.2.4 6.3 Instruction register. 138 Boundary scan register . 138 Pin Function . 139 6.3.1 JCK (JTAG Clock) pin . 139 6.3.2 JMS (JTAG Mode Select) pin. 139 6.3.3 JDO (JTAG Data Output) pin . 139 6.3.5 6.4 JDI (JTAG Data Input) pin . 139 6.3.4 JRST_B (JTAG Reset) pin . 139 Operation Description . 140 6.4.1 6.5 6.6 6.7 TAP controller . 140 6.4.2 TAP controller state. 140 TAP Controller Operation. 145 Initializing TAP Controller . 148 Instruction Register . 148 6.7.1 BYPASS instruction . 149 6.7.2 EXTEST instruction. 149 6.7.3 SAMPLE/PRELOAD Instruction . 149 6.7.4 Boundary scan data bit definition . 149 CHAPTER 7 BOARD LAYOUT. 150 CHAPTER 8 CONSTRAINTS. 152 8.1 8.2 Constraints . 152 Description . 152 8.2.1 Clearing error of performance counter . 152 8.2.2 Output error of RCLAV signal in RCASEL = 1 mode . 153 8.2.3 Abnormal operation in ALP mode . 156 8.2.4 Fixed receiver circuit status in RPLP mode . 157 User's Manual S11821EJ5V0UM S11821EJ5V0UM 9 LIST OF FIGURES (1/2) Figure No. Title Page 3-1 Structure of ATM Cell (user-network interface (UNI). 29 3-2 Outline of Frame Format . 29 3-3 Outline of µPD98404 PD98404's Frame Transmission Function. 31 3-4 Vacant Cell Format Inserted by µPD98404 PD98404. 31 3-5 Format of AU Pointer (H1 through H3 bytes) . 32 3-6 Outline of µPD98404 PD98404's Frame Reception Function . 34 3-7 Pointer Status Transition . 36 3-8 Cell Synchronization Status Transition . 37 3-9 HEC Check Status Transition in Cell Synchronization Status. 38 3-10 Counter-Related Registers (Example: HEC error counter) . 49 3-11 Overhead Byte with Insert/Drop Register. 50 3-12 Loopback Function. 56 4-1 Single PHY and Multi-PHY Modes . 59 4-2 Transmission Timing of Octet Level Handshake (1) . 60 4-3 Transmission Timing of Octet Level Handshake (2) . 61 4-4 Octet Level Handshake Reception Timing (two-state operation) . 61 4-5 Octet Level Handshake Reception Timing (three-state operation) . 62 4-6 Cell Level Handshake Transmission Timing . 64 4-7 Cell Level Handshake Reception Timing (two-state operation) . 64 4-8 Cell Level Handshake Reception Timing (three-state operation). 65 4-9 RCLAV Changing Timing . 66 4-10 Transmission Timing of Multi-PHY . 68 4-11 End and Cell Transmission and Re-transmission . 68 4-12 Stopping Cell Transmission. 69 4-13 Example of Reception Timing in Multi-PHY Mode (1) . 70 4-14 Example of Reception Timing in Multi-PHY Mode (2) . 71 4-15 Example of Transmitting Two Cells in Succession from the Same µPD98404 PD98404 (1). 71 4-16 Example of Transmitting Two Cells in Succession from the Same µPD98404 PD98404 (2). 72 4-17 Example of ATM Layer Device Stopping Transfer . 72 4-18 Example of Connection in Serial Interface Mode (with internal PLL used) . 74 4-19 Outline of PMD Layer Block . 77 4-20 Example of Connection in Serial Interface Mode (with external PLL used) . 78 4-21 Read Operation . 81 4-23 Write Operation . 83 4-24 Differences in Operation of Interrupt Cause Register Bit and PHINT_B due to Interrupt Mode. 85 4-25 10 Management Interface . 80 4-22 Relationship between Interrupt Cause Registers . 86 User's Manual S11821EJ5V0UM S11821EJ5V0UM LIST OF FIGURES (2/2) Figure No. Title Page 6-1 Block Diagram of Boundary Scan Circuit . 138 6-2 State Transition of TAP Controller . 140 6-3 Operation Timing in Controller State. 141 6-4 Operation of Test Logic (instruction scan) . 146 6-5 Operation of Test Logic (data scan). 147 7-1 Example of Capacitor Insertion . 150 7-2 Board Layout Image. 151 8-1 Timing of Change in RCLAV . 154 8-2 Problem of RCLAV (1) (if the number of cells in receive FIFO increases from 0 to 2). 154 8-3 Problem of RCLAV (2) (if the number of cells in receive FIFO increases from 3 to 0). 154 8-4 ALP Mode and TPLP Mode . 156 8-5 RPLP Mode. 158 User's Manual S11821EJ5V0UM S11821EJ5V0UM 11 LIST OF TABLES Table No. Title Page 3-1 Synchronization Pattern . 35 3-2 OCD Bit . 37 3-3 HEC Error Correction Mode . 39 3-4 Example When CLP Bit Is Used. 40 3-5 Transmitting Alarm . 41 3-6 Alarm and Failure List . 45 3-7 Performance Cause Register (PCR register) . 47 3-8 Counters. 48 3-9 PHYALM Pin Report Contents . 51 3-10 PMDALM Pin Function . 52 3-11 Pseudo Error Frame. 53 3-12 Registers of µPD98404 PD98404 . 54 3-13 Loopback Function. 55 4-1 Mode of ATM Layer Interface. 59 4-2 Selecting Timing Mode of Changing TCLAV Signal. 63 4-3 PMD Interface Mode . 73 4-5 Management Interface Mode . 79 4-6 Mode Select Condition When MSEL Pin Is Low . 79 4-7 Setting/Resetting Condition of Each Bit of Interrupt Cause Registers . 87 5-1 ATM Layer Interface Modes Selected by Combination of CSEL and HSEL Bits and UMPSEL Pin. 95 6-1 Operation in Each Controller State. 145 7-1 12 Selecting Changing Timing Mode of RCLAV Signal . 66 4-4 Power and Ground Pins of µPD98404 PD98404 . 150 User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 1 The µPD98404 PD98404 NEASCOT-P30 NEASCOT-P30 TM GENERAL is one of ATM-LAN LSIs and is intended for use in ATM adapter boards, ATM hubs, and ATM switches to connect an personal computer or an workstation to an ATM network. This LSI provides the functions of the TC sublayer of the SONET/SDH-base physical layer of the ATM protocol specified by ATM Forum UNI3.1 Recommendation. Its main functions include a transmission function to map an ATM cell passed from an ATM layer to the payload of 155 Mbps SONET STS-3c/SDH STM-1 frame and transmit the circuit side to the PMD (Physical Media Dependent) sublayer of the physical layer, and a reception function to separate the overhead and ATM cell from the data string received from the circuit side and transmit the ATM cell to the ATM layer device. In addition, the µPD98404 PD98404 also has a clock recovery function to extract sync clock for reception of receive data from the bit stream, and a clock synthesis function to generate a clock for transmission. 1.1 Features · Clock recovery function/clock synthesis function · Supplies function of TC sublayer of ATM protocol physical layer · Supports 155 Mbps SONET STS-3c frame/SDH STM-1 frame formats · Conforms to ATM Forum UTOPIA interface Level2 V1.0 (June 1995), and supports three modes for the interface with the ATM layer device. · Single PHY octet level handshake · Single PHY cell level handshake · Multi-PHY mode · Selectable drop/pass length for unassigned cells · Supports internal PMD layer return and ATM layer return loopback functions · Supports two types of PMD interfaces: serial and parallel · · · 155.52 Mbps serial interface 19.44 MHz parallel interface Overhead information writing/reading registers SOH (Section Overhead): J0 byte, Z0 (first and second) byte, F1 byte LOH (Line Overhead) : K1 byte, K2 byte POH (Pass Overhead) : F2 byte, C2 byte, H4 byte · Supports pseudo transmission test function for each errors · Supports JTAG boundary scan test (IEEE 1149.1) · CMOS technology · +3.3 V single power source · Many OAM (Operation And Maintenance) functions User's Manual S11821EJ5V0UM S11821EJ5V0UM 13 CHAPTER 1 GENERAL Transmission side Reception side · · Transmission of various types of alarm signals · Detection of alarm and error signals OOF (Out Of Frame) Line REI, Path REI LOF (Loss Of Frame) Transmission on command LOP (Loss Of Pointer) Line AIS, Path AIS · LOS (Loss Of Signal) Line RDI, Path RDI · Automatic return transmission on occurrence OCD (Out of Cell Delineation) Pseudo error generation frame transmission function LOC (Loss Of Cell delineation) LOS generation frame Line RDI, Path RDI OOF, LOF generation frame Line AIS, Path AIS LOP generation frame · Detection and indication of cause of quality OCD, LCD generation frame degradation B1 error generation frame B1 error, B2 error, B3 error, Line REI, Path REI B2 error generation frame · B3 error generation frame Counters counting number of times of error generation B1 byte error counter (16-bit width) B2 byte error counter (20-bit width) B3 byte error counter (16-bit width) Line REI error counter (20-bit width) Path REI error counter (16-bit width) Reception side Frequency Justification processing counter (12-bit width) HEC error dropped cell counter (20-bit width) FIFO overflow dropped cell counter (20-bit width) Valid cell counter (20-bit width) 1.2 Ordering Information Part Number µPD98404GJ-KEU PD98404GJ-KEU 14 Package 144-pin plastic QFP (fine pitch) (20 × 20) User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 1 1.3 GENERAL System Configuration Example An example of a system using the µPD98404 PD98404 is shown below. ATM adapter card application Control memory SAR chip µ PD98409 PD98409 NEASCOT-S40CTM NEASCOT-S40CTM Optical fiber transceiver/ receiver PHY chip µ PD98404 PD98404 NEASCOT-P30 NEASCOT-P30 19.44 MHz Oscillator Bus bridge Hub (terminal side) application Microprocessor Switch device µ PD98412 PD98412 NEASCOT-X15TM NEASCOT-X15TM UTOPIA Level 2 interface Oscillator µ PD98404 PD98404 NEASCOT-P30 NEASCOT-P30 Optical fiber transceiver/ receiver µ PD98404 PD98404 NEASCOT-P30 NEASCOT-P30 Optical fiber transceiver/ receiver User's Manual S11821EJ5V0UM S11821EJ5V0UM 15 Cell descrambler RxFIFO 7 cells Descrambler Transmission timing generator Reception overhead processor (K2, Z2, G1, H1, H2, H3) OAM controller (performance register, etc.) HEC generator TxFIFO 7 cells Management interface signal Transmission overhead register (J0, Z0, C2, K2, etc.) Reception overhead register (J0, Z0, C2, K2, etc.) Interrupt cause register Mode register GENERAL BIP generator (reception side) Transmission overhead processor (A1, A2, K2, Z2, G1, H1, H2, H3) Cell scrambler UTOPIA interface signal CHAPTER 1 BIP generator (transmission side) Scrambler + Parallel serial ATM layer interface Cell synchronization HEC verification HEC correction Controller interface Pointer processor Block Diagram Frame synchronization (A1, A2) + User's Manual S11821EJ5V0UM S11821EJ5V0UM Clock recovery & clock synthesizer & PMD layer interface 1.4 16 PMD interface signal Serial parallel CHAPTER 1 1.5 GENERAL Pin Configuration Test interface TEST0-TEST2 PMD interface RDIT, RDIC RCIT, RCIC TDOT, TDOC Serial RDO0-RDO7 RCLK 8 RSOC TCOT, TCOC RENBL_B TFKT, TFKC EMPTY_B/RCLAV RADD0-RADD4 AIN1 TDI0-TDI7 REFCLK 5 ATM layer interface 8 TCLK PSEL0, PSEL1 2 TSOC RPD0-RPD7 TENBL_B 8 RPC TPD0-TPD7 FULL_B/TCLAV Parallel TADD0-TADD4 8 TPC UMPSEL 5 TFC MSEL PMDALM MADD0-MADD6 PHYALM0-PHYALM2 7 3 MD0-MD7 RXFP CS_B TXFP DS_B/RD_B TFSS 8 Management interface R/W_B/WR_B RCL ACK_B/RDY_B TCL PHINT_B JDI JDO JCK GND, GND-TPE, GND-RPE GND-SP, GND-CS, GND-CR RESET_B JMS VDD, VDD-TPE, VDD-RPE VDD-SP, VDD-CS, VDD-CR JRST_B Power supply/ ground JTAG boundary scan interface User's Manual S11821EJ5V0UM S11821EJ5V0UM 17 CHAPTER 2 2.1 PIN FUNCTION Pin Configuration 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 GND GND RADD4 RADD3 RADD2 RADD1 RADD0 RDO7 RDO6 RDO5 RDO4 RDO3 RDO2 RDO1 RDO0 VDD RCLK RENBL_B RSOC EMPTY_B/RCLAV GND FULL_B/TCLAV TSOC TENBL_B TCLK VDD TDI7 TDI6 TDI5 TDI4 TDI3 TDI2 TDI1 TDI0 GND GND · 144-pin plastic QFP (fine pitch) (20 × 20) (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 GND GND-SP VDD-TPE TFKT TFKC GND-TPE TCOT TCOC VDD-TPE GND-TPE TDOT TDOC VDD-TPE GND-TPE RCIT RCIC VDD-RPE RDIT RDIC GND-RPE GND-CR VDD-CR RPC VDD RPD0 RPD1 RPD2 RPD3 RPD4 RPD5 RPD6 RPD7 PSEL0 PSEL1 GND GND 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 VDD JCK JDO JDI JMS JRST_B TEST0 TEST1 TEST2 PHYALM0 PHYALM1 PHYALM2 TFSS TXFP TCL GND TPD0 TPD1 TPD2 TPD3 TPD4 TPD5 TPD6 TPD7 TPC TFC VDD REFCLK GND-CS GND-CS AIN1 VDD-CS VDD-CS GND-CS VDD-SP VDD 18 User's Manual S11821EJ5V0UM S11821EJ5V0UM 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 VDD TADD4 TADD3 TADD2 TADD1 TADD0 GND RESET_B PHINT_B ACK_B/RDY_B R/W_B/WR_B DS_B/RD_B CS_B VDD MD7 MD6 MD5 MD4 MD3 MD2 MD1 MD0 GND UMPSEL MADD6 MADD5 MADD4 MADD3 MADD2 MADD1 MADD0 MSEL PMDALM RCL RXFP VDD CHAPTER 2 PIN FUNCTION Pin Assignment Number Pin Name Number Pin Name Number Pin Name Number Pin Name 1 VDD 37 GND 73 VDD 109 GND 2 JCK 38 GND-SP 74 RxFP 110 GND 3 JDO 39 VDD-TPE 75 RCL 111 TDI0 4 JDI 40 TFKT 76 PMDALM 112 TDI1 5 JMS 41 TFKC 77 MSEL 113 TDI2 6 JRST_B 42 GND-TPE 78 MADD0 114 TDI3 7 TEST0 43 TCOT 79 MADD1 115 TDI4 8 TEST1 44 TCOC 80 MADD2 116 TDI5 9 TEST2 45 VDD-TPE 81 MADD3 117 TDI6 10 PHYALM0 46 GND-TPE 82 MADD4 118 TDI7 11 PHYALM1 47 TDOT 83 MADD5 119 VDD 12 PHYALM2 48 TDOC 84 MADD6 120 TCLK 13 TFSS 49 VDD-TPE 85 UMPSEL 121 TENBL_B 14 TxFP 50 GND-RPE 86 GND 122 TSOC 15 TCL 51 RCIT 87 MD0 123 FULL_B/TCLAV 16 GND 52 RCIC 88 MD1 124 GND 17 TPD0 53 VDD-RPE 89 MD2 125 EMPTY_B/RCLAV 18 TPD1 54 RDIT 90 MD3 126 RSOC 19 TPD2 55 RDIC 91 MD4 127 RENBL_B 20 TPD3 56 GND-RPE 92 MD5 128 RCLK 21 TPD4 57 GND-CR 93 MD6 129 VDD 22 TPD5 58 VDD-CR 94 MD7 130 RDO0 23 TPD6 59 RPC 95 VDD 131 RDO1 24 TPD7 60 VDD 96 CS_B 132 RDO2 25 TPC 61 RPD0 97 DS_B/RD_B 133 RDO3 26 TFC 62 RPD1 98 R/W_B/WR_B 134 RDO4 27 VDD 63 RPD2 99 ACK_B/RDY_B 135 RDO5 28 REFCLK 64 RPD3 100 PHINT_B 136 RDO6 29 GND-CS 65 RPD4 101 RESET_B 137 RDO7 30 GND-CS 66 RPD5 102 GND 138 RADD0 31 AIN1 67 RPD6 103 TADD0 139 RADD1 32 VDD-CS 68 RPD7 104 TADD1 140 RADD2 33 VDD-CS 69 PSEL0 105 TADD2 141 RADD3 34 GND-CS 70 PSEL1 106 TADD3 142 RADD4 35 VDD-SP 71 GND 107 TADD4 143 GND 36 VDD 72 GND 108 VDD 144 GND User's Manual S11821EJ5V0UM S11821EJ5V0UM 19 CHAPTER 2 PIN FUNCTION ACK_B : Read/write Cycle Receive RDY_B REFCLK : System Clock AIN1 : External Filter Connection RENBL_B : Receive Data Enable CS : Chip Select RESET_B : System Reset DS_B : Data Strobe RPC : Receive Parallel Data Clock EMPTY_B : Output Buffer Empty RPD0-RPD7 : Receive Parallel Data FULL_B : Buffer Full RSOC : Receive Start Address of ATM Cell Acknowledge : Ready Signal GND : Ground RxFP : Receive Frame Pulse GND-RPE : Ground for Receive PECL buffer R/W_B : Read/write Control GND-CR : Ground for Clock Recovery Circuit TADD0-TADD4 : Transmit PHY Device Address GND-CS : Ground for Clock Synthesis TCL GND-SP : Ground for Serial/Parallel Circuit TCLAV : Transmit Cell Available GND-TPE : Ground for Transmit PECL buffer TCLK : Transmit Data Transferring Clock JCK : JTAG Clock TCOC : Transmit Clock Output Complement JDI : JTAG Data Input TCOT : Transmit Clock Output True JDO : JTAG Data Output TDI0-TDI7 : Transmit Data Input from the ATM Layer JMS : JTAG Mode Select TDOC : Transmit Data Output Complement JRST_B : JTAG Reset : Internal Transmit System Clock TDOT : Transmit Data Output True MADD0-MADD6 : Management Interface Address Bus TENBL_B : Transmit Data Enable MD0-MD7 : Management Interface Data Bus TEST0-TEST2 : Test Mode Pin MSEL : Management Interface Mode Select TFC : Transmit Reference Clock PHINT_B : Physical Interrupt TFKC : Transmit Reference Clock Complement PHYALM0- : PHY Alarm Detection TFKT : Transmit Reference Clock True TFSS : Transmit Frame Set Signal : PMD Device Alarm TPC : Transmit Parallel Data Clock PHYALM2 PMDALM PSEL0, PSEL1 : PMD Mode Select TPD0-TPD7 : Transmit Parallel Data RADD0-RADD4 : Receive PHY Device Address TSOC : Transmit Start Address of ATM Cell RCIC : Receive Clock Input Complement TxFP : Transmit Frame Pulse RCIT : Receive Clock Input True UMPSEL : UTOPIA Multi-PHY Mode Select RCL : Internal Receive System Clock VDD : Supply Voltage for Logic Circuit RCLAV : Receive Cell Available VDD_RPE : Voltage Supply for Receive PECL buffer RCLK : Receive Data Transferring Clock VDD-CR : Voltage Supply for Clock Recovery Circuit RD_B : Read Select VDD-CS : Voltage Supply for Clock Synthesis RDIC : Receive Data Input Complement VDD-SP : Voltage Supply for Serial/Parallel Circuit RDIT : Receive Data Input True VDD_TPE : Voltage Supply for Transmit PECL buffer RDO0-RDO7 : Receive Data Output WR_B : Write Select 20 User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 2 2.2 PIN FUNCTION Pin Function 2.2.1 PMD interface (1/3) Pin Name Pin No. I/O Level I/O RDIT 54 P-ECL True (+) I RDIC 55 P-ECL Complement (-) I RCIT 51 P-ECL True (+) I RCIC 52 P-ECL Complement (-) I TDOT 47 P-ECL True (+) O TDOC 48 P-ECL Complement (-) O TCOT 43 P-ECL True (+) O TCOC 44 P-ECL Complement (-) O TFKT 40 P-ECL True (+) I TFKC 41 P-ECL Complement (-) I RPD0RPD7 61-68 TTL I Receive parallel data input pins. These pins input receive data when PSEL[1:0] = "1X". The data input to these pins is sampled in synchronization with the rising of receive parallel clock RPC. 59 TTL I Receive parallel clock input pin (19.44 MHz). In the parallel mode when PSEL[1:0] = "1X", this pin is used to input a clock (19.44 MHz) synchronized with a receive data. 17-24 TTL O Transmit parallel data output pins. In the parallel mode when PSEL[1:0] = "1X", transmit data is output from these pins in synchronization with the rising of PC. TPC 25 TTL O Transmit parallel clock output pin. When PSEL[1:0] = "1X", the clock (19.44 MHz) input to TFC is output. TFC 26 TTL I Transmit parallel clock input pin. In the parallel mode when PSEL[1:0] = "1X", this pin is used to input the transmit clock (19.44 MHz). If the TxCL bits [1:0] of the MDR1 register are set to 10 in the serial mode with PSEL[1:0] = "00", input the 19.44 MHz source clock of the internal clock synthesizer PLL. RPC TPD0-TPD7 Function Receive serial data input pins. The input data is sampled with the recovered clock from the internal clock recovery PLL when PSEL[1:0] = "00". When PSEL[1:0] = "01", the data is sampled with the clock input to RCIT/RCIC. Receive serial clock input pins (155.52 MHz). When PSEL[1:0] = "01", these pins are used as the receive clock. Transmit serial data output pins. Data is output from these pins in synchronization with the rising of serial clock TCOT. Transmit serial clock output pins (155.52 MHz). The clock generated by the internal synthesizer PLL is output as the transmit clock when PSEL[1:0] = "00". When PSEL[1:0] = "01", the clock input to TFKT/TFKC is output. Depending on the mode selected, the transmit data may be latched by the receive clock for output. Even in such a case, this pin outputs the clock of the internal synthesizer or the clock input to the TFKT/TFKC pin in accordance with the setting of the PSEL[1:0] pins. It does not output the receive recovery clock. Transmit serial clock input pins (155.52 MHz). When PSEL[1:0] = "01", these pins are used as the transmit clock. User's Manual S11821EJ5V0UM S11821EJ5V0UM 21 CHAPTER 2 PIN FUNCTION 2.2.1 PMD interface (2/3) Pin Name Pin No. I/O Level I/O REFCLK 28 TTL I Reference clock input. Inputs the system clock (19.44 MHz) to the internal clock recovery/synthesizer. Always input this clock. PSEL0, PSEL1 69, 70 TTL I PMD interface mode select input. Selects the mode of the PMD layer interface. PSEL[1:0] = 00: Serial mode. The clock generated by the internal clock recovery & synthesizer PLL is used for transmission/reception. 01: Serial mode. An external clock is input to RCIT/RCIC TFKT/TFKC for transmission/reception. 1x: Parallel mode. The clock input to RPC & TFC is used. AIN1 31 Analog I/O PMDALM 76 TTL I PMD layer alarm signal input. The signal level of this pin is reflected in a state bit in an internal register, and a change in that bit can be used as an interrupt source. Input the state signal of a peripheral device to this pin. Input to this pin can be added as a condition of detecting the LOS error according to the setting of the PMD bit of the IACM register. For details, refer to 3.5 Alarm Report Pins (PHYALM[2:0], PMDALM). 10-12 TTL O PHY layer alarm detection signal output. These signals report the detection of the internally monitored errors (PMDALM, CMDARM, LOS, OOF, LOF, LOP, OCD, LCD, Line AIS, Path AIS, Line RDI, Path RDI). One error or two or more errors ORed can be output to one of these pins. The errors to be reported can be selected by using the internal AMPR, AMR1, and AMR2 registers. For details on use, refer to 3.5 Alarm Report Pins (PHYALM[2:0], PMDALM) in µPD98404 PD98404 User's Manual (S11821E S11821E). RxFP 74 TTL O Reception-side frame pulse output pin (8 kHz). Outputs a pulse signal with a width of one clock cycle in synchronization with the RCL clock. TxFP 14 TTL O Transmission-side frame pulse output pin (8 kHz). Outputs a pulse signal with a width of one clock cycle in synchronization with the TCL clock. TFSS 13 TTL I Transmit frame output disable signal input. When this signal goes high, output of the transmit frame is stopped; when it goes low, transmission is started from the beginning of the frame. The µPD98404 PD98404 samples this signal at the rising of the TCL clock. Transmission frame output is resumed after the TCL clock has risen for the 9th time after the rising edge at which the high level of this signal was last detected. RCL 75 TTL O Reception side internal system clock output (19.44 MHz). This pin outputs the receive clock divided by eight. The source receive clock differs depending on the mode selected (clock generated by the internal clock recovery or clock supplied from the RCIT/RCIC or RFC pin). Clock output from this pin is stopped while the device is being reset. PHYALM0PHYALM2 22 Function Pin for connecting a loop filter for internal synthesizer PLL. Leave open. User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 2 PIN FUNCTION 2.2.1 PMD interface (3/3) Pin Name TCL Pin No. I/O Level I/O Function 15 TTL O Transmission side internal system clock output (19.44 MHz). This pin outputs the transmit clock divided by eight. The source transmit clock differs depending on the mode selected (clock generated by the internal synthesizer or clock supplied from the TCIT/TCIC or TFC pin). Clock output from this pin is stopped while the device is being reset. User's Manual S11821EJ5V0UM S11821EJ5V0UM 23 CHAPTER 2 PIN FUNCTION 2.2.2 ATM layer interface (1/2) Pin Name Pin No. I/O Level I/O RDO0RDO7 130-137 TTL O (2-/3-state) Receive data output pins. These pins form an 8-bit data bus to output receive data to an ATM layer device. Data is output in synchronization with the rising of the RCLK clock. These pins operate in 2-state or 3-state mode in accordance with the UTOPIA interface mode. RCLK 128 TTL I Receive clock input pin. Inputs a clock for receive data transfer. A clock of up to 40 MHz is input. RSOC 126 TTL O (2-/3-state) RENBL_B 127 TTL I EMPTY_B/ RCLAV 125 TTL O (2-/3-state) RADD0RADD4 138-142 TTL I Reception-side PHY address input pins. These pins input an address to select a PHY layer device in the multiPHY mode. TDI0-TDI7 111-118 TTL I Transmit data input pins. These pins form an 8-bit data bus that inputs the transmit data. Data is input in synchronization with the rising of the TCLK clock. TCLK 120 TTL I Transmit clock input pin. Inputs a clock for transmit data transfer. A clock of 20 to 40 MHz is input. Caution The µPD98404 PD98404 also uses this clock as the system clock of the management interface block. Therefore, always input a clock of 20 MHz or higher. TSOC 122 TTL I Transmit cell start position output pin. This pin inputs a signal that indicates the position of the first byte of a transmit cell input to the µPD98404 PD98404. TENBL_B 121 TTL I Transmit enable input pin. Inputs a signal that indicates that an ATM layer device outputs valid transmit data to TDI0 through TDI7. 24 Function Receive cell start position signal output pin. Outputs a signal that indicates the position of the first byte of a receive cell. This pin operates in 2-state or 3-state mode in accordance with the UTOPIA interface mode. Receive enable signal input pin. Inputs a signal that indicates that the ATM layer is ready to accept receive data. Receive FIFO data transfer disable signal output or receive FIFO cell data transfer enable output pin. This pin operates in two ways depending on the selected mode of the UTOPIA interface. EMPTY_B indicates that no byte of receive data to be transferred to the ATM layer exists in the receive FIFO. RCLAV indicates that 1 or more bytes to be transferred to the ATM layer exist in the receive FIFO. User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 2 PIN FUNCTION 2.2.2 ATM layer interface (2/2) Pin Name Pin No. I/O Level I/O Function FULL_B/ TCLAV 123 TTL O (2-/3-state) Transmit FIFO data transfer disable signal output or transmit FIFO cell data transfer enable output pin. This pin operates in two modes depending on the mode of the UTOPIA interface. FULL_B indicates that there is no vacant area available in the transmit FIFO that receives data transferred from the ATM layer. TCLAV indicates that one cell or more of vacant area is available in the transmit FIFO to store the data transferred. TADD0TADD4 103-107 TTL I Transmission-side PHY address input pin. Inputs an address to select a PHY layer device in the multi-PHY mode. UMPSEL 85 TTL I Multi-PHY mode select signal input. High : Multi-PHY mode. When a high level is input to this pin, the multi-PHY mode is selected. Low : Single PHY mode. 2.2.3 Management interface (1/2) Pin Name Pin No. I/O Level I/O 77 TTL I Management interface mode select signal input pin. The mode of the management interface changes depending on the input level to this pin. MSEL=: 1 : Selects as pin function. 0 : Selects as pin function. MADD0MADD6 78-84 TTL I Address input pins. These pins form an address bus that inputs the addresses of the internal registers of the µPD98404 PD98404. MD0-MD7 87-94 TTL I/O (3-state) 8-bit data bus. This data bus reads or writes the data of the internal registers of the µPD98404 PD98404. CS_B 96 TTL I Chip select signal input pin. When this pin goes low, access to the internal registers is enabled. DS_B/ RD_B 97 TTL I Data strobe signal input or read signal input pin. This pin has two functions: DS_B and RD_B. The function to be used depends on the mode selected by the MSEL pin. MSEL = 0: Data strobe signal DS_B MSEL = 1: RD_B that selects a read access. MSEL Function User's Manual S11821EJ5V0UM S11821EJ5V0UM 25 CHAPTER 2 PIN FUNCTION 2.2.3 Management interface (2/2) Pin Name Pin No. I/O Level I/O Function R/W_B/ WR_B 98 TTL I Read/write signal input or write signal input pin. This pin has two functions: R/W_B and WR_B. The function to be used depends on the mode selected by the MSEL pin. MSEL = 0 : Read/write control signal R/W_B, as follows: R/W_B=: High level: Read cycle Low level : Write cycle MSEL = 1 : WR_B that selects write access to the internal registers. ACK_B/ RDY_B 99 TTL O (3-state) PHINT_B 100 TTL O Interface interrupt signal output pin. This reports to the host that an interrupt has been generated by making it low active. RESET_B 101 TTL I System reset signal input pin. Initializes the µPD98404 PD98404. Input a low-level pulse at least 1 µs wide. Particularly on power application, this pulse width must be maintained after the level of the supply voltage has reached 90% of the rated value. When the RESET_B signal is input, the following clock must be input in accordance with the mode of the PMD interface. In serial mode : TCLK/RCLK clock In parallel mode : All TCLK/RCLK and TFC/RPC clocks Pin No. I/O Level I/O Function JDI 4 TTL I JDO 3 TTL O (3-state) JCK 2 TTL I Boundary scan clock input. Ground this pin when not used. JMS 5 TTL I Boundary scan mode select signal input. Ground this pin when not used. JRST_B 6 TTL I Boundary scan reset signal input. Ground this pin when not used. Data acknowledge signal output or ready signal output. This pin has two functions: ACK_B and RDY_B. The function to be used depends on the mode selected by the MSEL pin. MSEL = 0 : Data strobe signal ACK_B MSEL = 1 : Read access select signal RDY_B 2.2.4 JTAG boundary scan Pin Name 26 Boundary scan data input. Ground this pin when not used. Boundary scan data output. Open this pin when not used. User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 2 Remark PIN FUNCTION Processing of JTAG boundary scan pins not used (during normal operation) The reason that the JRST_B pin is grounded when it is not used (during normal operation) is to better prevent malfunctioning of the JTAG logic. The JTAG pin may be also processed in either of the following ways: · Reset the JTAG logic without using the JRST_B pin Reset the JTAG logic by using the JMS and JCK pins and keep it in the reset status (the JRST_B pin is pulled up). Fix the JMS pin to 1 (pull up) and input 5 clock cycles or more to the JCK pin. · Reset the JTAG logic by using the JRST_B pin Input a low pulse of the same width as RESET_B of the µPD98404 PD98404 to the JRST_B pin. If both the JMS and JRST_B pins are pulled up and kept high, the JTAG logic is not released from the reset status. Therefore, the normal operation is not affected. Fix the input level of the JDI and JCK pins by pulling them down or up. 2.2.5 Internal test pin Pin Name TEST0TEST2 Pin No. I/O Level I/O 7-9 TTL I Function These pins are used to test the µPD98404 PD98404. Usually, ground all these pins. TEST[2:0] = "000" : Normal operation TEST[2:0] = Other than "000": Test mode 2.2.6 Power supply and ground Pin Name Pin No. I/O VDD 1, 27, 36, 60, 73, 95, 108, 119, 129 GND 16, 37, 71, 72, 86, 102, 109, 110, 124, 143, 144 VDD-TPE 39, 45, 49 GND-TPE 42, 46 VDD-RPE 53 GND-RPE 50, 56 VDD-SP 35 GND-SP 38 VDD-CS 32, 33 GND-CS 29, 30, 34 VDD-CR 58 GND-CR 57 Function General-purpose logic power supply (+3.3 V ± 0.15 V) and ground. Output PECL I/O power supply (+3.3 V ± 0.15 V) and ground. Noise on this power supply pin affects the jitter characteristics. Prevent noise by using a filter. Input PECL I/O power supply (+3.3 V± 0.15 V) and ground. Noise on this power supply pin affects the jitter characteristics. Prevent noise by using a filter. Serial/parallel block power supply (+3.3 V ± 0.15 V) and ground. Noise on this power supply pin affects the jitter characteristics. Prevent noise by using a filter. Clock synthesizer PLL block power supply (+3.3 V ± 0.15 V) and ground. Noise on this power supply pin affects the jitter characteristics. Prevent noise by using a filter. Clock recovery PLL block power supply (+3.3 V ± 0.15 V) and ground. Noise on this power supply pin affects the jitter characteristics. Prevent noise by using a filter. User's Manual S11821EJ5V0UM S11821EJ5V0UM 27 CHAPTER 2 2.3 PIN FUNCTION Processing of Unused Pins Pin Processing of Unused Pins Each input pin at level other than P-ECL Each input pin at P-ECL level Pull up True(+) pins (TFKT, RCIT, RDIT) to 3.3 V. Connect Complement(-) pins (TFKC, RCIC, RDIC) to ground. Output pin Leave open. (Parallel input pins in serial mode) TPD0 to TPD7 TPC (others) TxFP, RxFP, TCL, RCL Output pin at P-ECL level Leave open. TDOT, TDOC, TCOT, TCOC AIN1 28 Connect to ground (parallel input pin in serial mode) RPD0 through RPD7, RPC, TFC (Multi-PHY pins in single PHY mode) TADD0 to TADD4, RADD0 through RADD4 (others) TFSS (essential) Leave Open. Because noise on this pin affects the characteristics of the internal PLL, do not wire a clock line in the vicinity. User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 3 FUNCTIONAL OUTLINE The major functions of the µPD98404 PD98404 are to insert an ATM cell received from the ATM layer into a 155 Mbps SONET STS-3c/SDH STM-1 frame and output the cell to the circuit, or to receive the ATM cell from a receive SONET/SDH frame and output the cell to the ATM layer. Figure 3-1 outlines the formats of an ATM cell (user-network interface) and a STS-3c frame. Figure 3-1. Structure of ATM Cell (user-network interface (UNI) Transfer sequence 5 6 1 2 3 4 5 6 7 8 . . . . . . . . . . . . 53 (bytes) HEC VCI PTI Segment 48 bytes VPI GFC VPI 1 2 3 4 5 6 7 8 2 3 4 CLP 1 GFC: Generic Flow Control, PTI: Payload Type Identifier VPI: Virtual Path Identifier, CLP: Cell Priority VCI: Virtual Channel Identifier, HEC: Header Error Control Figure 3-2. Outline of Frame Format (1/2) Transmission direction SOH 3 LOH 6 A1 B1 D1 A1 A1 A2 A2 E1 D2 A2 J0 F1 D3 Z0 Z0 J1 B3 C2 H1 B2 D4 H1 H1 H2 H2 H2 H3 H3 H3 G1 B2 K1 D5 K2 D6 F2 H4 D8 D11 D9 D12 Z3 Z4 B2 D7 D10 S1 Z1 Z1 Z2 Z2 M1 E2 ATM cells Payload area Z5 9 bytes 261 bytes STS-3 POH User's Manual S11821EJ5V0UM S11821EJ5V0UM 29 CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-2. Outline of Frame Format (2/2) A1 (F6) SOH (Section Over Head) A1 (F6) A1 (F6) A1 (28) A1 (28) A1 (28) J0 (01) Z0 (02) Z0 (03) J1 (00) B1 (­ ­) E1 (00) F1 (00) B3 (­ ­) D1 (00) D2 (00) D3 (00) C2 (13) H1 (62) H1 (93) H1 (93) H1 (0A) B2 (­ ­) B2 (­ ­) B2 (­ ­) K1 (00) K2 (00) F2 (00) D4 (00) D5 (00) D6 (00) H4 (00) D7 (01) D8 (01) D9 (00) Z3 (00) D10 (00) D11 (00) D12 (00) Z4 (00) E2 (00) Z5 (00) LOH (Line Over Head) S1 (00) Z1 (00) Z1 (00) Z2 (00) H2 (FF) Z2 (00) H2 (FF) M1 (­ ­) H3 (00) H3 (FF) H3 (FF) G1 (­ ­) Path Overhead (POH) ( ) : Transmitter side default value (H) : Byte area automatically inserted/verified by µ PD98404 PD98404 : Byte area that can be read or written by register access : Byte area some bits of which can be changed by register write. (Only SS bit of H1 byte can be rewritten.) (Bits 1 through 5 of K2 byte can be rewritten.) : Byte area that cannot be read or written : Unused byte area. Insert 00H to this area. A1, A2 : Framing B2 : BIP-24 BIP-24 J1 : Path trace J0 K1 : Protection switching channel B3 : Path BIP-8 : Section alarm indication : Section trace Z0 : Spare K2 B1 : BIP-8 D4-D12 D4-D12: Data communication channel G1 C2 : Signal label : Error indication, path status E1 : Order wire S1 : Synchronization status F2 : Path user channel F1 : User channel Z1 : Spare H4 : Position indicator D1-D3 : Data communication channel Z2 : Spare Z3-Z5 : Spare H1, H2: Pointer M1 : Error indication H3 E2 : Order wire 30 : Pointer action User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 3 FUNCTIONAL OUTLINE 3.1 Transmission Function The transmission function of the µPD98404 PD98404 inserts an ATM cell received from an ATM layer device into a SONET STS-3c/SDH STM-1 frame, and outputs the cell to the PMD interface. This section explains the frame transmission function of the µPD98404 PD98404 mainly based on the flow of processing. Figure 3-3. Outline of µPD98404 PD98404's Frame Transmission Function PMD layer interface ATM layer interface (UTOPIA) 155.52 Mbps STS-3c/STM-1 frame Cell from ATM layer device µ PD98404 PD98404 NEASCOT-P30 NEASCOT-P30 Cell Overhead On power application, the µPD98404 PD98404 starts operation in the mode determined by the default value of each mode register, and transmits STS-3c frames until the setting of the mode register is changed. At this time, the µPD98404 PD98404 inserts idle cells (vacant cells) in the frames until it receives an ATM cell from an ATM layer device. The µPD98404 PD98404 processes transmit data in the following sequence: (1) Cell data reception from ATM layer device The µPD98404 PD98404 receives 53 byte length cell data from an ATM layer device via the ATM layer interface and stores the data in the transmit FIFO. The transmit FIFO has a capacity of about 7 cells (384 bytes) and has a buffer function to adjust the rate between the ATM layer and PMD. If there is a period during which no cell data is sent from the ATM layer and if the transmit data in the FIFO is 1 cell or less, vacant cell is inserted in the frame. The vacant cell to be inserted is in the idle cell format in the default mode. However, its format can be changed to the unassigned cell format by setting the idlenb bit of the mode register 2 (MDR2). Figure 3-3 shows these formats. For the details of the ATM layer interface, refer to 4.1 ATM Layer Interface. Figure 3-4. Vacant Cell Format Inserted by µPD98404 PD98404 Header: 5 bytes Payload: 48 bytes 1 3 4 5 1 2 ··· 47 48 Idle cell 00H 00H 00H 01H 52H 6AH 6AH ··· 6AH 6AH Unassigned cell Remark 2 00H 00H 00H 00H 55H 00H 00H ··· 00H 00H If cells in the idle cell or unassigned cell format are input to the ATM layer interface at the transmitter side of the µPD98404 PD98404, the µPD98404 PD98404 handles them in the same manner as normal valid data, maps them to a frame and outputs the frame to the circuit side. It does not internally discard the cells. User's Manual S11821EJ5V0UM S11821EJ5V0UM 31 CHAPTER 3 FUNCTIONAL OUTLINE (2) Generation of HEC CRC operation is performed on the high-order 4 bytes of the 5 bytes of the header of an ATM cell. The value resulting from the operation plus "55H" is overwritten to the fifth byte position of the ATM header to carry out HEC (Header Error Check). 8 2 Polynomial G (X) = X + X + X + 1 Remark The µPD98404 PD98404 does not check the content of the fifth byte (position of HEC) from the beginning of the cell data input from the ATM layer device, or does not internally use the content. Because the value of the calculated HEC is overwritten to this byte area, the ATM layer device must insert a dummy byte such as ""00H" into this area. (3) Scramble of ATM cell The data of an ATM is scrambled by using the following polynomial. The range of scramble is limited to the payload of the ATM cell. 43 Polynomial G (X) = X + 1 The user can select a scramble stop mode for the purpose of testing. The scramble stop mode is set by the CSCRM bit of mode register 3 (MDR3). (4) Generation of frame SONET frame format is generated by multiplexing the overhead information on successive ATM cells. The µPD98404 PD98404 generates H1, H2, H3, K2, Z2, G1, A1, and A2 bytes as frame overhead information, links these bytes with the payload. For the format of the frame, refer to Figure 3-2. Outline of Frame Format. (a) AU pointer and generation of byte information The transmit frame sent out by the µPD98404 PD98404 does not change the position of POH (Path Overhead). Nor is the position of the J1 byte changed. Therefore, the pointer value to be assigned to the H1 and H2 bytes is always 20AH = "1000001010", and NDF is fixed to "0110" (disable). The SS bits, which are the fifth and sixth bits of the H1 byte, are "00" as default assumption. These bits can be changed by setting the SS bit table of the MDR1 register. Because the transmitter side does not request Frequency Justification (stuff operation), no data is stored in the H3 bytes that are used as de-stuff bytes. Figure 3-5. Format of AU Pointer (H1 through H3 bytes) 1st H1 byte 1st H2 byte 1st through 3rd H3 byte 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 N N N N S S I D I NDF (4 bits) SS 0 0 1 S S I D I D I D Pointer (10 bits) 2nd and 3rd H1 byte 1 D 1 2nd and 3rd H2 byte 1 1 1 1 1 1 1 1 1 Concatenation indication 32 User's Manual S11821EJ5V0UM S11821EJ5V0UM Negative stuff bytes CHAPTER 3 FUNCTIONAL OUTLINE Remark NDF : New Data Flag. Enable or disable command when the pointer value is changed. The µPD98404 PD98404 does not change the pointer value (disable). SS bit : Indicates the type of the virtual container. Insert the bit stored in the SS table of MDR1. The default value is "00". Pointer : Indicates the position of the first byte J1 of POH and indicates Frequency Justification (stuff operation). I (Increment bit) : Positive Justification (positive stuff) operation request D (Decrement bit) : Negative Justification (negative stuff) operation request Concatenation indication : Indicates concatenation. H1 through H3 Bytes of Transmit Frame H1 Byte H2 Byte H3 Byte 1st 0110 SS10 0000 1010 0000 0000 2nd 1001 SS11 1111 1111 1111 1111 3rd 1001 SS11 1111 1111 1111 1111 Insert registers are available for bytes J0, Z0, F1, K1, K2, F2, C2, and H4 of the byte information of the overhead. Any value can be stored and transmitted by setting the insert register. The µPD98404 PD98404 transmits the default value unless changed. (b) Transmit BIP generation The µPD98404 PD98404 performs a BIP (Bit Interleaved Parity) operation on the transmit data, and inserts the result of the operation to the positions equivalent to the B1, B2, and B3 bytes of the next transmit overhead data. For details, refer to 3.3.1 (2) Functions related to monitoring circuit quality on transmission side. (5) Scramble of frame The frame to be transmitted is scrambled with the polynomial below. The entire range of the STS-3c/SDH STM-1 frame, except the 9 bytes from the beginning "A1 (1), A1 (2), A1 (3), A2 (1), A2 (2), A2 (3), C1 (1), C1 (2), C1 (3)", is scrambled. 6 7 Polynomial G (X) = 1 + X + X The user can select a scramble stop mode for the purpose of testing. The scramble stop mode is selected by the FSCRM bit of mode register 3 (MDR3). (6) Output from PMD interface The PMD interface converts data into an 8-bit parallel string or serial data string for output. The user can select the serial or parallel interface mode and the use of the transmit clock synthesizer PLL by using the PSEL[1:0] pins. For the details of the PMD interface, refer to 4.2 PMD Interface. User's Manual S11821EJ5V0UM S11821EJ5V0UM 33 CHAPTER 3 FUNCTIONAL OUTLINE 3.2 Reception Function The reception function of the µPD98404 PD98404 extracts an ATM cell from the frame received from the PMD interface, and outputs cell to an ATM layer device by outputting it to the ATM interface. Figure 3-6. Outline of µPD98404 PD98404's Frame Reception Function PMD layer interface ATM layer interface (UTOPIA) 155.52 Mbps STS-3c/STM-1 frame Cell from ATM layer device µ PD98404 PD98404 NEASCOT-P30 NEASCOT-P30 Cell Overhead After power application, the µPD98404 PD98404 immediately starts receiving a frame in the default operation mode. This section explains the reception function of the µPD98404 PD98404 mainly based on the flow of processing. The µPD98404 PD98404 processes receive data in the following sequence: (1) Frame reception The µPD98404 PD98404 receives the data stream of the frame from the PMD interface. In the serial interface mode, the µPD98404 PD98404 samples the data signal input to the RDIC/RDIT pin with the receive clock generated by the internal clock recovery or the clock synchronized with the data input to the RCIC/RCIT pin. In the parallel interface mode, the µPD98404 PD98404 samples the data signals input to the RPD0 through RPD7 pins with the synchronization clock input to the RPC pin. The serial or parallel interface mode and the use of the receive clock recovery PLL is selected by using the PSEL[1:0] pins. For the details of the PMD interface, refer to 4.2 PMD Interface. 34 User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 3 FUNCTIONAL OUTLINE (2) Synchronization of receive frame The µPD98404 PD98404 monitors the bit string of the receive data if frame synchronization is not established. If the synchronization pattern of bytes A1 and A2 (6 bytes) is detected in a bit string, the bit string at the position of bytes A1 and A2 of the next frame is checked. If the bit string in bytes A1 and A2 has the same synchronization pattern, the frame synchronization (In frame) status is established. Table 3-1. Synchronization Pattern Frame Synchronization Byte A1 11110110 (F6H) A2 00101000 (28H) Even in the frame synchronization status, the µPD98404 PD98404 always monitors the A1 and A2 byte positions (6 bytes) of the receive frame. If four or more frames having a pattern different from the patterns of the A1 and A2 bytes are received at the positions of the A1 and A2 bytes in succession, the µPD98404 PD98404 enters the frame nonsynchronization (Out of Frame) status. If the OOF status continues for 3 ms, the LOF (Loss Of Frame) status takes place. LOF is cleared if frame synchronization status continues for 3 ms. (3) Descramble of receive frame After synchronization has been established, the received frame is descrambled with the polynomial shown below. The entire range of the frame, except the 9 bytes from the beginning, "A1 (1), A1 (2), A1 (3), A2 (1), A2 (2), A2 (3), C1 (1), C1 (2), C1 (3)" is descrambled. 6 7 Polynomial G (X) = 1 + X + X The user can select a descramble stop mode for the purpose of testing. The descramble stop mode is selected by the FSCRM bit of mode register 3 (MDR3). (4) Pointer processing Frame descramble detects the pointer that indicates the first J1 byte address in the received data string to extract the payload area, and updates the pointer each time a frame has been received. If the pointer cannot be updated, the LOP (Loss Of Pointer) status occurs. Path AIS is also detected from the H1 and H2 bytes of SOH. User's Manual S11821EJ5V0UM S11821EJ5V0UM 35 CHAPTER 3 FUNCTIONAL OUTLINE Figure 3-7. Pointer Status Transition a, b, c Normal d, e f g i, j h LOP P-AIS k Normal status : The received pointer is normal and reception is performed normally. Path-AIS status : An error occurred in an upstream unit or transmission path, and reception is not performed normally. LOP status : The received pointer value is abnormal and reception is not performed normally. Transition a Normal Normal Condition NDF Disable + Same valid pointer three times in a row b NDF Enable + Valid pointer c Positive justification/negative justification d Normal LOP e Eight pointers other than valid pointer in a row Eight NDF Enables in a row f Normal Path-AIS H1 and H2 bytes are all "1" three times in a row. g LOP Normal NDF Disable + Same valid pointer three times in a row h LOP Path-AIS H1 and H2 bytes are all "1" three times in a row. i Path-AIS Normal NDF Disable + Same valid pointer three times in a row j k NDF Enable + Valid pointer Path-AIS LOP H1 and H2 bytes are not all "1" and eight pointer values in a row that do not satisfy the above conditions i and j. (5) Reception Frequency Justification (stuff operation) Frequency Justification (stuff operation) is detected and the following operation is performed if three or more bits of the I/D bits (5 bits) are inverted during pointer processing (refer to Figure 3-5 Format of AU Pointer (H1 through H3 bytes). Positive Justification (positive stuff) : The byte at pointer address 0 is not received as payload data if it is detected that three or more bits of I bits are inverted. Negative Justification (negative stuff) : The H3 byte area is received as payload data if it is detected that three bits or more of the D bits are inverted. 36 User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 3 FUNCTIONAL OUTLINE (6) Cell synchronization The boundary of cells is detected to extract an ATM cell from the area excluding the overhead in the frame. The status in which the boundary is correctly detected and the cell can be extracted is called cell synchronization status. The cell boundary is detected by HEC (header error check) processing included in the header of a cell as shown in the status transition in Figure 3-8. The number of protection stages is 7 forward and 6 backward. Figure 3-8. Cell Synchronization Status Transition Hunting status (HUNT) No HEC error HEC error 7 times in row HEC error Preceding synchronization status (PRESYNC) HEC without error 6 times in row Cell synchronization status (SYNC) · In the hunting status, whether an HEC error has occurred is checked. Once HEC has been satisfied and HEC without an error has been detected, the preceding synchronization status is established. · In the preceding synchronization status, reception is repeated until HEC without an error is detected six times in a row. If an HEC error is detected, the hunting status is set again. · In the cell synchronization status, it is judged that cell synchronization is no longer established if a HEC error is detected seven times in a row, and the hunting status is set again. · Whether cell synchronization is established or not is indicated by the OCD (Out of Cell Delineation) bit of the ACR register. Table 3-2. OCD Bit Status OCD Bit HUNT/PRESYNC status SYNC status · 1 0 If the OCD status lasts for 4 ms, the LCD (Loss of Cell Delineation) status occurs. LCD is cleared if the cell synchronization status lasts for 4 ms. User's Manual S11821EJ5V0UM S11821EJ5V0UM 37 CHAPTER 3 FUNCTIONAL OUTLINE (7) HEC error detection/correction HEC errors are detected and corrected while cell synchronization is established. Figure 3-9. HEC Check Status Transition in Cell Synchronization Status Cell synchronization status (SYNC) Multiple bit error detection (cell dropped) No error (cell passes) Correction mode No error Error detection Cell dropped Detection mode (Cell passes) From preceding synchronization status to cell synchronization status 1-bit error detection (Cell passes) From cell synchronization status to hunting status · An error of only 1 bit is corrected in the correction mode and then the detection mode is set. · HEC errors are continuously monitored in the correction mode. If errors are detected seven times, the status is changed from the cell synchronization status to the hunting status. · Cell header error control differs depending on the setting of the HECENB and CORENB bits of mode register 3 (MDR3). With the µPD98404 PD98404, the HEC check processing in the cell synchronization status can be changed as follows by using the HECENB and CORENB bits of the MDR3 register. 38 User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 3 FUNCTIONAL OUTLINE Table 3-3. HEC Error Correction Mode HECENB CORENB Current Mode Correction mode Event No error Processing New Mode Correction mode 1-bit error detection Detection mode Detection mode Multiple bit error detection 0 Error correction Cell dropped Detection mode No error Correction mode 1-bit error detection Correction mode Detection mode Multiple bit error detection 0 Cell dropped Cell dropped Detection mode No error Correction mode 1-bit error detection Detection mode Detection mode Multiple bit error detection 1 Cell dropped Cell dropped Detection mode No error Correction mode 1-bit error detection Cell dropped Detection mode Multiple bit error detection Cell dropped Detection mode Detection mode Detection mode No error Correction mode Detection mode Multiple bit error detection Detection mode Correction mode Multiple bit error detection x 1-bit error detection 1 No error 1-bit error detection Correction mode Detection mode (8) Descramble of ATM cell In the cell synchronization status, the data of the ATM cell is descrambled by the following polynomial. The range of descramble is limited to the payload of the ATM cell. 43 Polynomial G (X) = X + 1 The user can select a descramble stop mode for the purpose of testing. The descramble stop mode is selected by the CSCRM bit of mode register 3 (MDR3). (9) Dropping idle cell (vacant cell) The µPD98404 PD98404 drops an ATM cell whose high-order 4 bytes are "00 00 00 01H" as an idle cell. User's Manual S11821EJ5V0UM S11821EJ5V0UM 39 CHAPTER 3 FUNCTIONAL OUTLINE (10) Unassigned cell dropping mode After power application, the µPD98404 PD98404 passes an unassigned cell, as default operation, with the high-order 4 bytes of its ATM header being "00 00 00 00H" to the ATM layer as a valid cell when it has received such a cell. The µPD98404 PD98404 also has a mode in which this unassigned cell is dropped if received. To use the µPD98404 PD98404 in the unassigned cell dropping mode, set the CLP bit of both DCHPR and DCHPMR registers. (a) Functions of DCHPR and DCHPMR registers The CLP field of a receive cell with VPI/VCI fields all at 0 is compared with the contents of the DCHPR register. If this field coincides with the register contents, the cell is dropped. DCHPMR is a register that masks a bit to be compared. If the CLP bit of this register is set to "1", the field of the receive cell is not compared with the CLP bit of DCHPR. Table 3-4. Example When CLP Bit Is Used DCHPR DCHPMR Cells Dropped 01 00 Drops idle cells (default mode) 00 00 Drops unassigned cells 00 01 Drops idle cells and unassigned cells (11) Output of ATM cell from ATM layer interface The ATM cell is stored to a receive FIFO with a capacity of about 4 cells (256 bytes) to adjust the rate with the ATM layer interface. The ATM cell is always output to an ATM layer device via the ATM layer interface. For the details of the ATM layer interface, refer to 4.1 ATM Layer Interface. 40 User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 3 FUNCTIONAL OUTLINE 3.3 OAM Information Control Function The µPD98404 PD98404 has an OAM (Operation And Maintenance) function to maintain and monitor the network. This section explains the OAM functions supported by the µPD98404 PD98404. 3.3.1 Transmission OAM control (1) Transmitting alarm Alarm is written to a specific overhead area of the transmit frame and transmitted. Table 3-5. Transmitting Alarm Alarm Transmission Method Line AIS/Path AIS Transmitted/cleared by command Line RDI Path RDI Transmitted/cleared by command Automatically transmitted by occurrence of internal problem (automatic transmission can be masked) Line REI/Path REI Automatically generated and transmitted internally (a) Transmitting Line AIS (Line Alarm Indication Signal) Line AIS is a line alarm indication signal that detects a failure in the upstream and sends an alarm to the downstream during relaying. The µPD98404 PD98404 changes the sixth through eighth bits of the K2 byte of the transmit frame to "111" and sets the bits in all the areas of POH and payload (before scramble) to "1" for transmission if the LAIS bit of command register 1 (CMR1) is set to 1. Whether Line AIS is transmitted or cleared is determined by the user. Transmission overhead : K2 byte (6th through 8th bits) = 111 and areas of POH and payload = 1 Transmission/clearing condition: Transmission or clearing is controlled by the host by setting the LAIS bit of the command register 1 (CMR1). (b) Transmitting Path AIS (Path Alarm Indication Signal) Path AIS is a path far-end reception failure information that is reported to the downstream when a failure is detected in the upstream and alarm is issued during relaying. The µPD98404 PD98404 changes all the bits of the overhead H1, H2, and H3 bytes of the transmit frame to "1" and all the bits in the SPE area (before scramble) to "1" for transmission if the PAIS bit of command register 1 (CMR1) is set to 1. Transmission overhead : H1 through H3 bytes = all "1" & SPE bit area = all "1" Transmission/clearing condition: Transmission/clearing is controlled by the host by setting the PAIS bit of command register 1 (CMR1). User's Manual S11821EJ5V0UM S11821EJ5V0UM 41 CHAPTER 3 FUNCTIONAL OUTLINE (c) Transmitting Line RDI (Line Remote Detect Indication) Line RDI is a signal that reports detection of a line receive failure (LOS, LOF, or Line AIS) to a unit in the upstream. The µPD98404 PD98404 sets the sixth through eight bits of overhead K2 byte of the transmit frame to "110" for transmission if the LRDI bit of command register 1 (CMR1) is set to 1. It also automatically transmits these bits when an internal problem (occurrence of LOS, LOF, or Line AIS) is detected. This automatic transmission due to occurrence of an internal problem can be masked by the IACM register. Transmission overhead : K2 byte (6th through 8th bits) = 110 Transmission/clearing condition: · · Setting by command register Automatic transmission/clearing by occurrence of the following internal actions (can be masked by command register) Detection/clearing of LOF Detection/clearing of LOS Detection/clearing of Line AIS Caution If the µPD98404 PD98404 is used in the mode in which the PSEL[1:0] pins = 01 (serial mode in which the externally supplied RCIT/RCIC and TFKT/TFKC clocks are used as transmit/receive clocks), the µPD98404 PD98404 does not automatically transmit Line-RDI even if LOS, LOF, or LineAIS is detected at the receiver circuit side, unless the receive clock is input to the RCIT/RCIC pin. This is because the automatic transmitter circuit of Line-RDI needs part of the receive clock. Therefore, be sure to input the receive clock when using the Line-RDI automatic detection function in the mode in which the PSEL[1:0] pins = 01. (d) Transmitting Path RDI (Path Remote Detect Indication) Path RDI is a signal that reports detection of a path receive failure (LOS, LOF, Line AIS, LOP, LCD, or Path AIS) to a unit in the upstream. The µPD98404 PD98404 sets the fifth bit of the overhead G1 byte of the transmit frame to "1" for transmission if the PRDI bit of the command register 1 (CMR1) is set to 1. It also automatically transmits this bit if an internal problem (occurrence of LOS, LOF, Line AIS, LOP, LCD, or Path AIS) is detected. This automatic transmission due to occurrence of an internal problem can be masked by the IACM register. Transmission overhead : G1 byte (5th bit) = 1 Transmission/clearing condition: · · Setting by command register Automatic transmission/clearing by occurrence of the following internal actions (can be masked) Detection/clearing of LOF Detection/clearing of Line AIS Detection/clearing of LOP 42 Detection/clearing of LCD Detection/clearing of LOS Detection/clearing of Path AIS User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 3 FUNCTIONAL OUTLINE (2) Functions related to monitoring circuit quality on transmission side (a) Bit Interleaved Parity (BIP) B1 byte (Section BIP-8): BIP-8 operation is performed on all the frame data (data after scramble) except the first line of SOH (Section Overhead) of the transmit frame, BIP-8 operation is performed on a specific area, and the result of the operation is inserted in the B1 byte of the transmit frame and transmitted. 270 bytes SOH 1 frame 9 rows After scramble B1 SOH 1 frame 9 rows Before scramble : BIP operation range B1: BIP-8 operation result of preceding frame B2 byte (Line BIP-24 BIP-24): BIP-24 BIP-24 operation is performed on all frame data (data before scramble) except the first, second, and third lines of SOH one frame before, and the result of the operation is inserted to the B2 byte of the next transmit frame and transmitted. 9 bytes 270 bytes 3 rows 1 frame 9 rows Before scramble 6 rows 1 frame 9 rows Before scramble [B2 × 24 ] : BIP operation range B2 × 24: BIP operation result of preceding frame User's Manual S11821EJ5V0UM S11821EJ5V0UM 43 CHAPTER 3 FUNCTIONAL OUTLINE B3 byte (Path BIP-8): BIP-8 operation is performed on all the payload data (data before scramble), and the result of the operation is inserted to the B3 byte of POH (Path Overhead) of the next transmit frame and transmitted. 271 bytes 9 rows P O H 9 rows B3 Before scramble Before scramble : BIP operation range B3: BIP-8 operation result of preceding frame (b) Detecting Line REI (Line Remote Error Indication) Whether Line BIP-24 BIP-24 error has occurred is reported to a unit in the upstream. When the µPD98404 PD98404 detects a B2 error in the receive frame, it automatically stores the number of errors in the M1 byte (fourth through eighth bits) of the transmit frame and transmits the byte. (c) Transmitting Path REI (Path Remote Error Indication) Whether Path BIP-8 error occurs is reported to a unit in the upstream. When the µPD98404 PD98404 detects a B3 error in the receive frame, it automatically stores the number of errors to the G1 byte (first through fourth bits) of the transmit frame and transmits the byte. 44 User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 3 FUNCTIONAL OUTLINE 3.3.2 Reception OAM Control (1) Detection of alarm and failure The µPD98404 PD98404 sets the corresponding bit of the internal interrupt cause register if any of the following alarms or failures is detected, to report the occurrence of the alarm or failure to cause the host via an interrupt signal. The host can identify the alarm or failure that has occurred by reading the corresponding interrupt cause register. Each interrupt cause can be masked or unmasked. Detection of an alarm or failure can be reported cause using three PHYALM (2 through 0) output pins. Which alarm or failure is output to each PHYALM pin is specified by the AMPR, AMP1, and AMR2 registers. Table 3-6. Alarm and Failure List (1/2) PMD (PMD Layer Device) Alarm Indicates that PMDALM pin goes high. Detection : Detects high level of the PMDALM pin Clear : Detects that PMDALM pin goes back low LOS (Loss Of Signal) Receive signal lost status Detection : If a pattern of all 0s or all 1s is received for about 80 µs continuously or if the PMDALM pin goes high when the PMD bit of the IACM register = 0 Clear : If LOS condition is not detected for 125 µs or if the PMDALM pin goes low when the PMD bit of the IACM register = 0 OOF (Out Of Frame) Frame non-synchronization Detection : If frame synchronization pattern (A1, A2) error of receive data is detected in four successive frames Clear : If frame synchronization pattern is detected in two successive frames LOF (Loss Of Frame) Loss of Frame Detection : If OOF status lasts for 3 ms Clear : If not OOF status lasts for 3 ms LOP (Loss Of Pointer) Pointer error detection Detection : Refer to 3.2 (4) Pointer processing. Clear : Refer to 3.2 (4) Pointer processing. If OOF is detected, LOP status is forcibly set. OCD (Out of Cell Delineation) Cell non-synchronization Detection : If cells having header in which error is detected as result of HEC check are received seven times continuously. OCD status is forcibly set if OOF, LOP, or PATH-AIS is detected. Clear : If cells having valid header are detected seven times continuously LCD (Loss of Cell Delineation) Cell non-synchronization detection Detection : If OCD status lasts for 4 ms Clear : If cell synchronization status lasts for 4 ms Line AIS (Line Alarm Indication Signal) Line alarm indication signal. Detects occurrence of Line AIS in unit of transmission source (upstream). Detection : If frames with overhead K2 byte (6th through 8th bits) being "111" are received five times continuously Clear : If frames with overhead K2 byte (6th through 8th bits) not being "111" are received five times continuously User's Manual S11821EJ5V0UM S11821EJ5V0UM 45 CHAPTER 3 FUNCTIONAL OUTLINE Table 3-6. Alarm and Failure List (2/2) Path AIS (Path Alarm Indication Signal) Path alarm indication signal. Detects occurrence of Path AIS in unit of transmission source (upstream). Detection : Refer to 3.2 (4) Pointer processing. Clear : Refer to 3.2 (4) Pointer processing. Line RDI (Line Remote Defect Indication) Line remote reception failure information. Indicates detection of line reception failure (LOS, LOF, or Line AIS) in unit of transmission destination (downstream). Detection : If frames with overhead K2 byte (6th through 8th bits) being "110" are received five times continuously Clear : If frames with overhead K2 byte (6th through 8th bits) being other than "110" are received five times continuously Path RDI (Path Remote Defect Indication) Path remote reception failure information. Indicates detection of path reception failure (LOS, LOF, Line AIS, LOP, LCD, or Path AIS) in unit of transmission destination (downstream). Detection : If frames with 5th bit of overhead G1 byte being "1" are received five times continuously Clear : If frames with 5th bit of overhead G1 byte being "0" are received five times continuously OOL (Out Of Link) Indicates whether the receive clock recovery PLL has correctly locked on to the receive data stream, and whether it is the expected clock signal. Detection : When the difference between the clock signal input to the REFCLK pin and the clock signal generated by the recovery PLL divided by eight is greater than 244 ppm. Clear : When the difference between the clock signal input to the REFCLK pin and the clock signal generated by the recovery PLL divided by eight is within 244 ppm. 46 User's Manual S11821EJ5V0UM S11821EJ5V0UM CHAPTER 3 FUNCTIONAL OUTLINE (2) Reporting degradation of reception side circuit quality (performance monitor) The µPD98404 PD98404 sets the corresponding bit of the internal interrupt cause register and reports to the host using an interrupt signal if it detects degradation of the circuit quality. The host can identify the cause of degradation of the circuit quality by reading the interrupt cause register. Each interrupts cause can be masked or unmasked. Table 3-7. Performance Cause Register (PCR register) B1 error detection Detects section layer BIP-8 error in receive data. BIP-8 operation is performed on all frame data (data after scramble) except first line of SOH one frame before, result of this operation is verified against result of Section BIP-8 operation performed at transmission source (upstream) and stored to B1 byte of current frame, and B1 error is checked. B2 error detection Detects line layer BIP-24 BIP-24 error in receive data. BIP-24 BIP-24 operation is performed on all frame data (data before scramble) except first, second, and third lines of SOH one frame before, result of this operation is verified against result of Line BIP-24 BIP-24 operation performed at transmission source (upstream) and stored to B2 byte of current fame, and B2 error is checked. B3 error detection Detects path layer BIP-8 error in receive data. BIP-8 operation is performed on all payload data (data before scramble) one frame before, result of this operation is verified against result of Path BIP-8 operation performed at transmission source (upstream) and stored to B3 byte of current frame, and B3 error is checked. Line REI detection (Line Remote Error Indication) Line far end block error information. Detects Line BIP-24 BIP-24 errors in unit at transmission destination (downstream). Detection : Line REI is detected if 4th through 8th bits of receive M1 byte are 01 to 18 (H) Clear : Line REI is cleared if 4th through 8th bits of receive M1 byte are 00 (H) Path REI detection (Path Remote Error Indication) Path far end block error information. Detects Path BIP-8 errors in unit at transmission destination (downstream). Detection : Path REI is detected if 1st through 4th bits of receive G1 byte are 1 to 8 (H) Clear : Path REI is cleared if 1st through 4th bits of receive G1 byte are 0 (H) Occurrence of Frequency Justification Detects occurrence of Frequency Justification User's Manual S11821EJ5V0UM S11821EJ5V0UM 47 CHAPTER 3 FUNCTIONAL OUTLINE (3) Monitoring circuit quality using count register The µPD98404 PD98404 counts the number of faults that degrade the circuit quality, the number of times receive Frequency Justification has occurred, and the number of cells dropped due to occurrence of an HEC error with counters, in order to monitor the circuit quality. The host can obtain the value of these counters by reading the registers. Table 3-8. Counters Counter Name Count Contents Number of Counter Bits B1 error counter Number of times B1 error has been detected 16 B2 error counter Number of times B2 error has been detected 20 B3 error counter Number of times B3 error has been detected 16 Line-REI counter Total number of errors received by Line REI 20 Path-REI counter Total number of errors received by Path REI 16 FJ counter Number of Frequency Justification operations 12 HEC counter Total number of cells dropped by HEC processing 20 FIFO full counter Total number of cells dropped due to FIFO overflow 20 Idle cell counter Total number of received idle cells (cells dropped by setting of DCHPR and DCHPMR registers) 20 Information cell counter Total number of valid cells transferred to ATM layer device (including cell with HEC error corrected) 20 The counter functions are implemented by the following registers. These registers are provided to each of the above counters. Counter : Counter that counts the internal events. When the count value reaches "F(H)", the corresponding bits of the PCOCR1 and PCOCR2 registers are set, and detection of an overflow is reported. The count value of the counter returns to 0 and the counter continues counting up. Load registers : If the SMP bit of the PCSR register is set to "1" by the host, the current count values of all the counters are stored to the corresponding load registers. The contents of this register are retained until the SMP bit is set to 1 next time. Window register: This is an 8-bit register used by the host to read the contents of the load registers. To obtain a load register value 12 or 16 bits wide, the value of the load register is output in 8-bit units, in the order of the low-order 8 bits, high-order 8-bits, the low-order 8-bits, high-order 8-bit