PD8875 PD8875CY-A S18949EJ1V0DS00 S10800 S10799 S18949EJ1V0DS C-500S HA-50 - Datasheet Archive

 

Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

 

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT PD8875 PD8875 (5400+5400) PIXELS × 3 COLOR + (5400+5400) PIXELS B&W CCD LINEAR IMAGE SENSOR DESCRIPTION The PD8875CY-A PD8875CY-A is a color CCD (Charge Coupled Device) linear image sensor that changes optical images to electrical signal. It has 3 rows of (5400 + 5400) staggered color pixels and (5400 + 5400) staggered pixels of black and white , and each row has dual-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi / A4 color image scanners. FEATURES · Valid photocell : (5400 + 5400) staggered pixels of RGB + (5400 + 5400) staggered pixels of B&W · Photocell's size : 5.25 × 5.75 m (RGB), 5.25 × 3.2 m (B&W) · Line spacing : 63 m (12 lines) Red line - Green line, Green line - Blue line 63 m (12 lines) Blue odd line - B&W even line · Color filter : High transmittance new color filter Primary colors (red, green and blue), pigment filter (with light resistance 107 lx·hour) · Resolution : 48 dot/mm A4 (210 × 297 mm) size (shorter side) for color and B&W 1200 dpi US letter (8.5" × 11") size (shorter side) for color and B&W · Drive clock level : CMOS output under 5 V operation · Data rate : 20 MHz Max (RGB), 40 MHz Max (B&W at 600 dpi mode) · Power supply : + 12 V · On-chip circuits : Reset feed-through level clamp circuits Voltage amplifiers ORDERING INFORMATION Part Number Package PD8875CY-A PD8875CY-A CCD linear image sensor 22 pin plastic DIP (10.16 mm (400) Remark The PD8875CY-A PD8875CY-A is a lead-free product. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. S18949EJ1V0DS00 S18949EJ1V0DS00 (1st edition) Date Published September 2007 NS Printed in Japan 2007 PD8875 PD8875 BLOCK DIAGRAM SEL1 2 2L 2 1 17 15 14 12 16 CCD analog shift register D67 D65 Photocell (B&W_EVEN) S10800 S10800 S4 S2 D17 D63 Tansfer gate . CCD analog shift register D66 D64 S10799 S10799 Photocell (B&W_ODD) S3 . S1 D18 Tansfer gate Tansfer gate CCD analog shift register GND 19 CCD analog shift register D67 S10800 S10800 D65 D66 Photocell (Blue) D64 S4 S2 Photocell (Blue) S10799 S10799 . D63 . S3 D18 VOUT1 (Blue, 20 B&W_EVEN) S1 D17 Tansfer gate Tansfer gate CCD analog shift register VOD2 2 CCD analog shift register D67 S10800 S10800 D65 D66 Photocell (Green) D64 S2 S4 D63 Photocell (Green) S10799 S10799 . S3 D18 V OUT2 (Green, 22 B&W_ODD) S1 D17 Tansfer gate . Tansfer gate 13 CCD analog shift register CCD analog shift register D66 D65 D67 S10800 S10800 D64 S10799 S10799 S4 S2 D63 Photocell (Red) Photocell (Red) S3 . S1 1 D18 V OUT3 (Red, B&W_ODD) D17 Tansfer gate . Tansfer gate CCD analog shift register VOD1 21 4 7 CLB SEL2 2 3 8 5 9 10 11 R 1L 1 1 2 GND Data Sheet S18949EJ1V0DS S18949EJ1V0DS TG PD8875 PD8875 PIN CONFIGURATION (Top View) CCD linear image sensor 22-pin plastic DIP (10.16 mm (400) PD8875CY-A PD8875CY-A VOUT2 Output signal 2 (Green, B&W_ODD) Output drain voltage 2 VOD2 2 21 VOD1 Output drain voltage 1 Reset gate clock R 3 20 VOUT1 Output signal 1 (Blue, B&W_EVEN) Reset feed-through level clamp clock CLB 4 19 GND Ground Shift register clock 1 1 5 18 NC No connection No connection NC 6 17 2 Shift register clock 2 Color/B&W selector SEL2 7 16 2L Last gate shift register clock 2 Last gate shift register clock 1 1L 8 15 2 Shift register clock 2 Shift register clock 1 1 9 14 1 Shift register clock 1 Shift register clock 2 2 10 13 TG Transfer gate clock Ground GND 11 12 SEL1 Mode selector Caution Black & White 10800 Blue 10800 Green 10800 Red 10800 1 22 1 1 1 VOUT3 1 Output signal 3 (Red, B&W_ODD) Connect the No connection pins (NC) to GND. Data Sheet S18949EJ1V0DS S18949EJ1V0DS 3 PD8875 PD8875 PHOTOCELL STRUCTURE DIAGRAM 3.2 m 5.75 m 2.5 m 2.75 m 2.5 m 2.75 m Channel stopper Aluminum shield Aluminum shield Red, Green, Blue Channel stopper Black & White PHOTOCELL ARRAY STRUCTURE DIAGRAM 3.2 m Black & White photocell array 31.5 m 3.2 m Black & White photocell array 63 m 5.75 m 4.75 m 5.75 m Blue photocell array 10.5 m Blue photocell array 52.5 m 5.75 m 4.75 m 5.75 m 63.0 m Green photocell array 10.5 m Green photocell array 52.5 m 63.0 m 5.75 m 4.75 m 5.75 m 4 Red photocell array 10.5 m Red photocell array Data Sheet S18949EJ1V0DS S18949EJ1V0DS PD8875 PD8875 ABSOLUTE MAXIMUM RATINGS (TA = +25°C) Parameter Symbol Ratings Unit Output drain voltage - 0.3 to +15 V V 1, V 2 - 0.3 to +8 V Last gate shift register clock voltage V 1L, V 2L - 0.3 to +8 V Reset gate clock voltage V R - 0.3 to +8 V Reset feed-through level clamp clock voltage V CLB - 0.3 to +8 V Mode select signal voltage V SEL1, V SEL2 - 0.3 to +8 V Transfer gate clock voltage V TG - 0.3 to +8 V Operating ambient temperature Note TA 0 to +55 °C Storage temperature Note VOD1, VOD2 Shift register clock voltage Tstg - 40 to +70 °C Use at the condition without dew condensation. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. RECOMMENDED OPERATING CONDITIONS (TA = +25°C) Parameter Symbol MIN. TYP. MAX. Unit Output drain voltage VOD1, VOD2 11.4 12.0 12.6 V Shift register clock high level V 1H, V 2H, V 1LH, 4.75 5.0 5.5 V 0 0 +0.15 V 4.75 5.0 5.5 V V 2LH Shift register clock low level V 1L, V 2L, V 1LL, V 2LL Reset gate clock high level V RH Reset gate clock low level V RL 0 0 +0.15 V Reset feed-through level clamp clock high level V CLBH 4.75 5.0 5.5 V Reset feed-through level clamp clock low level V CLBL 0 0 +0.15 V Mode select signal high level V SEL1H, V SEL2H 4.75 5.0 5.5 V Mode select signal low level V SEL1L, V SEL2L 0 0 +0.15 V Transfer gate clock high level V TGH 4.75 V 1H Note V 1H Note V Transfer gate clock low level V TGL 0 0 +0.15 V Data rate f R - 2 20 MHz Clock pulse frequency f 1, f 2 - 1 20 MHz Note When Transfer gate clock high level (V TGH) is higher than shift register clock high level (V 1H), image lag increases. Data Sheet S18949EJ1V0DS S18949EJ1V0DS 5 PD8875 PD8875 ELECTRICAL CHARACTERISTICS TA = +25°C, VOD = +12 V, data rate (f R) = 2 MHz, storage time = 5.5 ms, input clock = 5 Vp-p light source: 3200 K halogen lamp + C-500S C-500S (infrared cut filter, t = 1 mm)+ HA-50 HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol Saturation voltage Test Conditions Saturation exposure Red MAX. Unit 3.0 ­ V ­ SE_R TYP. 2.5 Vsat MIN. 0.3 ­ lx·s Green SE_G ­ 0.33 ­ lx·s Blue SE_B ­ 0.6 ­ lx·s B&W SE_B&W ­ 0.24 ­ lx·s Photo response non-uniformity PRNU_RGB VOUT = 1.0 V Average dark signal ­ 6.0 20.0 % ­ PRNU_B&W 10.0 25.0 % 0.2 2.0 mV ADS Light shielding ­ Dark signal non-uniformity DSNU Light shielding ­ 1.5 10.0 mV Power consumption PW Light shielding ­ 360 540 mW Output impedance ZO ­ 0.2 0.4 k Response Red RR 7.0 10.0 13.0 V/lx·s Green RG 6.3 9.0 11.7 V/lx·s Blue RB 3.5 5.0 6.5 V/lx·s B&W RB&W 8.7 12.3 16.1 V/lx·s Image lag IL Offset level VOS Output fall delay time Note Total transfer efficiency VOUT = 1.0 V 7.0 % 7.5 8.5 V ­ 15 ­ ns VOUT = 1.0 V, 92 98 ­ % ­ 1.0 4.0 % ­ TTE 3.0 VOUT = 1.0 V td Note ­ 6.5 610 ­ nm data rate = 20 MHz Register imbalance Response peak RI VOUT = 1.0 V Red Green 535 ­ nm ­ 460 ­ nm B&W Dynamic range ­ Blue ­ 540 ­ nm ­ 2000 ­ times Note 6 Vsat/ CDS ­ 1363 ­ times RFTN Light shielding ­2000 ­100 500 mV PRFTN Random noise (CDS) Vsat/DSNU DR2 Reset feed-through noise DR1 Light shielding ­ 500 800 mV CDS Light shielding ­ 2.2 ­ mV When the fall time of 1L and 2L (t1, t2) is typical value. (Refer to TIMING CHART 2-1 to 2-3) Data Sheet S18949EJ1V0DS S18949EJ1V0DS PD8875 PD8875 INPUT PIN CAPACITANCE (TA = +25°C, VOD = +12 V) Parameter 1 MIN. TYP. MAX. Unit 5 ­ 600 ­ pF ­ 600 ­ pF 14 C 1 Pin name Pin No 9 Shift register clock pin capacitance 1 Symbol ­ 600 ­ pF C 1 total capacitance C 2 2 ­ 1800 ­ pF 10 ­ 600 ­ pF 15 Shift register clock pin capacitance 2 ­ 600 ­ pF pF 17 ­ 600 ­ ­ C 2 total capacitance 1800 ­ pF Last gate shift register clock pin capacitance 1 C 1L 1L 8 ­ 10 ­ pF Last gate shift register clock pin capacitance 2 C 2L 2L 16 ­ 10 ­ pF Reset gate clock pin capacitance C R R 3 ­ 10 ­ pF Reset feed-through level clamp clock pin C CLB CLB 4 ­ 10 ­ pF Select signal pin capacitance C SEL1 SEL1 12 ­ 10 ­ pF C SEL2 7 ­ 10 ­ pF Transfer gate clock pin capacitance C TG TG 13 ­ 300 ­ pF capacitance Remark SEL2 1. Pins 5, 9, 14 ( 1) and pins 10, 15, 17 ( 2) are each connected inside of the device. 2. C 1 and C 2 show the equivalent capacity of the real drive including the capacity of between 1 and 2. Data Sheet S18949EJ1V0DS S18949EJ1V0DS 7 Data Sheet S18949EJ1V0DS S18949EJ1V0DS Note D15 D3 Dummy pixel (16 pixels) D58 D18 Optical black (43 pixels) D59 D17 D16 D2 D1 Note Set the R to low level and the CLB to high level during this period. VOUT1 to VOUT3 CLB (At line clamp) CLB (At bit clamp) R 2, ( 2L) 1, ( 1L) TG D63 D60 Invalid photocell (4 pixels) D61 8 D62 TIMING CHART 1-1 (Color 1200 dpi Mode, ( SEL1 = "H", SEL2 = "H") S10798 S10798 S10797 S10797 S3 Valid photocell (10800 pixels) D67 D66 D65 D64 Invalid photocell (4 pixels) CCD shift register signal Not e PD8875 PD8875 S10800 S10800 S10799 S10799 S2 S1 Data Sheet S18949EJ1V0DS S18949EJ1V0DS Note Note D13 D3 Dummy pixel (8 pixels) Optical black (22 pixels) D19 D17 D15 D1 Set the R to low level and the CLB to high level during this period. VOUT1 to VOUT3 CLB (At line clamp) CLB (At bit clamp) R 2, ( 2L) 1, ( 1L) TG D57 TIMING CHART 1-2 (Color 600 dpi Mode, ( SEL1 = "L", SEL2 = "H") S2 D63 D61 Invalid photocell (2 pixels) S10798 S10798 S4 Valid photocell (5400 pixels) D67 D65 Invalid photocell (2 pixels) CCD shift register signal Note PD8875 PD8875 9 S10800 S10800 D59 Note Data Sheet S18949EJ1V0DS S18949EJ1V0DS Note D1+D3 Dummy pixel (4 pixels) D13+D15 Optical black (11 pixels) Set the R to low level and the CLB to high level during this period. VOUT1 to VOUT3 CLB (At line clamp) CLB (At bit clamp) R 2, ( 2L) 1, ( 1L) TG D17+D19 10 D57+D59 TIMING CHART 1-3 (Color 300 dpi Mode, ( SEL1 = "L", SEL2 = "H") D61+D63 Invalid photocell (1 pixel) S10798 S10798 +S10800 S10800 S2+S4 Valid photocell (2700 pixels) D65+D67 Invalid photocell (1 pixel) CCD shift register signal Note PD8875 PD8875 Note Note Dummy pixel (8 pixels) Dummy pixel (4 pixels) Dummy pixel (5 pixels) D17 D1 Optical black (11 pixels) Optical black (10 pixels) Optical black (22 pixels) Invalid photocell (1 pixel) Invalid photocell (1 pixel) Set the R to low level and the CLB to high level during this period. (B&W_ODD) VOUT3 (B&W_ODD) VOUT2 VOUT1 (B&W_EVEN) CLB (At line clamp) CLB (At bit clamp) R 2, ( 2L) 1, ( 1L) TG D5 D10 D8 D2 D0 D7 D14 D12 D3 D6 D4 D9 D18 D16 D31 D62 D60 D11 D20 D29 D58 D56 D34 D32 D33 S3 S1 D35 Invalid photocell (2 pixels) S7 Valid photocell (2700 pixels) Valid photocell (2700 pixels) S5 S5364 S5364 Valid photocell (5400 pixels) S10791 S10791 S10789 S10789 D61 S59 S57 S5366 S5366 S10795 S10795 S10793 S10793 D63 S63 S61 S5368 S5368 S10799 S10799 S10800 S10800 CCD shift register signal Invalid photocell (1 pixel) D65 CCD shift register signal S5372 S5372 Invalid photocell (1 pixel) CCD shift register signal Invalid photocell (1 pixel) S10797 S10797 S2 S67 S65 S5370 S5370 D66 S4 S71 S69 Data Sheet S18949EJ1V0DS S18949EJ1V0DS D64 TIMING CHART 1-4 (B&W Mode, ( SEL1 = N/A, SEL2 = "L") Note PD8875 PD8875 11 PD8875 PD8875 TIMING CHART 2-1 (Color 1200 dpi Mode, ( SEL1 = "H", SEL2 = "H") t1 1 ( 1L) 90% 10% 2 ( 2L) t2 90% 10% R 90% 10% t4 t3 t5 t11 t8 t6 CLB (At bit clamp) CLB (At line clamp) t4 t3 t5 t7 t9 t6 t10 t11 t8 t7 t9 t10 90% 10% "H" td td VOUT 10% Symbol 10% MIN. TYP. MAX. Unit t1, t2 0 25 ­ ns t3 10 50 ­ ns t4, t5 0 20 ­ ns t6 0 70 ­ ns t7 15 50 ­ ns t8, t9 0 20 ­ ns t10 5 45 ­ ns t11 10 70 ­ ns Note 12 TYP. is the case of R = 2 MHz Data Sheet S18949EJ1V0DS S18949EJ1V0DS PD8875 PD8875 TIMING CHART 2-2 (Color 600 dpi Mode, ( SEL1 = "L", SEL2 = "H") / B&W Mode, ( SEL1 = N/A, SEL2 = "L") t1 t2 1 ( 1L) 90% 10% 2 ( 2L) 90% 10% t4 R t3 t5 90% 10% t11 t8 t7 t9 t6 CLB (At bit clamp) CLB (At line clamp) t10 90% 10% "H" td VOUT 10% Symbol MIN. TYP. MAX. Unit t1, t2 0 25 ­ ns t3 10 50 ­ ns t4, t5 0 20 ­ ns t6 0 70 ­ ns t7 15 50 ­ ns t8, t9 0 20 ­ ns t10 5 45 ­ ns t11 10 70 ­ ns Note TYP. is the case of R = 2 MHz Data Sheet S18949EJ1V0DS S18949EJ1V0DS 13 PD8875 PD8875 TIMING CHART 2-3 (Color 300 dpi Mode, ( SEL1 = "L", SEL2 = "H") t2 t1 1 ( 1L) 90% 10% 2 ( 2L) 90% 10% 10% 90% t4 t3 t5 R 90% 10% t11 t8 t6 CLB (At bit clamp) CLB (At line clamp) t7 t9 10% t10 90% "H" td VOUT 10% Symbol MIN. TYP. MAX. Unit t1, t2 0 25 ­ ns t3 10 50 ­ ns t4, t5 0 20 ­ ns t6 0 70 ­ ns t7 15 50 ­ ns t8, t9 0 20 ­ ns t10 5 45 ­ ns t11 10 70 ­ ns Note 14 TYP. is the case of R = 1 MHz Data Sheet S18949EJ1V0DS S18949EJ1V0DS PD8875 PD8875 TG, 1 ( 1L), 2 ( 2L) TIMING CHART t14 t13 t15 90% 10% TG t16 1 ( 1L) t17 90% 2 ( 2L) Note t18 R t19 t11 10% t6 t6 CLB (At bit clamp) t6 t20 CLB (At line clamp) t7 Symbol MIN. TYP. MAX. Unit t6 0 70 ­ ns t7 15 50 ­ ns t11 10 50 ­ ns t13 5000 10000 50000 ns t14, t15 0 50 ­ ns t16, t17 900 1000 ­ ns t18, t19 200 400 ­ ns t20 10 350 ­ ns Note Set the R to low level and the CLB to high level during this period. Data Sheet S18949EJ1V0DS S18949EJ1V0DS 15 PD8875 PD8875 1, 2 CROSS POINT t25 t27 1 0.25 V 1.5 V to 3.5 V 2 t26 Symbol MIN. TYP. MAX. Unit t25 50 ­ ­ ns t26, t27 20 ­ ­ ns 1, 2L CROSS POINT 1 2.0 V or more 0.5 V or more 2L 2, 1L CROSS POINT 2 2.0 V or more 0.5 V or more 1L 16 Data Sheet S18949EJ1V0DS S18949EJ1V0DS 4.75 V PD8875 PD8875 TG, SEL TIMING CHART 90% t28 10% TG t29 SEL1 (High Low) SEL2 (High Low) 90% SEL1 (Low High) SEL2 (Low High) 10% Symbol MIN. TYP. MAX. Unit t28 0 0 ­ ns t29 4500 9500 ­ ns SELECTION OF RESOLUTION MODE The uPD8875CY-A uPD8875CY-A has function of two readout modes, High Resolution Mode and Low Resolution Mode. These two modes can be selected by SEL1 switch. Mode SEL1 Description High Resolution Mode 1200 dpi (Max.) High level Low Resolution Mode 600 dpi (Max.) (even line readout mode) Low level (1) High Resolution Mode In this mode, both signals in odd lines and even lines can be read out. This mode enables 1200 dpi (max.) resolution with A4 size (210 × 297 mm, shorter side). Please refer to TIMING CHART 1-1 and TIMING CHART 2-1. (2) Low Resolution Mode In this mode, only signal output in even lines can be read out. Signal output in even lines: Can be read out Signal output in odd lines: Can not be read out This mode enables 600 dpi (max) resolution with A4 size. To use intermittent reset drive enable signal charges of adjacent pixels in even line to add at the charge to voltage conversion area. Then it can achieve low resolution with A4 size such as 300, 200, 150 dpi. Please refer to TIMING CHART 1-2, 1-3 and TIMING CHART 2-2, 2-3. Data Sheet S18949EJ1V0DS S18949EJ1V0DS 17 PD8875 PD8875 DEFINITIONS OF CHARACTERISTIC 1. Saturation voltage : Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity : PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = x × 100 x x : maximum of | xj - x | 10800 x= x j=1 j 10800 xj : Output voltage of valid pixel number j VOUT x Register Dark DC level x 4. Average dark signal : ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 10800 d j=1 j ADS (mV) = 10800 dj : Dark signal of valid pixel number j 18 Data Sheet S18949EJ1V0DS S18949EJ1V0DS PD8875 PD8875 5. Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of | dj - ADS | j = 1 to 10800 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU 6. Output impedance : ZO Impedance of the output pins viewed from outside. 7. Response : R Output voltage divided by exposure (lx·s). Note that the response varies with a light source (spectral characteristic). 8. Image lag : IL The rate between the last output voltage and the next one after read out the data of a line. TG ON Light OFF VOUT V1 VOUT IL (%) = V1 VOUT × 100 Data Sheet S18949EJ1V0DS S18949EJ1V0DS 19 PD8875 PD8875 9. Register imbalance : RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. 2 n RI (%) = n 2 (V2j ­ 1 ­ V2j) j=1 1 n × 100 n V j j=1 n : Number of valid pixels Vj : Output voltage of each pixel 10. Offset level : VOS DC level of output signal is defined as follows. 11. Reset feed-through noise : RFTN, PRFTN Reset feed-through noise (RFTN) and peak of RFTN (PRFTN) are defined as follows. + PRFTN VOUT PRFTN ­ RFTN VOS 20 Data Sheet S18949EJ1V0DS S18949EJ1V0DS PD8875 PD8875 12. Random noise (CDS) : CDS Random noise CDS is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding). CDS is calculated by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get "VDi". 3. The output level is measured during the video output time averaged over 100 ns to get "VOi". 4. The correlated double sampling output is defined by the following formula. VCDSi = VDi ­ VOi 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation CDS using the following formula equation. 100 CDS (mV) = (VCDS ­ V) i=1 i 2 100 , V= 1 100 VCDS i 100 i = 1 The following figure shows output waveform (valid photocell under dark condition). Reset feed-through Video output Data Sheet S18949EJ1V0DS S18949EJ1V0DS 21 PD8875 PD8875 STANDARD CHARACTERISTIC CURVES (1) (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25°C) 2 8 1 Relative Output Voltage Relative Output Voltage 4 2 1 0.5 0.2 0.25 0.1 0 10 20 30 40 0.1 50 1 5 10 Storage Time (ms) Operating Ambient Temperature TA (°C) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (Without infrared cut filter and heat absorbing filter) (TA = +25 °C) 100 G Response Ratio(%) Response Ration (%) 80 R B 60 B&W 40 20 0 400 500 600 Wavelength(nm) Wavelength (nm) 22 Data Sheet S18949EJ1V0DS S18949EJ1V0DS 700 800 PD8875 PD8875 APPLICATION CIRCUIT EXAMPLE +12 V A equivalent circuit +12 V + 47 F + +5 V 0.1 F 47 F + VOUT3 VOUT2 22 B2 A 47 F 0.1 F 1 2 VOD2 VOD1 21 A R 3 R 4 CLB 5 1 6 NC 1 1 1 1 B3 VOUT1 20 GND 19 NC 18 2 17 +5 V + B1 CLB 47 1 3 4.7 SEL2 7 150 1L 8 SEL2 Red Green Blue Black & white 47 2L 2 2 1L 2L 16 2 2 15 47 9 1 10 4.7 2 150 1 2 14 TG 13 10800 10800 10800 10800 2 3 4.7 47 1 0.1 F 47 F 4.7 2 1 2 4.7 TG 4.7 11 SEL1 GND SEL1 12 10 Caution Connect the no connection pins (NC) to GND. Remark The inverters are the 74AC04 74AC04, and pins 5, 9, 10, 13, 14 and 17 connect two or three inverters in parallel. B1 to B3 EQUIVALENT CIRCUIT +12 V + 1.5 k 47 F/25 V 110 CCD VOUT 2SA1206 2SA1206 Data Sheet S18949EJ1V0DS S18949EJ1V0DS 23 PD8875 PD8875 PACKAGE DRAWING PD8875CY-A PD8875CY-A CCD LINEAR IMAGE SENSOR 22-PIN 22-PIN PLASTIC DIP (10.16 mm (400) (Unit : mm) 44.0±0.3 9.25±0.3 12 22 1 0.7±0.3 1st valid pixel 11 1 2.0 37.5 4 4 0.46±0.1 (1.72) 3 4.39±0.4 (5.42) 2.54±0.25 10.16±0.2 2 2.62±0.2 1.02 ±0.15 0.25±0.05 0.7 10.16 + 0.2 4.21±0.5 Name Plastic cap Dimensions 42.7×8.35×0.8(0.7 5) Refractive index 1.5 1 Distance between the 1st valid pixel and the center of the pin1 2 Distance between the top of the cap and the surface of the CCD chip 3 Distance between the bottom of the package and the surface of the CCD chip 4 Transparent window 5 Thickness of the transparent window 22C-1CCD-PKG20 22C-1CCD-PKG20 NEC Electronics Corporation 2007 24 Data Sheet S18949EJ1V0DS S18949EJ1V0DS PD8875 PD8875 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. Type of Through-hole Device PD8875CY-A PD8875CY-A: CCD linear image sensor 22-pin plastic DIP (10.16 mm (400) Process Partial heating method Conditions Pin temperature: 380°C or below, Heat time: 3 seconds or less (per pin). Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the glass cap. The optical characteristics could be degraded by such contact. 2. Soldering by the solder flow method may have deleterious effects on prevention of glass cap soiling and heat resistance. So the method cannot be guaranteed. Data Sheet S18949EJ1V0DS S18949EJ1V0DS 25 PD8875 PD8875 NOTES ON HANDLING THE PACKAGES 1 DUST AND DIRT PROTECTING The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don't either touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents. CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Symbol Ethyl Alcohol Methyl Alcohol EtOH MeOH Isopropyl Alcohol N-methyl Pyrrolidone IPA NMP 2 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to use a IC-inserter when you assemble to PCB. Also, be care that the any of the following can cause the package to crack or dust to be generated. 1. Applying heat to the external leads for an extended period of time with soldering iron. 2. Applying repetitive bending stress to the external leads. 3. Rapid cooling or heating 3 OPERATE AND STORAGE ENVIRONMENTS Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid storage or usage in such conditions. Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the devices are transported from a low-temperature environment to a high-temperature environment. Avoid such rapid temperature changes. For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E C12769E) 4 ELECTROSTATIC BREAKDOWN CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes detected. Before handling be sure to take the following protective measures. 1. 2. 3. 4. 5. 6. 26 Ground the tools such as soldering iron, radio cutting pliers of or pincer. Install a conductive mat or on the floor or working table to prevent the generation of static electricity. Either handle bare handed or use non-chargeable gloves, clothes or material. Ionized air is recommended for discharge when handling CCD image sensor. For the shipment of mounted substrates, use box treated for prevention of static charges. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 M. Data Sheet S18949EJ1V0DS S18949EJ1V0DS PD8875 PD8875 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Data Sheet S18949EJ1V0DS S18949EJ1V0DS 27 PD8875 PD8875 · The information in this document is current as of September, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. · No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. · NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. · Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. · While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. · NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1