PD78P054 78P058 PD78054 78K/0 PD78P054KK-T 78P058KK-T 78054Y U11747E U12326E - Datasheet Archive

 

MOS INTEGRATED CIRCUIT µPD78P054, 78P058 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD78P054 and 78P058 are

 

DATA SHEET MOS INTEGRATED CIRCUIT µPD78P054 PD78P054, 78P058 78P058 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD78P054 PD78P054 and 78P058 78P058 are the members of the µPD78054 PD78054 Subseries of 78K/0 78K/0 Series products, in which the on-chip mask ROM of the µPD78054 PD78054 and 78058 is replaced with one-time PROM or EPROM. Because these devices can be programmed by users, they are ideally suited to applications involving the evaluation of systems in development stages, small-scale production of many different products, and rapid development and time-to-market of a new product. The reliability of the µPD78P054KK-T PD78P054KK-T and 78P058KK-T 78P058KK-T is not guaranteed when used in mass- Caution production applications. Please use these devices only experimentally or for evaluation during trial manufacture. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. µPD78054 PD78054, 78054Y 78054Y Subseries User's Manual: U11747E U11747E 78K/0 78K/0 Series User's Manual Instructions: U12326E U12326E FEATURES · Pin compatible with mask ROM versions (except the VPP pin) · Internal high-capacity PROM and RAM Parameter Internal Data Memory Program Memory (PROM) Part Number µPD78P054 PD78P054 32 µPD78P058 PD78P058 High-Speed RAM Buffer RAM 60 KbytesNote 1 KbytesNote 1 · µPD78P05xKK-T: 1024 bytesNote 1 32 bytes Expansion RAM None 1024 bytesNote 2 Reprogrammable (ideal for system evaluation) · µPD78P05xGC, 78P05xGK: Programmable once only (ideal for small-scale production) · Operable in the same supply voltage range as mask ROM versions (VDD = 2.0 to 6.0 V) · Corresponding to QTOPTM microcontrollers Notes 1. The internal PROM and internal high-speed RAM capacity can be changed using the internal memory size switching register (IMS). 2. The internal expansion RAM capacity can be changed using the internal expansion RAM size switching register (IXS). Remarks 1. QTOP microcontroller is the general name of the microcontrollers with one-time PROM that are totally supported by the NEC writing service (from writing to marking, screening, and testing). 2. For the differences between PROM versions and mask ROM versions, refer to 1. DIFFERENCES BETWEEN µPD78P054 PD78P054, 78P058 78P058 AND MASK ROM VERSIONS. In this document, "PROM" is used in sections common to the one-time PROM and EPROM versions. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U10417EJ3V0DS00 U10417EJ3V0DS00 (3rd edition) Date Published August 1999 N CP(K) Printed in Japan The mark shows major revised points. © 1994, 1999 µPD78P054 PD78P054, 78P058 78P058 ORDERING INFORMATION Part Number Package Internal ROM Quality Grade µPD78P054GC-8BT PD78P054GC-8BT 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm) One-time PROM Standard µPD78P054GK-BE9 PD78P054GK-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm) One-time PROM Standard µPD78P054KK-T PD78P054KK-T 80-pin ceramic WQFN (14 × 14 mm) EPROM Not applicable µPD78P058GC-8BT PD78P058GC-8BT 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm) One-time PROM Standard µPD78P058KK-T PD78P058KK-T 80-pin ceramic WQFN (14 × 14 mm) EPROM Not applicable Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 2 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 78K/0 78K/0 SERIES LINEUP The products in the 78K/0 78K/0 Series are listed below. The names enclosed in boxes are subseries names. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control EMI-noise reduced version of the µ PD78078 PD78078 µ PD78075B PD78075B µ PD78078 PD78078 µ PD78070A PD78070A µPD78078Y PD78078Y µPD78054 PD78054 with timer added and enhanced external interface µ PD78070AY PD78070AY 80-pin µ PD780058 PD780058 µ PD780018AY PD780018AY µ PD780058Y PD780058Y ROM-less version of the µPD78078 PD78078 µPD78078Y PD78078Y with enhanced serial I/O and limited functions 80-pin µ PD78058F PD78058F µPD78054 PD78054 µPD780065 PD780065 µ PD78058FY PD78058FY µ PD780078 PD780078 µ PD780034A PD780034A µ PD780024A PD780024A µPD78014H PD78014H µ PD780078Y PD780078Y µ PD780034AY PD780034AY µPD78018F PD78018F µ PD78083 PD78083 µ PD78018FY PD78018FY 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin µ PD78054Y PD78054Y µ PD78054 PD78054 with enhanced serial I/O EMI-noise reduced version of the µ PD78054 PD78054 µPD78018F PD78018F with added UART and D/A converter and enhanced I/O µPD780024 PD780024 with increased RAM capacity µ PD780024AY PD780024AY A timer added to the µPD780034A PD780034A and serial I/O enhanced µ PD780024 PD780024 with enhanced A/D converter µPD78018F PD78018F with enhanced serial I/O EMI-noise reduced version of the µPD78018F PD78018F Basic subseries for control On-chip UART, capable of operating at low voltage (1.8 V) Inverter control 64-pin µPD780988 PD780988 On-chip inverter control circuit and UART. EMI-noise reduced. FIPTM drive µ PD780208 PD780208 µ PD780228 PD780228 µPD78044F PD78044F with enhanced I/O and FIP C/D. Display output total: 53 µPD78044H PD78044H with enhanced I/O and FIP C/D. Display output total: 48 µ PD780232 PD780232 µPD78044H PD78044H For panel control. On-chip FIP C/D. Display output total: 53 80-pin 80-pin µPD78044F PD78044F Basic subseries for driving FIP. Display output total: 34 100-pin 78K/0 78K/0 Series 100-pin 80-pin µPD78044F PD78044F with added N-ch open drain I/O. Display output total: 34 LCD drive 100-pin µ PD780308 PD780308 100-pin µPD78064B PD78064B µPD78064 PD78064 100-pin µ PD780308Y PD780308Y µPD78064 PD78064 with enhanced SIO, and increased ROM, RAM capacity. EMI-noise reduced version of the µ PD78064 PD78064 µ PD78064Y PD78064Y Basic subseries for driving LCDs, on-chip UART Call ID supported 80-pin µ PD780841 PD780841 On-chip Call ID function, simple DTMF. EMI-noise reduced. Bus interface supported 100-pin µ PD780948 PD780948 80-pin µ PD78098B PD78098B On-chip D-CAN controller µ PD78054 PD78054 with IEBusTM controller added. EMI-noise reduced. 80-pin µ PD780701Y PD780701Y On-chip D-CAN/IEBus controller 80-pin µ PD780833Y PD780833Y On-chip controller compliant with J1850 J1850 (Class 2) Meter control µPD780958 PD780958 µPD780955 PD780955 For industrial meter control 80-pin 80-pin µPD780973 PD780973 On-chip automobile meter controller/driver 100-pin Ultra low-power consumption. On-chip UART. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 3 µPD78P054 PD78P054, 78P058 78P058 The major functional differences among the subseries are listed below. Function Subseries Name ROM Capacity Timer 8-Bit 10-Bit 8-Bit 8-bit 16-bit Watch WDT A/D A/D D/A µPD78075B PD78075B 32K to 40K 4c h 1 ch 1 ch 1 ch 8 ch µPD78078 PD78078 Control Serial Interface I/O VDD MIN. External Value Expansion 48K to 60K µPD78070A PD78070A ­ 2 ch 3 ch (UART: 1 ch) ­ 88 1.8 V 61 2.7 V µPD780058 PD780058 24K to 60K 2 ch 3 ch (time division UART: 1 ch) 68 1.8 V µPD78058F PD78058F 48K to 60K 3 ch (UART: 1 ch) 69 2.7 V µPD78054 PD78054 16K to 60K µPD780065 PD780065 40K to 48K 4 ch (UART: 1 ch) 60 2.7 V µPD780078 PD780078 48K to 60K 3 ch (UART: 2 ch) 52 1.8 V 3 ch (UART: 1 ch) 51 2 ch 53 2.0 V - 2 ch µPD780034A PD780034A 8K to 32K - 8 ch 1 ch µPD780024A PD780024A 8 ch - µPD78014H PD78014H µPD78018F PD78018F 8K to 60K µPD78083 PD78083 8K to 16K µPD780988 PD780988 16K to 60K 3 ch Note µPD780208 PD780208 32K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch µPD780228 PD780228 48K to 60K 3 ch µPD780232 PD780232 16K to 24K µPD78044H PD78044H 32K to 48K 2 ch 1 ch 1 ch µPD78044F PD78044F 16K to 40K µPD780308 PD780308 48K to 60K 2 ch 1 ch 1 ch 1 ch 8 ch µPD78064B PD78064B 32K µPD78064 PD78064 Inverter 16K to 32K - - 1 ch (UART: 1 ch) 33 - 3 ch (UART: 2 ch) 47 4.0 V - - 2 ch 74 2.7 V - 1 ch 72 4.5 V 2 ch 40 8 ch 1 ch 8 ch 4 ch - 1 ch 68 2.7 V 3 ch (time division UART: 1 ch) 57 2.0 V - - - - control FIP drive LCD drive Call ID µPD780841 PD780841 supported Bus µPD780948 PD780948 interface supported µPD78098B PD78098B - - 2 ch (UART: 1 ch) 1 ch 1 ch 2 ch - 2 ch 2 ch 1 ch 1 ch 8 ch - 40K to 60K - 1 ch µPD780958 PD780958 48K to 60K 4 ch 2 ch µPD780955 PD780955 40K µPD780973 PD780973 Meter control - 2 ch 24K to 32K 2 ch 60K - 24K to 32K 3 ch - 2 ch (UART: 1 ch) 61 2.7 V - 3 ch (UART: 1 ch) 79 4.0 V 69 2.7 V - 69 2.2 V - 2 ch - 6 ch 1 ch 1 ch - - - 1 ch 1 ch 2 ch (UART: 2 ch) 50 2.2 V 5 ch 2 ch (UART: 1 ch) 56 4.5 V Note 16-bit timer: 2 channels 10-bit timer: 1 channel 4 2 ch (UART: 1 ch) Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 OVERVIEW OF FUNCTIONS µPD78P054 PD78P054 Part Number µPD78P058 PD78P058 Item PROM 32 KbytesNote 1 High-speed RAM 1024 bytesNote 1 Buffer RAM 32 bytes Expansion RAM Internal memory 60 KbytesNote 1 None 1024 bytesNote 2 Memory space 64 Kbytes General registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time Minimum instruction execution time is variable. When main system clock is selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0-MHz operation) When subsystem clock is selected 122 µs (@ 32.768-kHz operation) Instruction set · · · · 16-bit operation Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjust, etc. I/O ports Total: 69 · CMOS input: 2 · CMOS input/output: 63 · N-ch open-drain input/output: 4 A/D converter 8-bit resolution × 8 ch D/A converter 8-bit resolution × 2 ch Serial interface · 3-wire serial I/O, SBI, or 2-wire serial I/O mode selectable: 1 ch · 3-wire serial I/O mode (with on-chip max. 32-byte automatic transmit/receive function): 1 ch · 3-wire serial I/O or UART mode selectable: 1 ch Timer · 16-bit timer/event counter: 1 ch · 8-bit timer/event counter: 2 ch · Watch timer: 1 ch · Watchdog timer: 1 ch Timer outputs 3 (14-bit PWM output capable: 1) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, and 5.0 MHz (@ 5.0-MHz operation with main system clock) 32.768 kHz (@ 32.768-kHz operation with subsystem clock) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz and 9.8 kHz (@ 5.0-MHz operation with main system clock) Vectored interrupt Maskable Non-maskable Internal: 1 Software sources Internal: 13, external: 7 1 Test inputs Internal: 1, external: 1 Supply voltage VDD = 2.0 to 6.0 V Operating ambient temperature TA = ­40 to +85°C Package · 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm) · 80-pin plastic TQFP (fine pitch) (12 × 12 mm) : µPD78P054 PD78P054 only · 80-pin ceramic WQFN (14 × 14 mm) Notes 1. The internal PROM/internal high-speed RAM capacity can be changed using the internal memory size switching register (IMS). 2. The internal expansion RAM capacity can be changed using the internal expansion RAM size switching register (IXS). Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 5 µPD78P054 PD78P054, 78P058 78P058 PIN CONFIGURATIONS (Top View) (1) Normal operating mode · 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm) µPD78P054GC-8BT PD78P054GC-8BT, 78P058GC-8BT 78P058GC-8BT · 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µPD78P054GK-BE9 PD78P054GK-BE9 · 80-pin ceramic WQFN (14 × 14 mm) P00/INTP0/TI00 P00/INTP0/TI00 P01/INTP1/TI01 P01/INTP1/TI01 P02/INTP2 P02/INTP2 P03/INTP3 P03/INTP3 P04/INTP4 P04/INTP4 P05/INTP5 P05/INTP5 P06/INTP6 P06/INTP6 VDD X2 X1 VPP XT2 XT1/P07 XT1/P07 AVDD AVREF0 P10/ANI0 P10/ANI0 P11/ANI1 P11/ANI1 P12/ANI2 P12/ANI2 P13/ANI3 P13/ANI3 P14/ANI4 P14/ANI4 µPD78P054KK-T PD78P054KK-T, 78P058KK-T 78P058KK-T 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P15/ANI5 P15/ANI5 1 60 RESET P16/ANI6 P16/ANI6 2 59 P127/RTP7 P127/RTP7 P17/ANI7 P17/ANI7 3 58 P126/RTP6 P126/RTP6 AVSS 4 57 P125/RTP5 P125/RTP5 P130/ANO0 P130/ANO0 5 56 P124/RTP4 P124/RTP4 P131/ANO1 P131/ANO1 6 55 P123/RTP3 P123/RTP3 AVREF1 7 54 P122/RTP2 P122/RTP2 P70/SI2/RXD P70/SI2/RXD 8 53 P121/RTP1 P121/RTP1 P71/SO2/TXD P71/SO2/TXD 9 52 P120/RTP0 P120/RTP0 P72/SCK2/ASCK P72/SCK2/ASCK 10 51 P37 P20/SI1 P20/SI1 11 50 P36/BUZ P36/BUZ P21/SO1 P21/SO1 12 49 P35/PCL P35/PCL P22/SCK1 P22/SCK1 13 48 P34/TI2 P34/TI2 P23/STB P23/STB 14 47 P33/TI1 P33/TI1 P24/BUSY P24/BUSY 15 46 P32/TO2 P32/TO2 P25/SI0/SB0 P25/SI0/SB0 16 45 P31/TO1 P31/TO1 P26/SO0/SB1 P26/SO0/SB1 17 44 P30/TO0 P30/TO0 P67/ASTB P67/ASTB P27/SCK0 P27/SCK0 Cautions 1. Connect the VPP pin directly to VSS. 2. Connect the AVDD pin to VDD. 3. Connect the AVSS pin to VSS. 6 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 P64/RD P64/RD P63 P62 P61 P60 P57/A15 P57/A15 P56/A14 P56/A14 VSS P55/A13 P55/A13 P54/A12 P54/A12 P53/A11 P53/A11 P51/A9 P51/A9 P52/A10 P52/A10 P50/A8 P50/A8 P47/AD7 P47/AD7 P46/AD6 P46/AD6 P45/AD5 P45/AD5 42 20 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P44/AD4 P44/AD4 19 P41/AD1 P41/AD1 P43/AD3 P43/AD3 P40/AD0 P40/AD0 P42/AD2 P42/AD2 18 43 P66/WAIT P66/WAIT P65/WR P65/WR µPD78P054 PD78P054, 78P058 78P058 A8 to A15: Address Bus RD: Read Strobe AD0 to AD7: Address/Data Bus RESET: Reset ANI0 to ANI7: Analog Input RTP0 to RTP7: Real-Time Output Port ANO0, ANO1: Analog Output RxD: Receive Data ASCK: Asynchronous Serial Clock SB0, SB1: Serial Bus ASTB: Address Strobe SCK0 to SCK2: Serial Clock AVDD: Analog Power Supply SI0 to SI2: Serial Input AVREF0, AVREF1: Analog Reference Voltage SO0 to SO2: Serial Output AVSS: Analog Ground STB: Strobe BUSY: Busy TI00, TI01: Timer Input BUZ: Buzzer Clock TI1, TI2: Timer Input INTP0 to INTP6: External Interrupt Input TO0 to TO2: Timer Output P00 to P07: Port 0 TxD: Transmit Data P10 to P17: Port 1 VDD: Power Supply P20 to P27: Port 2 VPP: Programming Power Supply P30 to P37: Port 3 VSS: Ground P40 to P47 : Port 4 WAIT: Wait P50 to P57 : Port 5 WR: Write Strobe P60 to P67: Port 6 X1, X2: Crystal (Main System Clock) P70 to P72: Port 7 XT1, XT2: Crystal (Subsystem Clock) P120 to P127: Port 12 P130, P131: Port 13 PCL: Programmable Clock Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 7 µPD78P054 PD78P054, 78P058 78P058 (2) PROM programming mode · 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm) µPD78P054GC-8BT PD78P054GC-8BT, 78P058GC-8BT 78P058GC-8BT · 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µPD78P054GK-BE9 PD78P054GK-BE9 · 80-pin ceramic WQFN (14 × 14 mm) 1 (L) A9 (L) PGM (L) VDD Open (L) VPP Open (L) VDD VSS (L) µPD78P054KK-T PD78P054KK-T, 78P058KK-T 78P058KK-T 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 RESET 2 3 58 4 57 5 56 6 55 7 54 8 53 9 52 10 51 D7 11 50 D6 12 49 D5 13 48 D4 14 47 D3 15 46 D2 16 45 D1 17 VSS 59 44 D0 (L) VDD (L) (L) CE OE (L) A15 VSS A14 A13 A12 A11 A10 A16 A8 A7 A6 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 A5 A1 A4 42 A2 43 19 A3 18 A0 (L) Individually connect to VSS via a pull-down resistor. Cautions 1. (L): 2. VSS: Connect to GND. 3. RESET: Set to low level. 4. Open: No connection A0 to A16: RESET: Reset CE: Chip Enable VDD: Power Supply D0 to D7: Data Bus VPP: Programming Power Supply OE : Output Enable VSS: Ground PGM: 8 Address Bus Program Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 BLOCK DIAGRAM TO1/P31 TI1/P33 TI1/P33 TO2/P32 TI2/P34 TI2/P34 16-Bit TIMER/ EVENT COUNTER PORT 0 P00 P01 to P06 P07 8-Bit TIMER/ EVENT COUNTER 1 PORT 1 P10 to P17 8-Bit TIMER/ EVENT COUNTER 2 PORT 2 P20 to P27 PORT 3 P30 to P37 PORT 4 P40 to P47 PORT 5 P50 to P57 PORT 6 P60 to P67 PORT 7 P70 to P72 PORT 12 P120 to P127 PORT 13 TO0/P30 TI00/INTP0/P00 TI00/INTP0/P00 TI01/INTP1/P01 TI01/INTP1/P01 P130, P131 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SI0/SB0/P25 SO0/SB1/P26 SO0/SB1/P26 SERIAL INTERFACE 0 78K/0 78K/0 CPU CORE PROM SCK0/P27 SCK0/P27 SI1/P20 SI1/P20 SO1/P21 SO1/P21 SCK1/P22 SCK1/P22 STB/P23 STB/P23 SERIAL INTERFACE 1 BUSY/P24 BUSY/P24 RAM SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 SCK2/ASCK/P72 SERIAL INTERFACE 2 ANI0/P10 ANI0/P10 to ANI7/P17 ANI7/P17 AVDD AVSS AVREF0 ANO0/P130 ANO0/P130 to ANO1/P131 ANO1/P131 AVSS AVREF1 INTP0/P00 INTP0/P00 to INTP6/P06 INTP6/P06 BUZ/P36 BUZ/P36 A/D CONVERTER REAL-TIME OUTPUT PORT AD0/P40 AD0/P40 to AD7/P47 AD7/P47 A8/P50 A8/P50 to A15/P57 A15/P57 D/A CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL BUZZER OUTPUT CLOCK OUTPUT CONTROL RD/P64 RD/P64 WR/P65 WR/P65 WAIT/P66 WAIT/P66 ASTB/P67 ASTB/P67 SYSTEM CONTROL PCL/P35 PCL/P35 RTP0/P120 RTP0/P120 to RTP7/P127 RTP7/P127 VDD VSS VPP RESET X1 X2 XT1/P07 XT1/P07 XT2 Remark The internal PROM and internal RAM capacities differ depending on the product. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 9 µPD78P054 PD78P054, 78P058 78P058 CONTENTS 1. DIFFERENCES BETWEEN µPD78P054 PD78P054, 78P058 78P058 AND MASK ROM VERSIONS . 11 2. PIN FUNCTIONS .12 2.1 Pins in Normal Operating Mode . 12 2.2 Pins in PROM Programming Mode . 15 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins . 16 3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) .20 4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) (µPD78P058 PD78P058 ONLY) . 22 5. PROM PROGRAMMING .23 5.1 Operating Modes . 23 5.2 PROM Write Procedure . 25 5.3 PROM Read Procedure . 29 6. ERASURE METHOD (µPD78P054KK-T PD78P054KK-T, 78P058KK-T 78P058KK-T ONLY) .30 7. ERASURE WINDOW OPAQUE FILM (µPD78P054KK-T PD78P054KK-T, 78P058KK-T 78P058KK-T ONLY) .30 8. SCREENING OF ONE-TIME PROM VERSIONS.30 9. ELECTRICAL SPECIFICATIONS .31 10. CHARACTERISTICS CURVES (FOR REFERENCE ONLY) .66 11. PACKAGE DRAWINGS .70 12. RECOMMENDED SOLDERING CONDITIONS .73 APPENDIX A. DEVELOPMENT TOOLS .75 APPENDIX B. RELATED DOCUMENTS .81 10 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 1. DIFFERENCES BETWEEN µPD78P054 PD78P054, 78P058 78P058 AND MASK ROM VERSIONS The µPD78P054 PD78P054 and 78P058 78P058 are single-chip microcontrollers with on-chip one-time writable PROM or with onchip EPROM which has program write, erasure, and rewrite capability. It is possible to make all the functions, except for the PROM specification and mask option of P60 to P63 pins, the same as those of mask ROM versions by setting the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS). Differences between the PROM versions (µPD78P054 PD78P054 and 78P058 78P058) and mask ROM versions (µPD78052 PD78052, 78053, 78054, 78055, 78056, and 78058) are shown in Table 1-1. Table 1-1. Differences between µPD78P054 PD78P054, 78P058 78P058 and Mask ROM Versions Item Internal ROM structure µPD78P054 PD78P054, 78P058 78P058 One-time PROM/EPROM Mask ROM Versions Mask ROM Internal ROM capacity µPD78P054 PD78P054: 32 Kbytes µPD78P058 PD78P058: 60 Kbytes µPD78052 PD78052: µPD78053 PD78053: µPD78054 PD78054: µPD78055 PD78055: µPD78056 PD78056: µPD78058 PD78058: 16 Kbytes 24 Kbytes 32 40 48 60 Kbytes Kbytes Kbytes Kbytes Internal high-speed RAM capacity 1024 bytes µPD78052 PD78052: 512 bytes Other than µPD78052 PD78052: 1024 bytes Internal expansion RAM capacity µPD78P054 PD78P054: None µPD78P058 PD78P058: 1024 bytes µPD78058 PD78058: 1024 bytes Other than µPD78058 PD78058: None Change of internal ROM and internal high-speed RAM capacity by internal memory size switching register (IMS) Can be changedNote 1 Cannot be changed Change of internal expansion RAM capacity by internal expansion RAM size switching register (IXS) Can be changedNote 2 Cannot be changed IC pin None Provided VPP pin Provided None Pull-up resistor on-chip mask option of P60 to P63 pins None Provided Electrical specifications, recommended soldering conditions Refer to the data sheet for each product. Notes 1. The internal PROM capacity and internal high-speed RAM capacity become as follows by RESET input. Internal PROM capacity: 32 Kbytes (µPD78P054 PD78P054), 60 Kbytes (µPD78P058 PD78P058) Internal high-speed RAM capacity: 1024 bytes 2. The internal expansion RAM capacity becomes 1024 bytes by RESET input (µPD78P058 PD78P058 only). Caution The PROM version and mask ROM version differ in noise tolerance and noise emission. When replacing a PROM version with a mask ROM version when switching from experimental production to mass production, make a thorough evaluation with a CS (commercial sample) version (not ES (engineering sample) version) of the mask ROM version. Remarks 1. The µPD78P054 PD78P054 is a PROM version of the µPD78052 PD78052, 78053, and 78054. The µPD78P058 PD78P058 is a PROM version of the µPD78055 PD78055, 78056, and 78058. 2. The internal expansion RAM size switching register (IXS) is included only in the µPD78058 PD78058 and 78P058 78P058. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 11 µPD78P054 PD78P054, 78P058 78P058 2. PIN FUNCTIONS 2.1 Pins in Normal Operating Mode (1) Port pins (1/2) Pin Name Input/Output P00 Input P01 Input/output Function Port 0 8-bit input/output port After Reset Alternate Function Input only Input INTP0/TI00 INTP0/TI00 Input/output can be specified Input INTP1/TI01 INTP1/TI01 INTP2 P04 in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of P05 software. INTP5 P02 P03 INTP3 INTP4 P06 INTP6 P07Note 1 Input P10 to P17 Input/output P20 Input/output P21 P22 Input only Input XT1 Port 1 8-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software.Note 2 Input ANI0 to ANI7 Port 2 8-bit input/output port Input/output can be specified in 1-bit units. Input SCK1 When used as an input port, an on-chip pull-up resistor can be specified by means of software. P23 SI1 SO1 STB P24 BUSY P25 SI0/SB0 P26 SO0/SB1 P27 SCK0 P30 P31 P32 P33 Input/output Port 3 8-bit input/output port Input/output can be specified in 1-bit units. Input When used as an input port, an on-chip pull-up resistor can be specified by means of software. TO0 TO1 TO2 TI1 P34 TI2 P35 PCL P36 BUZ P37 - Notes 1. When using the P07/XT1 P07/XT1 pin as an input port, set bit 6 (FRC) of the processor clock control register (PCC) to 1 (be sure not to use the feedback resistor of the subsystem clock oscillation circuit). 2. When using the P10/ANI0 P10/ANI0 to P17/ANI7 P17/ANI7 pins as the A/D converter analog input pins, set port 1 to the input mode. At this time, the pull-up resistors are automatically disconnected. 12 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 (1) Port pins (2/2) After Reset Alternate Function Port 4 8-bit input/output port Input/output can be specified in 8-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. Set the test input flag (KRIF) to 1 by falling edge detection. Input AD0 to AD7 Input/output Port 5 8-bit input/output port LEDs can be driven directly. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. Input A8 to A15 Input/output Port 6 8-bit input/output port Input/output can be specified in 1-bit units. N-ch open-drain input/output port. LEDs can be driven directly. Input - When used as an input port, an on-chip pull-up resistor can Input Pin Name Input/Output P40 to P47 Input/output P50 to P57 P60 P61 P62 Function P63 P64 P65 be specified by means of software. P66 WAIT P67 P70 RD WR ASTB Input/output Port 7 Input 3-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can P71 P72 SI2/RXD SO2/TXD SCK2/ASCK be specified by means of software. P120 to P127 Input/output Port 12 8-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. Input RTP0 to RTP7 P130, P131 Input/output Port 13 2-bit input/output port Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by means of software. Input ANO0, ANO1 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 13 µPD78P054 PD78P054, 78P058 78P058 (2) Non-port pins (1/2) Pin Name Input/Output Function After Reset Alternate Function INTP0 Input External interrupt request input for which the valid edge (rising edge, falling edge, and both rising and falling edges) can be Input P00/TI00 P00/TI00 INTP1 P01/TI01 P01/TI01 specified. INTP2 P02 INTP3 P03 INTP4 P04 INTP5 P05 INTP6 SI0 P06 Input Serial interface serial data input Input P25/SB0 P25/SB0 SI1 P20 SI2 P70/RXD P70/RXD SO0 Output Serial interface serial data output Input P26/SB1 P26/SB1 SO1 P21 SO2 P71/TXD P71/TXD SB0 Input/output Serial interface serial data input/output Input SB1 SCK0 P25/SI0 P25/SI0 P26/SO0 P26/SO0 Input/output Serial interface serial clock input/output Input P27 SCK1 P22 SCK2 P72/ASCK P72/ASCK STB Output Serial interface automatic transmit/receive strobe output Input P23 BUSY Input Serial interface automatic transmit/receive busy input Input P24 RX D Input Serial data input for asynchronous serial interface Input P70/SI2 P70/SI2 T XD Output Serial data output for asynchronous serial interface Input P71/SO2 P71/SO2 ASCK Input Serial clock input for asynchronous serial interface Input P72/SCK2 P72/SCK2 TI00 Input External count clock input to 16-bit timer (TM0) Input P00/INTP0 P00/INTP0 TI01 Capture trigger signal input to capture register (CR00) TI1 External count clock input to 8-bit timer (TM1) P33 TI2 External count clock input to 8-bit timer (TM2) P34 TO0 Output 16-bit timer (TM0) output (also used for 14-bit PWM output) P01/INTP1 P01/INTP1 Input P30 TO1 8-bit timer (TM1) output P31 TO2 8-bit timer (TM2) output P32 PCL Output Clock output (for trimming of main system clock and subsystem clock) Input P35 BUZ Output Buzzer output Input P36 RTP0 to RTP7 Output Real-time output port which outputs data in synchronization with a trigger Input P120 to P127 AD0 to AD7 Input/output Lower address/data bus for expanding memory externally Input P40 to P47 A8 to A15 Output Higher address bus for expanding memory externally Input P50 to P57 RD Output Strobe signal output for reading from external memory Input P64 Strobe signal output for writing to external memory Input P65 WR 14 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 (2) Non-port pins (2/2) After Reset Alternate Function Wait insertion when accessing external memory Input P66 Strobe output that externally latches address information output to ports 4 and 5 to access external memory Input P67 Analog input of A/D converter Input P10 to P17 Analog output of D/A converter Input P130, P131 - - Reference voltage input of D/A converter - - - Analog power supply of A/D converter. Connect to VDD. - - - Ground potential of A/D converter and D/A converter. Connect to VSS. - - Input System reset input - - Input Connecting crystal resonator for main system clock oscillation - - Pin Name Input/Output WAIT Input ASTB Output ANI0 to ANI7 Input ANO0, ANO1 Output AVREF0 Input Reference voltage input of A/D converter AVREF1 Input AVDD AVSS RESET X1 X2 - XT1 Input XT2 - VDD - VPP - VSS - Function - - Input P07 - - Positive power supply - - High-voltage applied during program write/verify. - - - - Connecting crystal resonator for subsystem clock oscillation Connect directly to VSS in normal operating mode. 2.2 Ground potential Pins in PROM Programming Mode Pin Name Input/Output Function RESET Input PROM programming mode setting When +5 V or +12.5 V is applied to the VPP pin and a low-level signal is applied to the RESET pin, this chip is set in the PROM programming mode. VPP Input PROM programming mode setting and high-voltage applied during program write/verification A0 to A16 Input Address bus D0 to D7 Input/output Data bus CE Input PROM enable input/program pulse input OE Input Read strobe input to PROM PGM Input Program/program inhibit input in PROM programming mode VDD - Positive power supply VSS - Ground potential Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 15 µPD78P054 PD78P054, 78P058 78P058 2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1. For the input/output circuit configuration of each type, see Figure 2-1. Table 2-1. Pin Input/Output Circuits (1/2) Input/Output Circuit Type I/O P00/INTP0/TI00 P00/INTP0/TI00 2 Input P01/INTP1/TI01 P01/INTP1/TI01 8-A I/O 16 Input P10/ANI0 P10/ANI0 to P17/ANI7 P17/ANI7 11 I/O P20/SI1 P20/SI1 8-A P21/SO1 P21/SO1 5-A P22/SCK1 P22/SCK1 8-A P23/STB P23/STB 5-A P24/BUSY P24/BUSY 8-A P25/SI0/SB0 P25/SI0/SB0 10-A Pin Name Recommended Connection of Unused Pins Connect to VSS. Independently connect to VSS via a resistor. P02/INTP2 P02/INTP2 P03/INTP3 P03/INTP3 P04/INTP4 P04/INTP4 P05/INTP5 P05/INTP5 P06/INTP6 P06/INTP6 P07/XT1 P07/XT1 Connect to VDD or VSS. Independently connect to VDD or VSS via a resistor. P26/SO0/SB1 P26/SO0/SB1 P27/SCK0 P27/SCK0 P30/TO0 P30/TO0 5-A P31/TO1 P31/TO1 P32/TO2 P32/TO2 P33/TI1 P33/TI1 8-A P34/TI2 P34/TI2 P35/PCL P35/PCL 5-A P36/BUZ P36/BUZ P37 P40/AD0 P40/AD0 to P47/AD7 P47/AD7 P50/A8 P50/A8 to P57/A15 P57/A15 P60 to P63 P64/RD P64/RD 5-E 5-A 13-D 5-A Independently connect to VDD via a resistor. Independently connect to VDD or VSS via a resistor. Independently connect to VDD via a resistor. Independently connect to VDD or VSS via a resistor. P65/WR P65/WR P66/WAIT P66/WAIT P67/ASTB P67/ASTB P70/SI2/RxD 8-A P71/SO2/TxD 5-A P72/SCK2/ASCK P72/SCK2/ASCK 8-A P120/RTP0 P120/RTP0 to P127/RTP7 P127/RTP7 5-A P130/ANO0 P130/ANO0, P131/ANO1 P131/ANO1 12-A 16 Independently connect to VSS via a resistor. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 Table 2-1. Pin Input/Output Circuit Type (2/2) Input/Output Circuit Type I/O Recommended Connection of Unused Pins RESET 2 Input - XT2 16 - AVREF0 - Pin Name AVREF1 Leave open. Connect to VSS. Connect to VDD. AVDD AVSS Connect to VSS. VPP Connect directly to VSS. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 17 µPD78P054 PD78P054, 78P058 78P058 Figure 2-1. Pin Input/Output Circuits (1/2) Type 2 Type 8-A VDD Pullup enable P-ch VDD IN Data P-ch IN/OUT Output disable N-ch Schmitt-triggered input with hysteresis characteristic Type 5-A Type 10-A VDD VDD Pullup enable Pullup enable P-ch P-ch VDD VDD Data Data IN/OUT Output disable P-ch P-ch N-ch IN/OUT Open drain Output disable N-ch Input enable Type 11 Type 5-E VDD VDD Pullup enable Pullup enable P-ch VDD P-ch Data P-ch Output disable N-ch VDD Data IN/OUT P-ch IN/OUT Output disable P-ch Comparator N-ch N-ch VREF (Threshold voltage) Input enable 18 + ­ Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 Figure 2-1. Pin Input/Output Circuits (2/2) Type 12-A Type 16 VDD Pullup enable Feedback cut-off P-ch P-ch VDD Data P-ch IN/OUT Output disable Input enable N-ch Analog output voltage XT1 P-ch XT2 N-ch Type 13-D IN/OUT Data Output disable N-ch VDD RD P-ch Middle-voltage input buffer Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 19 µPD78P054 PD78P054, 78P058 78P058 3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) IMS is a register that is set by software and is used to specify a part of the internal memory that is not to be used. By setting IMS, the internal memory (ROM, RAM) of the µPD78P054 PD78P054, 78P058 78P058 can be mapped identically to that of a mask ROM version. IMS is set with an 8-bit memory manipulation instruction. RESET input sets IMS to C8H (µPD78P054 PD78P054)/CFH (µPD78P058 PD78P058). Figure 3-1. Format of Internal Memory Size Switching Register (µPD78P054 PD78P054) Symbol IMS 7 6 5 RAM2 RAM1 RAM0 4 0 3 2 1 0 Address After reset R/W FFF0H C8H R/W ROM3 ROM2 ROM1 ROM0 ROM3 ROM2 ROM1 ROM0 Selection of internal ROM capacity 0 1 0 0 16 Kbytes 0 1 1 0 24 Kbytes 1 0 0 0 32 Kbytes Other than above Setting prohibited RAM2 RAM1 RAM0 Selection of internal high-speed RAM capacity 0 1 0 512 bytes 1 1 0 1024 bytes Other than above Setting prohibited Table 3-1 shows the setting values of IMS which make the memory map the same as that of the various mask ROM versions. Table 3-1. Internal Memory Size Switching Register Setting Values (µPD78P054 PD78P054) Target Mask ROM Version IMS Setting Value µPD78052 PD78052 C6H µPD78054 PD78054 20 44H µPD78053 PD78053 C8H Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 Figure 3-2. Format of Internal Memory Size Switching Register (µPD78P058 PD78P058) Symbol IMS 7 6 5 RAM2 RAM1 RAM0 4 0 3 2 1 0 Address After reset R/W FFF0H CFH R/W ROM3 ROM2 ROM1 ROM0 ROM3 ROM2 ROM1 ROM0 Selection of internal ROM capacity 0 1 0 0 16 Kbytes 0 1 1 0 24 Kbytes 1 0 0 0 32 Kbytes 1 0 1 0 40 Kbytes 1 1 0 0 48 Kbytes 1 1 1 0 56 Kbytes Note 1 1 1 1 60 Kbytes Other than above Setting prohibited RAM2 RAM1 RAM0 Selection of internal high-speed RAM capacity 0 1 0 512 bytes 1 1 0 1024 bytes Other than above Note Setting prohibited Set the internal ROM capacity to 56 Kbytes or less when the external device expansion function is used. Table 3-2 shows the setting values of IMS which make the memory map the same as that of the various mask ROM versions. Table 3-2. Internal Memory Size Switching Register Setting Values (µPD78P058 PD78P058) Target Mask ROM Version IMS Setting Value µPD78052 PD78052 44H µPD78053 PD78053 C6H µPD78054 PD78054 C8H µPD78055 PD78055 CAH µPD78056 PD78056 CCH µPD78058 PD78058 CFH Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 21 µPD78P054 PD78P054, 78P058 78P058 4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) (µPD78P058 PD78P058 ONLY) IXS is a register that is set by software and is used to set the internal expansion RAM capacity. By setting IXS, it is possible to get the same memory map as that of a mask ROM version having a different internal expansion RAM capacity. IXS is set with an 8-bit memory manipulation instruction. RESET input sets IXS to 0AH. Figure 4-1. Format of Internal Expansion RAM Size Switching Register Symbol 7 6 5 4 IXS 0 0 0 0 3 2 1 0 Address R/W FFF4H IXRAM3 IXRAM2 IXRAM1 IXRAM0 After reset 0AH W IXRAM3 IXRAM2 IXRAM1 IXRAM0 Selection of internal expansion RAM capacity 1 1 0 0 0 byte 1 0 1 0 1024 bytes Other than above Setting prohibited Table 4-1 shows the setting values of IXS which make the memory map the same as that of the various mask ROM versions. Table 4-1. Internal Expansion RAM Size Switching Register Setting Values Target Mask ROM Version IXS Setting Value µPD78052 PD78052 0CH µPD78053 PD78053 µPD78054 PD78054 µPD78055 PD78055 µPD78056 PD78056 µPD78058 PD78058 0AH Remark Even if a µPD78P058 PD78P058 program that includes "MOV IXS, #0CH" is implemented in the µPD78052 PD78052, 78053, 78054, 78055, or 78056, operation will not be affected. 22 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 5. PROM PROGRAMMING The µPD78P054 PD78P054 and 78P058 78P058 have 32 Kbytes and 60 Kbytes respectively of on-chip PROM as program memory. For programming, set the PROM programming mode with the VPP and RESET pins. For the connector of unused pins, refer to PIN CONFIGURATIONS (Top View) (2) PROM programming mode. Caution The program of the µPD78P054 PD78P054 should be written in the address range 0000H 0000H to 7FFFH (the last address, 7FFFH, should be specified). The program of the µPD78P058 PD78P058 should be written in the address range 0000H 0000H to EFFFH (the last address, EFFFH, should be specified). Writing cannot be performed with a PROM programmer that cannot specify the write addresses. 5.1 Operating Modes When +5 V or +12.5 V is applied to the VPP pin and a low level signal is applied to the RESET pin, the PROM programming mode is set. This mode will become the operating mode as shown in Table 5-1 when the CE, OE and PGM pins are set as shown. Further, when the read mode is set, it is possible to read the contents of the PROM. Table 5-1. Operating Modes of PROM Programming Pin RESET VPP VDD CE L +12.5 V +6.5 V OE PGM D0 to D7 Operating Mode Page data latch H L H Data input Page write H H L High-impedance Byte write L H L Data input Program verify L L H Data output Program inhibit × H H High-impedance × L L L L H Data output Output disable L H × High-impedance Standby H × × High-impedance Read Remark +5 V +5 V ×: L or H Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 23 µPD78P054 PD78P054, 78P058 78P058 (1) Read mode Read mode is set if CE = L, OE = L is set. (2) Output disable mode Data output becomes high-impedance, and is in the output disable mode, if OE = H is set. Therefore, data can be read from any device by controlling the OE pin, if multiple µPD78P054s or 78P058s are connected to the data bus. (3) Standby mode Standby mode is set if CE = H is set. In this mode, data output becomes high-impedance irrespective of the OE status. (4) Page data latch mode Page data latch mode is set if CE = H, PGM = H, OE = L is set when page write mode is entered. In this mode, 1-page 4-byte data is latched in an internal address/data latch circuit. (5) Page write mode After 1 page 4 bytes of addresses and data are latched in the page data latch mode, a page write is executed by applying a 0.1-ms program pulse (active low) to the PGM pin with CE = H, OE = H. Program verification can then be performed when CE = L, OE = L is set. If programming is not performed by a one-time program pulse, X (X 10) write and verification operations should be executed repeatedly. (6) Byte write mode Byte write is executed when a 0.1-ms program pulse (active low) is applied to the PGM pin with CE = L, OE = H. Program verification can then be performed when OE = L is set. If programming is not performed by a one-time program pulse, X (X 10) write and verification operations should be executed repeatedly. (7) Program verify mode Program verify mode is set if CE = L, PGM = H, OE = L is set. In this mode, after writing, check if the write operation was performed correctly. (8) Program inhibit mode Program inhibit mode is used when the OE pin, VPP pin, and D0 to D7 pins of multiple µPD78P054s or 78P058s are connected in parallel and a write is performed to one of those devices. When a write operation is performed, the page write mode or byte write mode described above is used. At this time, a write is not performed to a device which has the PGM pin driven high. 24 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 5.2 PROM Write Procedure Figure 5-1. Page Program Mode Flowchart Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 Latch Address = Address + 1 Latch Address = Address + 1 Latch Address = Address + 1 Address = Address + 1 Latch No X=X+1 X = 10? 0.1-ms program pulse Verify 4 bytes Yes Fail Pass No Address = N? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All pass End of writing Defective product Remark G = Start address N = Program last address Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 25 µPD78P054 PD78P054, 78P058 78P058 Figure 5-2. Page Program Mode Timing Page data latch Page program Program verify A2 to A16 A0, A1 Hi-Z D0 to D7 Data input Data output VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL 26 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 Figure 5-3. Byte Program Mode Flowchart Start Address = G VDD = 6.5 V, VPP = 12.5 V X=0 X=X+1 No X = 10? 0.1-ms program pulse Yes Address = Address + 1 Fail Verify Pass No Address = N? Yes VDD = 4.5 to 5.5 V, VPP = VDD Pass Verify all bytes Fail All pass End of writing Defective product Remark G = Start address N = Program last address Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 27 µPD78P054 PD78P054, 78P058 78P058 Figure 5-4. Byte Program Mode Timing Program Program verify A0 to A16 Hi-Z Data input D0 to D7 Data output VPP VPP VDD VDD + 1.5 VDD VDD VIH CE VIL VIH PGM VIL VIH OE VIL Cautions 1. V DD should be applied before VPP and removed after VPP. 2. VPP must not exceed +13.5 V including overshoot. 3. Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being applied to VPP. 28 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 5.3 PROM Read Procedure The contents of PROM can be read out to the external data bus (D0 to D7) using the read procedure shown below. (1) Fix the RESET pin at low level, supply +5 V to the VPP pin, and connect all other unused pins as shown in PIN CONFIGURATIONS (Top View) (2) PROM programming mode. (2) Supply +5 V to the VDD and VPP pins. (3) Input the address of data to be read to the A0 to A16 pins. (4) Read mode (5) Output data to D0 to D7 pins. The timing of the above steps (2) to (5) is shown in Figure 5-5. Figure 5-5. PROM Read Timing Address input A0 to A16 CE (Input) OE (Input) D0 to D7 Hi-Z Data output Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 Hi-Z 29 µPD78P054 PD78P054, 78P058 78P058 6. ERASURE METHOD (µPD78P054KK-T PD78P054KK-T, 78P058KK-T 78P058KK-T ONLY) The µPD78P054KK-T PD78P054KK-T and 78P058KK-T 78P058KK-T are capable of erasing (FFH) the contents of data written in a program memory and rewriting. When erasing the data, irradiate light having a wavelength of less than about 400 nm to the window on the top of the package. Normally, ultraviolet rays of 254-nm wavelength should be used. The volume of irradiation required to completely erase the data is as follows: · UV intensity × erasing time: 30 W·s/cm2 or more · Erasing time: 40 minutes or more (When a UV lamp of 12 mW/cm2 is used. However, a longer time may be needed because of deterioration in performance of the UV lamp, contamination of the erasing window, etc.) When erasing the data, set up the UV lamp within 2.5 cm from the erasing window. Further, if a filter is provided on the UV lamp, remove the filter during the erasure process. 7. ERASURE WINDOW OPAQUE FILM (µPD78P054KK-T PD78P054KK-T, 78P058KK-T 78P058KK-T ONLY) To protect from unintentional erasure by other than EPROM erasure lamp light, or to protect internal circuits other than EPROM from malfunction due to light coming in through the window, mask the window with the attached opaque film when EPROM erasure is not being performed. 8. SCREENING OF ONE-TIME PROM VERSIONS The one-time PROM versions (µPD78P054GC-8BT PD78P054GC-8BT, 78P054GK-BE9 78P054GK-BE9, and 78P058GC-8BT 78P058GC-8BT) cannot be tested completely by NEC before being shipped, because of their structure. It is recommended to perform screening to verify PROM after writing the necessary data and following high-temperature storage under the conditions below. Storage Temperature Storage Time 125°C 24 hours At present, a fee is charged by NEC for the one-time PROM writing, marking, screening, and verifying service for QTOP microcontrollers. For details, contact your sales representative. 30 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 9. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Unit ­0.3 to +7.0 V ­0.3 to +13.5 V AVDD ­0.3 to VDD + 0.3 V AVREF0 ­0.3 to VDD + 0.3 V AVREF1 ­0.3 to VDD + 0.3 V AVSS Input voltage Ratings VDD VPP Supply voltage Symbol ­0.3 to +0.3 V ­0.3 to VDD + 0.3 V ­0.3 to +16 V ­0.3 to +13.5 V ­0.3 to VDD + 0.3 V AVSS ­ 0.3 to AVREF0 + 0.3 V VI1 Conditions P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131, X1, X2, XT2, RESET VI2 P60 to P63 N-ch open-drain VI3 A9 PROM programming mode Output voltage VO Analog input voltage VAN P10 to P17 Output current, high IOH Per pin ­10 mA Total for P01 to P06, P30 to P37, P56, P57, P60 to P67, P120 to P127 ­15 mA Total for P10 to P17, P20 to P27, P40 to P47, P50 to P55, P70 to P72, P130, P131 ­15 mA Per pin peak value 30 mA r.m.s. value 15 mA peak value 100 mA r.m.s. value 70 mA peak value 100 mA r.m.s. value 70 mA Total for P10 to P17, P20 to P27, peak value 50 mA P40 to P47, P70 to P72, P130, P131 r.m.s. value 20 mA Total for P01 to P06, P30 to P37, peak value 50 mA P64 to P67, P120 to P127 r.m.s value 20 mA Output current, low IOLNote Analog input pins Total for P50 to P55 Total for P56, P57, P60 to P63 Operating ambient temperature TA ­40 to +85 °C Storage temperature Tstg ­65 to +150 °C Note r.m.s. values should be calculated as follows: [r.m.s. value] = [peak value] × Duty Caution Product quality may suffer if the absolute maximum rating is exceeded momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions which ensure that the absolute maximum ratings are not exceeded. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 31 µPD78P054 PD78P054, 78P058 78P058 Main System Clock Oscillator Characteristics (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) Resonator Recommended Circuit Ceramic resonator X2 X1 C2 VPP C1 Crystal resonator X2 X1 C2 VPP C1 Parameter Conditions Oscillation frequency (fX)Note 1 VDD = Oscillation voltage range Oscillation stabilization timeNote 2 MIN. TYP. MAX. Unit After VDD has reached MIN. of oscillation voltage range Oscillation frequency (fX)Note 1 Oscillation stabilization timeNote 2 1.0 ms 5.0 MHz 10 VDD = 4.5 to 6.0 V MHz 4 1.0 5.0 ms 30 External clock X2 µ PD74HCU04 PD74HCU04 X1 X1 input frequency (fX)Note 1 1.0 5.0 MHz X1 input high-/low-level width (tXH/t XL) 85 500 ns Notes 1. Indicates only the oscillator characteristics. See the AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after a reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. · Keep the wiring length as short as possible. · Do not cross the wiring with the other signal lines. · Do not route the wiring near a signal line through which a high fluctuating current flows. · Always make the ground point of the oscillator capacitor the same potential as VSS. · Do not ground the capacitor to a ground pattern through which a high current flows. · Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. 32 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 Subsystem Clock Oscillator Characteristics (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) Resonator Recommended Circuit Ceramic resonator VPP XT2 XT1 Parameter Conditions Oscillation frequency (fXT)Note 1 MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s R1 C4 Oscillation stabilization timeNote 2 C3 VDD = 4.5 to 6.0 V 10 External clock XT2 µ PD74HCU04 PD74HCU04 XT1 XT1 input frequency (fXT)Note 1 32 100 kHz XT1 input high-/lowlevel width (tXTH/tXTL) 5 15 µs Notes 1. Indicates only the oscillator characteristics. See the AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN. Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. · Keep the wiring length as short as possible. · Do not cross the wiring with the other signal lines. · Do not route the wiring near a signal line through which a high fluctuating current flows. · Always make the ground point of the oscillator capacitor the same potential as VSS. · Do not ground the capacitor to a ground pattern through which a high current flows. · Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 33 µPD78P054 PD78P054, 78P058 78P058 Recommended Oscillator Constant (1) µPD78P054 PD78P054 Main system clock: Ceramic resonator (TA = ­40 to +85°C) Manufacturer Product Name Frequency (MHz) TDK Corp. Recommended Circuit Oscillation Voltage Range Constant C1 (pF) C2 (pF) MIN. (V) MAX. (V) CCR4.0MC3 4.0 On-chip On-chip 2.0 6.0 CCR5.0MC3 5.0 On-chip On-chip 2.0 6.0 Subsystem clock: Crystal resonator (TA = ­40 to +85°C) Manufacturer Product Name Frequency (kHz) Daishinku Corp. Caution DT-38 DT-38 (1TA252E00 1TA252E00, load capacitance 12.5 pF) 32.768 Recommended Circuit Constant Oscillation Voltage Range C3 (pF) C4 (pF) R1 (k) MIN. (V) MAX. (V) 22 22 330 2.0 6.0 The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. 34 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 (2) µPD78P058 PD78P058 Main system clock: Ceramic resonator (TA = ­20 to +80°C) Manufacturer Product Name (MHz) Kyocera Corp. Recommended Circuit Frequency KBR-4.19MKS 19MKS Constant Oscillation Voltage Range C1 (pF) MIN. (V) MAX. (V) On-chip 4.19 C2 (pF) On-chip 2.0 6.0 Main system clock: Ceramic resonator (TA = ­40 to +85°C) Manufacturer Product Name Frequency (MHz) Murata Mfg. Co., Ltd. Caution Recommended Circuit Constant Oscillation Voltage Range C1 (pF) C2 (pF) MIN. (V) MAX. (V) CST5.00MGW 00MGW 5.0 On-chip On-chip 2.7 6.0 CSA5.00MG 5.0 30 30 2.7 6.0 The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz, Unmeasured pins returned to 0 V 15 pF Input/output capacitance CIO f = 1 MHz Unmeasured pins returned to 0 V P01 to P06, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 15 pF P60 to P63 20 pF Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 35 µPD78P054 PD78P054, 78P058 78P058 DC Characteristics (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) Parameter Symbol Unit VDD V 0.8VDD VDD V 0.8VDD VDD V 0.85VDD 85VDD VDD V 0.7VDD 15 V 0.8VDD 15 V VDD ­ 0.5 VDD V VDD V 4.5 V VDD 6.0 V 0.8VDD VDD V 2.7 V VDD < 4.5 V 0.9VDD VDD V 2.0 V VDD < 2.7 0.9VDD VDD V 0 0.3VDD V 0 0.2VDD V 0 0.2VDD V 0 0.15VDD 15VDD V 4.5 V VDD 6.0 V 0 0.3VDD V 2.7 V VDD < 4.5 V 0 0.2VDD V 0 0.1VDD V 0 0.4 V 0 0.2 V 4.5 V VDD 6.0 V 0 0.2VDD V 2.7 V VDD < 4.5 V VIH2 MAX. 0.7VDD VDD ­ 0.2 VIH1 P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 6.0 V P35 to P37, P40 to P47, P50 to P57, P64 to P67, P71, P120 to P127, P130, P131 Input voltage, high Conditions 0 0.1VDD V 0 0.1VDD V P00 to P06, P20, P22, P24 to P27, MIN. VDD = 2.7 to 6.0 V P33, P34, P70, P72, RESET VIH3 P60 to P63 VDD = 2.7 to 6.0 V (N-ch open-drain) VIH4 VIH5 Input voltage, low VIL1 X1, X2 VDD = 2.7 to 6.0 V XT1/P07 XT1/P07, XT2 P10 to P17, P21, P23, P30 to P32, P35 to P37, P40 to P47, VNote VDD = 2.7 to 6.0 V P50 to P57, P64 to P67, P71, P120 to P127, P130, P131 VIL2 P00 to P06, P20, P22, P24 to P27, VDD = 2.7 to 6.0 V P33, P34, P70, P72, RESET VIL3 VIL4 VIL5 P60 to P63 X1, X2 VDD = 2.7 to 6.0 V XT1/P07 XT1/P07, XT2 2.0 V VDD < 2.7 Output voltage, high VOL1 VDD = 4.5 to 6.0 V, IOH = ­1 mA VDD ­ 1.0 V IOH = ­100 µA Output voltage, low VOH1 VNote TYP. VDD ­ 0.5 V P50 to P57, P60 to P63 VDD = 4.5 to 6.0 V, IOL = 15 mA VOL2 SB0, SB1, SCK0 VOL3 VDD = 4.5 to 6.0 V, N-ch open-drain, with pull-up resistor (R = 1 k) IOL = 400 µA 2.0 V 0.4 V 0.2VDD V 0.5 P01 to P06, P10 to P17, P20 to P27, VDD = 4.5 to 6.0 V, P30 to P37, P40 to P47, P64 to P67, IOL = 1.6 mA P70 to P72, P120 to P127, P130, P131 0.4 V Note When the XT1/P07 XT1/P07 pin is used as P07, the inverse phase of P07 should be input to XT2 using an inverter. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. 36 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 DC Characteristics (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) Parameter Input leakage current, high Symbol ILIH1 Conditions ILIH2 MAX. Unit P00 to P06, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P72, P120 to P127, P130, P131, RESET 3 µA X1, X2, XT1/P07 XT1/P07, XT2 VIN = VDD MIN. TYP. 20 µA ILIH3 VIN = 15 V P60 to P63 80 µA ILIL1 Input leakage current, low VIN = 0 V P00 to P06, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131, RESET ­3 µA X1, X2, XT1/P07 XT1/P07, XT2 ­20 µA ­3Note 1 µA ILIL2 ILIL3 P60 to P63 Output leakage current, high ILOH1 VOUT = VDD 3 µA Output leakage ILOL1 VOUT = 0 V ­3 µA 90 k 500 k current, low Software pull-up resistorNote 2 R2 VIN = 0 V, P01 to P06, P10 to P17, 4.5 V VDD 6.0 V P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, 2.7 V VDD < 4.5 V P120 to P127, P130, P131 15 20 40 Notes 1. For P60 to P63, a low-level input leakage current of ­200 µA (MAX.) flows only for 1.5 clocks (without wait) after the read instruction has been executed to port 6 (P6) or port mode register 6 (PM6). At times other than this 1.5-clock interval a ­3 µA (MAX.) current flows. 2. A software pull-up resistor can only be used in the range or VDD = 2.7 to 6.0 V. Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port pins. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 37 µPD78P054 PD78P054, 78P058 78P058 DC Characteristics (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) Parameter Symbol Supply currentNote 5 IDD1 Conditions TYP. MAX. Unit VDD = 5.0 V ±10%Note 1 5 15 mA VDD = 3.0 V ±10%Note 2 0.7 2.1 mA VDD = 2.2 V ±10%Note 2 0.4 1.2 mA VDD = 5.0 V ±10%Note 1 9.0 27.0 mA VDD = 3.0 V ±10%Note 2 1.0 3.0 mA 5.0-MHz crystal oscillation HALT VDD = 5.0 V ±10% 1.4 4.2 mA mode (fXX = 2.5 MHz)Note 3 VDD = 3.0 V ±10% 0.5 1.5 mA VDD = 2.2 V ±10% 280 840 µA 5.0-MHz crystal oscillation HALT VDD = 5.0 V ±10% 1.6 4.8 mA mode (fXX = 5.0 MHz)Note 4 VDD = 3.0 V ±10% 0.65 1.95 mA 32.768-kHz VDD = 5.0 V ±10% 135 270 µA crystal oscillation operating VDD = 3.0 V ±10% 95 190 µA VDD = 2.2 V ±10% 70 140 µA 32.768-kHz VDD = 5.0 V ±10% 25 55 µA crystal oscillation HALT modeNote 6 VDD = 3.0 V ±10% 5 15 µA VDD = 2.2 V ±10% 2.5 12.5 µA XT1 = VDD VDD = 5.0 V ±10% 1 30 µA STOP mode VDD = 3.0 V ±10% 0.5 10 µA Feedback resistor used VDD = 2.2 V ±10% 0.3 10 µA XT1 = VDD VDD = 5.0 V ±10% 0.1 30 µA STOP mode VDD = 3.0 V ±10% 0.05 10 µA Feedback resistor not used VDD = 2.2 V ±10% 0.05 10 µA 5.0-MHz crystal oscillation operating mode (fXX = 2.5 MHz)Note 3 5.0-MHz crystal oscillation operating mode (fXX = 5.0 IDD2 IDD3 MHz)Note 4 modeNote 6 IDD4 IDD5 IDD6 MIN. Notes 1. High-speed mode operation (when the processor clock control register (PCC) is set to 00H) 2. Low-speed mode operation (when PCC is set to 04H) 3. Operation with main system clock fXX = fX/2 (when the oscillation mode selection register (OSMS) is set to 00H) 4. Operation with main system clock fXX = fX (when OSMS is set to 01H) 5. Refers to the current flowing through the VDD and AVDD pins. The current flowing to the A/D converter, D/A converter, and on-chip pull-up resistors is not included. 6. When the main system clock operation is stopped. 38 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 AC Characteristics (1) Basic operation (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) Parameter Symbol TCY (minimum instruction Conditions Operating with main system clock (fXX = 2.5 execution time) MIN. Unit 64 µs 2.2 64 µs 4.5 V VDD 6.0 V 0.4 32 µs 2.7 V VDD < 4.5 V 0.8 32 µs 125 µs 0 4 MHz 275 kHz VDD = 2.7 to 6.0 V MHz)Note 1 Operating with main system clock (fXX = 5.0 MAX. 0.8 0 Cycle time MHz)Note 2 40Note 3 122 Operating with subsystem clock TI01, TI1, TI2 input fTI TYP. VDD = 4.5 to 6.0 V frequency 8/fsamNote 4 tINTH, INTP0 high-/low-level width tINTL INTP1 to INTP6, KR0 to KR7 10 µs µs 10 µs 20 Interrupt request input µs 20 tTIL µs 8/fsamNote 4 tTIH, high-/low-level width ns µs tTIL TI01, TI1, TI2, input 100 tTIH, level width µs 1.8 TI00 input high-/low- RESET low-level tRSL VDD = 4.5 to 6.0 V VDD = 2.7 to 6.0 V VDD = 2.7 to 6.0 V width Notes 1. Operation with main system clock fXX = fX/2 (when the oscillation mode selection register (OSMS) is set to 00H) 2. Operation with main system clock fXX = fX (when OSMS is set to 01H) 3. Value when an external clock is used. When a crystal resonator is used, it is 114 µs (MIN.). 4. Selection of fsam = fXX/2N, fXX/32, fXX/64, fXX/128 is possible using bits 0 and 1 (SCS0 and SCS1) of the sampling clock selection register (SCS) (when N = 0 to 4). Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 39 µPD78P054 PD78P054, 78P058 78P058 TCY vs VDD (At fXX = fX/2 main system clock operation) TCY vs VDD (At fXX = fX main system clock operation) 60 Cycle time TCY [µs] Cycle time TCY [µs] 60 10 Guaranteed operation range 2.0 10 Guaranteed operation range 2.0 1.0 1.0 0.5 0.4 0.5 0.4 0 1 2 3 4 5 6 0 Supply voltage VDD [V] 40 1 2 3 4 5 Supply voltage VDD [V] Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 6 µPD78P054 PD78P054, 78P058 78P058 (2) Read/write operations (a) When MCS = 1, PCC2 to PCC0 = 000B (TA = ­40 to +85°C, VDD = 4.5 to 6.0 V) Parameter Symbol Conditions MIN. MAX. Unit ASTB high-level width tASTH 0.85tCY ­ 50 ns Address setup time tADS 0.85tCY ­ 50 ns Address hold time tADH 50 ns Data input time from address tADD1 (2.85 + 2n)tCY ­ 80 ns tADD2 (4 + 2n)tCY ­ 100 ns tRDD1 (2 + 2n)tCY ­ 100 ns tRDD2 (2.85 + 2n)tCY ­ 100 ns Data input time from RD Read data hold time tRDH 0 ns RD low-level width tRDL1 (2 + 2n)tCY ­ 60 ns tRDL2 (2.85 + 2n)tCY ­ 60 ns WAIT input time from RD 0.85tCY ­ 50 ns tRDWT2 WAIT input time from WR tRDWT1 2tCY ­ 60 ns tWRWT 2tCY ­ 60 ns (2 + 2n)tCY ns WAIT low-level width tWTL (1.15 + 2n)tCY Write data setup time tWDS (2.85 + 2n)tCY ­ 100 ns Write data hold time tWDH 20 ns WR low-level width tWRL1 (2.85 + 2n)tCY ­ 60 ns RD delay time from ASTB tASTRD 25 ns WR delay time from ASTB tASTWR 0.85tCY + 20 ns ASTB delay time from RD in external fetch tRDAST 0.85tCY ­ 10 1.15tCY + 20 ns Address hold time from RD in external fetch tRDADH 0.85tCY ­ 50 1.15tCY + 50 ns Write data output time from RD tRDWD 40 ns Write data output time from WR tWRWD 0 50 ns Address hold time from WR tWRADH 0.85tCY 1.15tCY + 40 ns RD delay time from WAIT tWTRD 1.15tCY + 40 3.15tCY + 40 ns WR delay time from WAIT tWTWR 1.15tCY + 30 3.15tCY + 30 ns Remarks 1. MCS: Bit 0 of the oscillation mode selection register (OSMS) 2. PCC2 to PCC0: Bit 2 to bit 0 of the processor clock control register (PCC) 3. tCY = TCY/4 4. n indicates the number of waits. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 41 µPD78P054 PD78P054, 78P058 78P058 (b) Except when MCS = 1, PCC2 to PCC0 = 000B (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) (1/2) Parameter ASTB high-level width Symbol MIN. Unit Data input time from address tADH tADD1 ns ns 0.4tCY ­ 10 VDD = 2.7 to 6.0 V ns tCY ­ 80 VDD = 2.7 to 6.0 V ns ns 0.37tCY ­ 40 Address hold time tCY ­ 80 tCY ­ 150 tADS VDD = 2.7 to 6.0 V MAX. tCY ­ 150 Address setup time tASTH Conditions ns Read data hold time tRDH RD low-level width tRDL1 ns (2.4 + 2n)tCY ­ 70 VDD = 2.7 to 6.0 V ns ns (2.37 + 2n)tCY ­ 120 tRDD2 ns (1.4 + 2n)tCY ­ 70 VDD = 2.7 to 6.0 V ns (1.37 + 2n)tCY ­ 120 tRDD1 ns (4 + 2n)tCY ­ 200 VDD = 2.7 to 6.0 V ns (4 + 2n)tCY ­ 300 Data input time from RD (3 + 2n)tCY ­ 160 (3 + 2n)tCY ­ 320 tADD2 VDD = 2.7 to 6.0 V ns (1.4 + 2n)tCY ­ 20 ns ns (2.4 + 2n)tCY ­ 20 ns (2.37 + 2n)tCY ­ 20 WAIT input time from RD ns (1.37 + 2n)tCY ­ 20 tRDL2 0 ns VDD = 2.7 to 6.0 V VDD = 2.7 to 6.0 V tRDWT1 VDD = 2.7 to 6.0 V tCY ­ 100 tCY ­ 200 tWTL Write data setup time tWDS (1 + 2n)tCY ns (2 + 2n)tCY ns ns 20 ns (2.4 + 2n)tCY ­ 20 ns (2.37 + 2n)tCY ­ 20 tWRL1 ns ns tWDH WR low-level width (2.4 + 2n)tCY ­ 60 (2.37 + 2n)tCY ­ 100 Write data hold time VDD = 2.7 to 6.0 V ns 2tCY ­ 200 WAIT low-level width ns 2tCY ­ 100 tWRWT VDD = 2.7 to 6.0 V ns 2tCY ­ 200 WAIT input time from WR ns 2tCY ­ 100 tRDWT2 VDD = 2.7 to 6.0 V ns VDD = 2.7 to 6.0 V Remarks 1. MCS: Bit 0 of the oscillation mode selection register (OSMS) 2. PCC2 to PCC0: Bit 2 to bit 0 of the processor clock control register (PCC) 3. tCY = TCY/4 4. n indicates the number of waits. 42 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 (b) Except when MCS = 1, PCC2 to PCC0 = 000B (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) (2/2) Parameter RD delay time from ASTB Symbol Conditions MAX. Unit ns ns 1.4tCY ­ 30 ns 1.37tCY ­ 50 tASTWR VDD = 2.7 to 6.0 V 0.4tCY ­ 30 0.37tCY ­ 50 WR delay time from ASTB tASTRD VDD = 2.7 to 6.0 V MIN. ns ASTB delay time from RD in external fetch tRDAST tCY ­ 10 tCY + 20 ns Address hold time from RD in external fetch tRDADH tCY ­ 50 tCY + 50 ns Write data output time from RD VDD = 2.7 to 6.0 V ns ns VDD = 2.7 to 6.0 V tWTWR VDD = 2.7 to 6.0 V 120 ns tCY tCY + 60 ns tCY + 120 ns 0.6tCY + 180 2.6tCY + 180 ns 2.63tCY + 350 ns 0.6tCY + 120 2.6tCY + 120 ns 0.63tCY + 240 WR delay time from WAIT tWTRD ns 0.63tCY + 350 RD delay time from WAIT 60 tCY tWRADH VDD = 2.7 to 6.0 V 0 0 Address hold time from WR tWRWD VDD = 2.7 to 6.0 V 0.4tCY ­ 20 0.37tCY ­ 40 Write data output time from WR tRDWD 2.63tCY + 240 ns Remarks 1. MCS: Bit 0 of the oscillation mode selection register (OSMS) 2. PCC2 to PCC0: Bit 2 to bit 0 of the processor clock control register (PCC) 3. tCY = TCY/4 4. n indicates the number of waits. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 43 µPD78P054 PD78P054, 78P058 78P058 (3) Serial interface (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0 . Internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 1600 ns ns tKCY1/2 ­ 50 ns tKCY1/2 ­ 100 ns 4.5 V VDD 6.0 V 100 ns 150 ns 300 tKH1, ns 2.7 V VDD < 4.5 V SCK0 high-/low-level width 800 3200 tKCY1 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V SCK0 cycle time ns 400 ns VDD = 4.5 to 6.0 V tKL1 SI0 setup time (to SCK0) SI0 hold time (from SCK0) SO0 output delay time from SCK0 tSIK1 tKSI1 tKSO1 C= 100pFNote 300 ns MAX. Unit Note C is the load capacitance of the SO0 output line. (ii) 3-wire serial I/O mode (SCK0 . External clock input) Parameter Symbol Conditions MIN. TYP. 800 ns 1600 ns 3200 tKCY2 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V SCK0 cycle time ns tKH2, 4.5 V VDD 6.0 V 400 ns tKL2 2.7 V VDD < 4.5 V 800 ns 1600 SCK0 high-/low-level width ns 100 ns 400 ns SI0 setup time (to SCK0) tSIK2 SI0 hold time (from SCK0) tKSI2 SO0 output delay time from SCK0 tKSO2 C = 100 SCK0 rise, fall time tR2, tF2 pFNote 300 ns When using external device expansion function 160 ns When not using external 1000 ns device expansion function Note C is the load capacitance of the SO0 output line. 44 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 (iii) SBI mode (SCK0 . Internal clock output) Parameter SCK0 cycle time Symbol Conditions TYP. MAX. Unit 800 SB0, SB1 setup time (to SCK0) tSIK3 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from tKSO3 SCK0 R = 1 k, C = 100 VDD = 4.5 to 6.0 V ns ns tKCY3/2 tKSI3 ns 100 VDD = 4.5 to 6.0 V ns tKCY3/2 ­ 150 tKL3 ns tKCY3/2 ­ 50 VDD = 4.5 to 6.0 V ns 300 tKH3, VDD = 4.5 to 6.0 V MIN. 3200 SCK0 high-/low-level width tKCY3 ns 0 250 ns 0 pFNote 1000 ns SB0, SB1 from SCK0 tKSB tKCY3 ns SCK0 from SB0, SB1 tSBK tKCY3 ns SB0, SB1 high-level width tSBH tKCY3 ns SB0, SB1 low-level width tSBL tKCY3 ns Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output lines. (iv) SBI mode (SCK0 . External clock input) Parameter SCK0 cycle time Symbol TYP. MAX. Unit 800 SB0, SB1 setup time (to SCK0) tSIK4 SB0, SB1 hold time (from SCK0) SB0, SB1 output delay time from tKSO4 R = 1 k, VDD = 4.5 to 6.0 V C = 100 pFNote SCK0 ns ns tKCY4/2 tKSI4 ns 100 VDD = 4.5 to 6.0 V ns 1600 tKL4 ns 400 VDD = 4.5 to 6.0 V ns 300 tKH4, VDD = 4.5 to 6.0 V MIN. 3200 SCK0 high-/low-level width tKCY4 Conditions ns 0 300 ns 0 1000 ns SB0, SB1 from SCK0 tKSB tKCY4 ns SCK0 from SB0, SB1 tSBK tKCY4 ns SB0, SB1 high-level width tSBH tKCY4 ns SB0, SB1 low-level width tSBL tKCY4 ns SCK0 rise, fall time tR4, When using external device tF4 expansion function When not using external 160 ns 1000 ns device expansion function Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 45 µPD78P054 PD78P054, 78P058 78P058 (v) 2-wire serial I/O mode (SCK0 . Internal clock output) Parameter SCK0 cycle time Symbol tKCY5 Conditions R = 1 k, C = 100 SCK0 high-level width VDD = 2.7 to 6.0 V TYP. MAX. Unit ns 3200 pFNote ns ns ns 4.5 V VDD 6.0 V 300 ns 2.7 V VDD < 4.5 V 350 ns 400 tSIK5 ns VDD = 4.5 to 6.0 V tKCY5/2 ­ 50 tKL5 ns tKCY5/2 ­ 100 SB0, SB1 setup time (to SCK0) VDD = 2.7 to 6.0 V tKCY5/2 ­ 160 tKCY5/2 ­ 190 SCK0 low-level width tKH5 MIN. 1600 ns ns SB0, SB1 hold time (from SCK0) tKSI5 600 SB0, SB1 output delay time from SCK0 tKSO5 0 300 ns Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output lines. (vi) 2-wire serial I/O mode (SCK0 . External clock input) Parameter SCK0 cycle time Symbol TYP. MAX. Unit tKL6 ns ns 800 VDD = 2.7 to 6.0 V ns 650 VDD = 2.7 to 6.0 V ns ns 1600 SCK0 low-level width 1600 1300 tKH6 VDD = 2.7 to 6.0 V MIN. 3200 SCK0 high-level width tKCY6 Conditions ns SB0, SB1 setup time (to SCK0) tSIK6 100 ns SB0, SB1 hold time (from SCK0) tKSI6 tKCY6/2 ns SB0, SB1 output delay time tKSO6 from SCK0 SCK0 rise, fall time R = 1 k, C = 100 VDD = 4.5 to 6.0 V pFNote tR6, 300 ns 0 500 ns 160 ns 1000 ns When using external device tF6 0 expansion function When not using external device expansion function Note R and C are the load resistance and load capacitance of the SB0 and SB1 output lines. 46 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 (b) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1 . Internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit SCK1 high-/low-level width SI1 setup time (to SCK1) 800 ns 1600 ns 3200 tKCY7 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V SCK1 cycle time ns tKH7, tKL7 VDD = 4.5 to 6.0 V tSIK7 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V tKCY7/2 ­ 50 ns tKCY7/2 ­ 100 ns 100 ns SI1 hold time (from SCK1) SO1 output delay time from SCK1 tKSO7 C = 100 ns ns 400 tKSI7 150 300 ns pFNote 300 ns MAX. Unit Note C is the load capacitance of the SO1 output line. (ii) 3-wire serial I/O mode (SCK1 . External clock input) Parameter Symbol Conditions MIN. TYP. tKH8, tKL8 ns 1600 ns ns 4.5 V VDD 6.0 V 400 ns 2.7 V VDD < 4.5 V 800 ns 1600 SCK1 high-/low-level width 800 3200 tKCY8 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V SCK1 cycle time ns SI1 setup time (to SCK1) tSIK8 100 ns SI1 hold time (from SCK1) tKSI8 400 ns pFNote SO1 output delay time from SCK1 tKSO8 C = 100 SCK1 rise, fall time tR8, tF8 When using external device expansion function When not using external device expansion function 300 ns 160 ns 1000 ns Note C is the load capacitance of the SO1 output line. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 47 µPD78P054 PD78P054, 78P058 78P058 (iii) Automatic transmit/receive function 3-wire serial I/O mode (SCK1 . Internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 1600 ns ns tKCY9/2 ­ 50 ns tKCY9/2 ­ 100 ns 4.5 V VDD 6.0 V 100 ns 150 ns 300 tKH9, ns 2.7 V VDD < 4.5 V SCK1 high-/low-level width 800 3200 tKCY9 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V SCK1 cycle time ns 400 ns VDD = 4.5 to 6.0 V tKL9 SI1 setup time (to SCK1) SI1 hold time (from SCK1) tSIK9 tKSI9 SO1 output delay time from SCK1 tKSO9 STB from SCK1 tSBD Strobe signal high-level width tSBW tBYS Busy signal hold time tBYH ns tKCY9/2 ­ 100 VDD = 2.7 to 6.0 V 300 tKCY9/2 + 100 ns tKCY9 ­ 30 tKCY9 + 30 ns tKCY9 ­ 60 Busy signal setup time (to busy signal detection timing) C = 100 pFNote tKCY9 + 60 ns Note 4.5 V VDD 6.0 V 100 ns 150 ns 200 SCK1 from busy inactive ns 2.7 V VDD < 4.5 V (from busy signal detection timing) 100 ns 2tKCY9 tSPS ns C is the load capacitance of the SO1 output line. (iv) Automatic transmit/receive function 3-wire serial I/O mode (SCK1 . External clock input) Parameter Symbol Conditions MIN. TYP. MAX. Unit 800 ns 1600 ns 3200 tKCY10 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V SCK1 cycle time ns tKH10, 4.5 V VDD 6.0 V 400 ns tKL10 2.7 V VDD < 4.5 V 800 ns 1600 SCK1 high-/low-level width ns 100 ns 400 ns SI1 setup time (to SCK1) tSIK10 SI1 hold time (from SCK1) tKSI10 SO1 output delay time from SCK1 tKSO10 C = 100 SCK1 rise, fall time tR10, tF10 pFNote 300 ns When using external device expansion function 160 ns When not using external 1000 ns device expansion function Note C is the load capacitance of the SO1 output line. 48 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 (c) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2 . Internal clock output) Parameter Symbol Conditions MIN. TYP. MAX. Unit 1600 ns ns tKCY11/2 ­ 50 ns tKCY11/2 ­ 100 ns 4.5 V VDD 6.0 V 100 ns 150 ns 300 tKH11, ns 2.7 V VDD < 4.5 V SCK2 high-/low-level width 800 3200 tKCY11 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V SCK2 cycle time ns 400 ns VDD = 4.5 to 6.0 V tKL11 SI2 setup time (to SCK2) SI2 hold time (from SCK2) SO2 output delay time from SCK2 tSIK11 tKSI11 tKSO11 C = 100 pFNote 300 ns MAX. Unit Note C is the load capacitance of the SO2 output line. (ii) 3-wire serial I/O mode (SCK2 . External clock input) Parameter Symbol Conditions MIN. TYP. 800 ns 1600 ns 3200 tKCY12 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V SCK2 cycle time ns tKH12, 4.5 V VDD 6.0 V 400 ns tKL12 2.7 V VDD < 4.5 V 800 ns 1600 SCK2 high-/low-level width ns 100 ns 400 ns SI2 setup time (to SCK2) tSIK12 SI2 hold time (from SCK2) tKS1I2 pFNote SO2 output delay time from SCK2 tKSO12 C = 100 SCK2 rise, fall time tR12, tF12 When using external device expansion function When not using external 300 ns 160 ns 1000 ns device expansion function Note C is the load capacitance of the SO2 output line. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 49 µPD78P054 PD78P054, 78P058 78P058 (iii) UART mode (Dedicated baud rate generator output) Parameter Symbol MAX. Unit 4.5 V VDD 6.0 V 78125 bps 2.7 V VDD < 4.5 V 39063 bps 19531 Transfer rate Conditions MIN. TYP. bps MAX. Unit (iv) UART mode (External clock input) Parameter Symbol Conditions MIN. TYP. 800 ns 1600 ns 3200 tKCY13 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V ASCK cycle time ns tKH13, 4.5 V VDD 6.0 V 400 ns tKL13 2.7 V VDD < 4.5 V 800 ns 1600 ASCK high-/low-level width ns 4.5 V VDD 6.0 V 50 19531 bps bps 1000 ns 160 tR13, tF13 bps 9766 ASCK rise, fall time 39063 2.7 V VDD < 4.5 V Transfer rate ns VDD = 4.5 to 6.0 V, when not using external device expansion function Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 AC Timing Test Points (Excluding X1, XT1 inputs) 0.8 VDD 0.8 VDD Test Points 0.2 VDD 0.2 VDD Clock Timing 1/fX tXL tXH VIH4 (MIN.) VIL4 (MAX.) X1 Input 1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.) XT1 Input TI Timing 1/fTI tTIL tTIH TI00, TI01, TI1, TI2 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 51 µPD78P054 PD78P054, 78P058 78P058 Read/Write Operations External fetch (no wait): A8 to A15 Higher 8-bit address Lower 8-bit address tADD1 Hi-Z AD0 to AD7 tADS tASTH Operation code tRDD1 tADH tRDADH tRDAST ASTB RD tRDL1 tASTRD tRDH External fetch (wait insertion): A8 to A15 Higher 8-bit address Lower 8-bit address t ADD1 Hi-Z AD0 to AD7 t ADS t ADH Operation code t RDD1 tRDADH tRDAST t ASTH ASTB RD t ASTRD t RDH t RDL1 WAIT t RDWT1 52 t WTL Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 tWTRD µPD78P054 PD78P054, 78P058 78P058 External data access (no wait): A8 to A15 Higher 8-bit address Lower 8-bit address tADD2 Hi-Z AD0 to AD7 tADS Hi-Z Read data Hi-Z Write data tRDD2 tADH tASTH tRDH ASTB RD tASTRD tRDWD tRDL2 tWDH t WRADH tWDS tWRWD WR tWRL1 tASTWR External data access (wait insertion): Lower 8-bit address A8 to A15 Higher 8-bit address tADD2 Hi-Z AD0 to AD7 Read data Hi-Z Hi-Z Write data tADS tASTH tADH tRDD2 tRDH ASTB tASTRD RD tRDL2 tWDS tRDWD tWDH tWRWD WR tASTWR tWRADH tWRL1 WAIT tRDWT2 tWTL tWTRD Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 tWRWT tWTL tWTWR 53 µPD78P054 PD78P054, 78P058 78P058 Serial Transfer Timing 3-wire serial I/O mode: tKCYm tKHm tKLm tRn tFn SCK0 to SCK2 tSIKm SI0 to SI2 tKSIm Input data tKSOm SO0 to SO2 Output data Remark m = 1, 2, 7, 8, 11, 12 n = 2, 8, 12 SBI mode (bus release signal transfer): tKCY3, 4 tKL3, 4 tKH3, 4 tR4 tF4 SCK0 tKSB tSBL tSBH tSBK tSIK3, 4 SB0, SB1 tKSO3, 4 54 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 tKSI3, 4 µPD78P054 PD78P054, 78P058 78P058 SBI mode (command signal transfer): tKL3, 4 tKCY3, 4 tKH3, 4 tR4 tF4 SCK0 tSBK tKSB tSIK3, 4 tKSI3, 4 SB0, SB1 tKSO3, 4 2-wire serial I/O mode: tKCY5, 6 tKL5, 6 tKH5, 6 tR6 tF6 SCK0 tSIK5, 6 tKSI5, 6 tKSO5, 6 SB0, SB1 Automatic transmit/receive function 3-wire serial I/O mode: SO1 SI1 D2 D2 D1 D0 D1 D7 D0 t SIK9, 10 D7 t KSI9, 10 t KH9, 10 t KSO9, 10 t F10 SCK1 t KL9, 10 t R10 t SBD t SBW t KCY9, 10 STB Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 55 µPD78P054 PD78P054, 78P058 78P058 Automatic transmit/receive function 3-wire serial I/O mode (busy processing): 7 SCK1 9Note 8 10+n Note 10Note t BYS t BYH 1 t SPS BUSY (Active high) Note The signal is not actually driven low here; It is shown as such to indicate the timing. UART mode (external clock input): tKCY13 tKH13 tKL13 t R13 ASCK 56 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 t F13 µPD78P054 PD78P054, 78P058 78P058 A/D Converter Characteristics (TA = ­40 to +85°C, AVDD = VDD = 2.7 to 6.0 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 8 8 8 bit µPD78P054 PD78P054 1.0 % µPD78P058 PD78P058 1.4 % 200 µs Resolution Overall 2.7 V AVREF0 AVDD errorNote Conversion time tCONV 19.1 Sampling time tSAMP 12/fXX Analog input voltage VIAN AVSS AVREF0 AVDD Reference voltage AVREF0 2.7 Resistance between AVREF0 and AVSS RAIREF0 µs 4 V V k Note Excludes quantization error (±1/2LSB). Shown as a percentage of the full scale value. Remark fXX: Main system clock frequency (fX or fX/2) fX: Main system clock oscillation frequency D/A Converter Characteristics (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V, AVSS = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Resolution 8 R=2 1.2 % R=4 MNote 1 0.8 % 0.6 % 4.5 V AVREF1 6.0 V 10 µs 2.7 V AVREF1 < 4.5 V 15 µs 2.0 V AVREF1 < 2.7 V Overall error bit MNote 1 20 µs R = 10 MNote 1 Settling time Output resistance C = 30 pFNote 1 RO0 DACS0 = 55H 10 k RO1 DACS1 = 55H 10 k Analog reference voltage AVREF1 AVREF1 current AIREF1 Note 2 2.0 VDD V 1.5 mA Notes 1. R and C are the load resistance and load capacitance of the D/A converter output pin. 2. Value for one D/A converter channel. Remark DACS0, DACS1: D/A conversion value setting register 0, 1 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 57 µPD78P054 PD78P054, 78P058 78P058 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = ­40 to +85°C) Parameter Symbol Data retention supply voltage Data retention supply current IDDDR Release signal set time Conditions MIN. VDDDR tSREL TYP. VDDDR = 1.8 V Subsystem clock unused (XT1 = VDD), feedback resistor disconnected 0.1 MAX. Unit 6.0 1.8 V 10 µA µs 0 tWAIT Release by RESET ms Release by interrupt request Oscillation stabilization wait time 217/fX Note ms Note Selection of 212/fXX, or 214/fXX through 217/fXX is possible using bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS). Remark fXX: Main system clock frequency (fX or fX/2) fX: Main system clock oscillation frequency Data Retention Timing (STOP mode release by RESET) Internal reset operation HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution RESET tWAIT Data Retention Timing (Standby release signal: STOP mode release by interrupt request signal) HALT mode Operating mode STOP mode Data retention mode VDD VDDDR tSREL STOP instruction execution Standby release signal (Interrupt request) tWAIT 58 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 Interrupt Request Input Timing t INTL t INTH INTP0 to INTP6 RESET Input Timing t RSL RESET Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 59 µPD78P054 PD78P054, 78P058 78P058 PROM Programming Characteristics DC Characteristics (1) PROM write mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V) Symbol SymbolNote MAX. Unit Input voltage, high VIH VIH 0.7VDD VDD V Input voltage, low VIL VIL 0 0.3VDD V Output voltage, high VOH VOH IOH = ­1 mA Output voltage, low VOL VOL IOL = 1.6 mA ILI ILI 0 VIN VDD VPP supply voltage VPP VPP VDD supply voltage VDD VCC VPP supply current IPP IPP VDD supply current IDD ICC Parameter Input leakage current Conditions MIN. TYP. VDD ­ 1.0 V 0.4 V +10 ­10 µA V 12.2 12.5 12.8 6.25 6.5 6.75 V 50 mA 50 mA MAX. Unit 0.7VDD VDD V 0 0.3VDD V PGM = VIL (2) PROM read mode (TA = 25 ±5°C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V) Parameter Input voltage, high Input voltage, low Symbol SymbolNote VIH VIH Conditions MIN. TYP. Output voltage, low VIL VIL VOH1 VOH1 IOH = ­1 mA VDD ­ 1.0 V VOH2 Output voltage, high VOH2 IOH = ­100 µA VDD ­ 0.5 V VOL VOL IOL = 1.6 mA 0.4 V Input leakage current ILI ILI 0 VIN VDD ­10 +10 µA Output leakage current ILO ILO 0 VOUT VDD, OE = VIH ­10 +10 µA VPP supply voltage VPP VPP VDD + 0.6 V VDD supply voltage VDD VCC VPP supply current IPP IPP VDD supply current IDD ICCA1 VDD ­ 0.6 4.5 5.0 5.5 V VPP = VDD 100 µA CE = VIL, VIN = VIH 50 mA Note Corresponding symbols for the µPD27C1001A PD27C1001A. 60 VDD Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 AC Characteristics (1) PROM write mode (a) Page program mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V) Parameter Symbol SymbolNote Conditions MIN. TYP. MAX. Unit Address setup time (to OE) tAS tAS 2 µs OE set time tOES tOES 2 µs CE setup time (to OE) tCES tCES 2 µs Input data setup time (to OE) tDS tDS 2 µs Address hold time (from OE) tAH tAH 2 µs tAHL tAHL 2 µs tAHV tAHV 0 µs Input data hold time (from OE) tDH tDH 2 µs Data output float delay time from OE tDF tDF 0 250 ns VPP setup time (to OE) tVPS tVPS 1.0 ms VDD setup time (to OE) tVDS tVCS 1.0 ms Program pulse width tPW tPW 0.095 Valid data delay time from OE tOE tOE 0.1 0.105 ms 1 µs tLW tLW 1 µs PGM set time tPGMS tPGMS 2 µs CE hold time tCEH tCEH 2 µs OE hold time tOEH tOEH 2 µs OE pulse width during data latching (b) Byte program mode (TA = 25 ±5°C, VDD = 6.5 ±0.25 V, VPP = 12.5 ±0.3 V) Parameter Symbol SymbolNote Conditions MIN. TYP. MAX. Unit Address setup time (to PGM) tAS tAS 2 µs OE set time tOES tOES 2 µs CE setup time (to PGM) tCES tCES 2 µs Input data setup time (to PGM) tDS tDS 2 µs Address hold time (from OE) tAH tAH 2 µs Input data hold time (from PGM) tDH tDH 2 µs Data output float delay time from OE tDF tDF 0 250 ns VPP setup time (to PGM) tVPS tVPS 1.0 ms VDD setup time (to PGM) tVDS tVCS 1.0 ms Program pulse width tPW tPW 0.095 Valid data delay time from OE tOE tOE OE hold time tOEH - 0.105 ms 1 2 0.1 µs µs Note Corresponding symbols for the µPD27C1001A PD27C1001A. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 61 µPD78P054 PD78P054, 78P058 78P058 (2) PROM read mode (TA = 25 ±5°C, VDD = 5.0 ±0.5 V, VPP = VDD ±0.6 V) Parameter Symbol SymbolNote MAX. Unit Data output delay time from address tACC tACC CE = OE = VIL 800 ns Data output delay time from CE tCE tCE OE = VIL 800 ns Data output delay time from OE tOE tOE CE = VIL 200 ns 60 ns Conditions MIN. Data output float delay time from OE tDF tDF CE = VIL 0 Data hold time from address tOH tOH CE = OE = VIL TYP. 0 ns Note Corresponding symbols for the µPD27C1001A PD27C1001A. (3) PROM programming mode setting (TA = 25°C, VSS = 0 V) Parameter Symbol PROM programming mode setup time tSMA 62 Conditions MIN. 10 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 TYP. MAX. Unit µs µPD78P054 PD78P054, 78P058 78P058 PROM Write Mode Timing (Page program mode) Page data latch Program verify Page program A2 to A16 tAS tAHL tAHV tDS tDH tDF A0, A1 D0 to D7 Hi-Z Hi-Z Data input tVPS Hi-Z tPGMS tOE Data output tAH VPP VPP VDD tVDS VDD + 1.5 VDD VDD tCES tOEH VIH CE VIL tCEH tPW VIH PGM VIL tLW tOES VIH OE VIL Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 63 µPD78P054 PD78P054, 78P058 78P058 PROM Write Mode Timing (Byte program mode) Program Program Verify A0 to A16 tAS D0 to D7 Hi-Z tDF Hi-Z Page Data input Data Latch tDS Hi-Z Data output tDH tAH VPP VPP VDD tVPS VDD + 1.5 VDD VDD tVDS tOEH VIH CE VIL tCES tPW VIH PGM VIL tOES tOE VIH CE VIL Cautions 1. V DD should be applied before VPP and removed after VPP. 2. VPP must not exceed +13.5 V including overshoot. 3. Reliability may be adversely affected if removal/reinsertion is performed while +12.5 V is being applied to VPP. PROM Read Mode Timing Effective address A0 to A16 VIH CE VIL tCE VIH OE VIL tACC D0 to D7 Note 1 Hi-Z tOE tDF Note 2 Note 1 tOH Data output Hi-Z Notes 1. To read within the tACC range, make the delay time from the OE input to the fall of CE a maximum of tACC ­ tOE. 2. tDF is the time from when either OE or CE first reaches VIH. 64 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 PROM Programming Mode Setting Timing VDD VDD 0 RESET VDD VPP 0 tSMA A0 to A16 Effective address Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 65 µPD78P054 PD78P054, 78P058 78P058 10. CHARACTERISTICS CURVES (FOR REFERENCE ONLY) (1) Characteristics curves of µPD78P054 PD78P054 (1/2) IDD vs VDD (fX = 5.0 MHz, fXX = 2.5 MHz) (TA = 25°C) 10.0 PCC = 00H 5.0 PCC = 01H PCC = 02H PCC = 03H PCC = 04H PCC = 30H HALT (X1 oscillation, XT1 oscillation) 1.0 Supply current IDD [mA] 0.5 PCC = B0H 0.1 0.05 HALT (X1 stop, XT1 oscillation) 0.01 0.005 0.001 0 2 3 4 5 Supply voltage VDD [V] 66 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 6 7 8 µPD78P054 PD78P054, 78P058 78P058 (1) Characteristics curves of µPD78P054 PD78P054 (2/2) IDD vs VDD (fX = fXX = 5.0 MHz) (TA = 25°C) 10.0 PCC = 00H PCC = 01H 5.0 PCC = 02H PCC = 03H PCC = 04H PCC = 30H HALT (X1 oscillation, XT1 oscillation) 1.0 Supply current IDD [mA] 0.5 PCC = B0H 0.1 0.05 HALT (X1 stop, XT1 oscillation) 0.01 0.005 0.001 0 2 3 4 5 6 7 8 Supply voltage VDD [V] Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 67 µPD78P054 PD78P054, 78P058 78P058 (2) Characteristics curves of µPD78P058 PD78P058 (1/2) IDD vs VDD (fX = 5.0 MHz, fXX = 2.5 MHz) (TA = 25°C) 10.0 PCC = 00H 5.0 PCC = 01H PCC = 02H PCC = 03H PCC = 04H PCC = 30H HALT (X1 oscillation, XT1 oscillation) 1.0 Supply current IDD [mA] 0.5 PCC = B0H 0.1 0.05 HALT (X1 stop, XT1 oscillation) 0.01 0.005 0.001 0 2 3 4 5 Supply voltage VDD [V] 68 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 6 7 8 µPD78P054 PD78P054, 78P058 78P058 (2) Characteristics curves of µPD78P058 PD78P058 (2/2) IDD vs VDD (fX = fXX = 5.0 MHz) (TA = 25°C) 10.0 PCC = 00H PCC = 01H 5.0 PCC = 02H PCC = 03H PCC = 04H PCC = 30H HALT (X1 oscillation, XT1 oscillation) 1.0 Supply current IDD [mA] 0.5 PCC = B0H 0.1 0.05 HALT (X1 stop, XT1 oscillation) 0.01 0.005 0.001 0 2 3 4 5 6 7 8 Supply voltage VDD [V] Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 69 µPD78P054 PD78P054, 78P058 78P058 11. PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14×14) A B 60 61 41 40 detail of lead end C S D R Q 80 1 21 20 F G H I M J P K M N NOTE L ITEM MILLIMETERS INCHES A 17.20±0.20 0.677±0.008 B 14.00±0.20 0.551 +0.009 ­0.008 C 14.00±0.20 0.551 +0.009 ­0.008 D Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. 17.20±0.20 0.677±0.008 F 0.825 0.032 G 0.825 0.032 H 0.32±0.06 0.013 +0.002 ­0.003 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.60±0.20 0.063±0.008 L 0.80±0.20 0.031 +0.009 ­0.008 M 0.17 +0.03 ­0.07 0.007 +0.001 ­0.003 N 0.10 0.004 P 1.40±0.10 0.055±0.004 Q 0.125±0.075 0.005±0.003 R 3° +7° ­3° 3° +7° ­3° S 1.70 MAX. 0.067 MAX. P80GC-65-8BT P80GC-65-8BT Remark The dimensions and materials of ES products are the same as those of mass-production products. 70 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 80 PIN PLASTIC TQFP (FINE PITCH) (12x12) A B 60 41 61 40 detail of lead end S C D Q R 21 80 1 20 F G H I J M K P M N S L NOTE S ITEM Each lead centerline is located within 0.10 mm of its true position (T.P.) at maximum material condition. MILLIMETERS A 14.00±0.20 B 12.00±0.20 C 12.00±0.20 D F 14.00±0.20 1.25 G 1.25 H 0.22 +0.05 ­0.04 I 0.10 J 0.50 (T.P.) K 1.00±0.20 L 0.50±0.20 M 0.145 +0.055 ­0.045 N 0.10 P 1.05±0.07 Q 0.10±0.05 R 5°±5° S 1.27 MAX. P80GK-50-BE9-6 P80GK-50-BE9-6 Remark The dimensions and materials of ES products are the same as those of mass-production products. Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 71 µPD78P054 PD78P054, 78P058 78P058 80 PIN CERAMIC WQFN A Q K B D 80 S W C U1 T H U 1 I M R G F J Z X80KW-65A-1 X80KW-65A-1 NOTE Each lead centerline is located within 0.06 mm (0.003 inch) of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS INCHES A 14.0 ± 0.2 0.551 ± 0.008 B 13.6 0.535 C 13.6 0.535 D 0.551 ± 0.008 1.84 0.072 G 3.6 MAX. 0.142 MAX. H 0.45 ± 0.10 0.018+0.004 ­0.005 I 0.06 0.003 J 0.65 (T.P.) 0.024 (T.P.) K 1.0 ± 0.15 0.039+0.007 ­0.006 Q C 0.3 C 0.012 R 0.825 0.032 S 0.825 0.032 T R 2.0 R 0.079 U 9.0 0.354 U1 2.1 0.083 W 0.75 ± 0.15 0.030+0.006 ­0.007 Z 72 14.0 ± 0.2 F 0.10 0.004 Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 12. RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E C10535E). For soldering methods and conditions other than those recommended below, please contact your NEC sales representative. Table 12-1. Surface Mount Type Soldering Conditions (1/2) (1) µPD78P054GC-8BT PD78P054GC-8BT : 80-pin plastic QFP (14 × 14 mm, resin thickness: 1.4 mm) µPD78P058GC-8BT PD78P058GC-8BT : 80-pin plastic QFP (14 × 14 mm, resin thickness: 1.4 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: 2 times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) IR35-107-2 IR35-107-2 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: 2 times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) VP15-107-2 VP15-107-2 Wave soldering Solder bath temperature: 260°C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120°C max. (package surface temperature), Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) WS60-107-1 WS60-107-1 Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering methods together (except for partial heating). Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 73 µPD78P054 PD78P054, 78P058 78P058 Table 12-1. Surface Mount Type Soldering Conditions (2/2) (2) µPD78P054GK-BE9 PD78P054GK-BE9 : 80-pin plastic TQFP (fine pitch) (12 × 12 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235°C, Time: 30 seconds max. (at 210°C or higher), Count: 3 times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) IR35-107-3 IR35-107-3 VPS Package peak temperature: 215°C, Time: 40 seconds max. (at 200°C or higher), Count: 3 times or less, Exposure limit: 7 daysNote (after that, prebake at 125°C for 10 hours) VP15-107-3 VP15-107-3 Partial heating Pin temperature: 300°C max., Time: 3 seconds max. (per pin row) - Note After opening the dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period. Caution 74 Do not use different soldering methods together (except for partial heating). Data Sheet U10417EJ3V0DS00 U10417EJ3V0DS00 µPD78P054 PD78P054, 78P058 78P058 APPENDIX A. DEVELOPMENT TOOLS The following support tools are available for system development using the µPD78P054 PD78P054 and 78P058 78P058. Refer to (5) Cautions on Using Development Tools. (1) Language Processing Software RA78K/0 RA78K/0 Assembler package common to 78K/0 78K/0 Series CC78K/0 CC78K/0 C compiler package common to 78K/0 78K/0 Series DF78054 DF78054 µPD78054 PD78054 Subseries device file CC78K/0-L CC78K/0-L C compiler library source file common to 78K/0 78K/0 Series (2) PROM Writing Tools PG-1500 PG-1500 PROM programmer PA-78P054GC PA-78P054GC PA-78P054GK PA-78P054GK PA-78P054KK-T PA-78P054KK-T Programmer adapter connected to a PG-1500 PG-1500 PG-1500 PG-1500 controller PG-1500 PG-1500 control program (3) Debugging Tools · When using in-circuit emulator IE-78K0-NS IE-78K0-NS IE-78K0-NS IE-78K0-NS In-circuit emul