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78K0/KB1 PD78F0101H PD78F0102H PD78F0103H U16846EJ1V0UD00 U16846EJ1V0UD HP9000 - Datasheet Archive
78K0/KB1+ 8-Bit Single-Chip Microcontrollers µPD78F0101H µPD78F0102H µPD78F0103H Document No. U16846EJ1V0UD00
Preliminary User's Manual 78K0/KB1 78K0/KB1+ 8-Bit Single-Chip Microcontrollers µPD78F0101H PD78F0101H µPD78F0102H PD78F0102H µPD78F0103H PD78F0103H Document No. U16846EJ1V0UD00 U16846EJ1V0UD00 (1st edition) Date Published November 2003 N CP(K) 2003 Printed in Japan [MEMO] 2 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. SuperFlash® is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 3 Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, inc. · The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the product prior to its production. · Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. · No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. · NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. · Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. · While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. · NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics products depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M5D 02. 11-1 4 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: · Device availability · Ordering information · Product release schedule · Availability of related technical literature · Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) · Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) NEC Electronics (Europe) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Duesseldorf, Germany Tel: 0211-65 03 01 Hong Kong Tel: 2886-9318 · Sucursal en España Madrid, Spain Tel: 091-504 27 87 · Succursale Française Vélizy-Villacoublay, France Tel: 01-30-67 58 00 · Filiale Italiana Milano, Italy Tel: 02-66 75 41 · Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 · Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai, Ltd. Shanghai, P.R. China Tel: 021-6841-1138 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 · United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J03.4 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 5 INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/KB1 78K0/KB1+ and design and develop application systems and programs for these devices. The target products are as follows. 78K0/KB1 78K0/KB1+: µPD78F0101H PD78F0101H, 78F0102H 78F0102H, 78F0103H 78F0103H Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization The 78K0/KB1 78K0/KB1+ manual is separated into two parts: this manual and the instructions edition (common to the 78K/0 78K/0 Series). 78K0/KB1 78K0/KB1+ 78K/0 78K/0 Series User's Manual User's Manual (This Manual) Instructions · Pin functions · CPU functions · Internal block functions · Instruction set · Interrupts · Explanation of each instruction · Other on-chip peripheral functions · Electrical specifications (target) How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. · To gain a general understanding of functions: Read this manual in the order of the CONTENTS. · How to interpret the register format: For a bit number enclosed in brackets, the bit name is defined as a reserved word in the assembler, and is already defined in the header file named sfrbit.h in the C compiler. · To check the details of a register when you know the register name: Refer to APPENDIX C REGISTER INDEX. · To know details of the 78K/0 78K/0 Series instructions: Refer to the separate document 78K/0 78K/0 Series Instructions User's Manual (U12326E U12326E). 6 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: ××× (overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information . ×××× or ××××B Numerical representations: Binary Decimal . ×××× Hexadecimal . ××××H Differences Between 78K0/KB1 78K0/KB1+ and 78K0/KB1 78K0/KB1 Series Name 78K0/KB1 78K0/KB1+ 78K0/KB1 78K0/KB1 Item Mask ROM version None Available Flash Power supply Single power supply Two power supplies memory Self-programming function Available None Option byte Ring-OSC can be stopped/cannot be None version stopped selectable Power-on clear function 2.1 V ±0.1 V (fixed) 2.85 V ±0.15 V or 3.5 V ±0.2 V selectable Minimum instruction execution time 0.125 µs (at 16 MHz operation) 0.2 µs (at 10 MHz operation) Note Note This value may change after evaluation. Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0/KB1 78K0/KB1+ User's Manual This manual 78K0/KB1 78K0/KB1 User's Manual U15836E U15836E 78K/0 78K/0 Series Instructions User's Manual U12326E U12326E Documents Related to Development Tools (Software) (User's Manuals) Document Name RA78K0 RA78K0 Assembler Package Document No. Operation U14445E U14445E Language U14446E U14446E Structured Assembly Language U11789E U11789E Operation CC78K0 CC78K0 C Compiler U14297E U14297E Language SM78K SM78K Series System Simulator Ver. 2.30 or Later U14298E U14298E TM Operation (Windows Based) External Part User Open Interface U15373E U15373E U15802E U15802E Specifications ID78K ID78K Series Integrated Debugger Ver. 2.30 or Later Operation (Windows Based) Project Manager Ver. 3.12 or Later (Windows Based) U15185E U15185E U14610E U14610E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 7 Documents Related to Development Tools (Hardware) (User's Manuals) Document Name Document No. IE-78K0-NS IE-78K0-NS In-Circuit Emulator U13731E U13731E IE-78K0-NS-A IE-78K0-NS-A In-Circuit Emulator U14889E U14889E Documents Related to Flash Memory Programming Document Name PG-FP4 Flash Memory Programmer User's Manual Document No. U15260E U15260E Other Documents Document Name Document No. SEMICONDUCTOR SELECTION GUIDE - Products and Packages - X13769X X13769X Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. 8 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CONTENTS CHAPTER 1 OUTLINE . 15 1.1 Features . 15 1.2 Applications. 16 1.3 Ordering Information . 16 1.4 Pin Configuration (Top View). 17 1.5 K1 Family Lineup . 18 1.5.1 1.5.2 1.6 1.7 78K0/Kx1, 78K0/Kx1+ product lineup .18 V850ES/Kx1, V850ES/Kx1+ product lineup .21 Block Diagram . 24 Outline of Functions . 25 CHAPTER 2 PIN FUNCTIONS . 27 2.1 Pin Function List . 27 2.2 Description of Pin Functions . 29 2.2.1 P00 to P03 (port 0).29 2.2.2 P10 to P17 (port 1).29 2.2.3 P20 to P23 (port 2).30 2.2.4 P30 to P33 (port 3).30 2.2.5 P120 (port 12) .30 2.2.6 P130 (port 13) .31 2.2.7 AVREF .31 2.2.8 AVSS .31 2.2.9 RESET .31 2.2.10 X1 and X2 .31 2.2.11 CL1 and CL2 .31 2.2.12 VDD .31 2.2.13 VSS .31 2.2.14 FLMD0 and FLMD1.31 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins. 32 CHAPTER 3 CPU ARCHITECTURE. 34 3.1 Memory Space. 34 3.1.1 Internal program memory space .38 3.1.2 Special function register (SFR) area .39 3.1.4 3.2 Internal data memory space.39 3.1.3 Data memory addressing .40 Processor Registers . 43 3.2.1 General-purpose registers .47 3.2.3 3.3 Control registers.43 3.2.2 Special Function Registers (SFRs) .48 Instruction Address Addressing . 52 3.3.1 Relative addressing.52 3.3.2 Immediate addressing.53 3.3.3 Table indirect addressing .54 3.3.4 Register addressing .54 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 9 3.4 Operand Address Addressing . 55 3.4.1 Implied addressing . 55 3.4.2 Register addressing . 56 3.4.3 Direct addressing . 57 3.4.4 Short direct addressing . 58 3.4.5 Special function register (SFR) addressing . 59 3.4.6 Register indirect addressing . 60 3.4.7 Based addressing. 61 3.4.8 Based indexed addressing . 62 3.4.9 Stack addressing. 63 CHAPTER 4 PORT FUNCTIONS . 64 4.1 Port Functions . 64 4.2 Port Configuration. 65 4.2.1 Port 1. 69 4.2.3 Port 2. 74 4.2.4 Port 3. 75 4.2.5 Port 12. 76 4.2.6 4.3 4.4 Port 0. 66 4.2.2 Port 13. 77 Registers Controlling Port Function . 77 Port Function Operations . 81 4.4.1 Writing to I/O port . 81 4.4.2 Reading from I/O port. 81 4.4.3 Operations on I/O port. 81 CHAPTER 5 CLOCK GENERATOR . 82 5.1 Functions of Clock Generator. 82 5.2 Configuration of Clock Generator . 82 5.3 Registers Controlling Clock Generator. 84 5.4 System Clock Oscillator . 91 5.4.1 5.4.2 Ring-OSC oscillator. 95 5.4.3 5.5 5.6 5.7 5.8 High-speed system clock oscillator . 91 Prescaler . 95 Clock Generator Operation . 95 Time Required to Switch Between Ring-OSC Clock and High-Speed System Clock . 100 Time Required for CPU Clock Switchover. 100 Clock Switching Flowchart and Register Setting . 101 5.8.1 Switching from Ring-OSC clock to high-speed system clock .101 5.8.2 Switching from high-speed system clock to Ring-OSC clock .102 5.8.3 Register settings.103 CHAPTER 6 16-BIT 16-BIT TIMER/EVENT COUNTER 00 . 104 6.1 Functions of 16-Bit Timer/Event Counter 00 . 104 6.2 Configuration of 16-Bit Timer/Event Counter 00. 105 6.3 Registers Controlling 16-Bit Timer/Event Counter 00 . 109 6.4 Operation of 16-Bit Timer/Event Counter 00 . 115 6.4.1 10 Interval timer operation.115 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 6.4.2 PPG output operations.118 6.4.3 Pulse width measurement operations .121 6.4.4 Square-wave output operation .132 6.4.6 6.5 External event counter operation .129 6.4.5 One-shot pulse output operation .134 Cautions for 16-Bit Timer/Event Counter 00 . 139 CHAPTER 7 8-BIT TIMER/EVENT COUNTER 50. 142 7.1 Functions of 8-Bit Timer/Event Counter 50. 142 7.2 Configuration of 8-Bit Timer/Event Counter 50 . 143 7.3 Registers Controlling 8-Bit Timer/Event Counter 50. 145 7.4 Operations of 8-Bit Timer/Event Counter 50 . 148 7.4.1 Operation as external event counter .150 7.4.3 Operation as square-wave output .151 7.4.4 7.5 Operation as interval timer .148 7.4.2 Operation as PWM output .152 Cautions for 8-Bit Timer/Event Counter 50 . 154 CHAPTER 8 8-BIT TIMERS H0 AND H1 . 155 8.1 Functions of 8-Bit Timers H0 and H1 . 155 8.2 Configuration of 8-Bit Timers H0 and H1 . 155 8.3 Registers Controlling 8-Bit Timers H0 and H1. 159 8.4 Operation of 8-Bit Timers H0 and H1 . 163 8.4.1 Operation as interval timer/square-wave output.163 8.4.2 Operation as PWM output mode .166 CHAPTER 9 WATCHDOG TIMER . 172 9.1 Functions of Watchdog Timer . 172 9.2 Configuration of Watchdog Timer. 174 9.3 Registers Controlling Watchdog Timer . 174 9.4 Operation of Watchdog Timer . 177 9.4.1 Watchdog timer operation when "Ring-OSC cannot be stopped" is selected by option byte .177 9.4.2 Watchdog timer operation when "Ring-OSC can be stopped by software" is selected by option byte .178 9.4.3 Watchdog timer operation in STOP mode (when "Ring-OSC can be stopped by software" is selected by option byte).179 9.4.4 Watchdog timer operation in HALT mode (when "Ring-OSC can be stopped by software" is selected by option byte).181 CHAPTER 10 A/D CONVERTER . 182 10.1 Function of A/D Converter . 182 10.2 Configuration of A/D Converter. 183 10.3 Registers Used in A/D Converter . 185 10.4 A/D Converter Operations. 189 10.4.1 Basic operations of A/D converter.189 10.4.2 Input voltage and conversion results.191 10.4.3 A/D converter operation mode .192 10.5 How to Read A/D Converter Characteristics Table . 195 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 11 10.6 Cautions for A/D Converter. 197 CHAPTER 11 SERIAL INTERFACE UART0 (µPD78F0102H PD78F0102H AND 78F0103H 78F0103H ONLY) . 202 11.1 Functions of Serial Interface UART0. 202 11.2 Configuration of Serial Interface UART0 . 203 11.3 Registers Controlling Serial Interface UART0. 206 11.4 Operation of Serial Interface UART0 . 211 11.4.1 Operation stop mode.211 11.4.2 Asynchronous serial interface (UART) mode .212 11.4.3 Dedicated baud rate generator.218 CHAPTER 12 SERIAL INTERFACE UART6 . 223 12.1 Functions of Serial Interface UART6. 223 12.2 Configuration of Serial Interface UART6 . 227 12.3 Registers Controlling Serial Interface UART6. 230 12.4 Operation of Serial Interface UART6 . 240 12.4.1 Operation stop mode.240 12.4.2 Asynchronous serial interface (UART) mode .241 12.4.3 Dedicated baud rate generator.256 CHAPTER 13 SERIAL INTERFACE CSI10 CSI10 . 263 13.1 Functions of Serial Interface CSI10 CSI10. 263 13.2 Configuration of Serial Interface CSI10 CSI10 . 263 13.3 Registers Controlling Serial Interface CSI10 CSI10. 265 13.4 Operation of Serial Interface CSI10 CSI10 . 268 13.4.1 Operation stop mode.268 13.4.2 3-wire serial I/O mode .269 CHAPTER 14 INTERRUPT FUNCTIONS . 277 14.1 Interrupt Function Types . 277 14.2 Interrupt Sources and Configuration . 277 14.3 Registers Controlling Interrupt Function. 280 14.4 Interrupt Servicing Operations . 286 14.4.1 Maskable interrupt request acknowledgment .286 14.4.2 Software interrupt request acknowledgment .288 14.4.3 Multiple interrupt servicing.289 14.4.4 Interrupt request hold .292 CHAPTER 15 STANDBY FUNCTION . 293 15.1 Standby Function and Configuration. 293 15.1.1 Standby function.293 15.1.2 Registers controlling standby function.295 15.2 Standby Function Operation. 297 15.2.1 HALT mode .297 15.2.2 STOP mode.300 CHAPTER 16 RESET FUNCTION. 304 16.1 Register for Confirming Reset Source. 310 12 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CHAPTER 17 CLOCK MONITOR . 311 17.1 Functions of Clock Monitor . 311 17.2 Configuration of Clock Monitor . 311 17.3 Register Controlling Clock Monitor . 312 17.4 Operation of Clock Monitor. 313 CHAPTER 18 POWER-ON-CLEAR CIRCUIT . 318 18.1 Functions of Power-on-Clear Circuit . 318 18.2 Configuration of Power-on-Clear Circuit. 319 18.3 Operation of Power-on-Clear Circuit . 319 18.4 Cautions for Power-on-Clear Circuit. 320 CHAPTER 19 LOW-VOLTAGE DETECTOR . 322 19.1 Functions of Low-Voltage Detector . 322 19.2 Configuration of Low-Voltage Detector. 322 19.3 Registers Controlling Low-Voltage Detector . 323 19.4 Operation of Low-Voltage Detector. 325 19.5 Cautions for Low-Voltage Detector. 329 CHAPTER 20 OPTION BYTE. 332 CHAPTER 21 FLASH MEMORY. 333 21.1 Internal Memory Size Switching Register . 334 21.2 Writing with Flash Programmer. 335 21.3 Programming Environment. 339 21.4 Communication Mode . 339 21.5 Handling of Pins on Board. 342 21.5.1 FLMD0 pin .342 21.5.2 FLMD1 pin .342 21.5.3 Serial interface pins.343 21.5.4 RESET pin .345 21.5.5 Port pins.345 21.5.6 Other signal pins .345 21.5.7 Power supply.345 21.6 Programming Method. 346 21.6.1 Controlling flash memory .346 21.6.2 Flash memory programming mode .346 21.6.3 Selecting communication mode .347 21.6.4 Communication commands.348 21.7 Flash Memory Programming by Self-Writing. 349 21.7.1 Registers used for self-programming function.350 21.8 Boot Swap Function . 354 21.8.1 Outline of boot swap function .354 21.8.2 Memory map and boot area .355 CHAPTER 22 INSTRUCTION SET . 358 22.1 Conventions Used in Operation List. 358 22.1.1 Operand identifiers and specification methods .358 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 13 22.1.2 Description of operation column .359 22.1.3 Description of flag operation column .359 22.2 Operation List . 360 22.3 Instructions Listed by Addressing Type. 368 CHAPTER 23 ELECTRICAL SPECIFICATIONS (TARGET). 371 CHAPTER 24 PACKAGE DRAWING. 384 CHAPTER 25 CAUTIONS FOR WAIT. 385 25.1 Cautions for Wait. 385 25.2 Peripheral Hardware That Generates Wait . 386 25.3 Example of Wait Occurrence . 387 APPENDIX A DEVELOPMENT TOOLS. 388 A.1 Software Package. 392 A.2 Language Processing Software. 393 A.3 Control Software . 394 A.4 Flash Memory Writing Tools . 394 A.5 Debugging Tools (Hardware) . 395 A.5.1 When using in-circuit emulators IE-78K0-NS IE-78K0-NS and IE-78K0-NS-A IE-78K0-NS-A.395 A.5.2 When using in-circuit emulator IE-78K0K1-ET IE-78K0K1-ET .396 A.5.3 When using in-circuit emulator IECUBE for 78K0/Kx1+ (name pending) .396 A.6 Debugging Tools (Software) . 397 APPENDIX B NOTES ON TARGET SYSTEM DESIGN . 398 APPENDIX C REGISTER INDEX . 400 C.1 Register Index (In Alphabetical Order with Respect to Register Names) . 400 C.2 Register Index (In Alphabetical Order with Respect to Register Symbol) . 403 14 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CHAPTER 1 OUTLINE 1.1 Features Minimum instruction execution time can be changed from high speed (0.125 µs: @ 16 MHz operation with highspeed system clock) to low-speed (2.0 µs: @ 16 MHz operation with high-speed system clock) General-purpose register: 8 bits × 32 registers (8 bits × 8 registers × 4 banks) ROM, RAM capacities Program Memory Data Memory (ROM) Part Number (Internal High-Speed RAM) Item µPD78F0101H PD78F0101H Flash memory 8 KB Note µPD78F0102H PD78F0102H 16 KB Note µPD78F0103H PD78F0103H 24 KB 512 bytes Note 768 bytes Note The internal flash memory and internal high-speed RAM capacities can be changed using the internal memory size switching register (IMS). On-chip single-power-supply flash memory Self-programming (with boot swap function) On-chip power-on-clear (POC) circuit and low-voltage detector (LVI) Short startup is possible via the CPU default start using the on-chip Ring-OSC On-chip clock monitor function using on-chip Ring-OSC On-chip watchdog timer (operable with Ring-OSC clock) I/O ports: 22 Timer: 5 channels Serial interface: 2 channels UART (LIN (Local Interconnect Network)-bus supported): 1 channel CSI1/UARTNote 1: 1 channel (µPD78F0101H PD78F0101H only, CSI1: 1 channel) 10-bit resolution A/D converter: 4 channels Supply voltage: VDD = 2.7 to 5.5 V (with Ring-OSC clock: VDD = 2.0 to 5.5 VNote 2) Operating ambient temperature: TA = -40 to +85°C Notes 1. 2. Select either of the functions of these alternate-function pins. Use the product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-on-clear (POC) circuit is 2.1 V ±0.1 V. Caution The operating voltage range may be changed after evaluation of the device. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 15 CHAPTER 1 OUTLINE 1.2 Applications Automotive equipment · System control for body electricals (power windows, keyless entry reception, etc.) · Sub-microcontrollers for control Home audio, car audio AV equipment PC peripheral equipment (keyboards, etc.) Household electrical appliances · Outdoor air conditioner units · Microwave ovens, electric rice cookers Industrial equipment · Pumps · Vending machines · FA (Factory Automation) 1.3 Ordering Information · Flash memory version Part Number Package µPD78F0101HMC-5A4 PD78F0101HMC-5A4 µPD78F0102HMC-5A4 PD78F0102HMC-5A4 µPD78F0103HMC-5A4 PD78F0103HMC-5A4 30-pin plastic SSOP (7.62 mm (300) 16 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 30-pin plastic SSOP (7.62 mm (300) 30-pin plastic SSOP (7.62 mm (300) CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) · 30-pin plastic SSOP (7.62 mm (300) P33/INTP4 P33/INTP4 1 30 P120/INTP0 P120/INTP0 P32/INTP3 P32/INTP3 2 29 AVSS P31/INTP2 P31/INTP2 3 28 AVREF P30/INTP1 P30/INTP1 4 27 P20/ANI0 P20/ANI0 FLMD0 5 26 P21/ANI1 P21/ANI1 VSS 6 25 P22/ANI2 P22/ANI2 VDD 7 24 P23/ANI3 P23/ANI3 X1[CL1] 8 23 P130 X2[CL2] 9 22 P17/TI50/TO50/FLMD1 P17/TI50/TO50/FLMD1 RESET 10 21 P16/TOH1/INTP5 P16/TOH1/INTP5 P03 11 20 P15/TOH0 P15/TOH0 P02 12 19 P14/RxD6 P01/TI010/TO00 P01/TI010/TO00 13 18 P13/TxD6 P00/TI000 P00/TI000 14 17 P12/SO10 P12/SO10 P10/SCK10/TxD0Note 15 16 P11/SI10/RxD0Note Note TxD0 and RxD0 are available only in the µPD78F0102H PD78F0102H and 78F0103H 78F0103H. Caution Connect the AVSS pin to VSS. Remark Items in brackets are the pin names when external RC oscillation is used. Pin Identification ANI0 to ANI3: RESET: Analog input Note AVREF: Analog reference voltage RxD0 CL1, CL2: RC oscillator SCK10 SCK10: , RxD6: Reset Receive data Serial clock input/output FLMD0, FLMD1: Flash programming mode SI10: Serial data input INTP0 to INTP5: External interrupt input SO10: Serial data output P00 to P03: Port 0 TI000 TI000, TI010 TI010, TI50: Timer input P10 to P17: Port 1 TO00, TO50, TOH0, TOH1: Timer output P20 to P23: Port 2 TxD0Note, TxD6: Transmit data P30 to P33: Port 3 VDD: Power supply P120: Port 12 VSS: Ground P130: Port 13 X1, X2: Crystal oscillator (High-speed system clock) Note TxD0 and RxD0 are available only in the µPD78F0102H PD78F0102H and 78F0103H 78F0103H. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 17 CHAPTER 1 OUTLINE 1.5 K1 Family Lineup 1.5.1 78K0/Kx1, 78K0/Kx1+ product lineup · 30-pin SSOP (7.62 mm 0.65 mm pitch) 78K0/KB1 78K0/KB1 78K0/KB1 78K0/KB1+ µ PD78F0103 PD78F0103 µ PD780103 PD780103 Mask ROM: 24 KB, RAM: 768 B Single-power-supply flash memory: 24 KB, RAM: 768 B µPD780102 PD780102 Mask ROM: 16 KB, RAM: 768 B Two-power-supply flash memory: 24 KB, RAM: 768 B µPD78F0102H PD78F0102H Single-power-supply flash memory: 16 KB, RAM: 768 B µPD780101 PD780101 Mask ROM: 8 KB, RAM: 512 B µPD78F0103H PD78F0103H µPD78F0101H PD78F0101H Single-power-supply flash memory: 8 KB, RAM: 512 B · 44-pin LQFP (10 × 10 mm 0.8 mm pitch) 78K0/KC1 78K0/KC1 78K0/KC1 78K0/KC1+ µPD780114 PD780114 Mask ROM: 32 KB, RAM: 1 KB µPD78F0114 PD78F0114 Two-power-supply flash memory: 32 KB, RAM: 1 KB µPD780113 PD780113 Mask ROM: 24 KB, RAM: 1 KB µPD780112 PD780112 Mask ROM: 16 KB, RAM: 512 B µPD78F0114H/HDNote Single-power-supply flash memory: 32 KB, RAM: 1 KB µPD78F0113H PD78F0113H Single-power-supply flash memory: 24 KB, RAM: 1 KB µ PD78F0112H PD78F0112H Single-power-supply flash memory: 16 KB, RAM: 512 B µ PD780111 PD780111 Mask ROM: 8 KB, RAM: 512 B · 52-pin LQFP (10 × 10 mm 0.65 mm pitch) 78K0/KD1 78K0/KD1 78K0/KD1 78K0/KD1+ µPD780124 PD780124 Mask ROM: 32 KB, RAM: 1 KB µPD78F0124 PD78F0124 Two-power-supply flash memory: 32 KB, RAM: 1 KB µPD780123 PD780123 Mask ROM: 24 KB, RAM: 1 KB µPD780122 PD780122 Mask ROM: 16 KB, RAM: 512 B µPD78F0124H/HDNote Single-power-supply flash memory: 32 KB, RAM: 1 KB µ PD78F0123H PD78F0123H Single-power-supply flash memory: 24 KB, RAM: 1 KB µ PD78F0122H PD78F0122H Single-power-supply flash memory: 16 KB, RAM: 512 B µ PD780121 PD780121 Mask ROM: 8 KB, RAM: 512 B · 64-pin LQFP, TQFP (10 × 10 mm 0.5 mm pitch, 12 × 12 mm 0.65 mm pitch, 14 × 14 mm 0.8 mm pitch) 78K0/KE1 78K0/KE1 78K0/KE1 78K0/KE1+ µPD780138 PD780138 µ PD78F0138 PD78F0138 µPD78F0138H/HDNote Mask ROM: 60 KB, RAM: 2 KB µPD78F0134 PD78F0134 Single-power-supply flash memory: 60 KB, RAM: 2 KB µPD780136 PD780136 Mask ROM: 48 KB, RAM: 2 KB Two-power-supply flash memory: 60 KB, RAM: 2 KB µPD78F0136H PD78F0136H Single-power-supply flash memory: 48 KB, RAM: 2 KB µPD780134 PD780134 µPD78F0134H PD78F0134H Mask ROM: 32 KB, RAM: 1 KB Single-power-supply flash memory: 32 KB, RAM: 1 KB µ PD780133 PD780133 Mask ROM: 24 KB, RAM: 1 KB Two-power-supply flash memory: 32 KB, RAM: 1 KB Single-power-supply flash memory: 24 KB, RAM: 1 KB µPD780132 PD780132 Mask ROM: 16 KB, RAM: 512 B µ PD78F0133H PD78F0133H µ PD78F0132H PD78F0132H Single-power-supply flash memory: 16 KB, RAM: 512 B µ PD780131 PD780131 Mask ROM: 8 KB, RAM: 512 B · 80-pin TQFP, QFP (12 × 12 mm 0.5 mm pitch, 14 × 14 mm 0.65 mm pitch) 78K0/KF1 78K0/KF1 78K0/KF1 78K0/KF1+ µ PD78F0148 PD78F0148 Two-power-supply flash memory: 60 KB, RAM: 2 KB µPD780148 PD780148 Mask ROM: 60 KB, RAM: 2 KB µPD78F0148H/HDNote Single-power-supply flash memory: 60 KB, RAM: 2 KB µ PD780146 PD780146 Mask ROM: 48 KB, RAM: 2 KB µPD780144 PD780144 Mask ROM: 32 KB, RAM: 1 KB µ PD780143 PD780143 Mask ROM: 24 KB, RAM: 1 KB Note Product with on-chip debug function 18 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1 is shown below. Part Number 78K0/KB1 78K0/KB1+ 78K0/KC1 78K0/KC1 78K0/KD1 78K0/KD1 78K0/KE1 78K0/KE1 78K0/KF1 78K0/KF1 Item Number of pins Internal memory (bytes) 30 pins Mask ROM - Flash memory RAM 44 pins 8 K 16 K/ - 24 K - 24 K 512 52 pins 8 K/ 24 K/ - 16 K 32 K 768 - 32 K 512 1K Clock 0.2 µs (when 10 MHz, VDD = 4.0 to 5.5 V) 0.24 µs (when 8.38 MHz, VDD = 3.3 to 5.5 V) 0.4 µs (when 5 MHz, VDD = 2.7 to 5.5 V) 1K - 2K 60 K 1K 2K 32.768 kHz 240 kHz (TYP.) CMOS I/O 17 4 19 26 38 54 8 CMOS output 1 - N-ch open-drain I/O 4 16 bits (TM0) 1 ch 8 bits (TM5) 2 ch 1 ch 2 ch 1 ch 2 ch 1 ch 2 ch 8 bits (TMH) 2 ch - For watch 1 ch WDT 1 ch Note Serial 3-wire CSI interface Automatic transmit/ receive 3-wire CSI Note UART 1 ch - - 1 ch 1 ch 10-bit A/D converter 4 ch External Internal Key return input 8 ch 6 11 7 12 8 9 15 - 16 9 19 4 ch 17 20 8 ch RESET pin Provided 2.85 V ±0.15 V/3.5 V ±0.20 V (selectable by option byte) POC LVI 2 ch 1 ch UART supporting LIN-bus Reset 1K - 60 K 2 to 10 MHz CMOS input Interrupt 512 - 32 K 24 K/ 48 K/ - 32 K 60 K 0.2 µs (when 10 MHz, VDD = 4.0 to 5.5 V) 0.24 µs (when 8.38 MHz, VDD = 3.3 to 5.5 V) 0.4 µs (when 5 MHz, VDD = 2.7 to 5.5 V) X1 input Subclock Timer - - VDD = 2.7 to 5.5 V Ring-OSC Port 80 pins 8 K/ 24 K/ - 48 K/ 16 K 32 K 60 K 32 K 512 Power supply voltage Minimum instruction execution time 64 pins 8 K/ 24 K/ - 16 K 32 K 3.1 V/3.3 V ±0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V (selectable by software) Clock monitor Provided WDT Provided Clock output/buzzer output Multiplier/divider ROM correction Standby function Operating ambient temperature - Clock output only Provided 16 bits × 16 bits, 32 bits ÷ 16 bits - - Provided - HALT/STOP mode Standard products, special (A) products: -40 to +85°C Special (A1) products: -40 to +110°C (mask ROM version), -40 to +105°C (flash memory version) Special (A2) products: -40 to +125°C (mask ROM version) Note Select either of the functions of these alternate-function pins. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 19 CHAPTER 1 OUTLINE The list of functions in the 78K0/Kx1+ is shown below. Part Number 78K0/KB1 78K0/KB1+ 78K0/KC1 78K0/KC1+ 78K0/KD1 78K0/KD1+ 78K0/KE1 78K0/KE1+ 78K0/KF1 78K0/KF1+ 30 pins 44 pins 52 pins 64 pins 80 pins Item Number of pins Internal memory (bytes) Flash memory 8 K 16 K/24 K 16 K 24 K/32 K 16 K 24 K/32 K 16 K 24 K/32 K 48 K/60 K 60 K RAM 512 2K 768 Power supply voltage Minimum instruction execution time Clock 512 1K 512 1K Note 1 ) 2 to 16 MHz - 3 to 4 MHz - Subclock 32.768 kHz Ring-OSC 240 kHz (TYP.) CMOS I/O 17 CMOS input 19 4 26 38 54 8 CMOS output 1 - N-ch open-drain I/O 4 16 bits (TM0) 1 ch 2 ch 8 bits (TM5) 2 ch 8 bits (TMH) 1 ch 2 ch - For watch 1 ch WDT 1 ch Note 2 Serial 3-wire CSI interface Automatic transmit/ receive 3-wire CSI Note 2 UART 1 ch 2 ch - 1 ch - 1 ch UART supporting LIN-bus 1 ch 10-bit A/D converter 4 ch Interrupts External 6 Internal Key return input Reset 2K 0.125 µs (when 16 MHz, VDD = 4.0 to 5.5 V) 0.24 µs (when 8.38 MHz, VDD = 3.3 to 5.5 V) 0.4 µs (when 5 MHz, VDD = 2.7 to 5.5 V) RC Timer 1K VDD = 2.7 to 5.5 V (with Ring-OSC clock or subclock: VDD = 2.0 to 5.5 V Crystal/ceramic Ports 512 11 8 ch 7 12 8 - 16 9 19 4 ch 20 8 ch RESET pin Provided 2.1 V ±0.1 V (detection voltage is fixed) POC LVI 9 15 2.35 V/2.6 V/2.85 V/3.1 V/3.3 V ±0.15 V/3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V (selectable by software) Clock monitor Provided WDT Provided - Clock output/buzzer output Clock output only Provided - External bus interface Provided 16 bits × 16 bits, 32 bits ÷ 16 bits - Multiplier/divider - ROM correction Provided Self-programming function Provided Product with on-chip debug function - µPD78F0114HD PD78F0114HD, 78F0124HD 78F0124HD, 78F0138HD 78F0138HD, 78F0148HD 78F0148HD Standby function HALT/STOP mode Operating ambient temperature TA = -40 to +85°C Notes 1. Use the product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.1 V ±0.1 V. 2. 20 Select either of the functions of these alternate-function pins. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CHAPTER 1 OUTLINE 1.5.2 V850ES/Kx1, V850ES/Kx1+ product lineup · 64-pin plastic LQFP (10 × 10 mm, 0.5 mm pitch) · 64-pin plastic TQFP (12 × 12 mm, 0.65 mm pitch) · 64-pin plastic LQFP (14 × 14 mm, 0.8 mm pitch) V850ES/KE1 V850ES/KE1 µPD70F3207HY PD70F3207HY µPD70F3207H PD70F3207H Single-power-supply flash memory: 128 KB, RAM: 4 KB V850ES/KE1 V850ES/KE1+ µPD703207Y PD703207Y µPD703207 PD703207 Mask ROM: 128 KB, RAM: 4 KB µPD703206Y PD703206Y µPD70F3302Y PD70F3302Y µPD703302Y PD703302Y µPD70F3302 PD70F3302 Single-power-supply flash memory: 128 KB, RAM: 4 KB µPD703302 PD703302 Mask ROM: 128 KB, RAM: 4 KB µPD703301Y PD703301Y µPD703206 PD703206 µPD703301 PD703301 Mask ROM: 96 KB, RAM: 4 KB Mask ROM: 96 KB, RAM: 4 KB · 80-pin plastic TQFP (12 × 12 mm, 0.5 mm pitch) · 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch) V850ES/KF1 V850ES/KF1 µPD70F3211HY PD70F3211HY µPD70F3211H PD70F3211H Single-power-supply flash memory: 256 KB, RAM: 12 KB µPD70F3210HY PD70F3210HY µPD70F3210H PD70F3210H Single-power-supply flash memory: 128 KB, RAM: 6 KB µPD70F3210Y PD70F3210Y µPD70F3210 PD70F3210 Two-power-supply flash memory: 128 KB, RAM: 6 KB V850ES/KF1 V850ES/KF1+ µPD703211Y PD703211Y µPD703211 PD703211 Mask ROM: 256 KB, RAM: 12 KB µPD703210Y PD703210Y µPD703210 PD703210 Mask ROM: 128 KB, RAM: 4 KB µPD703209Y PD703209Y µPD70F3308Y PD70F3308Y µPD703308Y PD703308Y µPD703308 PD703308 µPD70F3308 PD70F3308 Single-power-supply flash memory: 256 KB, RAM: 12 KB Mask ROM: 256 KB, RAM: 12 KB µPD70F3306Y PD70F3306Y µPD70F3306 PD70F3306 Single-power-supply flash memory: 128 KB, RAM: 6 KB µPD703209 PD703209 Mask ROM: 96 KB, RAM: 4 KB µPD703208Y PD703208Y µPD703208 PD703208 Mask ROM: 64 KB, RAM: 4 KB · 100-pin plastic LQFP (14 × 14 mm, 0.5 mm pitch) · 100-pin plastic QFP (14 × 20 mm, 0.65 mm pitch) V850ES/KG1 V850ES/KG1 µPD70F3215HY PD70F3215HY µPD70F3215H PD70F3215H Single-power-supply flash memory: 256 KB, RAM: 16 KB µPD70F3214HY PD70F3214HY µPD70F3214H PD70F3214H Single-power-supply flash memory: 128 KB, RAM: 6 KB µPD70F3214Y PD70F3214Y µPD70F3214 PD70F3214 Two-power-supply flash memory: 128 KB, RAM: 6 KB V850ES/KG1 V850ES/KG1+ µPD703215Y PD703215Y µPD703215 PD703215 Mask ROM: 256 KB, RAM: 16 KB µPD703214Y PD703214Y µPD703214 PD703214 Mask ROM: 128 KB, RAM: 6 KB µPD703213Y PD703213Y µPD703313Y PD703313Y µPD70F3313Y PD70F3313Y µPD70F3313 PD70F3313 Single-power-supply flash memory: 256 KB, RAM: 16 KB µPD703313 PD703313 Mask ROM: 256 KB, RAM: 16 KB µPD70F3311Y PD70F3311Y µPD70F3311 PD70F3311 Single-power-supply flash memory: 128 KB, RAM: 6 KB µPD703213 PD703213 Mask ROM: 96 KB, RAM: 4 KB µPD703212Y PD703212Y µPD703212 PD703212 Mask ROM: 64 KB, RAM: 4 KB · 144-pin plastic LQFP (20 × 20 mm, 0.5 mm pitch) V850ES/KJ1 V850ES/KJ1 µPD70F3218HY PD70F3218HY µPD70F3218H PD70F3218H Single-power-supply flash memory: 256 KB, RAM: 16 KB V850ES/KJ1 V850ES/KJ1+ µPD703218Y PD703218Y µPD703218 PD703218 Mask ROM: 256 KB, RAM: 16 KB µPD70F3217HY PD70F3217HY µPD703217Y PD703217Y µPD70F3217H PD70F3217H µPD703217 PD703217 Single-power-supply flash memory: 128 KB, RAM: 6 KB µPD70F3217Y PD70F3217Y µPD70F3217 PD70F3217 Two-power-supply flash memory: 128 KB, RAM: 6 KB Mask ROM: 128 KB, RAM: 6 KB µPD703216Y PD703216Y µPD703318Y PD703318Y µPD70F3318Y PD70F3318Y µPD703318 PD703318 µPD70F3318 PD70F3318 Single-power-supply flash memory: 256 KB, RAM: 16 KB Mask ROM: 256 KB, RAM: 16 KB µPD70F3316Y PD70F3316Y µPD70F3316 PD70F3316 Single-power-supply flash memory: 128 KB, RAM: 6 KB µPD703216 PD703216 Mask ROM: 96 KB, RAM: 4 KB Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 21 CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1 is shown below. Part Number V850ES/KE1 V850ES/KE1 V850ES/KF1 V850ES/KF1 V850ES/KG1 V850ES/KG1 V850ES/KJ1 V850ES/KJ1 Item Number of pins Internal memory (bytes) Mask ROM 64 pins Flash memory RAM 80 pins - 96/128 - 128 4 - 100 pins - - 4 256 - 128 64/ 128 96 - 256 6 12 - 256 - 96/ 128 128 - 4 144 pins - 64/ 128 96 - 256 - 6 Power supply voltage 256 128 - 6 - 256 16 VDD = 2.7 to 5.5 V Minimum instruction execution time 16 - 50 ns @ 20 MHz Clock X1 input 2 to 10 MHz Subclock 32.768 kHz - Ring-OSC Ports 8 8 8 16 CMOS I/O 43 59 76 112 N-ch open-drain I/O Timer CMOS input 1 2 4 6 - 1 ch 2 ch 4 ch 6 ch 8 bits (TM5) 2 ch 2 ch 2 ch 2 ch 8 bits (TMH) 2 ch 2 ch 2 ch 2 ch Interval timer 1 ch 1 ch 1 ch 1 ch For watch 1 ch 1 ch 1 ch 1 ch WDT1 1 ch 1 ch 1 ch 1 ch WDT2 1 ch 1 ch 1 ch 1 ch 6 bits × 1 ch 6 bits × 1 ch 6 bits × 1 ch 6 bits × 2 ch 2 ch 2 ch 2 ch 3 ch - 1 ch 2 ch 2 ch 2 ch 2 ch 2 ch 3 ch - - - - Serial CSI interface Automatic transmit/ receive 3-wire CSI UART UART supporting LIN-bus 2 Note IC 1 ch - 1 ch 16 bits (TM0) RTO 1 ch - 16 bits (TMP) 1 ch 1 ch 1 ch 1 ch 2 ch Address space - 128 KB 3 MB 15 MB Address bus - 16 bits 22 bits 24 bits Mode - Multiplexed mode only - - - - 10-bit A/D converter 8 ch 8 ch 8 ch 16 ch 8-bit D/A converter - - 2 ch 2 ch Interrupts External 8 8 8 External bus DMA controller Internal Key return input Reset 26 8 ch RESET pin 26 29 31 8 ch Provided Not provided LVI Not provided Clock monitor Not provided WDT1 Provided WDT2 Provided ROM correction Regulator Standby function Operating ambient temperature 4 points Not provided Provided HALT/IDLE/STOP/sub-IDLE mode TA = -40 to +85°C Note Provided in the Y version only. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 8 34 8 ch POC 22 Multiplexed/separate mode 40 43 8 ch CHAPTER 1 OUTLINE The list of functions in the V850ES/Kx1+ is shown below. Part Number V850ES/KE1 V850ES/KE1+ V850ES/KF1 V850ES/KF1+ V850ES/KG1 V850ES/KG1+ V850ES/KJ1 V850ES/KJ1+ Item Number of pins Internal memory (bytes) Mask ROM 64 pins 80 pins 100 pins 144 pins 96/128 - 128 256 - 128/256 - 128/256 - - 128 - - 256 128 256 - 256 6 16 6 16 Flash memory RAM 4 6 12 Power supply voltage VDD = 2.7 to 5.5 V Minimum instruction execution time 50 ns @ 20 MHz Clock X1 input 2 to 10 MHz Subclock Ports 32.768 kHz Ring-OSC 240 kHz (TYP.) CMOS input 8 8 8 16 CMOS I/O 43 59 76 112 N-ch open-drain I/O 1 2 16 bits (TMP) 1 ch 1 ch 1 ch 1 ch 16 bits (TM0) 1 ch 2 ch 4 ch 6 ch 8 bits (TM5) Timer 4 6 2 ch 2 ch 2 ch 2 ch 8 bits (TMH) 2 ch 2 ch 2 ch 2 ch Interval timer 1 ch 1 ch 1 ch 1 ch For watch 1 ch 1 ch 1 ch 1 ch WDT1 1 ch 1 ch 1 ch 1 ch WDT2 1 ch 1 ch 1 ch 1 ch 6 bits × 1 ch 6 bits × 1 ch 6 bits × 1 ch 6 bits × 2 ch 2 ch 2 ch 2 ch 3 ch - 1 ch 2 ch 2 ch UART 1 ch 1 ch 1 ch 2 ch UART supporting LIN-bus 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 1 ch 2 ch Address space - 128 KB 3 MB 15 MB Address bus - 16 bits 22 bits 24 bits Mode - Multiplexed mode only - - 4 ch 4 ch 10-bit A/D converter 8 ch 8 ch 8 ch 16 ch 8-bit D/A converter - - 2 ch 2 ch Interrupts External 9 9 9 9 27 30 42 48 8 ch 8 ch 8 ch 8 ch RTO Serial CSI interface Automatic transmit/ receive 3-wire CSI 2 Note IC External bus DMA controller Internal Key return input Reset RESET pin Provided POC LVI Multiplexed/separate mode Fixed to 2.7 V or lower 3.1 V/3.3 V ±0.15 V or 3.5 V/3.7 V/3.9 V/4.1 V/4.3 V ±0.2 V (selectable by software) Clock monitor Provided (monitoring by Ring-OSC) WDT1 Provided WDT2 Provided ROM correction Regulator Standby function Operating ambient temperature 4 points Not provided Provided HALT/IDLE/STOP/sub-IDLE mode TA = -40 to +85°C Note Provided in the Y version only. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 23 CHAPTER 1 OUTLINE 1.6 Block Diagram TO00/TI010/P01 TI000/P00 TI000/P00 Port 0 P10 to P17 4 P20 to P23 Port 3 8-bit timer H1 8 4 P30 to P33 8-bit timer H0 TOH1/P16 P00 to P03 Port 2 TOH0/P15 4 Port 1 16-bit timer/ event counter 00 Port 12 P120 Port 13 78K/0 78K/0 CPU core 8-bit timer/ event counter 50 TI50/TO50/P17 TI50/TO50/P17 P130 Flash memory Watchdog timer Clock monitor RxD0Note/P11 TxD0Note/P10 Serial interface UART0Note RxD6/P14 TxD6/P13 Serial interface UART6 SI10/P11 SI10/P11 SO10/P12 SO10/P12 SCK10/P10 SCK10/P10 Serial interface CSI10 CSI10 Ring-OSC A/D converter System control ANI0/P20 ANI0/P20 to ANI3/P23 ANI3/P23 AVREF AVSS Power-on-clear/ low voltage indicator Internal high-speed RAM Reset control 4 INTP0/P120 INTP0/P120 INTP1/P30 INTP1/P30 to INTP4/P33 INTP4/P33 Interrupt control 4 VDD VSS FLMD0, FLMD1 Note µPD78F0102H PD78F0102H and 78F0103H 78F0103H only. Remark 24 Items in brackets are the pin names when external RC oscillation is used. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD POC/LVI control RESET X1[CL1] X2[CL2] CHAPTER 1 OUTLINE 1.7 Outline of Functions µPD78F0101H PD78F0101H Item Internal memory µPD78F0102H PD78F0102H Flash memory (self-programming supported) 8 KB High-speed RAM 512 bytes µPD78F0103H PD78F0103H 16 KB 24 KB 768 bytes Memory space 64 KB High-speed system clock (oscillation frequency) · Ceramic/crystal/external clock oscillation (2 to 16 MHz: VDD = 4.0 to 5.5 V, 2 to 8.38 MHz: VDD = 3.3 to 5.5 V, 2 to 5 MHz: VDD = 2.7 to 5.5 V) · External RC/external clock oscillation (3 to 4 MHz: VDD = 2.7 to 5.5 V) Ring-OSC clock (oscillation frequency) On-chip Ring oscillation (240 kHz (TYP.): VDD = 2.0 to 5.5 V) General-purpose registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 0.125 µs/0.25 µs/0.5 µs/1.0 µs/2.0 µs (high-speed system clock: @ fXP = 16 MHz operation) 8.3 µs/16.6 µs/33.2 µs/66.4 µs/132.8 µs (TYP.) (Ring-OSC clock: @ fR = 240 kHz (TYP.) operation) Instruction set · · · · I/O ports Total: 22 CMOS I/O CMOS input CMOS output 17 4 1 Timers · · · · Timer outputs 16-bit operation Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulate (set, reset, test, and Boolean operation) BCD adjust, etc. 16-bit timer/event counter: 8-bit timer/event counter: 8-bit timer: Watchdog timer: 1 channel 1 channel 2 channels 1 channel 4 (PWM: 3) A/D converter 10-bit resolution × 4 channels Serial interface · UART mode supporting LIN-bus: 1 channel Note 1 · 3-wire serial I/O mode/UART mode : 1 channel (µPD78F0101H PD78F0101H only, 3-wire serial I/O mode: 1 channel) Vectored interrupt sources Internal 11 External 6 12 Reset · · · · · Supply voltage VDD = 2.7 to 5.5 V (with Ring-OSC clock: VDD = 2.0 to 5.5 V Operating ambient temperature TA = -40 to +85°C Package 30-pin plastic SSOP (7.62 mm (300) Notes 1. 2. Reset using RESET pin Internal reset by watchdog timer Internal reset by clock monitor Internal reset by power-on-clear Internal reset by low-voltage detector Note 2 ) Select either of the functions of these alternate-function pins. Use the product in a voltage range of 2.2 to 5.5 V because the detection voltage (VPOC) of the power-onclear (POC) circuit is 2.1 V ±0.1 V. Caution The operating voltage range may be changed after evaluation of the device. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 25 CHAPTER 1 OUTLINE An outline of the timer is shown below. 16-Bit Timer/Event 8-Bit Timer/Event Counter 00 Counter 50 TMH0 TMH1 1 channel 1 channel 8-Bit Timers H0 and H1 Watchdog Timer Operation Interval timer 1 channel 1 channel mode External event counter 1 channel 1 channel - - - Function Timer output 1 output 1 output 1 output 1 output - PPG output 1 output - - - - PWM output - 1 output 1 output 1 output - Pulse width measurement 2 inputs - - - - Square-wave output 1 output 1 output 1 output 1 output - 2 1 1 1 - Interrupt source 26 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 1 channel CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are two types of pin I/O buffer power supplies: AVREF and VDD. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins AVREF P20 to P23 VDD Pins other than P20 to P23 (1) Port pins Pin Name P00 I/O I/O Port 0. After Reset Input 4-bit I/O port. P01 Alternate Function TI000 TI000 TI010/TO00 TI010/TO00 Input/output can be specified in 1-bit units. P02 - Use of an on-chip pull-up resistor can be specified by a P03 P10 Function software setting. I/O Port 1. Input 8-bit I/O port. P11 SI10/RxD0 Input/output can be specified in 1-bit units. P12 Note SO10 Use of an on-chip pull-up resistor can be specified by a P13 Note SCK10/TxD0 TxD6 software setting. P14 RxD6 P15 TOH0 P16 TOH1/INTP5 P17 TI50/TO50/FLMD1 TI50/TO50/FLMD1 P20 to P23 Input Port 2. Input ANI0 to ANI3 Input INTP1 to INTP4 Input INTP0 4-bit input-only port. P30 to P33 I/O Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P120 I/O Port 12. 1-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P130 Output Port 13. Output - 1-bit output-only port. Note TxD0 and RxD0 are available only in the µPD78F0102H PD78F0102H and 78F0103H 78F0103H. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 27 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Pin Name I/O Input INTP0 Function External interrupt request input for which the valid edge (rising After Reset P120 Input edge, falling edge, or both rising and falling edges) can be INTP1 to INTP4 P30 to P33 specified INTP5 Alternate Function P16/TOH1 P16/TOH1 SI10 Input Serial data input to serial interface Input P11/RxD0 SO10 Output Serial data output from serial interface Input P12 SCK10 SCK10 I/O Clock input/output for serial interface Input P10/TxD0 Input Serial data input to asynchronous serial interface Input Note P11/SI10 P11/SI10 Note RxD0 RxD6 TxD0 Note P14 Note Output Serial data output from asynchronous serial interface Input P10/SCK10 P10/SCK10 Input External count clock input to 16-bit timer/event counter 00 Input P00 TxD6 P13 TI000 TI000 Capture trigger input to capture registers (CR000 CR000, CR010 CR010) of 16-bit timer/event counter 00 Capture trigger input to capture register (CR000 CR000) of 16-bit TI010 TI010 P01/TO00 P01/TO00 timer/event counter 00 TO00 Output 16-bit timer/event counter 00 output Input P01/TI010 P01/TI010 TI50 Input External count clock input to 8-bit timer/event counter 50 Input P17/TO50/FLMD1 P17/TO50/FLMD1 TO50 Output 8-bit timer/event counter 50 output Input P17/TI50/FLMD1 P17/TI50/FLMD1 TOH0 Output 8-bit timer H0 output Input P15 TOH1 8-bit timer H1 output ANI0 to ANI3 Input A/D converter analog input AVREF Input P16/INTP5 P16/INTP5 A/D converter reference voltage input and positive power Input P20 to P23 - - - - supply for port 2 AVSS - A/D converter ground potential. Make the same potential as VSS. RESET Input System reset input - - X1[CL1] Input Connecting resonator for high-speed system clock - - - - X2[CL2] - [RC connection for high-speed system clock] VDD - Positive power supply - - VSS - Ground potential - - FLMD0 - Flash memory programming mode setting. FLMD1 Note TxD0 and RxD0 are available only in the µPD78F0102H PD78F0102H and 78F0103H 78F0103H. Remark 28 - Input Items in brackets are the pin names when external RC oscillation is used. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD - P17/TI50/TO50 P17/TI50/TO50 CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P00 to P03 (port 0) P00 to P03 function as a 4-bit I/O port. These pins also function as timer I/O. The following operation modes can be specified in 1-bit units. (1) Port mode P00 to P03 function as a 4-bit I/O port. P00 to P03 can be set to input or output in 1-bit units using port mode register 0 (PM0). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 0 (PU0). (2) Control mode P00 to P03 function as timer I/O. (a) TI000 TI000 This is the pins for inputting an external count clock to 16-bit timer/event counter 00 and is also for inputting a capture trigger signal to the capture registers (CR000 CR000, CR010 CR010) of 16-bit timer/event counter 00. (b) TI010 TI010 This is the pin for inputting a capture trigger signal to the capture register (CR000 CR000) of 16-bit timer/event counter 00. (c) TO00 This is a timer output pin. 2.2.2 P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O, and flash memory programming mode setting. The following operation modes can be specified in 1-bit units. (1) Port mode P10 to P17 function as an 8-bit I/O port. P10 to P17 can be set to input or output in 1-bit units using port mode register 1 (PM1). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 1 (PU1). (2) Control mode P10 to P17 function as external interrupt request input, serial interface data I/O, clock I/O, and timer I/O, and flash memory programming mode setting. (a) SI10 This is a serial data input pin of the serial interface. (b) SO10 This is a serial data output pin of the serial interface. (c) SCK10 SCK10 This is a serial clock I/O pin of the serial interface. (d) RxD0Note, RxD6 These are the serial data input pins of the asynchronous serial interface. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 29 CHAPTER 2 PIN FUNCTIONS (e) TxD0Note, TxD6 These are serial data output pins of the asynchronous serial interface. Note TxD0 and RxD0 are available only in the µPD78F0102H PD78F0102H and 78F0103H 78F0103H. (f) TI50 This is the pin for inputting an external count clock to 8-bit timer/event counter 50. (g) TO50, TOH0, and TOH1 These are timer output pins. (h) INTP5 This is an external interrupt request input pin for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (i) FLMD1 This pin sets the flash memory programming mode. 2.2.3 P20 to P23 (port 2) P20 to P23 function as a 4-bit input-only port. These pins also function as pins for A/D converter analog input. The following operation modes can be specified in 1-bit units. (1) Port mode P20 to P23 function as a 4-bit input-only port. (2) Control mode P20 to P23 function as A/D converter analog input pins (ANI0 to ANI3). When using these pins as analog input pins, see (5) ANI0/P20 ANI0/P20 to ANI3/P23 ANI3/P23 in 10.6 Cautions for A/D Converter. 2.2.4 P30 to P33 (port 3) P30 to P33 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input. The following operation modes can be specified in 1-bit units. (1) Port mode P30 to P33 function as a 4-bit I/O port. P30 to P33 can be set to input or output in 1-bit units using port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3). (2) Control mode P30 to P33 function as external interrupt request input pins (INTP1 to INTP4) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.5 P120 (port 12) P120 functions as a 1-bit I/O port. This pin also functions as a pin for external interrupt request input. The following operation modes can be specified in 1-bit units. (1) Port mode P120 functions as a 1-bit I/O port. P120 can be set to input or output in 1-bit units using port mode register 12 (PM12). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). 30 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CHAPTER 2 PIN FUNCTIONS (2) Control mode P120 functions as an external interrupt request input pin (INTP0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.6 P130 (port 13) P130 functions as a 1-bit output-only port. 2.2.7 AVREF This is the A/D converter reference voltage input pin. When A/D converter is not used, connect this pin directly to VDD. 2.2.8 AVSS This is the A/D converter ground potential pin. Even when the A/D converter is not used, always use this pin with the same potential as the VSS pin. 2.2.9 RESET This is the active-low system reset input pin. 2.2.10 X1 and X2 These are the pins for connecting a resonator for high-speed system clock oscillation. When supplying an external clock, input a signal to the X1 pin and input the inverse signal to the X2 pin. 2.2.11 CL1 and CL2 These are the pins for connecting a resistor (R) and capacitor (C) for high-speed system clock oscillation. When supplying an external clock, input a signal to the CL1 pin and input the inverse signal to the CL2 pin. 2.2.12 VDD This is the positive power supply pin. 2.2.13 VSS This is the ground potential pin. 2.2.14 FLMD0 and FLMD1 These pins set the flash memory programming mode. Connect FLMD0 to VSS in the normal operation mode (FLMD1 is not used in the normal operation mode). Always connect FLMD0 and FLMD1 to the flash programmer in the flash memory programming mode. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 31 CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuit and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuits of each type. Table 2-2. Pin I/O Circuit Types Pin Name P00/TI000 P00/TI000 I/O Circuit Type 8-A I/O Recommended Connection of Unused Pins Input: I/O Independently connect to VDD or VSS via a resistor. Output: Leave open. P01/TI010/TO00 P01/TI010/TO00 P02 P03 P10/SCK10/TxD0 P11/SI10/RxD0 Note Note P12/SO10 P12/SO10 5-A P13/TxD6 P14/RxD6 8-A P15/TOH0 P15/TOH0 5-A P16/TOH1/INTP5 P16/TOH1/INTP5 8-A P17/TI50/TO50/FLMD1 P17/TI50/TO50/FLMD1 P20/ANI0 P20/ANI0 to P23/ANI3 P23/ANI3 9-C Input P30/INTP1 P30/INTP1 to P33/INTP4 P33/INTP4 8-A I/O Connect to VDD or VSS. Input: Independently connect to VSS via a resistor. Output: Leave open. Input: P120/INTP0 P120/INTP0 Independently connect to VDD or VSS via a resistor. Output: Leave open. P130 3-C Output RESET 2 Input AVREF AVSS FLMD0 - Leave open. - Input Connect directly to VDD. - Connect directly to VSS. Connect to VSS. Note TxD0 and RxD0 are available only in the µPD78F0102H PD78F0102H and 78F0103H 78F0103H. 32 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List Type 8-A Type 2 VDD Pull-up enable P-ch IN VDD Data P-ch IN/OUT Schmitt-triggered input with hysteresis characteristics Output disable N-ch Type 9-C Type 3-C VDD IN P-ch Data Comparator P-ch + N-ch AVSS OUT VREF (threshold voltage) N-ch Input enable Type 5-A VDD Pull-up enable P-ch VDD Data P-ch IN/OUT Output disable N-ch Input enable Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 33 CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/KB1 78K0/KB1+ can each access a 64 KB memory space. Figures 3-1 to 3-3 show the memory maps. Caution Regardless of the internal memory capacity, the initial values of internal memory size switching register (IMS) of all products in the 78K0/KB1 78K0/KB1+ are fixed (IMS = CFH). Therefore, set the value corresponding to each product as indicated below. In addition, set the following values to the internal memory size switching register (IMS) when using the 78K0/KB1 78K0/KB1+ to evaluate the program of a mask ROM version of the 78K0/KB1 78K0/KB1. Table 3-1. Internal Memory Size Switching Register (IMS) Set Value Flash Memory Version Target Mask ROM Version Internal Memory Size (78K0/KB1 78K0/KB1+) (78K0/KB1 78K0/KB1) Switching Register (IMS) µPD78F0101H PD78F0101H 42H µPD78F0102H PD78F0102H µPD780102 PD780102 04H µPD78F0103H PD78F0103H 34 µPD780101 PD780101 µPD780103 PD780103 06H Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-1. Memory Map (µPD78F0101H PD78F0101H) F F F FH Special function registers (SFR) 256 × 8 bits F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 × 8 bits Internal high-speed RAM 512 × 8 bits 1 F F FH F D 0 0H F C F FH Program area Data memory space 1 0 0 0H 0 F F FH CALLF entry area Reserved 0 8 0 0H 0 7 F FH Program area 0 0 8 1H 0 0 8 0H 0 0 7 FH 2 0 0 0H 1 F F FH Program memory space 0 0 0 0H Option byte area CALLT table area Flash memory 8192 × 8 bits 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 35 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map (µPD78F0102H PD78F0102H) F F F FH Special function registers (SFR) 256 × 8 bits F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 × 8 bits Internal high-speed RAM 768 × 8 bits 3 F F FH F C 0 0H F B F FH Program area Data memory space 1 0 0 0H 0 F F FH CALLF entry area Reserved 0 8 0 0H 0 7 F FH Program area 0 0 8 1H 0 0 8 0H 0 0 7 FH CALLT table area 4 0 0 0H 3 F F FH Program memory space 0 0 0 0H 36 Option byte area Flash memory 16384 × 8 bits 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map (µPD78F0103H PD78F0103H) F F F FH Special function registers (SFR) 256 × 8 bits F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 × 8 bits Internal high-speed RAM 768 × 8 bits 5 F F FH F C 0 0H F B F FH Program area Data memory space 1 0 0 0H 0 F F FH CALLF entry area Reserved 0 8 0 0H 0 7 F FH Program area 0 0 8 1H 0 0 8 0H 0 0 7 FH 6 0 0 0H 5 F F FH Program memory space 0 0 0 0H Option byte area CALLT table area Flash memory 24576 × 8 bits 0 0 4 0H 0 0 3 FH Vector table area 0 0 0 0H Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 37 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/KB1 78K0/KB1+ products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM Structure µPD78F0101H PD78F0101H Capacity 8192 × 8 bits (0000H 0000H to 1FFFH) Flash memory µPD78F0102H PD78F0102H 16384 × 8 bits (0000H 0000H to 3FFFH) µPD78F0103H PD78F0103H 24576 × 8 bits (0000H 0000H to 5FFFH) The internal program memory space is divided into the following areas. (1) Vector table area The 64-byte area 0000H 0000H to 003FH 003FH is reserved as a vector table area. The program start addresses for branch upon reset signal input or generation of each interrupt request are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 3-3. Vector Table Vector Table Address 0000H 0000H Interrupt Source Vector Table Address RESET input, POC, LVI Interrupt Source 0016H 0016H INTST6 clock monitor, WDT 0004H 0004H INTLVI 0018H 0018H INTCSI10/INTST0 INTCSI10/INTST0 0006H 0006H INTP0 001AH 001AH INTTMH1 0008H 0008H INTP1 001CH 001CH INTTMH0 000AH 000AH INTP2 001EH 001EH INTTM50 INTTM50 000CH 000CH INTP3 0020H 0020H INTTM000 INTTM000 000EH 000EH INTP4 0022H 0022H INTTM010 INTTM010 0010H 0010H INTP5 0024H 0024H INTAD 0012H 0012H INTSRE6 0026H 0026H INTSR0 0014H 0014H Note INTSR6 Note Note Available only in the µPD78F0102H PD78F0102H and 78F0103H 78F0103H. (2) CALLT instruction table area The 64-byte area 0040H 0040H to 007FH 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area The option byte area is assigned to the 1-byte area of 0080H 0080H. Refer to CHAPTER 20 OPTION BYTE for details. (4) CALLF instruction entry area The area 0800H 0800H to 0FFFH can perform a direct subroutine call with a 2-byte call instruction (CALLF). 38 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space 78K0/KB1 78K0/KB1+ products incorporate the following internal high-speed RAM. Table 3-4. Internal High-Speed RAM Capacity Part Number Internal High-Speed RAM µPD78F0101H PD78F0101H 512 × 8 bits (FD00H FD00H to FEFFH) µPD78F0102H PD78F0102H 768 × 8 bits (FC00H FC00H to FEFFH) µPD78F0103H PD78F0103H The 32-byte area FEE0H to FEFFH is assigned to four general-purpose register banks consisting of eight 8-bit registers per bank. This area cannot be used as a program area in which instructions are written and executed. The internal high-speed RAM can also be used as a stack memory. 3.1.3 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H FF00H to FFFFH (refer to Table 3-5 Special Function Register List in 3.2.3 Special Function Registers (SFRs). Caution Do not access addresses to which SFRs are not assigned. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 39 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/KB1 78K0/KB1+, based on operability and other considerations. For areas containing data memory in particular, special addressing methods designed for the functions of special function registers (SFR) and general-purpose registers are available for use. Figures 3-4 to 3-6 show the correspondence between data memory and addressing. For details of each addressing mode, refer to 3.4 Operand Address Addressing. Figure 3-4. Correspondence Between Data Memory and Addressing (µPD78F0101H PD78F0101H) F F F FH Special function registers (SFR) 256 × 8 bits SFR addressing F F 2 0H F F 1 FH F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 × 8 bits Register addressing Short direct addressing Internal high-speed RAM 512 × 8 bits F E 2 0H F E 1 FH F D 0 0H F C F FH Direct addressing Register indirect addressing Based addressing Based indexed addressing Reserved 2 0 0 0H 1 F F FH Flash memory 8192 × 8 bits 0 0 0 0H 40 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Correspondence Between Data Memory and Addressing (µPD78F0102H PD78F0102H) F F F FH Special function registers (SFR) 256 × 8 bits SFR addressing F F 2 0H F F 1 FH F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 × 8 bits Register addressing Short direct addressing Internal high-speed RAM 768 × 8 bits F E 2 0H F E 1 FH Direct addressing F C 0 0H F B F FH Register indirect addressing Based addressing Based indexed addressing Reserved 4 0 0 0H 3 F F FH Flash memory 16384 × 8 bits 0 0 0 0H Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 41 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Correspondence Between Data Memory and Addressing (µPD78F0103H PD78F0103H) F F F FH Special function registers (SFR) 256 × 8 bits SFR addressing F F 2 0H F F 1 FH F F 0 0H F E F FH F E E 0H F E D FH General-purpose registers 32 × 8 bits Register addressing Short direct addressing Internal high-speed RAM 768 × 8 bits F E 2 0H F E 1 FH Direct addressing F C 0 0H F B F FH Register indirect addressing Based addressing Based indexed addressing Reserved 6 0 0 0H 5 F F FH Flash memory 24576 × 8 bits 0 0 0 0H 42 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers 78K0/KB1 78K0/KB1+ products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed. In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. RESET input sets the reset vector table values at addresses 0000H 0000H and 0001H 0001H to the program counter. Figure 3-7. Format of Program Counter 15 PC 0 PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution. Program status word contents are automatically stacked upon interrupt request generation or PUSH PSW instruction execution and are reset upon execution of the RETB, RETI and POP PSW instructions. RESET input sets the PSW to 02H. Figure 3-8. Format of Program Status Word 7 PSW IE 0 Z RBS1 AC RBS0 0 ISP CY (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledgment operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and maskable interrupt requests are all disabled. When 1, the IE flag is set to the interrupt enabled (EI) state and interrupt request acknowledgment enable is controlled with an in-service priority flag (ISP), an interrupt mask flag for various interrupt sources and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 43 CHAPTER 3 CPU ARCHITECTURE (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flag (ISP) This flag manages the priority of acknowledgeable maskable vectored interrupts. When this flag is 0, lowlevel vectored interrupt requests specified by a priority specification flag register (PR0L, PR0H, PR1L) (refer to 14.3 (3) Priority specification flag registers (PR0L, PR0H, PR1L) can not be acknowledged. Actual request acknowledgment is controlled by the interrupt enable flag (IE). (f) Carry flag (CY) This flag stores on overflow or underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Figure 3-9. Format of Stack Pointer 15 SP 0 SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 The SP is decremented ahead of write (save) to the stack memory and is incremented after read (restore) from the stack memory. Each stack operation saves/restores data as shown in Figures 3-10 and 3-11. Caution Since RESET input makes the SP contents undefined, be sure to initialize the SP before use. 44 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) SP FEE0H FEE0H FEDFH SP FEDEH Register pair upper FEDEH Register pair lower (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) SP FEE0H FEE0H FEDFH SP FEDEH PC15-PC8 PC15-PC8 FEDEH PC7-PC0 (c) Interrupt, BRK instructions (when SP = FEE0H) SP FEE0H FEE0H FEDFH FEDEH SP FEDDH PSW PC15-PC8 PC15-PC8 FEDDH PC7-PC0 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 45 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) SP FEE0H FEE0H FEDFH SP FEDEH Register pair upper FEDEH Register pair lower (b) RET instruction (when SP = FEDEH) SP FEE0H FEE0H FEDFH SP FEDEH PC15-PC8 PC15-PC8 FEDEH PC7-PC0 (c) RETI, RETB instructions (when SP = FEDDH) SP FEE0H FEE0H FEDFH FEDEH SP 46 FEDDH PSW PC15-PC8 PC15-PC8 FEDDH PC7-PC0 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4-register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. Figure 3-12. Configuration of General-Purpose Registers (a) Absolute name 16-bit processing 8-bit processing FEFFH R7 BANK0 RP3 R6 FEF8H R5 BANK1 RP2 R4 FEF0H R3 RP1 BANK2 R2 FEE8H R1 RP0 BANK3 R0 FEE0H 15 0 7 0 (b) Function name 16-bit processing 8-bit processing FEFFH H BANK0 HL L FEF8H D BANK1 DE E FEF0H B BC BANK2 C FEE8H A AX BANK3 X FEE0H 15 0 Preliminary User's Manual U16846EJ1V0UD U16846EJ1V0UD 7 0 47 CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special Function Registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type. Each manipulation bit unit can be specified as follows. · 1-bit manipulation Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This manipulation can also be specified with an address. · 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address. · 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address. Table 3-5 gives a list of the special function registers. The meanings of items in the table are as follows. · Symbol Symbol indicating the address of a special function register. It is a reserved word in the RA78K0 RA78K0, and