PD78E9860A 78E9861A PD78E9861A PD789860 78K/0S PD789861 U14826E U11047E - Datasheet Archive

 

MOS INTEGRATED CIRCUIT µPD78E9860A, 78E9861A 8-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The µPD78E9860A and

 

DATA SHEET MOS INTEGRATED CIRCUIT µPD78E9860A PD78E9860A, 78E9861A 78E9861A 8-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The µPD78E9860A PD78E9860A and µPD78E9861A PD78E9861A are µPD789860 PD789860, 789861 Subseries products in the 78K/0S 78K/0S Series. The µPD78E9860A PD78E9860A and µPD78E9861A PD78E9861A incorporate EEPROMTM in place of the internal ROM of the µPD789860 PD789860 and µPD789861 PD789861, respectively. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. µPD789860 PD789860, 789861 Subseries User's Manual: 78K/0S 78K/0S Series Instructions User's Manual: U14826E U14826E U11047E U11047E FEATURES Pin compatible with mask ROM product (except VPP pin) On-chip EEPROM as program memory: 4 KB On-chip EEPROM that can be read/written by program in RAM area: 32 bytes On-chip high-speed RAM: 128 bytes System clock oscillator · µPD78E9860A PD78E9860A: Crystal/ceramic oscillator · µPD78E9861A PD78E9861A: RC oscillator (externally attached resistor and capacitor) Minimum instruction execution time · µPD78E9860A PD78E9860A: 0.4 µs/1.6 µs (@ fX = 5.0 MHz operation) · µPD78E9861A PD78E9861A: 2.0 µs/8.0 µs (@ fCC = 1.0 MHz operation) I/O ports: 14 Timer: 3 channels · 8-bit timer/event counter: 1 channel · 8-bit timer: 1 channel · Watchdog timer: 1 channel On-chip power-on-clear circuit On-chip bit sequential buffer Power supply voltage: VDD = 1.8 to 5.5 V (µPD78E9860A PD78E9860A) VDD = 1.8 to 3.6 V (µPD78E9861A PD78E9861A) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. U16524EJ1V0DS00 U16524EJ1V0DS00 (1st edition) Date Published March 2003 N CP(K) 2003 µPD78E9860A PD78E9860A, 78E9861A 78E9861A APPLICATIONS Keyless entry and other automotive electrical equipment In this data sheet, the oscillation frequency of the crystal/ceramic oscillator (µPD78E9860A PD78E9860A) is described as fX and the oscillation frequency of the RC oscillator (µPD78E9861A PD78E9861A) is described as fCC. ORDERING INFORMATION Part Number µPD78E9860AMC-5A4 PD78E9860AMC-5A4 20-pin plastic SSOP (7.62 mm (300) µPD78E9861AMC-5A4 PD78E9861AMC-5A4 2 Package 20-pin plastic SSOP (7.62 mm (300) Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A 78K/0S 78K/0S SERIES LINEUP The products in the 78K/0S 78K/0S Series are listed below. The names enclosed in boxes are subseries names. Products under development Products in mass production Y Subseries products support SMB. Small-scale package, general-purpose applications µ PD789046 PD789046 44-pin 42-/44-pin µ PD789074 PD789074 with added subsystem clock µ PD789014 PD789014 with enhanced timer and increased ROM, RAM capacity µ PD789074 PD789074 with enhanced timer and increased ROM, RAM capacity µ PD789026 PD789026 with enhanced timer On-chip UART and capable of low voltage (1.8 V) operation RC oscillation version of the µ PD789052 PD789052 µ PD789860 PD789860 without EEPROM, POC, and LVI µ PD789026 PD789026 µ PD789088 PD789088 µ PD789074 PD789074 µ PD789014 PD789014 µ PD789062 PD789062 µ PD789052 PD789052 30-pin 30-pin 28-pin 20-pin 20-pin Small-scale package, general-purpose applications and A/D converter µ PD789177 PD789177 µ PD789167 PD789167 µ PD789156 PD789156 µ PD789146 PD789146 µ PD789134A PD789134A µ PD789124A PD789124A µ PD789114A PD789114A µ PD789104A PD789104A 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin µ PD789177Y PD789177Y µ PD789167Y PD789167Y µ PD789167 PD789167 with enhanced A/D converter (10 bits) µ PD789104A PD789104A with enhanced timer µ PD789146 PD789146 with enhanced A/D converter (10 bits) µ PD789104A PD789104A with added EEPROM µ PD789124A PD789124A with enhanced A/D converter (10 bits) RC oscillation version of the µ PD789104A PD789104A µ PD789104A PD789104A with enhanced A/D converter (10 bits) µ PD789026 PD789026 with added 8-bit A/D converter and multiplier LCD drive µ PD789835 PD789835 144-pin 88-pin µ PD789830 PD789830 UART, 8-bit A/D, and dot LCD (Total display output pins: 96) UART and dot LCD (40 × 16) 80-pin 52-pin µ PD789479 PD789479 µ PD789417A PD789417A µ PD789407A PD789407A µ PD789456 PD789456 µPD789446 PD789446 µ PD789436 PD789436 µ PD789426 PD789426 µ PD789316 PD789316 µ PD789306 PD789306 µ PD789467 PD789467 52-pin 78K/0S 78K/0S Series µ PD789489 PD789489 80-pin 80-pin µ PD789327 PD789327 8-bit A/D and on-chip voltage booster type LCD (23 × 4) SIO and resistance division type LCD (24 × 4) µ PD789800 PD789800 For PC keyboard and on-chip USB function 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin SIO, 10-bit A/D converter, and on-chip voltage booster type LCD (28 × 4) SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4) µ PD789407A PD789407A with enhanced A/D converter (10 bits) SIO, 8-bit A/D converter, and resistance division type LCD (28 × 4) µ PD789446 PD789446 with enhanced A/D converter (10 bits) SIO, 8-bit A/D, and on-chip voltage booster type LCD (15 × 4) µ PD789426 PD789426 with enhanced A/D converter (10 bits) SIO, 8-bit A/D, and on-chip voltage booster type LCD (5 × 4) RC oscillation version of the µ PD789306 PD789306 SIO and on-chip voltage booster type LCD (24 × 4) USB 44-pin Inverter control 44-pin µ PD789842 PD789842 On-chip inverter controller and UART On-chip bus controller 30-pin µ PD789850 PD789850 On-chip CAN controller Keyless entry 30-pin 20-pin 20-pin µ PD789862 PD789862 µ PD789861 PD789861 µ PD789860 PD789860 µ PD789860 PD789860 with enhanced timer, added SIO, and increased ROM, RAM capacity RC oscillation version of the µ PD789860 PD789860 On-chip POC and key return circuit VFD drive 52-pin µ PD789871 PD789871 On-chip VFD controller (Total display output pins: 25) Meter control 64-pin Remark µ PD789881 PD789881 UART and resistance division type LCD (26 × 4) TM VFD (Vacuum Fluorescent Display) is referred to as FIP (Fluorescent Indicator Panel) in some documents, but the functions of the two are the same. Data Sheet U16524EJ1V0DS U16524EJ1V0DS 3 µPD78E9860A PD78E9860A, 78E9861A 78E9861A The major functional differences between the subseries are listed below. Series for General-purpose applications and LCD drive Function ROM Capacity Timer 8-Bit 16-Bit Watch WDT 8-Bit 10-Bit A/D A/D Serial Interface I/O µPD789046 PD789046 16 KB 1 ch (UART: 1 ch) 34 µPD789026 PD789026 4 KB to 16 KB µPD789088 PD789088 16 KB to 32 KB 3 ch µPD789074 PD789074 2 KB to 8 KB 1 ch µPD789014 PD789014 2 KB to 4 KB 2 ch µPD789062 PD789062 4 KB 1 ch 1 ch 1 ch 1 ch - - - 1.8 V µPD789177 PD789177 - 22 - 14 RC oscillation version - - 8 ch 1 ch (UART: 1 ch) - 31 - 4 ch 4 ch - - 4 ch µPD789124A PD789124A 4 ch - µPD789114A PD789114A - 4 ch 4 ch - - - 3 ch 1.8 V 20 µPD789104A PD789104A µPD789167 PD789167 µPD789156 PD789156 µPD789146 PD789146 16 KB to 24 KB 3 ch 8 KB to 16 KB 1 ch 1 ch 1 ch 1 ch 8 ch - µPD789134A PD789134A 2 KB to 8 KB LCD drive µPD789835 PD789835 24 KB to 60 KB 6 ch - µPD789830 PD789830 24 KB 1 ch 1 ch µPD789489 PD789489 32 KB to 48 KB 3 ch µPD789479 PD789479 24 KB to 48 KB 1 ch 1 ch - 1 ch (UART: 1 ch) - 37 1.8 VNote Dot LCD supported 30 2.7 V 45 1.8 V - - 8 ch - On-chip EEPROM RC oscillation version 8 ch 2 ch (UART: 1 ch) µPD789417A PD789417A 12 KB to 24 KB µPD789407A PD789407A 7 ch 1 ch (UART: 1 ch) - 43 - 6 ch 30 6 ch - µPD789436 PD789436 - 6 ch µPD789426 PD789426 6 ch - µPD789456 PD789456 µPD789446 PD789446 µPD789316 PD789316 12 KB to 16 KB 7 ch 2 ch - 8 KB to 16 KB 40 2 ch (UART: 1 ch) 23 µPD789306 PD789306 µPD789467 PD789467 RC oscillation version - 4 KB to 24 KB µPD789327 PD789327 - - 1 ch - Note Flash memory version: 3.0 V 4 - 24 µPD789052 PD789052 Smallscale package, generalpurpose applications and A/D converter Remarks MIN. Value Subseries Name Smallscale package, generalpurpose applications VDD Data Sheet U16524EJ1V0DS U16524EJ1V0DS 1 ch 18 21 µPD78E9860A PD78E9860A, 78E9861A 78E9861A Series for ASSP Function ROM Capacity Timer 8-Bit 16-Bit Watch WDT 8-Bit 10-Bit A/D A/D Serial Interface I/O µPD789800 PD789800 8 KB 2 ch Inverter control µPD789842 PD789842 8 KB to 16 KB 3 ch Note 1 1 ch On-chip bus controller µPD789850 PD789850 16 KB 1 ch 1 ch Keyless entry µPD789861 PD789861 4 KB 2 ch - - - 1 ch - - 2 ch (USB: 1 ch) 31 4.0 V - 1 ch 8 ch - 1 ch (UART: 1 ch) 30 4.0 V - - 1 ch 4 ch - 2 ch (UART: 1 ch) 18 4.0 V - - 1 ch - - - 14 1.8 V RC oscillation version, onchip EEPROM µPD789860 PD789860 µPD789862 PD789862 16 KB VFD drive µPD789871 PD789871 4 KB to 8 KB 3 ch Meter control µPD789881 PD789881 16 KB 1 ch 2 ch Remarks MIN. Value Subseries Name USB VDD 2 ch 1 ch (UART: 1 ch) On-chip EEPROM 22 - 1 ch 1 ch - - 1 ch 33 1 ch - 1 ch - - 1 ch (UART: 1 ch) 28 2.7 V 2.7 V Note 2 - - Notes 1. 10-bit timer: 1 channel 2. Flash memory version: 3.0 V Data Sheet U16524EJ1V0DS U16524EJ1V0DS 5 µPD78E9860A PD78E9860A, 78E9861A 78E9861A OVERVIEW OF FUNCTIONS Part Number µPD78E9860A PD78E9860A Item Internal memory Program memory EEPROM 4 KB Data memory High-speed RAM 128 bytes EEPROM µPD78E9861A PD78E9861A 32 bytes Oscillator Ceramic/crystal oscillator RC oscillator Minimum instruction execution time 0.4 µs/1.6 µs (@ fX = 5.0 MHz operation) 2.0 µs/8.0 µs (@ fCC = 1.0 MHz operation) General-purpose registers 8 bits × 8 registers Instruction set · 16-bit operation · Bit manipulation (set, reset, test) etc. I/O ports Total: 14 CMOS I/O: 10 CMOS input: 4 Timer · 8-bit timer/event counter: 1 channel · 8-bit timer: 1 channel · Watchdog timer: 1 channel Power-on-clear circuit POC circuit Generates internal reset signal according to comparison of detection voltage to power supply voltage LVI circuit Generates interrupt request signal according to comparison of detection voltage to power supply voltage Bit sequence buffer 8 bits × 8 bits = 16 bits Key return function Generates key return signal according to falling edge detection Vectored interrupt sources Maskable Internal: 5 Non-maskable Internal: 1, External: 1 Power supply voltage Operating ambient temperature TA = ­40 to +85°C Package 6 VDD = 1.8 to 5.5 V (µPD78E9860A PD78E9860A) VDD = 1.8 to 3.6 V (µPD78E9861A PD78E9861A) 20-pin plastic SSOP (7.62 mm (300) Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A CONTENTS 1. PIN CONFIGURATION (TOP VIEW).9 2. BLOCK DIAGRAM .10 3. PIN FUNCTIONS .11 3.1 Port Pins .11 3.2 Non-Port Pins .11 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins .12 4. CPU ARCHITECTURE .13 4.1 Memory Space.13 4.2 Data Memory Addressing.14 4.3 Processor Registers .15 5. EEPROM (DATA MEMORY) .18 5.1 EEPROM Functions .18 5.2 EEPROM Configuration .18 5.3 Register That Controls EEPROM.18 5.4 Cautions for EEPROM Writing .21 6. PERIPHERAL HARDWARE FUNCTIONS .23 6.1 Ports.23 6.2 Clock Generator (µPD78E9860A PD78E9860A).26 6.3 Clock Generator (µPD78E9861A PD78E9861A).28 6.4 8-Bit Timer/Event Counter.30 6.5 Watchdog Timer.39 6.6 Power-on-Clear Circuits .42 6.7 Bit Sequential Buffer .47 6.8 Key Return Circuit .49 7. INTERRUPT FUNCTIONS .50 7.1 Types of Interrupt Functions .50 7.2 Sources and Configuration of Interrupts.50 7.3 Registers That Control Interrupt Functions .52 8. STANDBY FUNCTION .54 8.1 Standby Function.54 8.2 Register That Controls Standby Function (µPD78E9860A PD78E9860A Only).56 9. RESET FUNCTION.57 10. EEPROM (PROGRAM MEMORY) .59 10.1 Programming Environment.59 10.2 Communication Mode .60 10.3 On-Board Pin Processing .63 10.4 Connection of Adapter for EEPROM Writing.66 Data Sheet U16524EJ1V0DS U16524EJ1V0DS 7 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 11. INSTRUCTION SET SUMMARY . 68 11.1 Conventions . 68 11.2 List of Operations . 70 12. ELECTRICAL SPECIFICATIONS . 75 13. PACKAGE DRAWING. 87 14. RECOMMENDED SOLDERING CONDITIONS . 88 APPENDIX A. DIFFERENCES BETWEEN EEPROM PRODUCTS AND MASK ROM PRODUCTS. 89 APPENDIX B. DEVELOPMENT TOOLS . 90 APPENDIX C. RELATED DOCUMENTS. 92 8 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A 1. PIN CONFIGURATION (TOP VIEW) · 20-pin plastic SSOP (7.62 mm (300 ) ) µPD78E9860AMC-5A4 PD78E9860AMC-5A4 µPD78E9861AMC-5A4 PD78E9861AMC-5A4 RESET 1 20 P21/TMI P21/TMI X1(CL1) 2 19 P20/TMO/BSFO P20/TMO/BSFO X2(CL2) 3 18 P07 VSS 4 17 P06 VPP 5 16 P05 VDD 6 15 P04 P00 7 14 P43/KR13 P43/KR13 P01 8 13 P42/KR12 P42/KR12 P02 9 12 P41/KR11 P41/KR11 P03 10 11 P40/KR10 P40/KR10 Caution Connect the VPP pin directly to VSS. Remark Pin connections in parentheses apply to the µPD78E9861A PD78E9861A. BSFO: Bit Sequential Buffer Output TMI: Timer Input CL1, CL2: RC Oscillator TMO: Timer Output KR10 to KR13: Key Return VDD: Power Supply P00 to P07: Port 0 VPP: Programming Power Supply P20, P21: Port 2 VSS: Ground P40 to P43: Port 4 X1, X2: Crystal/Ceramic Oscillator RESET: Reset Data Sheet U16524EJ1V0DS U16524EJ1V0DS 9 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 2. BLOCK DIAGRAM Port 0 P00 to P07 Port 2 P20, P21 Port 4 P40 to P43 Cascaded 8-bit 16-bit timer 30 timer TMI/P21 TMI/P21 TMO/P20 TMO/P20 BSFO BSFO/P20 BSFO/P20 TMO 8-bit timer/ counter event counter 40 EEPROM 78K/0S 78K/0S CPU core (program memory) Bit seq. buffer System control Watchdog timer RAM KR10/P40 KR10/P40 to KR13/P43 KR13/P43 Key return 10 10 Power Power on on clear clear Low voltage indicator VDD Remark EEPROM (data memory) VSS VPP Items in parentheses apply to the µPD78E9861A PD78E9861A. Data Sheet U16524EJ1V0DS U16524EJ1V0DS RESET X1 (CL1) X2 (CL2) µPD78E9860A PD78E9860A, 78E9861A 78E9861A 3. PIN FUNCTIONS 3.1 Port Pins Pin Name I/O Function After Reset P00 to P07 I/O Port 0 8-bit I/O port Input/output can be specified in 1-bit units. Input P20 I/O Port 2 2-bit I/O port Input/output can be specified in 1-bit units. Input Port 4 4-bit input-only port Input Alternate Function P21 P40 to P43 3.2 Input - TMO/BSFO TM1 KR10 to KR13 Non-Port Pins Pin Name I/O Function After Reset Alternate Function TMI Input 8-bit timer (TM40) input Input P21 TMO Output 8-bit timer (TM40) output Input P20/BSFO P20/BSFO BSFO Output Bit sequential buffer (BSF10 BSF10) output Input P20/TMO P20/TMO KR10 to KR13 Input Key return input Input P40 to P43 X1Note 1 Input Connecting ceramic/crystal resonator for system clock oscillation X2Note 1 CL1Note 2 Input Note 2 CL2 RESET - Input System reset input - - - - Connecting resistor (R) and capacitor (C) for system clock oscillation - - - - - Input - VDD - Positive power supply - - VSS - Ground potential - - VPP - EEPROM programming mode setting. High-voltage application during programming write/verify. - - Notes 1. µPD78E9860A PD78E9860A only. 2. µPD78E9861A PD78E9861A only. Data Sheet U16524EJ1V0DS U16524EJ1V0DS 11 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type for each pin and recommended connections of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins Pin Name Input/Output Circuit Type P00 to P07 5 P20/TMO/BSFO P20/TMO/BSFO I/O 8 Recommended Connection of Unused Pins Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. I/O P21/TMI P21/TMI P40/KR10 P40/KR10 to P43/KR13 P43/KR13 Connect directly to VDD. 2 RESET - VPP - - Connect directly to VSS. Independently connect to a 10 k pull-down resistor or connect directly to VSS. Figure 3-1. Pin Input/Output Circuits Type 2 Type 8 VDD Data P-ch IN/OUT IN Output disable Schmitt triggered input with hysteresis characteristics Type 5 VDD Data P-ch IN/OUT Output disable N-ch VSS Input enable 12 Data Sheet U16524EJ1V0DS U16524EJ1V0DS N-ch VSS µPD78E9860A PD78E9860A, 78E9861A 78E9861A 4. CPU ARCHITECTURE 4.1 Memory Space The µPD78E9860A PD78E9860A and µPD78E9861A PD78E9861A can each access a 64 KB memory space. Figure 4-1 shows the memory map. Figure 4-1. Memory Map FFFFH Special function registers 256 × 8 bits FF00H FF00H FEFFH Internal high-speed RAM 128 × 8 bits FE80H FE80H FE7FH Reserved Data memory space F820H F820H F81FH F81FH EEPROM 32 × 8 bits F800H F800H F7FFH Reserved 0FFFH 1000H 1000H 0FFFH Program area 0080H 0080H 007FH 007FH Program memory space EEPROM 4096 × 8 bits CALLT table area 0040H 0040H 003FH 003FH Program area 000EH 000EH 000DH 000DH 0000H 0000H 0000H 0000H Data Sheet U16524EJ1V0DS U16524EJ1V0DS Vector table area 13 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 4.2 Data Memory Addressing The µPD78E9860A PD78E9860A and µPD78E9861A PD78E9861A provide ample addressing modes that take into account the manipulation of memory. Addressing peculiar to the special function registers (SFRs) and other functions is possible in on-chip data memory areas (FE80H FE80H to FFFFH) in particular. Figure 4-2 shows data memory addressing. Figure 4-2. Data Memory Addressing FFFFH Special function registers (SFRs) 256 × 8 bits SFR addressing FF20H FF20H FF1FH FF00H FF00H FEFFH Internal high-speed RAM 128 × 8 bits Short direct addressing FE80H FE80H FE7FH Reserved Direct addressing Register indirect addressing Based addressing F820H F820H F81FH F81FH EEPROM 32 × 8 bits F800H F800H F7FFH Reserved 1000H 1000H 0FFFH EEPROM 4096 × 8 bits 0000H 0000H 14 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A 4.3 Processor Registers 4.3.1 Control registers (1) Program counter (PC) The program counter is a 16-bit register that maintains address information about the program to be executed next. Figure 4-3. Configuration of Program Counter 15 0 PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 (2) Program status word (PSW) The program status word is an 8-bit register that shows the status of the CPU in terms of the results of instruction execution. Figure 4-4. Configuration of Program Status Word 7 PSW IE 0 Z 0 AC 0 0 1 CY (a) Interrupt enable flag (IE) The interrupt enable flag is a flag that controls CPU interrupt request acknowledgement operations. (b) Zero flag (Z) The zero flag is a flag that is set (1) when the result of an operation is zero and that is reset (0) otherwise. (c) Auxiliary carry flag (AC) The auxiliary carry flag is a flag that is set (1) when there is a carry from bit 3 or a borrow to bit 3 as a result of an operation and that is reset (0) otherwise. (d) Carry flag (CY) The carry flag is a flag that stores an overflow or underflow when an addition or subtraction instruction is executed. (3) Stack pointer (SP) The stack pointer is a 16-bit register that maintains the starting address of the stack area of memory. Only the internal high-speed RAM area (FE80H FE80H to FEFFH) can be set as the stack area. Figure 4-5. Configuration of Stack Pointer 15 0 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Caution Because stack pointer contents become undefined when RESET input, be sure to initialize the SP before executing an instruction. Data Sheet U16524EJ1V0DS U16524EJ1V0DS 15 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 4.3.2 General-purpose registers The general-purpose registers consist of eight 8-bit registers (X, A, C, B, E, D, L, H). Besides each register being usable as an 8-bit register, it is possible to pair two 8-bit registers and use them as a 16-bit register (AX, BC, DE, HL). Moreover, in addition to function names (X, A, C, B, E, D, L, H, AX, BC, DE, HL), general-purpose registers can also be described using absolute names (R0 to R7 and RP0 to RP3). Figure 4-6. Configuration of General-Purpose Registers (a) Absolute names 16-bit processing 8-bit processing R7 RP3 R6 R5 RP2 R4 R3 RP1 R2 R1 RP0 R0 15 0 7 0 (b) Function names 16-bit processing 8-bit processing H HL L D DE E B BC C A AX X 15 16 0 7 Data Sheet U16524EJ1V0DS U16524EJ1V0DS 0 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 4.3.3 Special function registers (SFRs) The special function registers are registers such as peripheral hardware mode registers and control registers that have special functions. They are mapped to the 256-byte space from FF00H FF00H to FFFFH. Note that bits whose names are reserved words in the RA78K0S RA78K0S or defined in the header file sfrbit.h in the CC78K0S CC78K0S have their bit number encircled in each register format. Refer to each register format in 6. PERIPHERAL HARDWARE FUNCTIONS. Table 4-1. List of Special Function Registers Bit Unit for Manipulation Address Special Function Register (SFR) Name Symbol R/W 1 bit 8 bits 16 bits - After Reset - FF00H FF00H Port 0 P0 FF02H FF02H Port 2 P2 FF04H FF04H Port 4 P4 R - FF10H FF10H Bit sequential buffer 10 data register L BSFRL10 BSFRL10 W - Note 1 FF11H FF11H Bit sequential buffer 10 data register H BSFRH10 BSFRH10 - FF20H FF20H Port mode register 0 PM0 - FF22H FF22H Port mode register 2 PM2 - FF42H FF42H Timer clock select register 2 TCL2 - - 00H FF50H FF50H 8-bit compare register 30 CR30 W - - Undefined FF51H FF51H 8-bit timer counter 30 TM30 R - - 00H FF52H FF52H 8-bit timer mode control register 30 TMC30 TMC30 R/W - FF53H FF53H 8-bit compare register 40 CR40 W - - FF54H FF54H 8-bit compare register H40 CRH40 CRH40 - - FF55H FF55H 8-bit timer counter 40 TM40 R - - FF56H FF56H 8-bit timer mode control register 40 TMC40 TMC40 R/W - FF57H FF57H Carrier generator output control register 40 TCA40 TCA40 W - - FF60H FF60H Bit sequential buffer output control register 10 BSFC10 BSFC10 R/W - FFD8H EEPROM write control register 10 EEWC10 EEWC10 - 08H FFDDH Power-on-clear register 1 POCF1 - 00HNote 2 FFDEH Low-voltage detection register 1 LVIF1 - 00H FFDFH Low-voltage detection level selection register 1 LVIS1 - FFE0H Interrupt request flag register 0 IF0 - FFE4H Interrupt mask flag register 0 MK0 - FFH WDTM - 00H FFFAH Oscillation stabilization time selection register OSTS - - 04H FFFBH Processor clock control register PCC - 02H FFF9H Watchdog timer mode register Note 3 R/W R/W 00H Undefined FFH Undefined 00H Notes 1. Specify address FF10H FF10H directly for 16-bit access. 2. This value is 04H only after a power-on-clear reset. 3. µPD78E9860A PD78E9860A only. Data Sheet U16524EJ1V0DS U16524EJ1V0DS 17 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 5. EEPROM (DATA MEMORY) 5.1 EEPROM Functions Besides internal high-speed RAM, the µPD78E9860A PD78E9860A and µPD78E9861A PD78E9861A have 32 × 8 bits of electrically erasable PROM (EEPROM) on-chip as data memory and 4096 × 8 bits of EEPROM as program memory. This section describes the EEPROM used as data memory (for EEPROM used as program memory, refer to 10. EEPROM (PROGRAM MEMORY). Unlike normal RAM, EEPROM can maintain its contents even if its power supply is cut. In addition, unlike EPROM, its electrical contents can be erased without using ultraviolet rays. EEPROM operations are performed using 8-bit memory manipulation instructions. 5.2 EEPROM Configuration EEPROM consists of the EEPROM itself and a control section. The control section consists of EEPROM write control register 10 (EEWC10 EEWC10) which controls EEPROM writing and a part that detects the termination of writing and generates an interrupt request signal (INTEE0). Figure 5-1. EEPROM Block Diagram Internal bus EEPROM write control register 10 (EEWC10 EEWC10) Data latch EWCS102 EWCS102 EWCS101 EWCS101 EWCS100 EWCS100 ERE10 ERE10 EWST10 EWST10 EWE10 EWE10 fX/23 to fX/28 EEPROM timer Prescaler 8-bit timer 40 output Address latch EEPROM (32 × 8 bits) Read/write controller INTEE0 5.3 Register That Controls EEPROM EEPROM is controlled by EEPROM write control register 10 (EEWC10 EEWC10). EEWC10 EEWC10 is the register that sets the EEPROM count clock selection, and EEPROM write control. Set EEWC10 EEWC10 using 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 08H. Figure 5-2 shows the format of EEPROM write control register 10. Tables 5-1 and 5-2 show EEPROM write times. 18 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A Figure 5-2. Format of EEPROM Write Control Register 10 Symbol 7 EEWC10 EEWC10 0 6 5 4 3 1 EWCS102 EWCS102 EWCS101 EWCS101 EWCS100 EWCS100 ERE10 ERE10 EWST10 EWST10 EWE10 EWE10 Address After reset FFD8H 08H R/W R/WNote EEPROM timer count clock selection EWCS102 EWCS102 EWCS101 EWCS101 EWCS100 EWCS100 When operating at fX = 5.0 MHz 3 When operating at fCC = 1.0 MHz 0 0 0 fX/2 (625 kHz) fCC/23 (125 kHz) 0 0 1 fX/24 (313 kHz) fCC/24 (62.5 kHz) 0 1 0 fX/25 (156 kHz) fCC/25 (31.3 kHz) 0 1 1 fX/26 (78.1 kHz) fCC/26 (15.6 kHz) 1 0 0 fX/27 (39.1 kHz) fCC/27 (7.81 kHz) 1 0 1 fX/28 (19.5 kHz) fCC/28 (3.91 kHz) 1 1 0 Output of 8-bit timer 40 1 1 1 Setting prohibited ERE10 ERE10 EWE10 EWE10 Write 0 0 Disabled Disabled 0 1 Setting prohibited 1 0 Disabled Enabled 1 1 Enabled Enabled Read Remarks EEPROM is in standby state (low power consumption mode) EWST10 EWST10 EEPROM write status flag 0 Not writing to EEPROM (EEPROM can be read or written. However, writing is disabled if EWE10 EWE10 = 0.) 1 Writing to EEPROM (EEPROM cannot be read or written.) Note Bit 1 is read only. Caution Be sure to set bit 3 to 1 and bit 7 to 0. Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: System clock oscillation frequency (RC oscillation) Data Sheet U16524EJ1V0DS U16524EJ1V0DS 19 µPD78E9860A PD78E9860A, 78E9861A 78E9861A Table 5-1. EEPROM Write Time (When Operating at fX = 5.0 MHz) EEPROM Timer Count Clock EEPROM Data Write TimeNote 1 EWCS102 EWCS102 EWCS101 EWCS101 EWCS100 EWCS100 0 0 0 fX/23 (625 kHz) 23/fX × 145 (setting prohibited)Note 2 0 0 1 fX/24 (313 kHz) 24/fX × 145 (setting prohibited)Note 2 0 1 0 fX/25 (156 kHz) 25/fX × 145 (setting prohibited)Note 2 0 1 1 fX/26 (78.1 kHz) 26/fX × 145 (setting prohibited)Note 2 1 0 0 fX/27 (39.1 kHz) 27/fX × 145 (3.71 ms) 1 0 1 fX/28 (19.5 kHz) 28/fX × 145 (setting prohibited)Note 2 1 1 0 Output of 8-bit timer 40 (Output of 8-bit timer 40) × 145 1 1 1 Setting prohibited Notes 1. Be sure to set the EEPROM write time within the range of 3.3 to 6.6 ms. The spec values of EEPROM write time are target values in the product development stage. Since they may change after evaluation, be sure to refer to the data sheet created after evaluation when designing. 2. Setting is prohibited because the condition that an EEPROM write time must be between 3.3 and 6.6 ms is not satisfied. Remark fX: System clock oscillation frequency (ceramic/crystal oscillation) Table 5-2. EEPROM Write Time (When Operating at fCC = 1.0 MHz) EEPROM Timer Count Clock EEPROM Data Write TimeNote 1 EWCS102 EWCS102 EWCS101 EWCS101 EWCS100 EWCS100 0 0 0 fCC/23 (12.5 kHz) 23/fCC × 145 (setting prohibited)Note 2 0 0 1 fCC/24 (62.5 kHz) 24/fCC × 145 (setting prohibited)Note 2 0 1 0 fCC/25 (31.3 kHz) 25/fCC × 145 (4.64 ms) 0 1 1 fCC/26 (15.6 kHz) 26/fCC × 145 (setting prohibited)Note 2 1 0 0 fCC/27 (7.81 kHz) 27/fCC × 145 (setting prohibited)Note 2 1 0 1 fCC/28 (3.91 kHz) 28/fCC × 145 (setting prohibited)Note 2 1 1 0 Output of 8-bit timer 40 (Output of 8-bit timer 40) × 145 1 1 1 Setting prohibited Notes 1. Be sure to set the EEPROM write time within the range of 3.3 to 6.6 ms. The spec values of EEPROM write time are target values in the product development stage. Since they may change after evaluation, be sure to refer to the data sheet created after evaluation when designing. 2. Setting is prohibited because the condition that an EEPROM write time must be between 3.3 and 6.6 ms is not satisfied. Remark 20 fCC: System clock oscillation frequency (RC oscillation) Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A 5.4 Cautions for EEPROM Writing The following cautions pertain to writing to EEPROM. (1) When fetching an instruction from EEPROM or stopping the system clock oscillator, be sure to do so after setting EEPROM to write-disabled (EWE10 EWE10 = 0). (2) Set the count clock in a state in which the selected clock is operating (oscillating). If the selected count clock is stopped, there is no transition to the state in which writing is possible even if the clock operation is subsequently started and EEPROM is set to write-enabled (EWE10 EWE10 = 1). (3) Be sure to set the EEPROM write time within the range of 3.3 to 6.6 ms. (4) When setting ERE10 ERE10 and EWE10 EWE10, be sure to use the following procedure. If you set these using other than the following procedure, there is no transition to the state in which writing to EEPROM is possible. Set ERE10 ERE10 to 1 (In a state in which EWE10 EWE10 = 0) Set EWE10 EWE10 to 1 (In a state in which ERE10 ERE10 = 1) Wait 1 ms or more using software Shift to state in which writing to EEPROM is possible ERE10 ERE10 A EWE10 EWE10 1 ms or more B D C A (ERE10 ERE10 = 1): Transition to state in which reading is possible B (EWE10 EWE10 = 1):Set count clock before this point. C: Transition to state in which writing is possible D: When ERE10 ERE10 is cleared (ERE10 ERE10 = 0), EWE10 EWE10 is also cleared (EWE10 EWE10 = 0). Reading or writing is not possible in this state. (5) When performing a write to EEPROM, execute it after confirming that EWST10 EWST10 = 0. If a write is executed to EEPROM when EWST10 EWST10 = 1, the instruction is ignored. Data Sheet U16524EJ1V0DS U16524EJ1V0DS 21 µPD78E9860A PD78E9860A, 78E9861A 78E9861A (6) Do not execute the following operations while writing to EEPROM, as execution will cause the EEPROM cell value at that address to become undefined. · Turn off the power · Execute a reset · Set ERE10 ERE10 to 0 · Set EWE10 EWE10 to 0 · Switch the EEPROM timer count clock (7) Do not execute the following operation while writing to EEPROM after selecting system clock division for the EEPROM timer count clock, as execution will cause the EEPROM cell value at that address to become undefined. · Execute a STOP instruction (8) Do not execute the following operations while writing to EEPROM after selecting 8-bit timer 40 output for the EEPROM timer count clock, as execution will cause the EEPROM cell value at that address to become undefined. · Execute a STOP instruction · Stop 8-bit timer 40 timer output · Stop 8-bit timer 40 operation (9) Do not execute the following operations while writing to or reading from EEPROM, as execution will cause the EEPROM data read next to become undefined, and a CPU runaway could result. · Set ERE10 ERE10 to 0 · Execute a write to EEPROM (10) When not writing to or reading from EEPROM, it is possible to enter low-power consumption mode by setting ERE10 ERE10 to 0. In the ERE10 ERE10 = 1 state, a current of about 0.27 mA (VDD = 3.6 V) is always flowing. If an instruction to read from EEPROM is then executed, a further 0.9 mA current will flow, increasing the total current flow at this time to approximately 1.17 mA (VDD = 3.6 V). In the ERE10 ERE10 = 1, EWE10 EWE10 = 1 state, a current of about 0.3 mA (VDD = 3.6 V) is always flowing. If an instruction to write to EEPROM is then executed, a further 0.7 mA current will flow, and if an instruction to read from EEPROM is executed, a further 0.9 mA current will flow, increasing the total current flow at this time to approximately 1.0 mA (VDD = 3.6 V) for the former case and 1.2 mA (VDD = 3.6 V) for the latter (refer to EEPROM Characteristics in 12. ELECTRICAL SPECIFICATIONS for details). (11) Execution of a STOP instruction causes an automatic change to low-power consumption mode, regardless of the ERE10 ERE10 and EWE10 EWE10 settings. The states of ERE10 ERE10 and EWE10 EWE10 at the time are maintained. During the wait time following STOP mode release, a current of approximately 300 µA (VDD = 3.6 V) flows. Executing a HALT instruction does not change the mode to low-power consumption mode. 22 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6. PERIPHERAL HARDWARE FUNCTIONS 6.1 Ports 6.1.1 Port functions The µPD78E9860A PD78E9860A and µPD78E9861A PD78E9861A are provided with the ports shown in Table 6-1, by which many kinds of control are possible. Moreover, these have a variety of alternate functions besides their functions as digital input/output ports. Refer to 3. PIN FUNCTIONS for details of the alternate functions. Table 6-1. Port Functions Name Pin Name Function Port 0 P00 to P07 I/O port. Input/output can be specified in 1-bit units. Port 2 P20, P21 I/O port. Input/output can be specified in 1-bit units. Port 4 P40 to P43 Input-only port. 6.1.2 Port Configuration A port consists of the following hardware. Table 6-2. Port Configuration Item Configuration Control register Port mode register (PMm: m = 0, 2) Port Total: 14 (CMOS input/output: 10, CMOS input: 4) Data Sheet U16524EJ1V0DS U16524EJ1V0DS 23 µPD78E9860A PD78E9860A, 78E9861A 78E9861A Figure 6-1. Basic Configuration of CMOS Port RDPORT Internal bus Selector WRPORT Output latch Pmn Pmn WRPM PMmn Caution Figure 6-1 is the basic configuration of a CMOS I/O port. The configuration varies according to the functions of alternate-function pins. Remark PMmn: Bit n of port mode register m (m = 0, 2 n = 0 to 7) Pmn: Port read signal WR: 24 Bit n of port m RD: Port write signal Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.1.3 Registers that control port functions A port is controlled using the following registers. · Port mode registers (PM0, PM2) (1) Port mode registers (PM0, PM2) The port mode registers are registers that set the port to input or output in 1-bit units. Each port mode register can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets these registers to FFH. When using a port pin as an alternate-function pin, set the port mode registers and output latch as shown in Table 6-3. Figure 6-2. Port Mode Register Format Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00 FF20H FF20H FFH R/W PM2 1 1 1 1 1 1 PM21 PM20 FF22H FF22H FFH R/W Selection of Pmn pin input/output mode (m = 0, 2 n = 0 to 7) PMmn 0 Output mode (Output buffer on) 1 Input mode (Output buffer off) Table 6-3. Port Mode Register and Output Latch Settings When Using Alternate Functions Alternate Function Pin Name PM×× Name P20 P×× I/O TMO Remark 0 Output 0 0 TMI ×: 0 BSFO P21 Output Input 1 × don't care PM××: Port mode register P××: Port output latch Data Sheet U16524EJ1V0DS U16524EJ1V0DS 25 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.2 Clock Generator (µPD78E9860A PD78E9860A) The clock generator specifications differ for the µPD78E9860A PD78E9860A and µPD78E9861A PD78E9861A. When using the µPD78E9861A PD78E9861A, refer to 6.3 Clock Generator (µPD78E9861A PD78E9861A). 6.2.1 Clock generator functions The clock generator is a circuit that generates the clocks that are provided to the CPU and peripheral hardware. · System clock oscillator (ceramic/crystal oscillation) Oscillates at frequency from 1.0 to 5.0 MHz. Oscillation can be stopped by executing the STOP instruction. 6.2.2 Configuration of clock generator The clock generator consists of the following hardware. Table 6-4. Configuration of Clock Generator Item Configuration Control register Processor clock control register (PCC) Oscillator System clock oscillator Figure 6-3. Clock Generator Block Diagram Prescaler Clock to peripheral hardware X2 System clock oscillator fX Prescaler fX 22 Selector X1 Standby controller Wait controller STOP PCC0 Processor clock control register (PCC) Internal bus 26 Data Sheet U16524EJ1V0DS U16524EJ1V0DS CPU clock (fCPU) µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.2.3 Register that controls clock generator The clock generator is controlled by the following register. · Processor clock control register (PCC) (1) Processor clock control register (PCC) The processor clock control register is a register that sets the CPU clock selection and division ratio. PCC can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 02H. Figure 6-4. Format of Processor Clock Control Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PCC 0 0 0 0 0 0 PCC0 0 FFFBH R/W PCC0 CPU clock (fCPU) selection 02H Minimum instruction execution time: 2/fCPU When operating at fX = 5.0 MHz 0 1 0.4 µs fX 1.6 µs 2 fX/2 Caution Be sure to set bits 0 and 2 to 7 to 0. Remark fX: System clock oscillation frequency (ceramic/crystal oscillator) Data Sheet U16524EJ1V0DS U16524EJ1V0DS 27 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.3 Clock Generator (µPD78E9861A PD78E9861A) 6.3.1 Clock generator functions The clock generator is a circuit that generates the clocks that are provided to the CPU and peripheral hardware. · System clock oscillator (RC oscillation) Oscillates at a frequency of 1.0 MHz ±15%. Oscillation can be stopped by executing the STOP instruction. 6.3.2 Configuration of clock generator The clock generator consists of the following hardware. Table 6-5. Configuration of Clock Generator Item Configuration Control register Processor clock control register (PCC) Oscillator System clock oscillator Figure 6-5. Clock Generator Block Diagram Prescaler Clock to peripheral hardware X2 System clock oscillator fCC Prescaler fCC 22 Selector X1 Standby controller Wait controller STOP PCC0 Processor clock control register (PCC) Internal bus 28 Data Sheet U16524EJ1V0DS U16524EJ1V0DS CPU clock (fCPU) µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.3.3 Register that controls clock generator The clock generator is controlled by the following register. · Processor clock control register (PCC) (1) Processor clock control register (PCC) The processor clock control register is a register that sets the CPU clock selection and division ratio. PCC can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 02H. Figure 6-6. Format of Processor Clock Control Register Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PCC 0 0 0 0 0 0 PCC0 0 FFFBH R/W PCC0 CPU clock (fCPU) selection 02H Minimum instruction execution time: 2/fCPU When operating at fCC = 1.0 MHz 0 1 2.0 µs fCC 8.0 µs 2 fCC/2 Caution Be sure to set bits 0 and 2 to 7 to 0. Remark fCC: System clock oscillation frequency (RC oscillation) Data Sheet U16524EJ1V0DS U16524EJ1V0DS 29 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.4 8-Bit Timer/Event Counter 6.4.1 8-bit timer/event counter functions The µPD78E9860A PD78E9860A and 78E9861A 78E9861A have on chip an 8-bit timer (Timer 30) (1 channel) and an 8-bit timer/event counter (Timer 40) (1 channel). The operation modes shown in the table below are possible by means of mode register settings. Table 6-6. Mode List Channel Timer 30 Timer 40 Mode 8-bit timer counter mode (discrete mode) 16-bit timer counter mode (cascade connection mode) Carrier generator mode × PWM output mode (1) 8-bit timer counter mode (discrete mode) The following functions can be used. · 8-bit resolution interval timer · 8-bit resolution external event timer (Timer 40 only) · 8-bit resolution square wave output (Timer 40 only) (2) 16-bit timer counter mode (cascade connection mode) Operates as a 16-bit timer/event counter due to cascade connection. The following functions can be used. · 16-bit resolution interval timer · 16-bit resolution external event counter · 16-bit resolution square wave output (3) Carrier generator mode In this mode, the carrier clock generated by timer 40 is output in the cycle set by timer 30. (4) PWM output mode Outputs a pulse of an arbitrary duty factor set by timer 40. 30 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.4.2 8-bit timer/event counter configuration The 8-bit timer/event counter consists of the following hardware. Table 6-7. Configuration of 8-Bit Timer/Event Counter Item Configuration Timer counter 8 bits × 2 (TM30, TM40) Registers Compare registers: 8 bits × 3 (CR30, CR40, CRH40 CRH40) Timer output 1 (TMO) Control registers 8-bit timer mode control register 30 (TMC30 TMC30) 8-bit timer mode control register 40 (TMC 40) Carrier generator output control register 40 (TCA40 TCA40) Port mode register 2 (PM2) Port 2 (P2) Data Sheet U16524EJ1V0DS U16524EJ1V0DS 31 32 Figure 6-7. 8-Bit Timer 30 Block Internal bus 8-bit timer mode control register 30 (TMC30 TMC30) TCE30 TCE30 TCL302 TCL302 TCL301 TCL301 TCL300 TCL300 TMD301 TMD301 TMD300 TMD300 8-bit compare register 30 (CR30) Decoder Selector Match Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) (From Figure 6-8 (C) Selector Data Sheet U16524EJ1V0DS U16524EJ1V0DS fCLK/26 fCLK/28 Timer 40 interrupt request signal (From Figure 6-8 (B) Selector Bit 7 of TM40 (From Figure 6-8 (A) 8-bit timer counter 30 (TM30) OVF Clear Internal reset signal Selector Cascade connection mode INTTM30 INTTM30 To Figure 6-8 (G) From Figure 6-8 (E) Timer 40 match signal (in cascade connection mode) Timer 30 match signal (in carrier generator mode) To Figure 6-8 (F) Timer 30 match signal (in cascade connection mode) Remark fCLK: fX or fCC µ µ µPD78E9860A PD78E9860A, 78E9861A 78E9861A µ From Figure 6-8 (D) Count operation start signal (in cascade connection mode) Figure 6-8. 8-Bit Timer 40 Block Internal bus 8-bit timer mode control register 40 (TMC40 TMC40) 8-bit compare register H40 (CRH40 CRH40) TCE40 TCE40 TCL402 TCL402 TCL401 TCL401 TCL400 TCL400 TMD401 TMD401 TMD400 TMD400 TOE40 Carrier generator output control register 40 (TCA40 TCA40) 8-bit compare register 40 (CR40) RMC40 RMC40 NRZB40 NRZB40 NRZ40 NRZ40 Decoder From Figure 6-7 (G) Timer counter match signal from timer 30 (in carrier generator mode) Selector Selector TMI/2 Clear Carrier generator mode TMO/P20/BSFO TMO/P20/BSFO To Figure 6-7 (C) Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) 8-bit timer counter 40 (TM40) TMI/P21 TMI/P21 Prescaler Data Sheet U16524EJ1V0DS U16524EJ1V0DS fCLK fCLK/22 Output controllerNote F/F Match OVF PWM mode Reset TMI/22 TMI/22 Cascade connection mode 3 TMI/2 To Figure 6-7 (A) Bit 7 of TM40 (in cascade connection mode) INTTM40 INTTM40 To Figure 6-7 (D) Count operation start signal to timer 30 (in cascade connection mode) To Figure 6-7 (E) TM40 timer counter match signal (in cascade connection mode) From Figure 6-7 (F) TM30 match signal (in cascade connection mode) Note For details, refer to Figure 6-9. 33 Remark fCLK: fX or fCC To Figure 6-7 (B) Timer 40 interrupt request signal count clock input signal to TM30 µ µ µPD78E9860A PD78E9860A, 78E9861A 78E9861A µ Internal reset signal µPD78E9860A PD78E9860A, 78E9861A 78E9861A Figure 6-9. Block Diagram of Output Controller (Timer 40) TOE40 RMC40 RMC40 NRZ40 NRZ40 P20 output latch PM20 Selector F/F TMO/P20/ TMO/P20/ BSFO Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) Carrier generator mode (1) 8-bit compare register 30 (CR30) This register is an 8-bit register that always compares the count value of 8-bit timer register 30 (TM30) with the value set in CR30 and generates an interrupt request (INTTM30 INTTM30) if they match. CR30 can be set using an 8-bit memory manipulation instruction. RESET input makes this register undefined. Caution CR30 cannot be used in PWM output mode. (2) 8-bit compare register 40 (CR40) This register is an 8-bit register that always compares the count value of 8-bit timer register 40 (TM40) with the value set in CR40 and generates an interrupt request (INTTM40 INTTM40) if they match. In addition, when cascade-connected to TM30 and used as a 16-bit timer/event counter, an interrupt request (INTTM40 INTTM40) is generated only if TM30 matches with CR30 and TM40 matches with CR40 simultaneously (INTTM30 INTTM30 is not generated). CR40 can be set using an 8-bit memory manipulation instruction. RESET input makes this register undefined. (3) 8-bit compare register H40 (CRH40 CRH40) In carrier generator mode or PWM output mode, writing a CRH40 CRH40 value sets the width of high level timer output. CRH40 CRH40 can be set using an 8-bit memory manipulation instruction. RESET input makes this register undefined. (4) 8-bit timer counters 30 and 40 (TM30, TM40) These 8-bit registers count pulse counts. Each of TM30 and TM40 can be read using an 8-bit memory manipulation instruction. RESET input sets these registers to 00H. The conditions under which TM30 and TM40 are cleared to 00H are shown next. 34 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A (a) Discrete mode (i) TM30 · Reset · Clearing of TCE30 TCE30 (bit 7 of 8-bit timer mode control register 30 (TMC30 TMC30) to 0 · Match of TM30 and CR30 · TM30 count value overflow (ii) TM40 · Reset · Clearing of TCE40 TCE40 (bit 7 of 8-bit timer mode control register 40 (TMC40 TMC40) to 0 · Match of TM40 and CR40 · TM40 count value overflow (b) Cascade connection mode (TM30, TM40 simultaneously cleared to 00H) · Reset · Clearing of the TCE40 TCE40 flag to 0 · Simultaneous match of TM30 with CR30 and TM40 with CR40 · TM30 and TM40 count values overflow simultaneously (c) Carrier generator/PWM output mode (TM40 only) · Reset · Clearing of the TCE40 TCE40 flag to 0 · Match of TM40 and CR40 · Match of TM40 and CRH40 CRH40 · TM40 count value overflow 6.4.3 Registers that control 8-bit timer/event counter The 8-bit timer/event counter is controlled by the following three registers. · 8-bit timer mode control register 30 (TMC30 TMC30) · 8-bit timer mode control register 40 (TMC40 TMC40) · Carrier generator output control register 40 (TCA40 TCA40) · Port mode register 2 (PM2) Data Sheet U16524EJ1V0DS U16524EJ1V0DS 35 µPD78E9860A PD78E9860A, 78E9861A 78E9861A (1) 8-bit timer mode control register 30 (TMC30 TMC30) 8-bit timer mode control register 30 (TMC30 TMC30) is the register that controls the setting of the timer 30 count clock and the setting of the operating mode. TMC30 TMC30 can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 6-10. Format of 8-Bit Timer Mode Control Register 30 Symbol 6 5 4 3 2 1 0 TMC30 TMC30 TCE30 TCE30 0 TCL302 TCL302 TCL301 TCL301 TCL300 TCL300 TMD301 TMD301 TMD300 TMD300 0 Address After reset FF52H FF52H 00H R/W R/W TM30 count operation controlNote 1 TCE30 TCE30 0 Clears TM30 count value and halt operation 1 Starts count operation Selection of timer 30 count clock TCL302 TCL302 TCL301 TCL301 TCL300 TCL300 When operating at fX = 5.0 MHz When operating at fCC = 1.0 MHz 0 0 0 fX/26 (78.1 kHz) fCC/26 (15.6 kHz) 0 0 1 fX/28 (19.5 kHz) fCC/28 (3.91 kHz) 0 1 0 Timer 40 match signal 0 1 1 Carrier clock (in carrier generator mode) or timer 40 output signal (in other than carrier generator mode) Other than above Setting prohibited Selection of timer 30, timer 40 operating modeNote 2 TMD301 TMD301 TMD300 TMD300 TMD401 TMD401 TMD400 TMD400 0 0 0 0 Discrete mode 0 1 0 1 Cascade connection mode 0 0 1 1 Carrier generator mode 0 0 1 0 PWM output mode Other than above Setting prohibited Notes 1. In cascade connection mode, since count operations are controlled by TCE40 TCE40 (bit 7 of TMC40 TMC40), TCE30 TCE30 is ignored even if it is set. 2. The selection of operating mode is made by combining the two registers TMC30 TMC30 and TMC40 TMC40. Cautions 1. Be sure to set bits 0 and 6 to 0. 2. In cascade connection mode, timer 40 output signal is forcibly selected for count clock. Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: System clock oscillation frequency (RC oscillation) 36 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A (2) 8-bit timer mode control register 40 (TMC40 TMC40) 8-bit timer mode control register 40 (TMC40 TMC40) is the register that controls the setting of the timer 40 count clock and the setting of the operating mode. TMC40 TMC40 can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 6-11. Format of 8-Bit Timer Mode Control Register 40 Symbol 6 5 4 3 2 1 TMC40 TMC40 TCE40 TCE40 0 TCL402 TCL402 TCL401 TCL401 TCL400 TCL400 TMD401 TMD401 TMD400 TMD400 TOE40 Address After reset FF56H FF56H 00H R/W R/W TM40 count operation controlNote 1 TCE40 TCE40 0 Clears TM40 count value and halt operation (in cascade connection mode, the TM30 count value is simultaneously cleared as well.) 1 Starts count operation (in cascade connection mode, the TM30 count operation is simultaneously started as well.) Selection of timer 40 count clock TCL402 TCL402 TCL401 TCL401 TCL400 TCL400 When operating at fX = 5.0 MHz 0 0 0 fX (5.0 MHz) When operating at fCC = 1.0 MHz fCC (1.0 MHz) 2 fCC/22 (250 MHz) 0 0 1 fX/2 (1.25 MHz) 0 1 0 fTMI 0 1 1 fTMI/2 1 0 0 fTMI/22 1 0 1 fTMI/23 TMD301 TMD301 TMD300 TMD300 TMD401 TMD401 TMD400 TMD400 0 0 0 0 Discrete mode 0 1 0 1 Cascade connection mode 0 0 1 1 Carrier generator mode 0 0 1 0 PWM output mode Other than above Selection of timer 30, timer 40 operating modeNote 2 Setting prohibited TOE40 Timer output control 0 Output disabled 1 Output enabled (port mode) Notes 1. In cascade connection mode, since count operations are controlled by TCE40 TCE40, TCE30 TCE30 (bit 7 of TMC30 TMC30) is ignored even if it is set. 2. The selection of operating mode is made by combining the two registers TMC30 TMC30 and TMC40 TMC40. Remarks. 1. fX: System clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: System clock oscillation frequency (RC oscillation) 3. fTMI: External clock input from TMI/P21 TMI/P21 pin Data Sheet U16524EJ1V0DS U16524EJ1V0DS 37 µPD78E9860A PD78E9860A, 78E9861A 78E9861A (3) Carrier generator output control register 40 (TCA40 TCA40) This register is used to set the timer output data in the carrier generator mode. TCA40 TCA40 is set using an 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 6-12. Format of Carrier Generator Output Control Register 40 Symbol 7 6 5 4 3 2 1 0 TCA40 TCA40 0 0 0 0 0 RMC40 RMC40 NRZB40 NRZB40 NRZ40 NRZ40 RMC40 RMC40 Address After reset FF57H FF57H 00H R/W W Remote controller output control 0 When NRZ40 NRZ40 = 1, a carrier pulse is output to the TMO/P20/BSFO TMO/P20/BSFO pin 1 When NRZ40 NRZ40 = 1, a high level is output to the TMO/P20/BSFO TMO/P20/BSFO pin NRZB40 NRZB40 This bit stores the data that NRZ40 NRZ40 will output next. Data is transferred to NRZ40 NRZ40 upon the generation of a timer 30 match signal. NRZ40 NRZ40 No return, zero data 0 A low level is output (the carrier clock is stopped) 1 A carrier pulse is output Caution TCA40 TCA40 cannot be set using a 1-bit memory manipulation instruction. Be sure to set this register using an 8-bit memory manipulation instruction. (4) Port mode register 2 (PM2) This register sets port 2 to input/output in 1-bit units. When using the P20/TMO/BSFO P20/TMO/BSFO pin as a timer output, set the PM20 and P20 output latch to 0. When using the P20/TMO/BSFO P20/TMO/BSFO pin as a timer input, set PM20 to 0. At this time, the P20 output latch can be set to 0 or 1. PM2 can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 6-13. Format of Port Mode Register 2 Symbol 7 6 5 4 3 2 1 0 PM2 1 1 1 1 1 1 PM21 PM20 PM21 P20 pin input/output mode 0 1 38 Output mode (output buffer on) Input mode (output buffer off) Data Sheet U16524EJ1V0DS U16524EJ1V0DS Address After reset FF22H FF22H FFH R/W R/W µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.5 Watchdog Timer 6.5.1 Watchdog timer functions The watchdog timer has the following functions. (1) Watchdog timer Detects program runaway. When runaway is detected, a non-maskable interrupt or RESET can be generated. (2) Interval timer Generates an interrupt at an arbitrary preset time interval. 6.5.2 Configuration of watchdog timer The watchdog timer consists of the following hardware. Figure 6-13 shows watchdog timer block diagram. Table 6-8. Configuration of Watchdog Timer Item Configuration Control register Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Figure 6-14. Watchdog Timer Block Diagram Internal bus fCLK 24 WDTMK Prescaler fCLK 26 fCLK 28 fCLK 210 Selector WDTIF 7-bit counter Control circuit INTWDT maskable interrupt request RESET INTWDT non-maskable interrupt request Clear 3 TCL22 TCL22 TCL21 TCL21 TCL20 TCL20 RUN WDTM4 WDTM3 Timer clock select register 2 (TCL2) Watchdog timer mode register (WDTM) Internal bus Remark fCLK: fX or fCC Data Sheet U16524EJ1V0DS U16524EJ1V0DS 39 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.5.3 Register that controls watchdog timer The watchdog timer is controlled by the following two registers. · Timer clock select register 2 (TCL2) · Watchdog timer mode register (WDTM) (1) Timer clock select register 2 (TCL2) This register sets the watchdog timer count clock. TCL2 is set with an 8-bit memory manipulation instruction. RESET input clears this register TCL2 to 00H. Figure 6-15. Format of Timer Clock Select Register 2 Symbol 7 6 5 4 3 TCL2 0 0 0 0 0 TCL22 TCL22 TCL21 TCL21 TCL20 TCL20 Watchdog timer count clock selection Address After reset FF42H FF42H 00H R/W R/W interval time TCL22 TCL22 TCL21 TCL21 TCL20 TCL20 0 0 0 fX/24 (312.5 kHz) fCC/24 (62.5 kHz) 211/ fX (410 µ s) 211/ fCC (2.05 ms) 0 1 0 fX/26 (78.1 kHz) fCC/26 (15.6 kHz) 213/ fX (1.64 ms) 213/ fCC (8.19 ms) 1 0 0 fX/28 (19.5 kHz) fCC/28 (3.91 kHz) 215/ fX (6.55 ms) 215/ fCC (32.8 ms) 1 1 0 fX/210 (4.88 kHz) fCC/210 (977 Hz) 217/ fX (26.2 ms) 217/ fCC (131.1 ms) Other than above Remarks 1. fX: At fX = 5.0 MHz operation At fCC = 1.0 MHz operation Setting prohibited System clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: System clock oscillation frequency (RC oscillation) 40 At fX = 5.0 MHz operation Data Sheet U16524EJ1V0DS U16524EJ1V0DS At fCC = 1.0 MHz operation µPD78E9860A PD78E9860A, 78E9861A 78E9861A (2) Watchdog timer mode register (WDTM) This register sets the watchdog timer operating mode and enables or disables counting. WDTM can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 6-16. Format of Watchdog Timer Mode Register Symbol 6 5 4 3 2 1 0 WDTM RUN 0 0 WDTM4 WDTM3 0 0 0 Address After reset FFF9H 00H R/W R/W Selection of watchdog timer operationNote 1 RUN 0 Count stop 1 Counter is cleared and then counting starts Selection of watchdog timer operating modeNote 2 WDTM4 WDTM3 0 0 Operation stop 0 1 Interval timer mode (maskable interrupt generated if overflow occurs)Note 3 1 0 Watchdog timer mode 1 (non-maskable interrupt generated if overflow occurs) 1 1 Watchdog timer mode 2 (reset operation started if overflow occurs) Notes 1. Once RUN is set (1), it cannot be cleared (0) by software. Therefore, once a count it is started cannot be stopped by RESET input. 2. Once WDTM3 and WDTM4 are set (1), they cannot only be cleared (0) by software. 3. Operation as an interval timer starts at the time that RUN is set to 1. Cautions 1. When the watchdog timer is cleared by setting RUN to 1, the actual overflow time is at most 0.8% shorter than the time set using timer clock selection register 2. 2. When using watchdog timer mode 1 or 2, set WDTM4 to 1 after confirming that TMIF4 (bit 0 of interrupt request flag register 0 (IF0) is 0. If watchdog timer mode 1 or 2 is selected when TMIF4 is 1, a non-maskable interrupt occurs at the same time as writing terminates. Data Sheet U16524EJ1V0DS U16524EJ1V0DS 41 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.6 Power-on-Clear Circuits 6.6.1 Power-on-clear circuit functions The power-on-clear circuits include the following two circuits, which have the following function. (1) Power-on-clear (POC) circuit · Compares the detection voltage (VPOC) with the power supply voltage (VDD) and generates an internal reset signal if VDD < VPOC. · This circuit can operate even in STOP mode. (2) Low-voltage detection (LVI) circuit · Compares the detection voltage (VLVI) to the power supply voltage (VDD) and generates an interrupt request signal (INTLVI1) if VDD < VLVI. · Eight levels of detection voltage can be selected using software. · This circuit stops operation in STOP mode. 6.6.2 Configuration of power-on-clear circuit Figures 6-17 and 6-18 show the block diagrams of the power-on-clear circuits. 42 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A Figure 6-17. Block Diagram of Power-on-Clear Circuit VDD VDD P-ch P-ch + Internal reset signal - Detection voltage source (VPOC) POCOF1 POCMK1 POCMK0 Power on clear register 1 (POCF1) Internal bus Figure 6-18. Block Diagram of Low-Voltage Detection Circuit VDD Low-voltage detection level selector P-ch VDD LVI stop signal (set during STOP instruction execution or reset signal generation) P-ch + INTLVI1 - N-ch Detection voltage source (VLVI) LVS12 LVS12 LVS11 LVS11 LVS10 LVS10 LVION1 LVF10 LVF10 Low-voltage detection level selection register 1 (LVIS1) Low-voltage detection register 1 (LVIF1) Internal bus Data Sheet U16524EJ1V0DS U16524EJ1V0DS 43 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.6.3 Registers that control power-on-clear circuits The following three registers control the power-on-clear circuits. · Power-on-clear register 1 (POCF1) · Low-voltage detection register 1 (LVIF1) · Low-voltage detection level selection register 1 (LVIS1) (1) Power-on-clear register 1 (POCF1) This register controls POC circuit operation. POCF1 can be set using a 1-bit or 8-bit memory manipulation instruction. Figure 6-19. Format of Power-on-Clear Register 1 Symbol 7 6 5 4 3 POCF1 0 0 0 0 0 POCOF1 POCOF1 POCMK1 POCMK0 Address After reset FFDDH 00HNote POC output detection flag 0 Non-generation of reset signal by POC or in cleared state due to a write operation to POCF1 1 Generation of reset signal by POC POCMK1 POC reset control 0 Generation of reset signal by POC enabled 1 Generation of reset signal by POC disabled POCMK0 POC operation control 0 POC operating 1 POC halted Note This value is 04H only after a power-on-clear reset. 44 Data Sheet U16524EJ1V0DS U16524EJ1V0DS R/W R/W µPD78E9860A PD78E9860A, 78E9861A 78E9861A (2) Low-voltage detection register 1 (LVIF1) This register controls the operation of the LVI circuit. LVIF1 can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 6-20. Format of Low-Voltage Detection Register 1 Symbol 6 5 4 3 2 1 LVIF1 LVION1 0 0 0 0 0 0 LVF10 LVF10 LVION1 Address After reset FFDEH 00H R/W R/WNote LVI operation enable flag 0 LVI disabled 1 LVI enabled LVF10 LVF10 LVI output detection flag 0 Power supply voltage (VDD) > LVI detection voltage (VLVI) or operation disabled 1 VDD < VLVI Note Bit 0 is read only. Caution When the LVI circuit enters STOP mode, it is automatically turned off (low-current consumption mode). When STOP mode is released, it necessary to wait about 2 ms for the operation of the LVI circuit to stabilize. Because it is possible for an interrupt request signal to be generated in this stabilization period, be sure to disable any interrupts by setting LVIMK1 (bit 3 of interrupt mask flag register 0 (MK0) (LVIMK1 = 1) before setting the STOP mode. The program example is shown below. Example After setting the STOP mode, an interrupt is enabled following the elapse of the operation stabilization time (for RC oscillation). SET1 LVIMK1 STOP MOV A, #0BCH DEC A BNZ $WAIT CLR1 LVIIF1 CLR1 LVIMK1 WAIT: 10 clocks Data Sheet U16524EJ1V0DS U16524EJ1V0DS 45 µPD78E9860A PD78E9860A, 78E9861A 78E9861A Because the required operation stabilization time following the release of STOP mode is 2 /fCC = 128 µs (when fCC = 1 MHz operation), it is necessary to make the program wait for 2 7 ms ­ 128 µs (approx. 1880 µs). When the CPU clock is 1 µs (when fCC = 1 MHz operation), secure the wait time by making the program loop 188 times. Caution In the case of a ceramic/crystal oscillator, because the oscillation stabilization time following release of STOP mode is 2 ms or more, the above program wait is unnecessary. (3) Low-voltage detection level selection register 1 (LVIS1) This register selects the level of the detection voltage (VLVI). LVIS1 can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 6-21. Format of Low-Voltage Detection Level Selection Register 1 Symbol 7 6 5 4 3 LVIS1 0 0 0 0 0 LVS12 LVS12 LVS11 LVS11 LVS10 LVS10 LVS12 LVS12 LVS11 LVS11 LVS10 LVS10 0 0 0 VLVI0 0 0 1 VLVI1 0 1 0 VLVI2 0 1 1 VLVI3 1 0 0 VLVI4 1 0 1 VLVI5 1 1 0 VLVI6 1 1 1 Address After reset R/W FFDFH R/W VLVI7 00H Selection of detection voltage (VLVI) levelNote Note Refer to 12. ELECTRICAL SPECIFICATIONS for detection voltage specifications. Caution When changing the detection voltage level (VLVI), an operation stabilization time of about 2 ms is required in order for the LVI output to stabilize. Do not, therefore, set the LVI circuit to operation-enable until the operation has stabilized. 46 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.7 Bit Sequential Buffer 6.7.1 Functions of bit sequential buffer The µPD78E9860A PD78E9860A and µPD78E9861A PD78E9861A have an on-chip bit sequential buffer of 8 bits × 8 bits = 16 bits. The functions of the bit sequential buffer are shown below. · If the value of the bit sequential buffer 10 data register (BSFRL10 BSFRL10, BSFRH10 BSFRH10) is shifted 1 bit to the lower side, the LSB can be output to the port at the same time. · It is possible to write to BSFRL10 BSFRL10 and BSFRH10 BSFRH10 using an 8-bit or 16-bit manipulation instruction. · Overwriting is enabled during a shift operation on the higher 8 bits only (the period in which shift clock is low level). 6.7.2 Configuration of bit sequential buffer The bit sequential buffer consists of the following hardware. Table 6-9. Configuration of Bit Sequential Buffer Item Configuration Data register Bit sequential buffer: 8 bits × 8 bits = 16 bits Control register Bit sequential buffer output control register 10 (BSFC10 BSFC10) Figure 6-22. Block Diagram of Bit Sequential Buffer Internal bus Timer 40 match interrupt request signal BSFRH10 BSFRH10 BSFRL10 BSFRL10 BSFO/P20 BSFO/P20 /TMO BSFE10 BSFE10 Bit sequential buffer output control register 10 (BSFC10 BSFC10) Internal bus Data Sheet U16524EJ1V0DS U16524EJ1V0DS 47 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.7.3 Register that controls the bit sequential buffer The following register controls the bit sequential buffer. · Bit sequential buffer output control register 10 (BSFC10 BSFC10) (1) Bit sequential buffer output control register 10 (BSFC10 BSFC10) This register controls the operation of the bit sequential buffer. BSFC10 BSFC10 can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 6-23. Format of Bit Sequential Buffer Output Control Register 10 Symbol 7 6 5 4 3 2 1 BSFC10 BSFC10 0 0 0 0 0 0 0 BSFE10 BSFE10 BSFE10 BSFE10 Bit sequential buffer operation control 0 1 48 Operation disabled Operation enabled Data Sheet U16524EJ1V0DS U16524EJ1V0DS Address After reset FF60H FF60H 00H R/W R/W µPD78E9860A PD78E9860A, 78E9861A 78E9861A 6.8 Key Return Circuit 6.8.1 Function of key return circuit In STOP mode, this circuit generates a key return interrupt by inputting a P40/KR10 P40/KR10 to P43/KR13 P43/KR13 falling edge. It can be used in judging the cause of a STOP mode release in software. Cautions 1. The key return interrupt is a non-maskable interrupt that is effective only in STOP mode. In addition, P40/KR10 P40/KR10 to P43/KR13 P43/KR13 key input cannot be performed by mask control. 2. The key return signal cannot be detected even if a falling edge is generated on the other key return pins while even one of the key return pins (P40/KR10 P40/KR10 to P43/KR13 P43/KR13) is low. 6.8.2 Configuration of key return circuit Figure 6-24 shows the block diagram of the key return circuit. Figure 6-24. Block Diagram of Key Return Circuit P40/KR10 P40/KR10 Falling edge detector P41/KR11 P41/KR11 Key return interrupt (INTKR1) P42/KR12 P42/KR12 P43/KR13 P43/KR13 STOP mode Data Sheet U16524EJ1V0DS U16524EJ1V0DS 49 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 7. INTERRUPT FUNCTIONS 7.1 Types of Interrupt Functions The following two types of interrupt functions are available. (1) Non-maskable interrupts A non-maskable interrupt is an interrupt that is accepted unconditionally even in a state in which interrupts are disabled. In addition, it is not subject to interrupt priority control and has a greater priority than all other interrupt requests. A non-maskable interrupt generates the standby release signal. Non-maskable interrupts have 1 internal interrupt source and 1 external interrupt source. (2) Maskable interrupts A maskable interrupt is an interrupt that is mask controlled. The order of priority when multiple interrupt requests are generated at the same time is determined as shown in Table 7-1. A maskable interrupt generates the standby release signal. Maskable interrupts have 5 internal interrupt sources. 7.2 Sources and Configuration of Interrupts There are a total of seven sources of interrupts for non-maskable interrupts and maskable interrupts combined (see Table 7-1). Table 7-1. List of Interrupt Sources Interrupt Type Interrupt Source PriorityNote 1 Name Trigger Internal/ External Vector Table Address Basic Configuration TypeNote 2 (A) INTKR1 Key return input falling edge detectedNote 3 External 0002H 0002H INTWDT Watchdog timer overflow (with watchdog timer mode 1 selected) Internal 0004H 0004H 0 INTWDT Watchdog timer overflow (with interval timer mode selected) 1 INTTM30 INTTM30 8-bit timer 30 match signal generation 0006H 0006H 2 INTTM40 INTTM40 8-bit timer 40 match signal generation 0008H 0008H 3 INTLVI1 LVI interrupt request signal 000AH 000AH 4 INTEE0 EEPROM write termination signal 000CH 000CH Nonmaskable - Maskable (B) Notes 1. The priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest and 4 is the lowest. 2. Basic configuration type (A) and (B) correspond to (A) and (B) in Figure 7-1. 3. Only in STOP mode. Interrupt request signals are not generated other than in STOP mode. Remark 50 Only one of watchdog timer interrupt sources (INTWDT), non-maskable or maskable, can be chosen. Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A Figure 7-1. Basic Configuration of Interrupt Functions (A) External/internal non-maskable interrupt Internal bus Vector table address generator Interrupt request Standby release signal (B) Internal maskable interrupt Internal bus MK Interrupt request IE Vector table address generator IF Standby release signal IF: Interrupt request flag IE: Interrupt enable flag MK: Interrupt mask flag Data Sheet U16524EJ1V0DS U16524EJ1V0DS 51 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 7.3 Registers That Control Interrupt Functions The following three registers control the interrupt functions. · Interrupt request flag register 0 (IF0) · Interrupt mask flag register 0 (MK0) · Program status word (PSW) Table 7-2 shows the names of the interrupt request flag and interrupt mask flag for each interrupt request. Table 7-2. Flags for Interrupt Request Signal Names Interrupt Request Signal Name Interrupt Request Flag Interrupt Mask Flag INTWDT TMIF4 TMMK4 INTTM30 INTTM30 TMIF30 TMIF30 TMMK30 TMMK30 INTTM40 INTTM40 TMIF40 TMIF40 TMMK40 TMMK40 INTLVI LVIIF1 LVIMK1 INTEE0 EEIF0 EEMK0 (1) Interrupt request flag register 0 (IF0) The interrupt request flag is a flag that is set (1) by the generation of a corresponding interrupt request or the execution of an instruction and that is cleared (0) by executing an instruction when an interrupt request is acknowledged or RESET is input. IF0 can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to 00H. Figure 7-2. Format of Interrupt Request Flag Register 0 Symbol 7 6 5 IF0 0 0 0 EEIF0 LVIIF1 TMIF40 TMIF40 TMIF30 TMIF30 TMIF4 ××IF× Address After reset R/W FFE0H R/W 00H Interrupt request flag 0 Interrupt request signal has not been generated 1 Interrupt request signal generated; interrupt request state Cautions 1. Be sure to set bits 5 to 7 to 0. 2. The TMIF4 flag can be read or written only when the watchdog timer is being used as an interval timer. Set the TMIF4 flag to 0 when using it in watchdog timer mode 1 or 2. 52 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A (2) Interrupt mask flag register 0 (MK0) The interrupt mask flag is a flag that sets the servicing of the corresponding maskable interrupt to enabled or disabled. MK0 can be set using a 1-bit or 8-bit memory manipulation instruction. RESET input sets this register to FFH. Figure 7-3. Format of Interrupt Mask Flag Register 0 Symbol 7 6 5 MK0 1 1 1 EEMK0 LVIMK1 ××MK× TMMK40 TMMK40 TMMK30 TMMK30 TMMK4 Address After reset R/W FFE4H R/W FFH Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Cautions 1. Be sure to set bits 5 to 7 to 1. 2. The TMMK4 flag can be read or written only when the watchdog timer is being used as an interval timer. Set the TMMK4 flag to 0 when using it in watchdog timer mode 1 or 2. (3) Program status word (PSW) The program status word is a register that maintains the current state with respect to the result of instruction execution or an interrupt request. The IE flag, which sets maskable interrupts to enabled or disabled, is mapped to it. Besides manipulation of reading or writing in 8-bit units, manipulation by bit manipulation instructions and dedicated instructions (EI, DI) is also possible. When a vector interrupt is acknowledged, the PSW is automatically saved in the stack and the IE flag is reset (0). RESET input sets the PSW to 02H. Figure 7-4. Configuration of Program Status Word Symbol 7 6 5 4 3 2 1 0 After reset PSW IE Z 0 AC 0 0 1 CY 02H Used when executing normal instructions Interrupt acknowledgement enabled/disabled IE 0 Disabled 1 Enabled Data Sheet U16524EJ1V0DS U16524EJ1V0DS 53 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 8. STANDBY FUNCTION 8.1 Standby Function The standby function is a function for decreasing the system's power consumption. Two standby modes available: HALT mode and STOP mode. Set the HALT mode using the HALT instruction and the STOP mode using the STOP instruction. (1) HALT mode In this mode, the CPU operation clock is stopped. Average power consumption can be reduced by intermittent operation combining this mode with the normal operation mode. (2) STOP mode In this mode, oscillation of the system clock is stopped. All the operations performed on the system clock are suspended, resulting in extremely small power consumption. Caution When switching to STOP mode, be sure to execute the STOP instruction after stopping peripheral hardware operations. 54 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A Table 8-1. HALT Mode Operating States Item HALT Mode Operating State System clock System clock oscillation is enabled Clock supply to CPU is stopped CPU Operation stopped EEPROM Operation enabledNote Ports (output latch) Maintain state before HALT mode was set 8-bit timer/event counter TM30 Operation enabled TM40 Operation enabled Watchdog timer Operation enabled Power-on-clear circuit POC Operation enabled LVI Operation enabled Bit sequential buffer Operation enabled Key return circuit Operation stopped Note HALT mode can be set after executing a write instruction. Table 8-2. STOP Mode Operating States Item STOP Mode Operating State System clock System clock oscillation is stopped Clock supply to CPU is stopped CPU Operation stopped EEPROM Operation stopped Ports (output latch) Maintain state at time STOP mode was set TM30 Operation enabledNote 1 TM40 8-bit timer/event counter Operation enabledNote 2 Watchdog timer Power-on-clear circuit Operation stopped POC Operation enabled LVI Operation stopped Bit sequential buffer Operation enabledNote 3 Key return circuit Operation enabled Notes 1. Operation is enabled only when cascade connected with TM40 (external clock selected for count clock). 2. Operation is enabled only when external clock is selected for count clock. 3. Operation is enabled only when external clock is selected for TM40 count clock and INTTM40 INTTM40 is generated. Data Sheet U16524EJ1V0DS U16524EJ1V0DS 55 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 8.2 Register That Controls Standby Function (µPD78E9860A PD78E9860A Only) Note The wait time from releasing STOP mode using an interrupt request until oscillation stabilizes is controlled by the oscillation stabilization time selection register (OSTS). OSTS can be set using an 8-bit memory manipulation instruction. 17 RESET input sets this register to 04H. Note that after RESET input the oscillation stabilization time is not 2 /fX but 15 2 /fX. Note There is no OSTS in the µPD78E9861A PD78E9861A. The oscillation stabilization time of the µPD78E9861A PD78E9861A is fixed at 7 2 /fCC. Figure 8-1. Format of Oscillation Stabilization Time Selection Register Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Address After reset R/W FFFAH R/W 04H Selection of oscillation stabilization time 15 0 1 0 2 /fX (6.55 ms) 1 0 0 217/fX (26.2 ms) Other than above Setting prohibited Caution For a ceramic/crystal oscillator, the wait time when STOP mode is released does not include the time until clock oscillation begins after RESET input or interrupt generation releases STOP mode (a in the figure below). STOP mode release X1 pin voltage waveform a Remarks 1. fX: System clock oscillation frequency (ceramic/crystal oscillator) 2. The parenthesized values apply to operation at fX = 5.0 MHz. 56 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A 9. RESET FUNCTION Reset signals are generated by the following three methods. (1) External reset by RESET signal input (2) Internal reset by watchdog timer runaway time detection (3) Internal reset by comparison of POC circuit power supply voltage and detection voltage An internal reset does not differ functionally from an external reset and both begin program execution at the address written in addresses 0000H 0000H and 0001H 0001H according to RESET input. If a low level is input to the RESET pin, a watchdog timer overflow occurs, or the POC circuit detects voltage, a reset occurs and each hardware item enters the state shown in Table 9-1. In addition, during reset input or during the time of oscillation stabilization immediately after reset release, each pin is in a state of high impedance. If a high level is input to the RESET pin, the reset is released and program execution begins after the oscillation stabilization time elapses. In addition, for a reset by a watchdog timer overflow, the reset is released automatically after reset and program execution begins after the oscillation stabilization time elapses. Cautions 1. When performing an external reset, input a low level to the RESET pin for at least 10 µs. 2. When releasing STOP mode using a reset, the contents at the time of STOP mode are maintained during reset input. However, port pins become high impedance. Figure 9-1. Reset Function Block Diagram RESET Reset controller Reset signal POC circuit Overflow Count clock Watchdog timer Interrupt function Stopped Data Sheet U16524EJ1V0DS U16524EJ1V0DS 57 µPD78E9860A PD78E9860A, 78E9861A 78E9861A Table 9-1. States of Hardware After Reset Hardware Note 1 State After Reset Program counter (PC) Contents of reset vector table (0000H 0000H, 0001H 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 02H EEPROM (EEWC10 EEWC10) 08H Data memory UndefinedNote 2 General-purpose registers RAM UndefinedNote 2 Ports (P0, P2) (Output latches) 00H Port mode registers (PM0, PM2) FFH Processor clock control register (PCC) 02H Note 3 Oscillation stabilization time selection register (OSTS) 04H 8-bit timer/event counter Timer counters (TM30, TM40) 00H Compare registers (CR30, CR40, CRH40 CRH40) Undefined Mode control registers (TMC30 TMC30, TMC40 TMC40) 00H Carrier generator output control register (TCA40 TCA40) 00H Timer clock select register 2 (TCL2) 00H Mode register (WDTM) 00H Power-on-clear register (POCF1) 00HNote 4 Low-voltage detection register (LVIF1) 00H Low-voltage detection level selection register (LVIS1) 00H Data registers (BSFRL10 BSFRL10, BSFRH10 BSFRH10) Undefined Output control register (BSFC10 BSFC10) 00H Request flag register (IF0) 00H Mask flag register (MK0) FFH Watchdog timer Power-on-clear circuit Bit sequential buffer Interrupts Notes 1. Among the hardware, only the contents of the PC are in an undefined state during reset input and during an oscillation stabilization time wait. For all other hardware, the state is the same as the state after a reset. 2. The state after a reset in standby mode is maintained. 3. µPD78E9860A PD78E9860A only. 4. This value is 04H only after a power-on-clear reset. 58 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A 10. EEPROM (PROGRAM MEMORY) The on-chip program memory in the µPD78E9860A PD78E9860A and 78E9861A 78E9861A is EEPROM. This chapter describes the functions of the EEPROM incorporated in the program memory area. For the EEPROM incorporated in data memory, see 5. EEPROM (DATA MEMORY). EEPROM can be written with the µPD78E9860A PD78E9860A and 78E9861A 78E9861A mounted on the target system (on-board). Connect the dedicated flash writer (Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4) to the host machine and target system to write to EEPROM. Remark FL-PR3 and FL-PR4 are products of Naito Densei Machida Mfg. Co., Ltd (TEL +81-45-475-4191). Programming using EEPROM has the following advantages. · Software can be modified after the microcontroller is solder-mounted on the target system. · Distinguishing software facilities small-quantity, varied model production · Easy data adjustment when starting mass production 10.1 Programming Environment The following shows the environment required for µPD78E9860A PD78E9860A, 78E9861A 78E9861A EEPROM programming. When Flashpro III (part no. FL-PR3, PG-FP3) or Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash programmer, a host machine is required to control the dedicated flash programmer. Communication between the host machine and flash programmer is performed via RS-232C/USB RS-232C/USB (Rev. 1.1). For details, refer to the manuals for Flashpro III/Flashpro IV. Remark USB is supported by Flashpro IV only. Figure 10-1. Environment for Writing Program to EEPROM (Program Memory) VPP VDD RS-232C RS-232C VSS USB RESET Dedicated flash programmer Pseudo 3-wire µ PD78E9860A PD78E9860A, µ PD78E9861A PD78E9861A Host machine Data Sheet U16524EJ1V0DS U16524EJ1V0DS 59 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 10.2 Communication Mode Use the communication mode shown in Table 10-1 to perform communication between the dedicated flash programmer and µPD78E9860A PD78E9860A, 78E9861A 78E9861A. Table 10-1. Communication Mode List Communication Mode TYPE SettingNote 1 SIO Clock Port A (Pseudo-3 wire) Pseudo 3-wire COMM PORT 100 Hz to 1 kHz CPU CLOCK In Flashpro 1, 2, 4, 5 MHzNotes 2, 3 Pins Used Note 1 On Target Board 1 to 5 MHzNote 2 Multiple Rate 1.0 P02 (serial data input) P01 (serial data output) P00 (serial clock input) Number of VPP Pulses 12 Notes 1. Be sure to use In Flashpro (system clock is supplied from a dedicated flash programmer) with the µPD78E9861A PD78E9861A. 2. The possible setting range differs depending on the voltage. 3. 2 or 4 MHz only with Flashpro III Figure 10-2. Communication Mode Selection Format 10 V VPP VDD 1 n 2 VSS VPP pulse VDD RESET VSS 60 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A Figure 10-3. Example of Connection with Dedicated Flash Programmer (a) Pseudo 3-wire (µPD78E9860A PD78E9860A) µ PD78E9860A PD78E9860A Dedicated flash programmer VPP1 VPP VDD VDD RESET RESET SCK P00 (serial clock) SO P02 (serial input) SI P01 (serial output) CLKNote X1 GND VSS (b) Pseudo 3-wire (µPD78E9861A PD78E9861A) µ PD78E9861A PD78E9861A Dedicated flash programmer VPP1 VPP VDD VDD RESET RESET SCK P00 (serial clock) SO P02 (serial input) P01 (serial output) SI CLK P03 GND VSS Note When supplying the system clock from a dedicated flash programmer, connect the CLK and X1 pins and cut off the resonator on the board. When using the clock oscillated by the on-board resonator, do not connect the CLK pin. Caution The VDD pin, if already connected to the power supply, must be connected to the VDD pin of the dedicated flash programmer. When using the power supply connected to the VDD pin, supply voltage before starting programming. Data Sheet U16524EJ1V0DS U16524EJ1V0DS 61 µPD78E9860A PD78E9860A, 78E9861A 78E9861A If Flashpro III (part no. FL-PR3, PG-FP3)/Flashpro IV (part no. FL-PR4, PG-FP4) is used as a dedicated flash programmer, the following signals are generated for the µPD78E9860A PD78E9860A, 78E9861A 78E9861A. For details, refer to the manual of Flashpro III/Flashpro IV. Table 10-2. Pin Connection List Signal Name VPP1 I/O Output GND CLK Write voltage I/O Pin Name Pseudo 3-Wire - × VPP - VPP2 VDD Pin Function - Note VDD voltage generation/voltage monitoring - Output VDD Ground VSS Clock output X1 (µPD78E9860A PD78E9860A) P03 (µPD78E9861A PD78E9861A) RESET Output Reset signal RESET SI Input Receive signal P01 SO Output Transmit signal P02 SCK Output Transfer clock P00 HS Input Handshake signal - Note VDD voltage must be supplied before programming is started. Remark : Pin must be connected. : If the signal is supplied on the target board, pin does not need to be connected. ×: Pin does not need to be connected. 62 Data Sheet U16524EJ1V0DS U16524EJ1V0DS × µPD78E9860A PD78E9860A, 78E9861A 78E9861A 10.3 On-Board Pin Processing When performing programming on the target system, provide a connector on the target system to connect the dedicated flash programmer. An on-board function that allows switching between normal operation mode and EEPROM programming mode may be required in some cases. In normal operation mode, input 0 V to the VPP pin. In EEPROM programming mode, a write voltage of 10.0 V (TYP.) is supplied to the VPP pin, so perform either of the following. (1) Connect a pull-down resistor RVPP = 10 k to the VPP pin. (2) Use the jumper on the board to switch the VPP pin input to either the programmer or directly to GND. A VPP pin connection example is shown below. Figure 10-4. VPP Pin Connection Example µ PD78E9860A PD78E9860A, 78E9861A 78E9861A Connection pin of dedicated flash programmer VPP Pull-down resistor (RVPP) The following shows the pins used by the serial interface. Serial Interface Pseudo 3-wire Pins Used P02, P01, P00 When connecting the dedicated flash programmer to a serial interface pin that is connected to another device onboard, signal conflict or abnormal operation of the other device may occur. Care must therefore be taken with such connections. Data Sheet U16524EJ1V0DS U16524EJ1V0DS 63 µPD78E9860A PD78E9860A, 78E9861A 78E9861A (1) Signal conflict If the dedicated flash programmer (output) is connected to a serial interface pin (input) that is connected to another device (output), a signal conflict occurs. To prevent this, isolate the connection with the other device or set the other device to the output high impedance status. Figure 10-5. Signal Conflict (Input Pin of Serial Interface) µ PD78E9860A PD78E9860A, 78E9861A 78E9861A Signal conflict Connection pin of dedicated flash programmer Input pin Other device Output pin In the EEPROM programming mode, the signal output by another device and the signal sent by the dedicated flash programmer conflict; therefore, isolate the signal of the other device. (2) Abnormal operation of other device If the dedicated flash programmer (output or input) is connected to a serial interface pin (input or output) that is connected to another device (input), a signal is output to the device, and this may cause an abnormal operation. To prevent this abnormal operation, isolate the connection with the other device or set so that the signals input to the other device are ignored. Figure 10-6. Abnormal Operation of Other Device µ PD78E9860A PD78E9860A, 78E9861A 78E9861A Connection pin of dedicated flash programmer Pin Other device Input pin If the signal output by the µ PD78E9860A PD78E9860A, 78E9861A 78E9861A affects another device in the EEPROM programming mode, isolate the signals of the other device. µ PD78E9860A PD78E9860A, 78E9861A 78E9861A Connection pin of dedicated flash programmer Pin Other device Input pin If the signal output by the dedicated flash programmer affects another device in the EEPROM programming mode, isolate the signals of the other device. 64 Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A If the reset signal of the dedicated flash programmer is connected to the RESET pin connected to the reset signal generator on-board, a signal conflict occurs. To prevent this, isolate the connection with the reset signal generator. If the reset signal is input from the user system in the EEPROM programming mode, a normal programming operation cannot be performed. Therefore, do not input other than reset signals from the dedicated flash programmer. Figure 10-7. Signal Conflict (RESET Pin) µ PD78E9860A PD78E9860A, 78E9861A 78E9861A Signal conflict Connection pin of dedicated flash programmer RESET Reset signal generator Output pin The signal output by the reset signal generator and the signal output from the dedicated flash programmer conflict in the EEPROM programming mode, so isolate the signal of the reset signal generator. When the µPD78E9860A PD78E9860A and 78E9861A 78E9861A enter the EEPROM programming mode, all the pins other than those that communicate with the flash programmer are in the same status as immediately after reset. If the external device does not recognize initial statuses such as the output high impedance status, therefore, connect the external device to VDD or VSS via a resistor. · In µPD78E9860A PD78E9860A When using the on-board clock, connect X1 and X2 as required in the normal operation mode. When using the clock output of the flash programmer, connect it directly to X1, disconnecting the main resonator on-board, and leave the X2 pin open. · In µPD78E9861A PD78E9861A Connect CL1 and CL2 as required in the normal operation mode, and connect the clock output of the flash programmer to the P03 pin. To use the power output from the flash programmer, connect the VDD pin to VDD of the flash programmer, and the VSS pin to GND of the flash programmer. To use the on-board power supply, make connections that accord with the normal operation mode. However, because the voltage is monitored by the flash programmer, be sure to connect VDD of the flash programmer. Data Sheet U16524EJ1V0DS U16524EJ1V0DS 65 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 10.4 Connection of Adapter for EEPROM Writing The following figures show the examples of recommended connection when the adapter for EEPROM writing is used. Figure 10-8. Wiring Example for EEPROM Writing Adapter with Pseudo 3-Wire (1/2) (a) µPD78E9860A PD78E9860A VDD (2.7 to 5.5 V) GND 20 2 19 3 18 4 17 µPD78E9860A PD78E9860A 1 5 6 16 15 7 14 8 13 9 12 10 11 GND VDD VDD2 (LVDD) SI 66 SO SCK CLKOUT RESET Data Sheet U16524EJ1V0DS U16524EJ1V0DS VPP RESERVE/HS µPD78E9860A PD78E9860A, 78E9861A 78E9861A Figure 10-8. Wiring Example for EEPROM Writing Adapter with Pseudo 3-Wire (2/2) (b) µPD78E9861A PD78E9861A VDD (2.7 to 3.6 V) GND 20 2 19 3 18 4 17 µPD78E9861A PD78E9861A 1 5 6 16 15 7 14 8 13 9 12 10 11 GND VDD VDD2 (LVDD) SI SO SCK CLKOUT RESET Data Sheet U16524EJ1V0DS U16524EJ1V0DS VPP RESERVE/HS 67 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 11. INSTRUCTION SET SUMMARY This section lists the µPD78E9860A PD78E9860A and µPD78E9861A PD78E9861A instruction set. 11.1 Conventions 11.1.1 Operand identifiers and description methods Operands are described in the Operand column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them. Alphabetic letters in capitals and symbols, #, !, $ and [ ] are keywords and must be described as they are. Each symbol has the following meaning. · #: Immediate data specification · $: Relative address specification · !: Absolute address specification · [ ]:Indirect address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, $, [ ] and symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in the table below, R0, R1, R2, etc.) can be used for description. Table 11-1. Operand Identifiers Forms and Description Methods Identifier Description Method r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) rp AX (RP0), BC (RP1), DE (RP2), HL (RP3) sfr Special function register symbol saddr FE20H FE20H to FF1FH immediate data or label saddrp FE20H FE20H to FF1FH immediate data or label (Even numbered addresses only) addr16 0000H 0000H to FFFFH immediate data or label (Even numbered addresses only if a 16-bit data transfer instruction) addr5 0040H 0040H to 007FH 007FH immediate data or label (Even numbered addresses only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label Remark 68 Refer to Table 4-1 List of Special Function Registers for special function register symbols. Data Sheet U16524EJ1V0DS U16524EJ1V0DS µPD78E9860A PD78E9860A, 78E9861A 78E9861A 11.1.2 Explanation of operation column A: A register; 8-bit accumulator X: X register B: B register C: C register D: D register E: E register H: H register L: L register AX: AX register pair; 16-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair PC: Program counter SP: Stack pointer PSW: Program status word CY: Carry flag AC: Auxiliary carry flag Z: Zero flag IE: Interrupt request enable flag NMIS: Non-maskable interrupt processing flag ( ): Contents of memory represented by contents of register or address in parentheses XH, XL: Higher 8 bits and lower 8 bits of 16-bit register : Logical product (AND) : Logical sum (OR) : Exclusive logical sum (exclusive OR) : Inverted data addr16: 16-bit immediate data or label jdisp8: Signed 8-bit data (displacement value) 11.1.3 Explanation of flags column (blank): No change 0: Cleared to 0 1: Set to 1 ×: Set or cleared according to result R: Previously saved value is stored Data Sheet U16524EJ1V0DS U16524EJ1V0DS 69 µPD78E9860A PD78E9860A, 78E9861A 78E9861A 11.2 List of Operations Flags Mnemonic Operand Bytes Clock Operation Z r. #byte 3 6 r byte saddr, #byte 3 6 (saddr) byte sfr, #byte MOV 3 6 sfr byte Note 1 2 4 Ar Note 1 2 4 rA A, saddr 2 4 A (saddr) saddr, A 2 4 (saddr) A A, sfr 2 4 A sfr sfr, A 2 4 sfr A A, !addr16 3 8 A (addr16) !addr16, A 3 8 (addr16) A PSW, #byte 3 6 PSW byte A, PSW 2 4 A PSW PSW, A 2 4 PSW A A, [DE] 1 6 A (DE) [DE], A 1 6 (DE) A A, [HL] 1 6 A (HL) [HL], A 1 6 (HL) A A, [HL + byte] 2 6 A (HL + byte) [HL + byte], A 2 6 (HL + byte) A A, X 1 4 A X A, r 2 6 A r A, saddr 2 6 A (saddr) A, sfr 2 6 A (sfr) A, [DE] 1 8 A (DE) A, [HL] 1 8 A (HL) A, [HL + byte] 2 8 A (HL+byte) rp, #word