PD78C17 78C18 PD78C18 IEU-1314 PD78C17CW PD78C17GF-3BE PD78C17GQ-36 IC-2789B - Datasheet Archive

 

Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

 

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT µ PD78C17 PD78C17, 78C18 78C18 8-BIT SINGLE-CHIP MICROCONTROLLER (WITH A/D CONVERTER) The µPD78C18 PD78C18 is an 8-bit CMOS microcontroller which integrates 16-bit ALU, ROM, RAM, an A/D converter, a multi-function timer/event counter, and a general-purpose serial interface onto a single chip, and whose memory (ROM/RAM) is externally expandable up to 31 Kbytes. The µPD78C18 PD78C18 can operate at low power consumption because of its CMOS architecure and is provided with a standby function that enables data retention with an even lower power consumption. The µPD78C17 PD78C17 is the ROM-less version of the µPD78C18 PD78C18. Its memory (ROM/RAM) is expandable externally up to 63 Kbytes. A detailed explanation of the functions is provided in the user's manual listed below. It should be read before starting design work. 87AD Series µ PD78C18 PD78C18 User's Manual: IEU-1314 IEU-1314 FEATURES · · · · 159 types of instructions: 87AD series instruction set plus multiply/divide and 16-bit operation instructions Instruction cycle: 0.8 µs (at 15-MHz operation) Internal ROM: 32768 x 8 bits (µPD78C18 PD78C18 only) Internal RAM: 1024 x 8 bits · · · · Up to 64 Kbytes of memory (ROM/RAM) can be directly addressed. High-resolution 8-bit A/D converter: 8 analog inputs General-purpose serial interface: Asynchronous, synchronous, I/O interface modes Multi-function 16-bit timer/event counter · Two 8-bit timers · I/O lines Input/output ports : 28 (µPD78C17 PD78C17), 40 (µPD78C18 PD78C18) Edge detection inputs : 4 · 11 interrupt functions External : 3, Internal: 8 (Non-maskable: 1, Maskable: 10) · Zero-cross detection function: (2 inputs) · Standby function: HALT mode, hardware/software STOP mode · Mask option pull-up resistors can be incorporated into Ports A, B, and C. (µPD78C18 PD78C18 only) ORDERING INFORMATION Part Number Package µPD78C17CW PD78C17CW µPD78C17GF-3BE PD78C17GF-3BE µPD78C17GQ-36 PD78C17GQ-36 µPD78C18CW-xxx µPD78C18GF-xxx-3BE µPD78C18GQ-xxx-36 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin plastic plastic plastic plastic plastic plastic shrink DIP (750 mils) QFP (14 x 20 mm) QUIP shrink DIP (750 mils) QFP (14 x 20 mm) QUIP The information in this document is subject to change without notice. Document No. IC-2789B IC-2789B (O.D.No. IC-8048B IC-8048B) Date Published June 1995 P Printed in Japan The mark 5 shows revised points. © 1995 1990 µPD78C17 PD78C17,78C18 78C18 PIN CONFIGURATION (TOP VIEW) 1 64 V DD PA1 2 63 STOP PA2 3 62 PD7 PA3 4 61 PD6 PA4 5 60 PD5 PA5 6 59 PD4 PA6 7 58 PD3 PA7 8 57 PD2 PB0 9 56 PD1 PB1 10 55 PD0 PB2 11 54 PF7 PB3 12 53 PF6 PB4 13 52 PF5 PB5 14 51 PF4 PB6 15 50 PF3 49 PF2 48 PF1 47 PF0 46 ALE 45 WR 44 RD AV DD PB7 16 PC0/T X D 17 PC1/R X D 18 PC2/SCK 19 PC3/INT2 20 PC4/TO 21 µPD78C17CW PD78C17CW, µPD78C17GQ-36 PD78C17GQ-36 µPD78C18CW-xxx, µPD78C18GQ-xxx-36 PA0 PC5/CI PC6/CO0 23 42 AV AREF PC7/CO1 24 41 AN7 NMI 25 40 AN6 INT1 26 39 AN5 MODE1 27 38 AN4 RESET 28 37 AN3 MODE0 29 36 AN2 X2 30 35 AN1 X1 31 34 AN0 V SS m 22 43 32 33 AV SS m 2 PD0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ALE WR RD AV DD V AREF AN7 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 PD4 AN5 PD1 51 52 50 PD3 AN6 PD2 µPD78C17 PD78C17,78C18 78C18 34 33 32 AN4 53 31 AN3 PD5 54 30 AN2 PD6 55 29 AN1 PD7 56 28 AN0 STOP 57 27 AV SS V DD 58 26 V SS PA0 59 25 X1 PA1 60 24 X2 PA2 61 23 MODE0 PA3 62 22 RESET PA4 63 21 MODE1 PA5 64 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0/T X D PC1/R X D PC2/SCK PC3/INT2 PC4/TO PC5/CI PC6/CO0 PC7/CO1 20 19 INT1 NMI 1 PA6 µPD78C17GF-3BE PD78C17GF-3BE µPD78C18GF-xxx-3BE 3 V B D H INT1 V' B' D' H' INT. CONTROL 4 8 8 8 8 8 8 MAIN G.R 16 10 PROGRAMNote 1 MEMORY (32-KBYTE 32-KBYTE) A' C' E' L' ALT G.R 8 DATANote 4 MEMORY (1-KBYTE) BUFFER PC3/INT2/TI TIMER PC4/TO TIMER/EVENT COUNTER PD7-0/ AD7-0Note 2 PC7-0Note 3 PB7-0Note 3 PA7-0Note 3 8/16 8 8 PC5/CI PC6/CO0 PC7/CO1 PF7-0/ AB15-8Note 2 15 EA' 8 8 8 A C E L NMI PORT F 8 PORT D SERIAL I/O PORT C PC0/TXD PC1/RXD PC2/SCK PORT B X2 8 8 LATCH INC/DEC PC SP EA PORT A OSC BLOCK DIAGRAM 4 8 16 X1 INTERNAL DATA BUS 16 8 16 LATCH LATCH 8 6 8 PSW INST.REG AN7-0 8 16 A/D CONVERTER VAREF AVDD AVSS 16 8 INST. DECODER ALU (8/16) 16 Notes 1. 3. 4. µPD78C17 PD78C17. PF3 to PF0 and PD7 to PD0 are operated only as AB11 to AB8 and AD7 to AD0 in the µPD78C17 PD78C17. Pull-up resistor can be incorporated by the mask option in the µPD78C18 PD78C18. Can be used only when RAE bit of MM register is 1. When it is 0, an external memory is necessary. READ/WRITE CONTROL RD WR SYSTEM CONTROL ALE MODE1 MODE0 RESET STAND BY CONTROL STOP VDD VSS µPD78C17 PD78C17,78C18 78C18 2. Program memory is not incorporated in the µPD78C17 PD78C17,78C18 78C18 CONTENTS 1. PIN FUNCTIONS . 7 1.1 1.2 1.3 1.4 2. LIST OF PIN FUNCTION .7 PIN INPUT/OUTPUT CIRCUITS .9 PIN MASK OPTIONS .15 UNUSED PIN CONNECTIONS .15 INTERNAL BLOCK FUNCTIONS .16 2.1 2.2 2.3 2.4 REGISTERS .16 ARITHMETIC LOGIC UNIT (ALU) .17 PROGRAM STATUS WORD (PSW) .17 MEMORY .19 2.5 2.6 2.7 2.8 PORT FUNCTIONS .22 TIMER .31 TIMER/EVENT COUNTER .34 SERIAL INTERFACE .41 2.9 ANALOG/DIGITAL CONVERTER .52 2.10 ZERO-CROSS DETECTOR .55 3. INTERRUPT FUNCTIONS .57 3.1 3.2 3.3 3.4 4. INTERRUPT CONTROL CIRCUIT CONFIGURATION .58 NON-MASKABLE INTERRUPT OPERATION .61 MASKABLE INTERRUPT OPERATION .63 INTERRUPT OPERATION BY SOFTI INSTRUCTION .64 STANDBY FUNCTIONS .65 4.1 HALT MODE .65 4.2 4.3 4.4 4.5 HALT MODE RELEASE .66 SOFTWARE STOP MODE .68 SOFTWARE STOP MODE RELEASE .68 HARDWARE STOP MODE .69 4.6 4.7 HARDWARE STOP MODE RELEASE .70 LOW SUPPLY VOLTAGE DATA RETENTION MODE . 71 5. RESET OPERATIONS .72 6. INSTRUCTION SET .73 6.1 6.2 IDENTIFIER/DESCRIPTION OF OPERAND .73 SYMBOL DESCRIPTION OF INSTRUCTION CODE .74 6.3 INSTRUCTION EXECUTION TIME .75 7. LIST OF MODE REGISTERS .87 8. ELECTRICAL SPECIFICATIONS .88 9. CHARACTERISTIC CURVES .99 10. PACKAGE DRAWINGS .102 5 µPD78C17 PD78C17,78C18 78C18 11. RECOMMENDED SOLDERING CONDITIONS .105 12. DIFFERENCES AMONG µPD78C18 PD78C18, µPD78C14 PD78C14, AND µPD78C12A PD78C12A .106 APPENDIX. DEVELOPMENT TOOLS .107 6 µPD78C17 PD78C17,78C18 78C18 1. PIN FUNCTIONS 1.1 LIST OF PIN FUNCTION (1/2) Pin Name I/O Function PA7 to PA0 (Port A) Input-output 8-bit input-output port, which can specify input/output (Port A) bit-wise. PB7 to PB0 (Port B) Input-output 8-bit input-output port, which can specify input/output (Port B) bit-wise. PC0/TXD Input-output/ Output PC1/RxD Input-output/ Input Port C 8-bit input-output port, which can specify input/output bit-wise. PC2/SCK Input-output/ Input-output Serial Clock Input-output pin for serial clock. It becomes output pin for the internal clock use, and input pin for the external. PC3/INT2/TI Input-output/ Input/Input Interrupt Request/Timer Input Maskable interrupt input pin of the edge trigger (falling edge), or an external clock input pin for a timer. Also, it can be used as a zero-cross detection pin for AC input. PC4/TO Input-output/ Output Timer Output Square wave defining one cycle of internal clock or timer counter time as half cycle is output. PC5/CI Input-output/ Input Counter Input External pulse input pin to timer/event counter. PC6/CO0 PC7/CO1 Input-output/ Output Counter Output 0, 1 Programmable square wave output by timer/event counter. PD7 to PD0/ AD7 to AD0 Input-output/ Input-output Port D 8-bit input-output port, which can specify input/output in byte units (µPD78C18 PD78C18). Address/Data Bus When external memory is used, it becomes multiplexed address/data bus. PF7 to PF0/ AB15 to AB8 Input-output/ Output Port F 8-bit input-output port, which can specify input/output bit-wise. Address Bus When external memory is used, it becomes address bus. WR (Write Strobe) Output Strobe signal which is output for write operation of external memory. It becomes high in any cycle other than the data write machine cycle of external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes output highimpedance. RD (Read Strobe) Output Strobe signal which is output for read operation of external memory. It becomes high in any cycle other than the read machine cycle of external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes output high-impedance. ALE (Address Latch Enable) Output Strobe signal to latch externally the lower address information which is output to PD7 to PD0 pins to access external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes output high-impedance. Transmit Data Output pin for serial data. Receive Data Input pin for serial data. 7 µPD78C17 PD78C17,78C18 78C18 1.1 LIST OF PIN FUNCTION (2/2) Pin Name Function Input-output MODE0 MODE1 (Mode) I/O The µPD78C18 PD78C18 sets MODE0 pin to "0" (low level), and MODE1 pin to "1" (high level).Note The µPD78C17 PD78C17 allows you to set MODE0, MODE1 pins to select 4 K, 16 K, or 63 Kbytes for the size of the memory which is installed externally. MODE0 MODE1 0 1 1 0 0 1 External Memory 4 Kbytes 16 Kbytes 63 Kbytes Also, when each of MODE0 and MODE1 pins is set to "1"Note, it is synchronized to ALE to output a control signal. NMI (Non-Maskable Interrupt) Input Non-maskable interrupt input pin of the edge trigger (falling edge) INT1 (Interrupt Request) Input A maskable interrupt input pin of the edge trigger (rising edge). Also, it can be used as a zero-cross detection pin for AC input. AN7 to AN0 (Analog Input) Input 8 pins of analog input to A/D converter. AN7 to AN4 can be used as edge detection (falling edge) input. VAREF (Reference Voltage) Input A common pin serving both as a reference voltage input pin for A/D converter and as a control pin for A/D converter operation. AVDD (Analog VDD) Power supply pin for A/D converter. AVSS (Analog VSS) GND pin for A/D converter. X1, X2 (Crystal) Crystal connection pins for system clock oscillation. X1 should be input when a clock is supplied from outside. Inverted clock of X1 should be input to X2. RESET (Reset) Input Low-level active system reset input. STOP (Stop) Input Control signal input pin in hardware STOP mode. The oscillation stops when the lowlevel is input. VDD Positive power supply pin. VSS GND pin. Note Connect a pull-up resistor. Resistance R should be 4 [k] R 0.4tCYC [k] (tCYC is in nanoseconds). Remark The µPD78C18 PD78C18 can incorporate (mask option) pull-up resistors on to ports A, B, and C. 8 µPD78C17 PD78C17,78C18 78C18 1.2 PIN INPUT/OUTPUT CIRCUITS Table 1-1 and 1-2, and figures (1) to (15) show input/output circuits of each pin in a schematic form. Table 1-1 Pin Type No. for µPD78C17 PD78C17 Pin Name Type No. Pin Name Type No. PA7 to PA0 5 RESET 2 PB7 to PB0 5 RD 4 PC1 and PC0 5 WR 4 PC2/SCK 8 ALE 4 PC3/INT2 10 STOP 2 PC7 to PC4 5 MODE0 11 AD7 to AD0 5 MODE1 11 AB11 to AB8 5 AN3 to AN0 7 PF7 to PF4 5 AN7 to AN4 12 NMI 2 VAREF 13 INT1 9 Table 1-2 Pin Type No. for µPD78C18 PD78C18 Pin Name Type No. Pin Name Type No. PA7 to PA0 5-A RESET 2 PB7 to PB0 5-A RD 4 PC1 and PC0 5-A WR 4 PC2/SCK 8-A ALE 4 PC3/INT2 10-A STOP 2 PC7 to PC4 5-A MODE0 11 PD7 to PD0 5 MODE1 11 PF7 to PF0 5 AN3 to AN0 7 NMI 2 AN7 to AN4 12 INT1 9 VAREF 13 9 µPD78C17 PD78C17,78C18 78C18 (1) Type 1 V DD P- ch IN N- ch (2) Type 2 IN (3) Type 4 V DD output data P-ch OUT output disable N-ch (4) Type 4-A V DD output data P-ch OUT output disable 10 N-ch µPD78C17 PD78C17,78C18 78C18 (5) Type 5 output data IN/OUT Type 4 output disable Type 1 (6) Type 5-A output data IN/OUT Type 4-A output disable Type 1 (7) Type 7 AV DD P-ch IN + N-ch AV DD ­ Sampling C AV SS Reference Voltage (from Voltage Tap of Serial Resistance String) (8) Type 8 output data output disable N-ch Type 5 IN/OUT N-ch Type 2 MCC 11 µPD78C17 PD78C17,78C18 78C18 (9) Type 8-A output data output disable N-ch Type 5-A IN/OUT N-ch Type 2 MCC (10) Type 9 self bias enable IN Type 2 data (11) Type 10 output data output disable Type 5 N-ch N-ch MCC 12 self bias enable Type 9 IN/OUT µPD78C17 PD78C17,78C18 78C18 (12) Type 10-A output data output disable Type 5-A IN/OUT N-ch N-ch self bias enable Type 9 MCC (13) Type 11 IN/OUT output data N-ch Type 1 (14) Type 12 IN Type 7 Type 2 Edge Detector 13 µPD78C17 PD78C17,78C18 78C18 (15) Type 13 IN STOP Mode Type 1 P-ch AV SS 14 µPD78C17 PD78C17,78C18 78C18 1.3 PIN MASK OPTIONS The µPD78C18 PD78C18 has the following mask options, which can be selected bit-wise according to the application. Pin Name Mask Options PA7 to PA0 PB7 to PB0 Pull-up resistor can be incorporated PC7 to PC0 Cautions 1.4 1. Zero-cross detection function will not operate properly if pull-up resistor is incorporated in PC3. 2. The µPD78C17 PD78C17 has no mask option. UNUSED PIN CONNECTIONS Pin PA7 PB7 PC7 PD7 PF7 to to to to to Recommended Connection PA0 PB0 PC0 PD0 PF0 RD WR ALE STOP INT1, NMI Connect to VSS or VDD via a resistor Leave open Connect to VDD Connect to VSS or VDD AVDD Connect to VDD AVAREF AVSS Connect to VSS AN7 to AN0 Connect to AVSS or AVDD 15 5 µPD78C17 PD78C17,78C18 78C18 2. INTERNAL BLOCK FUNCTIONS 2.1 REGISTERS The central registers are the sixteen 8-bit registers and four 16-bit registers shown in Fig. 2-1. Fig. 2-1 Register Configuration 15 0 PC SP 15 0 EA 7 0 7 0 V A B C D E H L 15 MAIN 0 EA' 7 0 7 0 V' A' B' C' D' E' H' L' ALT (a) General registers (B, C, D, E, H, L) There are two sets of general registers (MAIN: B, C, D, E, H, L; ALT: B', C', D', E', H', L'). They function as auxiliary registers for the accumulator, and have a data pointer function as register pairs (BC, DE, HL; B'C', D'E', H'L'). In particular, four register pairs DE, D'E', HL, and H'L', have a base register function. When the two sets are used, if an interrupt occurs in one set, the register contents are saved into the other register set without saving them into the memory so that interrupt servicing can be carried out. The other set of registers can also be used as data pointer expansion registers. Two addressing modes, singlestep automatic increment/decrement modes and a two-step automatic increment mode, are available for the register pairs, DE, HL, D'E', and H'L', so that the processing time can be reduced. BC, DE, and HL can be simultaneously replaced with the ALT register by means of the EXX instruction. The HL register can be independently replaced with the ALT register by means of the EXH instruction. (b) Working register vector register (V) When a working area is set in the memory space, the high-order 8 bits of the memory address are selected using the V register and the low-order 8 bits are addressed by the immediate data in the instruction. Thus, the memory area specified with the V register can be used as working registers with a 256 x 8bit configuration. Because a working register can be specified with a 1-byte address field, program reduction is possible by using the working area for software flags, parameters, and counters. The V register can be replaced with the ALT register paired with an accumulator by means of the EXA instruction. 16 µPD78C17 PD78C17,78C18 78C18 (c) Accumulator (A) In the µPD78C17 PD78C17 and 78C18 78C18, because an accumulator type architecture is used, 8-bit data processing such as 8-bit arithmetic and logical operation instructions is mainly performed by this accumulator. This accumulator can be replaced with the ALT register paired with the vector register (V) by means of the EXA instruction. (d) Expansion accumulator (EA) 16-bit data processing such as 16-bit arithmetic and logical operation instructions is mainly performed by EA. This accumulator can be replaced with the ALT register EA' by means of the EXA instruction. (e) Program counter (PC) This is a 16-bit register which holds information on the next program address to be executed. This register is normally incremented automatically according to the number of bytes of the instruction to be fetched. When an instruction associated with a branch is executed, immediate data or register contents are loaded. RESET input clears this counter to 0000H 0000H. (f) Stack pointer (SP) This is a 16-bit register which holds the start address of the memory stack area (LIFO format). SP contents are decremented when a CALL or PUSH instruction is executed or an interrupt is generated, and incremented when a RETURN or POP instruction is executed. 2.2 ARITHMETIC LOGIC UNIT (ALU) .16 BITS The ALU executes data processing such as 8-bit arithmetic and logical operations, shift and rotation, data processing such as 16-bit arithmetic and logical operations and shift operations, 8-bit multiplication and 16-bit by 8-bit division. 2.3 PROGRAM STATUS WORD (PSW) This word consists of 6 types of flags which are set/reset according to instruction execution results. Three of these flags (Z, HC, and CY) can be tested by an instruction. PSW contents are automatically saved to the stack when an interrupt (external, internal, or SOFTI instruction) is generated, and restored by the RETI instruction. RESET input resets all bits to (0). Fig. 2-2 PSW Configuration 7 6 5 4 3 2 1 0 0 Z SK HC L1 L0 0 CY (a) Z (Zero) When the operation result is zero, this flag is set (1). In all other cases, it is reset (0). (b) SK (Skip) When the skip condition is satisfied, this flag is set (1). If the condition is not satisfied, it is reset (0). (c) HC (Half Carry) If an 8-bit operation generates a carry out of bit 3 or a borrow into bit 3, this flag is set (1). In all other cases, it is reset (0). (d) L1 When the "MVI A, byte" instruction is stacked, this flag is set (1). In all other cases, it is reset (0). 17 µPD78C17 PD78C17,78C18 78C18 (e) L0 When the "MVI L, byte;LXI H, word" instruction is stacked, this flag is set (1). In all other cases, it is reset (0). (f) CY (Carry) When a 16-bit operation generates a carry out of or a borrow into bit 7 or 15, this flag is set (1). In all other cases, it is reset (0). When one of 35 types of ALU instructions, rotation instructions, or carry manipulation instructions is executed, various flags are affected as shown in Table 2-1. Table 2-1 Flag Operations 18 0 0 0 0 q 0 0 0 0 q 0 q 0 0 0 q 0 0 0 q 0 0 q 0 q 0 0 0 1 0 0 0 q q 0 q 0 1 q q q 0 q 1 q 0 q 0 q 0 0 q 0 q 0 q . q 0 q q 0 q 0 q 0 q 0 q 0 q 1 BIT SK SKN SKIT SKN IT RETS Other All instructions 0 ADD ADDX ADI ADDW ADC ADCX ACI ADCW SUB SUBX SUI SUBW SBB SBBX SBI SBBW DADD DADC DSUB DSBB EADD ESUB ANA ANAX ANIW ANI ANAW ORA ORAX ORIW ORI ORAW XRA XRAX XRI XRAW DAN DOR DXR ADDNC ADDNCW ADDNCX ADINC SUBNB SUBNBW SUBNBX SUINB GTA GTAX GTIW GTI GTAW LTA LTAX LTIW LTI LTAW DADDNC DSUBNB DGT DLT ONA ONAX ONIW ONI ONAW OFFA OFFIW OFFI OFFAW OFFAX DON DOFF NEA NEAX NEIW NEI NEAW EQA EQAX EQIW EQI EQAW DNE DEQ INR INRW DCR DCRW DAA RLR RLL SLR SLL DRLR DRLL DSLR DSLL SLRC SLLC STC CLC MVI A, byte MVI L, byte LXI H, word D6 D5 D4 D3 D2 D0 Z SK HC L1 L0 CY skip immediate Operation reg, memory 1 . 0 . q . Affected (Set or Reset) Set Reset No affected µPD78C17 PD78C17,78C18 78C18 2.4 MEMORY The µPD78C17 PD78C17 and 78C18 78C18 can address a maximum of 64 Kbytes of memory. The memory maps are shown in Figs. 2-3 and 2-4. The external memory area and the internal RAM area can be freely used as program memory and data memory. Because the access timing for internal memory and external memory are the same, processing can be executed at high speeds. (a) Interrupt start addresses The interrupt start addresses are all fixed as follows: NMI . 0004H 0004H INTT0/INTT1 . 0008H 0008H INT1/INT2 .0010H 0010H INTE0/INTE1 . 0018H 0018H INTEIN/INTAD . 0020H 0020H INTSR/INTST .0028H 0028H SOFTI .0060H 0060H (b) Call address table The call address of a 1-byte call instruction (CALT) can be stored in the 64-byte area (for 32 call addresses) from address 0080H 0080H to address 00BFH 00BFH. (c) Specific memory area The reset start address, interrupt start addresses, and the call table are allocated to addresses 0000H 0000H to 00BFH 00BFH, and this area takes account of these in use. Addresses 0800H 0800H to 0FFFH are directly addressable by a 2-byte call instruction (CALF). The µPD78C18 PD78C18 has on-chip mask programmable ROM in addresses 0000H 0000H to 7FFFH. (d) Internal data memory area 1-Kbyte RAM is incorporated in addresses FC00H FC00H to FFFFH. The RAM contents are retained for 1-Kbyte internal data memory area in standby operation. (e) External memory area With the µPD78C17 PD78C17, the external memory can be expanded in steps in 63-Kbyte area (0000H 0000H to FBFFH) by setting the MODE0 and MODE1 pins (see Table 2-3). With the µPD78C18 PD78C18, the external memory can be expanded in steps in 31-Kbyte area (8000H 8000H to FBFFH) by setting the MEMORY MAPPING register (see Fig. 2-13). The external memory is accessed using AD7 to AD0 (multiplexed address/data bus), AB7 to AB0 (address bus), and the RD, WR, and ALE signals. Both programs and data can be stored in the external memory. (f) Working register area A 256-byte working register area can be set in any memory location (specified by the V register) and working register addressing is possible. 19 µPD78C17 PD78C17,78C18 78C18 Fig. 2-3 µPD78C17 PD78C17 Memory Map 0000H 0000H 0000H 0000H 0004H 0004H RESET NMI 0008H 0008H INTT0/INTT1 0010H 0010H INT1/INT2 0018H 0018H INTE0/INTE1 0020H 0020H INTEIN/INTAD 0028H 0028H INTSR/INTST 0060H 0060H SOFTI 0080H 0080H LOW ADRS 0081H 0081H HIGH ADRS 0082H 0082H LOW ADRS 0083H 0083H HIGH ADRS 00BEH 00BEH LOW ADRS 00BFH 00BFH HIGH ADRS External Memory 64512 × 8 Bits FBFFH FC00H FC00H Internal RAMNote 1024 × 8 Bits Standby Area FFFFH Call Table Note Can only be used when the RAE bit of the MM register is 1. 20 t=0 t=1 t = 31 µPD78C17 PD78C17,78C18 78C18 Fig. 2-4 µPD78C18 PD78C18 Memory Map 0000H 0000H NMI 0008H 0008H INTT0/INTT1 0010H 0010H INT1/INT2 0018H 0018H INTE0/INTE1 0020H 0020H INTEIN/INTAD 0028H 0028H INTSR/INTST 0060H 0060H Internal ROM 32768 × 8 Bits RESET 0004H 0004H 0000H 0000H SOFTI 7FFFH 8000H 8000H External Memory 31744 × 8 Bits FBFFH FC00H FC00H Internal RAMNote 1024 × 8 Bits Standby Area FFFFH LOW ADRS 0080H 0080H 0081H 0081H Call Table HIGH ADRS 0082H 0082H 0083H 0083H HIGH ADRS LOW ADRS 00BEH 00BEH LOW ADRS 00BFH 00BFH 00C0H 00C0H HIGH ADRS t=0 t=1 t = 31 USER'S AREA Note Can only be used when the RAE bit of the MM register is 1. 7FFFH 21 µPD78C17 PD78C17,78C18 78C18 2.5 PORT FUNCTIONS (1) PA7 to PA0 (PORT A) This is an 8-bit input/output port which has input/output buffer and output latch functions. Port A can be set as to input or output bit-wise using the MODE A register. And µPD78C18 PD78C18 port A pull-up resistor specification is performed bit-wise by mask option. Port A is set as follows when setting the input port or after reset. High-impedance : Without pull-up resistor High level : With pull-up resistor Fig. 2-5 Port A WRM V DD MAn Latch Mask OptionNote Internal Bus WRP Output Latch RDO PAn Output Buffer RDI Note Only µ PD78C18 PD78C18 (a) When specified as output port (MAn = 0) The output latch is effective, enabling data exchange by a transfer instruction between the output latch and the accumulator. Direct bit setting/resetting of output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Once data is written to the output latch, the data is held until a port A manipulation instruction is executed or the data is reset. Fig. 2-6 Port A Specified as Output Port V DD Mask OptionNote Internal Bus WRP Output Latch PAn RDO Note Only µ PD78C18 PD78C18 22 µPD78C17 PD78C17,78C18 78C18 (b) When specified as input port (MAn = 1) PA line contents can be loaded into an accumulator by a transfer instruction. They can also be directly tested bit-wise by an arithmetic or logical operation instruction without the use of an accumulator. Fig. 2-7 Port A Specified as Input Port V DD Mask OptionNote WRP Internal Bus Output Latch PAn RDI Note Only µ PD78C18 PD78C18 Actual execution of an instruction which manipulates port A is performed in 8-bit units. If a port A read instruction (MOV A, PA) is executed, the input line contents of the port specified for input and the output latch contents of the port specified for output are loaded into an accumulator. When a port A write instruction (MOV PA, A) is executed, data is written to the output latch of both ports specified for input and output. However, the output latch contents of a bit specified as an input port cannot be loaded to the accumulator and are not output to an external pin (which functions as input pin), because the output buffer is off. · MODE A register (MA) 8-bit register which specifies port A input/output. Port A input/output can be specified bit-wise. If the MODE A register corresponding bit is set (1), this register is input, and if the bit is reset (0), this register is output. After RESET input or in the hardware STOP mode, all the bits are set, and port A is in the input mode resulting in the below status. High-impedance : Without pull-up resistor High level : With pull-up resistor Fig. 2-8 MODE A Register Format 7 6 5 4 3 2 1 MA 7 MA 6 MA 5 MA 4 MA 3 MA 2 MA 1 0 MA 0 0 PAn = Output 1 PAn = Input (n = 0 to 7) 23 µPD78C17 PD78C17,78C18 78C18 (2) PB7 to PB0 (PORT B) Like port A, port B is an 8-bit input/output port with input/output buffer and output latch functions. Port B can be set as an input or output port bit-wise using the MODE B register (MB). µPD78C18 PD78C18 port B pull-up resistor specification is performed bit-wise by mask option. Port B is set as follows when setting the input port or after reset. High-impedance : Without pull-up resistor High level : With pull-up resistor As with port A, direct bit setting/resetting of port B output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer to/from an accumulator is also possible. · MODE B Register (MB) Like the MODE A register, the MODE B register is an 8-bit register which specifies port B input/ output bit-wise. After RESET input or in the hardware STOP mode, all the bits are set (1), and port B is in the input mode resulting in the status below. High-impedance : Without pull-up resistor High level : With pull-up resistor Fig. 2-9 Mode B Register Format 7 6 5 4 3 2 MB 7 MB 6 MB 5 MB 4 MB 3 MB 2 1 0 MB 1 MB 0 0 PBn = Output 1 PBn = Input (n = 0 to 7) 24 µPD78C17 PD78C17,78C18 78C18 (3) PC7 to PC0 (PORT C) Port C (PC7 to PC0) is an 8-bit special input/output port which functions as various control signals as well as general-purpose input/output ports in which input/output is set bit-wise like port A. These are switched over bit-wise according to the setting of the MODE C register and MODE CONTROL C register as shown below. Table 2-2 Operation of PC7 to PC0 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 MCCn = 1 MCn = x TXD output RXD inpit SCK input/output INT2/TI input TO output CI input CO0 output CO1 output MCCn = 0 MCCn = 0 MCn = 1 Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input (n = 0 to 7) µPD78C18 PD78C18 port C pull-up resistor specification is performed bit-wise by mask option. In the operation when data is set in the general-purpose input/output ports, as with port A, direct bit setting/resetting/testing of port C output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer to/from an accumulator is also possible. · MODE CONTROL C Register (MCC) 8-bit register which specifies the port C port/ control signal input/output mode bit-wise. If the MODE CONTROL C register corresponding bits are set (1), PC7 to PC0 are in the control signal input/output mode, and if these are reset (0), in the port mode. After RESET input or in the hardware STOP mode, all the bits of the MODE CONTROL C register are reset (0), and the port mode is set. 25 µPD78C17 PD78C17,78C18 78C18 Fig. 2-10 MODE CONTROL C Register Format 7 6 5 4 3 2 1 0 MCC7 MCC6 MCC5 MCC4 MCC3 MCC2 MCC1 MCC0 0 1 PC0 = TXD output 0 PC1 = Port mode 1 PC1 = RXD input 0 PC2= Port mode 1 PC2 = SCK input/output 0 PC3 = Port mode 1 PC3 = INT2/TI input 0 PC4 = Port mode 1 PC4= TO output 0 PC5 = Port mode 1 PC5 = CI input 0 PC6= Port mode 1 PC6 = CO0 output 0 PC7 = Port mode 1 26 PC0 = Port mode PC7 = CO1 output µPD78C17 PD78C17,78C18 78C18 · MODE C register (MC) The MODE C register is an 8-bit register by which, like the MODE A register of port A, port C input/ output specification is performed bit-wise. Contents of the MODE C register corresponding to the bits set to the control mode by the MODE CONTROL C register are ignored. After RESET input or in the hardware STOP mode, all bits of the MODE C register are set (1). And this time, because all bits of the MODE CONTROL C register are reset (0), port C becomes an input port and the below state is set. High-impedance : Without pull-up resistor High level : With pull-up resistor Fig. 2-11 MODE C register Format 7 6 5 4 3 2 1 0 MC 7 MC 6 MC 5 MC 4 MC 3 MC 2 MC 1 MC 0 0 PCn = Output 1 PCn = Input (n = 0 to 7) (4) PD7 to PD0 (PORT D) s µPD78C17 PD78C17 Can be used for address/data bus. These have no functions as a port. s µPD78C18 PD78C18 8-bit general-purpose input/output ports also used as multiplexed address/data bus. These ports can be specified for input/output in byte units (8-bit units) as general-purpose input/output ports, and function as multiplexed address/data bus when external expansion memory is connected. This switchover is performed by the MEMORY MAPPING register. In the operation when data is set in the general-purpose input/output ports, unless input/output is specified in byte units, as with port A, direct bit setting/resetting/testing of port F output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer to/from an accumulator is also possible. 27 µPD78C17 PD78C17,78C18 78C18 (5) PF7 to PF0 (PORT F) s µPD78C17 PD78C17 General-purpose input/output ports also used as address bus. These pins function as address outputs corresponding to the size of externally installed memory according to the MODE0 and MODE1 pin settings. Pins which are not used for address output can be used for general-purpose input/output ports which have the same port function as for port A. Input/output setting is performed by the MODE F register. Table 2-3 Operation of µ PD78C17 PD78C17's PF7 to PF0 MODE1 MODE0 PF 7 PF 6 PF 5 PF 4 0 0 Port Port Port 0 1 Port Port AB13 AB12 1 0 1 1 External Address Space PF 3 PF 1 PF 0 AB11 AB10 AB9 AB8 4 Kbytes AB11 Port PF 2 AB10 AB9 AB8 16 Kbytes AB8 63 Kbytes Setting prohibited AB15 AB14 AB13 AB12 AB11 AB10 AB9 When this is set as general-purpose input/output ports, as with port A, direct bit setting/resetting/ testing of port C output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer to/from an accumulator is also possible. · µPD78C17 PD78C17 MEMORY MAPPING register (MM) A register which controls internal RAM access permission. Bit 3 (RAE) of the MEMORY MAPPING register controls whether or not internal RAM is permitted. When internal RAM is used in external extension and external memory is used in the area, RAE bit is set to "0" and internal RAM access is prohibited. Contents of RAE bit is retained, even if RESET signal is input in the normal operation. However, at power-on reset, RAE bit is undefined and RAE bit should be initialized by an instruction. Fig. 2-12 µPD78C17 PD78C17 MEMORY MAPPING Register Format 7 6 5 4 3 2 1 0 RAE 0 0 0 Internal RAM Access 0 1 28 Disable Enable µPD78C17 PD78C17,78C18 78C18 s µPD78C18 PD78C18 8-bit general-purpose input/output ports also used as address bus. Can specify input/output bit-wise as general-purpose input/output ports, and address signal is output according to external extension memory size when the external expansion memory of 256 bytes or greater is accessed. This switchover is performed by the MEMORY MAPPING and MODE F registers. PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 External Memory Port Port Port Port Port Port Port Port Maximum 256 bytes Port Port Port Port AB11 AB10 AB9 AB8 Maximum 4 Kbytes Port Port AB13 AB12 AB11 AB10 AB9 AB8 Maximum 16 Kbytes AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 Maximum 31 Kbytes When this is set as general-purpose input/ourput ports, as with port A, direct bit setting/resetting/testing of port C output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer to/from an accumulator is also possible. · µPD78C18 PD78C18 MEMORY MAPPING register (MM) 4-bit register which specifies PD7 to PD0 and PF7 to PF0 port/extension mode and controls internal RAM access permission. Bits 0, 1, and 2 (MM0, MM1, MM2) in the MEMORY MAPPING register control specification of PD7 to PD0 port/extension mode, input/output, and PF7 to PF0 address line. When bits MM1 and MM2 in the MEMORY MAPPING register are "0", PD7 to PD0 and PF7 to PF0 are set as general-purpose input/output port, input/output of PD7 to PD0 is specified by MM0, and input/output of PF7 to PF0 is specified by the MODE F register. 4 types of external extension memory (256 bytes, 4 Kbytes, 16 Kbytes, and 31 Kbytes) can be selected, and ports which are not used for address line are used as general-purpose input/output ports. Bit 3 (RAE) of the MEMORY MAPPING register controls whether or not the access to internal RAM is permitted. When internal RAM is not used in external extension and external memory uses the area, RAE bit is set to "0" and internal RAM access is prohibited. After RESET input or in the hardware STOP mode, bits MM0, MM1, and MM2 of the MEMORY MAPPING register are reset (0), and PD7 to PD0 become input ports (high-impedance). Even if the RESET signal is input in the normal operation, contents of the RAE bit are retained. However, the RAE bit is undefined after power-on reset, the RAE bit should be initialized by an instruction. 29 µPD78C17 PD78C17,78C18 78C18 Fig. 2-13 µPD78C18 PD78C18 MEMORY MAPPING Register Format 7 6 5 4 3 2 1 0 RAE MM2 MM1 MM0 PD7 to PD0 = Input port PF7 to PF0 = Port mode PD7 to PD0 = Output port 1 PF7 to PF0 = Port mode PD7 to PD0 = Extension 256 bytes 0 mode PF7 to PF0 = Port mode PD7 to PD0 = Extension 4 Kbytes PF3 to PF0 = 0 mode PF7 to PF4 = Port mode ExtenPD7 to PD0 = Extension sion 16 Kbytes PF5 to PF0 = mode 0 mode PF7 and PF6 = Port mode Extension 31 Kbytes PD7 to PD0 = 1 mode PF7 to PF0 = 0 0 0 0 0 0 1 1 0 1 1 1 1 Single Port mode chip Internal RAM Access 0 1 · Disable Enable MODE F register (MF) The MODE F register specifies port F input/output in the same way as for the MODE A register in port A. However, contents of the MODE F register corresponding to port F bits specified as address line by the MEMORY MAPPING register are in the output mode. After RESET input or in the hardware STOP mode, all the bits of the MODE F register are set (1) and port F is an input port (high-impedance). Fig. 2-14 MODE F Register Format 7 6 5 4 3 2 1 0 MF 7 MF 6 MF 5 MF 4 MF 3 MF 2 MF 1 MF 0 0 PFn = Output 1 PFn = Input (n = 0 to 7) 30 µPD78C17 PD78C17,78C18 78C18 2.6 TIMER This is an interval timer which has two 8-bit timers (TIMER0, TIMER1). These are programmable independently. By cascading these can also be used as 16-bit interval timer, and can be used for counting TI input. The timer is composed of TIMER0 and TIMER1, as shown in 2-15, including 8-bit TIMER REG (TM0, TM1), 8bit COMPARATOR, 8-bit UPCOUNTER, and TIMER F/F. Input selection, timer operation and TO output are controlled by the timer mode register (TMM). In TIMER0, 12 (1 µs: 12-MHz operation) and 384 (32 µs: 12-MHz operation) internal clock and TI input are input. In TIMER1, not only these inputs but also TIMER0 match signal are input. Because TIMER0 operates in the same way as TIMER1, TIMER0 operation is described below. At first, a count value is set in TIMER REG0, and TIMER0 input and TIMER0 start data (bit 4 in the timer mode register = "0") are set in the timer mode register to start TIMER0. The UPCOUNTER is incremented one input at a time. The COMPARATOR always compares contents of the incremented UPCOUNTER with those of TIMER REG0, and if these match, the match signal (internal interrupt: INTT0) is generated. This match clears contents of UPCOUNTER and increment starts again from 00H. Therefore, the interval is set by count time, which is a count value set by TIMER REG0. This allows the timer to operate as an interval timer which generates interrupts repeatedly. By setting (1) bit 1 (MKT0) of the interrupt mask register (MKL), internal interrupt (INTT0) is disabled. The TO output has timers COMPARATOR match signal and TIMER F/F complemented by 3 (250 ns: 12-MHz operation) internal clocks, and can obtain a square wave which has a half period of the count time or 3. By setting the timer/event counter mode register (ETMM), this output can be used for the timer event counter reference time. By setting the serial mode register (SMH), the timer can be used as the serial clock (SCK) in serial interface. 31 µPD78C17 PD78C17,78C18 78C18 Fig. 2-15 Timer Block Diagram 3 TIMER F/F TIMER1 TIMER0 PC3/TI Timer/Event Counter Serial Interface Clear 12 Clear 12 UPCOUNTER 384 UPCOUNTER 384 COMPARATOR COMPARATOR TIMER REG 0 (TM0) INTT0 TIMER REG 1 (TM1) Internal Bus 1. 3 = fXX x 1/3 2. 3. Remarks 32 PC4/TO 12 = f XX x 1/12 384 = fXX x 1/384 Where, fXX = oscillation frequency (MHz) INTT1 µPD78C17 PD78C17,78C18 78C18 (1) Timer mode register (TMM) This is an 8-bit register which controls TIMER0, TIMER1, and TIMER F/F operation (see Fig. 2-16). The timer mode register bits 0 and 1 (TF0, TF1) control the TIMER F/F operating mode, bits 2 and 3 (CK00, CK01) control TIMER0 input clock, bit 4 (TS0) controls TIMER0 operation. Bits 5 and 6 (CK10, CK11) control TIMER1 input clock, and bit 7 (TS1) controls TIMER1 operation. TS0 and TS1 bits clear these UPCOUNTERs to 00H by "1", and stop increment. By changing "1" to "0", the UPCOUNTER starts increment from 00H. The internal clock (3) divides the oscillator frequency by 3, the internal clock (12) divides it by 12, and the internal clock (384) divides it by 384. After RESET input, the timer mode register is set to FFH, the UPCOUNTERs in TIMER0 and TIMER1 are cleared in the suspended state, and TIMER F/F is reset. Fig. 2-16 Timer Mode Register (TMM) Format 7 TMM 6 5 4 3 2 1 TS1 CK11 CK10 TS0 CK01 CK00 TF1 0 TF0 TIMER F/F Input, Operating Mode 0 0 TIMER0 COMPARATOR match signal 0 1 TIMER1 COMPARATOR match signal 1 0 Internal clock (3) 1 1 TIMER F/F reset TIMER0 Input Clock 0 0 Internal clock (12) 0 1 Internal clock (384) 1 0 TI input 1 1 Disable TIMER0 Operation 0 Increment 1 Reset TIMER0 Input Clock 0 0 Internal clock (12) 0 1 Internal clock (384) 1 0 TI input 1 1 TIMER0 COMPARATOR match signal TIMER1 Operation 0 Increment 1 Reset 33 µPD78C17 PD78C17,78C18 78C18 2.7 TIMER/EVENT COUNTER The µPD78C17 PD78C17 and 78C18 78C18 have a 16-bit multi-function timer/event counter having the following functions. o o o o o o Interval timer External event counter Frequency measurement Pulse width measurement Programmable square wave output One pulse output The timer/event counters are composed of 16-bit timer/event counter upcounter (ECNT), timer/event counter capture register (ECPT), comparator, timer/event counter REG0 and REG1 (ETM0, ETM1), control circuits for I/O, interrupt, and clear. ECNT is a 16-bit upcounter which counts an input pulse, and cleared by the clear control circuit. The ECPT register is a 16-bit buffer register which retains the contents of ECNT. The timing to latch contents of ECNT by the ECPT register is the falling edge of CI input when input to ECNT is an internal clock, and is the falling edge of TO output when input to ECNT is CI input. The ETM0 and ETM1 registers are two 16-bit registers which set a number of counts and data is exchanged by 16-bit data transfer instructions via an extended accumulator. The comparator compares contents of ECNT with contents of the ETM0 and ETM1 registers, and if these match, a match signal is generated. The interrupt control circuit controls interrupts from the timer/event counter. The following interrupt sources are generated. These are generated by three signals: the ECNT and ETM0 register match signal (INTE0), the ECNT and ETM1 register match signal (INTE1), and the CI input or timer output (TO) falling edge (INTEIN). 34 µPD78C17 PD78C17,78C18 78C18 Fig. 2-17 Timer/Event Counter Block Diagram Internal Bus Timer/event Counter Capture Reg. (ECPT) 12 PC5/CI Input Control Timer/event Counter Capture Reg. (ECNT) Clear Control PC6/CO0 Output Control TO PC7/CO1 Comparator Comparator Timer/event Counter REG1 (ETM1) Timer/event Counter REG0 (ETM0) CP0 CP1 Mode Register (ETMM, EOM) INTE0 Interrupt Control INTE1 EIN INTEIN Internal Bus Edge Detection Remarks 12 = f XX x 1/12, where fXX = oscillation frequency (MHz) 35 µPD78C17 PD78C17,78C18 78C18 Next, using pulse width measurement as an example, the operation is described. This operation purpose is measurement for high-level width of external pulse input to CI. This is performed by setting the timer/event counter mode register (ETMM) to 09H. ECNT continues internal clock (12) count while CI is high. If the external pulse which is input to CI falls, the contents of ECNT are transferred to the ECPT register. ECNT is cleared and an internal interrupt (INTEIN) is generated (see Fig. 2-18). Therefore, using contents of the ECPT register and internal clock period, the pulse width is measured. Fig. 2-18 Pulse Width Measurement Reference Clock (12) CI Input ECNT Input EIN Interrupt Transfer ECNT contents to ECPT register Clear ECNT 36 µPD78C17 PD78C17,78C18 78C18 The µPD78C17 PD78C17 and 78C18 78C18 have an output control circuit which outputs pulses which can be changed in pulse width and period by interlocking with the timer/event counter. The output control circuit outputs are CO0 output and CO1 output. Because these share the same configuration, CO0 output is described. Fig. 2-19 shows the CO0 configuration. CO0 output is a master-slave type output. The first phase level F/F (LV0) retains the level which is output next, and the second phase output latch outputs the LV0 level to off-chip. By setting the timer/event counter output mode register (EOM), LV0 can be set/reset. LV0 has a level inversion pin (INV) and LV0 level can be inverted at the output time by setting the timer/event counter mode register. Timing when the output latch outputs LV0 level to off-chip is performed by output timing of the timer/event counter mode register setting. Fig. 2-19 Output Control Circuit Level Flipflop LRE0 R LRE1 S Q LD0 Output Latch LV0 D O PC6/CO0 CK INV CP0 CP1 CI LO0 37 µPD78C17 PD78C17,78C18 78C18 Next, the operation which outputs a square wave to the CO0 pin is described. At first, after ECNT is cleared, a count value (ETM0 < ETM1) is set in the ETM0 and ETM1 registers, and data for LV0 initial status specification and to enable LV0 level inversion is set in the timer/event counter output mode register. In the timer/event counter mode register, by setting an input to ECNT to 12 (1 µ s: 12-MHz operation) internal clock, the ECNT clear mode to the ECNT and ETM1 register match signal, and CO0 pin output timing to the ECNT and ETM0 register match signal or ECNT and ETM1 register match signal, the timer/event counter starts operation. ECNT is incremented one 12 internal clock at a time, the comparator compares incremented ECNT with the ETM0 and ETM1 registers, and if these match, the match signal (CP0, CP1) is generated. By this match signal, LV0 level is output to the CO0 pin, and LV0 level is inverted. ECNT is cleared by the ECNT and ETM1 register match signal (CP1), ECNT increments again from 0000H 0000H, and the above-mentioned steps are repeated (see Fig. 2-20). Therefore, a programmable square wave which has the ETM0 and ETM1 register count as a pulse width is output. Fig. 2-20 Square Wave Output Reference Clock (12) 0 m n0 CP0 CP1 CO0 Start Remarks ETM0 register = m ETM1 register = n 38 (m < n: m and n are count values.) m n0 µPD78C17 PD78C17,78C18 78C18 (1) Timer/event counter mode register (ETMM) This is an 8-bit register which controls the timer/event counter (see Fig. 2-21). The timer/event counter mode register bits 0 and 1 (ET0, ET1) control the timer event counter upcounter (ECNT) input clock, bits 2 and 3 (EM0, EM1) control the ECNT clear mode, bits 4 and 5 (CO00, CO01) control output timing when the output latch contents are output to the counter output0 (CO0). Bits 6 and 7 (CO10, CO11) control CO1 output timing. The internal clock (12) divides the oscillation frequency by 12. After RESET input or in the hardware STOP mode, the timer/event counter mode register is reset to 00H. Fig. 2-21 Timer/Event Counter Mode Register Format 7 ETMM 6 5 4 CO11 CO10 CO01 CO00 3 2 1 0 EM 1 EM 0 ET 1 ET 0 ECNT Input Clock 0 0 0 1 Internal clock (12) 12 while CI input is in the high level 1 0 CI input 1 1 CI input while TO is in the high level ECNT Clear Mode 0 0 Stop after clear 0 1 Free running Clear a full count at a time 1 0 Clear at the fall of CI input (ET1 = 0) Clear the fall of TO (ET1 = 1) 1 1 Clear by matching ECNT and ETM1 CO0 Output Timing 0 0 ECNT and ETM0 match 0 1 Setting prohibited 1 0 ECNT and ETM0 match, or CI input fall 1 1 ECNT and ETM0 match, or ECNT and ETM1 match CO1 Output Timing 0 0 ECNT and ETM1 match 0 1 Setting prohibited 1 0 ECNT and ETM1 match, or CI input fall 1 1 ECNT and ETM0 match, or ECNT and ETM1 match 39 µPD78C17 PD78C17,78C18 78C18 (2) Timer/event counter output mode register (EOM) This is an 8-bit register which controls the timer/event counters CO0 and CO1 (Counter Output 0, 1) operating mode. The timer/event counter output mode register bits 0 and 4 (LO0, LO1) control whether or not LV0 and LV1 level are output to the CO0 and CO1 pins, bits 1 and 5 (LD0, LD1) control whether or not LV0 and LV1 level are inverted at an output timing specified by the timer/event counter mode register, bits 2, 3, 6, and 7 (LRE0, LRE1, LRE2, LRE3) control LV0 and LV1 setting/resetting. Bits LO0, LO1, LRE0, LRE1, LRE2, and LRE3 are automatically reset (0) after individual operations. After RESET input or in the hardware STOP mode, the timer/event counter output mode register is reset to 00H. Fig. 2-22 Timer/Event Counter Output Mode Register (EOM) Format 7 6 5 4 3 2 1 0 LRE3 LRE2 LD 1 LO 1 LRE1 LRE0 LD 0 LO 0 LV0 Data Output 0 No operation 1 Output contents of LV0 LV0 Level Inversion 0 Disable 1 Enable LV0 Set/Reset 0 0 No operation 0 1 Resets LV0 1 0 Sets LV0 1 1 Setting prohibited LV1Data Output 0 No operation 1 Output contents of LV1 LV1 Level Inversion 0 Disable 1 Enable LV1 Set/Reset 0 No operation 0 1 Resets LV1 1 0 Sets LV1 1 40 0 1 Setting prohibited µPD78C17 PD78C17,78C18 78C18 2.8 SERIAL INTERFACE The µPD78C17 PD78C17 and 78C18 78C18 have the serial interface using the transmit/receive method by start/stop bit. The three types of operating modes are shown below. · Asynchronous (start-stop) mode : Establishes data bit synchronization and character synchronization by start bit. · Synchronous mode · I/O interface mode : Data transfer is performed in synchronization with the serial clock. : As for serial data transfer in the µPD7801/78C06A PD7801/78C06A etc., data transfer is performed in synchronization with the serial clock. The serial interface block is composed of the serial data input (RxD), serial data output (TxD), 3 serial clock input/output (SCK) pins, transfer control block, two 8-bit serial registers for transmission and reception, and 8bit transmission buffer and reception buffer (see Fig. 2-23). As the serial registers and buffers for transmission and reception are provided, transmission or reception is individually performed (full-duplex double buffer transmitter/receiver). However, the serial clock (SCK) is shared in transmission and reception, and half-duplex transmission/ reception is performed in the synchronous mode and I/O mode. Fig. 2-23 Serial Interface Block Diagram Internal Bus Serial Mode Register (SML, SMH) Receive Buffer (RXB) INTSR Serial Register (S¡P) PC1/R×D Reception Control Transmit Buffer (TXB) INTST Serial Register (P¡S) ER Transmission Control 24 PC2/SCK 384 TO Output SK1, SK2 PC0/T×D Remarks 24 = f XX x 1/24 384 = fXX x 1/384 Where, fXX = oscillation frequency (MHz) 41 µPD78C17 PD78C17,78C18 78C18 (1) Asynchronous mode In case of the asynchronous mode, clock rate, character length, number of stop bits, parity enable, and odd or even parity specifications can be controlled by the serial mode register (SML). Transmission operation is enabled by setting (1) bit 2 (TxE) of the serial mode register (SMH). If data is written to the transmission buffer by the "MOV TXB, A" instruction and preceding data transfer is terminated, contents of the transmission buffer are transferred to the serial register automatically. The start bit (1 bit), parity bit (odd/even number, no parity), and stop bit (1 or 2 bits) are automatically added to data which is transferred to the serial register. And this data is transmitted from the TxD pin starting from the least significant bit (LSB). If the transmit buffer is empty, the internal interrupt (INTST) is generated. Transmission data is transmitted from the TxD pin at the fall of SCK in the transfer speed of x1, x1/16, or x1/64 serial clock (SCK). The maximum data transfer speed in transmission is set by SCK and clock rate in 12-MHz operation as shown below. SCK Internal Clock SCK Data Transfer Speed SCK Data Transfer Speed 500 kHz 500 kbps 660 kHz 660 kbps Clock Rate x1 External Clock x16 125 kbps 125 kbps 2 MHz 2 MHz x64 31.25 kbps 31.25 kbps When TxE is "0" or the serial register has no transmitted data, the TxD pin is in the marking state (1). By setting bit 2 (MKST) of the interrupt mask register (MKH), the internal interrupt (INTST) is disabled. Fig. 2-24 Asynchronous Data Format Start Bit D0 D1 DN Parity Bit N = 6, 7 42 Stop Bit µPD78C17 PD78C17,78C18 78C18 Fig. 2-25 Serial Mode Register Format in Asynchronous Mode 7 SML 6 5 4 3 2 1 0 S2 S1 EP PEN L2 L1 B2 B1 Clock Rate 0 1 x1 1 0 x16 1 1 x64 Character Length 0 0 Setting prohibited 0 1 Setting prohibited 1 0 7 bits 1 1 8 bits Parity Enable 0 Disable 1 Enable Even Parity Generation/Check 0 Odd number 1 Even number Number of Stop Bits 0 SMH 4 3 2 1 0 0 0 RxE TxE SK2 0 Setting prohibited 1 2 bits 0 0 1 bit 1 5 1 1 6 Setting prohibited 0 7 0 SK1 SCK Selection 0 0 Internal clock (TO output) 0 1 Internal clock (384) 1 0 Internal clock (24) 1 1 External clock Transmission Enable 0 Disable 1 Enable Reception Enable 0 Disable 1 Enable 43 µPD78C17 PD78C17,78C18 78C18 Receive operation is enabled by setting (1) bit 3 (RxE) of the serial mode register (SMH). The start bit is confirmed by detecting the low level of RxD input and the low level after 1 or 2 bits. Reception is performed by sampling character bit, parity bit, and stop bit following the low level. When data specified in the serial register from RxD is input, data is transferred to the receive buffer. If the receive buffer is full, the internal interrupt (INTSR) is generated. By setting (1) bit 1 (MKSR) of the interrupt mask register (MKH), the internal interrupt (INTSR) is disabled. In reception, odd or even parity is checked (when PEN bit = 1). If data do not match (parity error), if stop bit is low (framing error), or if the next data is transferred to the receive buffer when the receive buffer is full (overrun error), the error flag is set (1). However, because error interrupt mechanism is not provided, test is executed by the skip instruction (SKIT, SKNIT). The serial clock (SCK) can be selected as an external or internal clock by the serial mode register (SMH). Three types of 24, 384, or TO outputs can be selected as internal clock. This clock can be output to offchip. Or the external serial clock can be input. By using the internal clock (TO output) as SCK, the data transfer speed can be flexibly changed by program. The maximum data transfer speed in reception is set by SCK and the clock rate in 12-MHz operation as shown below. SCK External Clock SCK Clock Rate x1 Internal Clock Note2 Data Transfer Speed SCK Data Transfer Speed 500 kHz 500 kbps 660 kHz 1 MHz 660 kbps 1 MbpsNote1 x16 125 kbps 125 kbps 2 MHz x64 Notes 2 MHz 31.25 kbps 31.25 kbps 1. If data of transfer speed 660 kbps to 1 Mbps is received, 2 stop bits are required. 2. In x1 clock rate, RxD and SCK synchronization needs to be externally established. For an example, when data is transferred in the data transfer speed of 110 to 9600 bps, when the timer input clock is set as internal clock (12), the timer count value (C) is shown below. Oscillation Frequency (MHz) Data Transfer N Speed (bps) 9600 C = 4800 2400 1200 600 300 150 110 44 7.3728 11.0592 64 16 2 4 C= 8 16 32 64 128 175 16 ­ 1 2 4 8 16 32 44 C= 14.7456 16 64 3 6 12 24 48 96 192 262 C= ­ ­ 3 6 12 24 48 65 C= 64 4 8 16 32 64 128 256 370 C= 1 2 4 8 16 32 64 88 µPD78C17 PD78C17,78C18 78C18 (2) Synchronous mode In the synchronous mode, data transfer is performed with 8-bit character length fixed, and with no parity bit. Therefore, the serial mode register (SML) is set to 0CH (see Fig. 2-26). Transmission operation is enabled by setting (1) bit 3 (TxE) of the serial mode register (SMH). If data is written to the transmit buffer by the "MOV TXB, A" instruction and preceding data transfer is terminated, the contents of the transmit buffer are automatically transferred to the serial register and converted to serial data, and data starting from LSB are transmitted from TxD at the falling edge of SCK. The serial data is transferred in the same rate as for SCK. Data transfer speed in transmission is maximum 500 kbps when an internal clock is used for SCK and maximum 1 Mbps when an external clock is used (12-MHz operation). When data is transferred from the transmit buffer to the serial register and the transmit buffer is empty, the internal interrupt (INTST) is generated. When TxE is "0" or the serial register has no transmitted data, the TxD pin is in the marking state (1). Fig. 2-26 Serial Mode Register Format in Synchronous Mode 7 SML 6 5 4 3 2 1 0 0 0 0 0 1 1 0 0 Synchronous Operation Character Length 8-Bit Fixed Parity Disable 7 SMH 6 5 4 3 2 1 0 0 0 0 SE RxE TxE SK 2 SK 1 SCK Selection 0 0 Internal clock (TO output) 0 1 Internal clock (384) 1 0 Internal clock (24) 1 1 External clock Transmission Enable 0 Disable 1 Enable Reception Enable 0 Disable 1 Enable Search Mode 0 Disable 1 Enable 45 µPD78C17 PD78C17,78C18 78C18 In the synchronous mode, 2 types of receive operation can be selected. This mode can be controlled by SE bit of the serial mode register (SMH). By setting SE bit (1), the search mode is set. On each 1-bit reception from the RxD pin, the contents of the serial register are transferred to the receive buffer and the internal interrupt (INTSR) is generated. Because the µPD78C17 PD78C17(A)/78C18 /78C18(A) don't have a synchronous character detection circuit by hardware, a synchronous character detection is required by software. If receive synchronization is established after a synchronous character is detected, SE bit is reset (0). By resetting the SE bit, the character mode is set. On each 8-bit data reception, the contents of the serial register are transferred to the receive buffer and the internal interrupt (INTSR) is generated. By setting (1) MKSR bit of the interrupt mask register, the internal interrupt (INTSR) is disabled. In the synchronous mode, data is output from TxD at the falling edge of SCK, and data is input from RxD at the rising edge of SCK. SCK can be selected as an internal clock or external clock by setting the serial mode register (SMH). Data transfer speed in reception is maximum 500 kbps when an internal clock is used for SCK and maximum 660 kbps when an external clock is used (12-MHz operation). 46 µPD78C17 PD78C17,78C18 78C18 (3) I/O interface mode When input/output is extended to off-chip or I/O controllers (A/D converter, liquid crystal display controller, etc.) are connected to this chip, this mode is effective. In the I/O interface mode, data transfer is performed starting from the most significant bit (MSB) with 8-bit character length fixed, and with no parity bits. Therefore, the serial mode register (SML) should be set to 0CH and bit 5 (IOE) of the serial mode register (SMH) is set to "1". This mode establishes synchronization by controlled SCK (8 cycles of the serial clock) and SCK should be high except during data transfer. The transmission operation is enabled by setting (1) bit 2 (TxE) of the serial mode register (SMH). If data is written by the "MOV TXB, A" instruction, data is transferred to the serial register automatically, and is output from TxD at the falling edge of controlled SCK. The transmit buffer is empty, the internal interrupt (INTST) is generated. Data transfer speed in transmission is maximum 500 kbps when an internal clock is used for SCK and maximum 1 Mbps when an external clock is used (12-MHz operation). The reception operation is enabled by setting (1) bit 3 (RxE) of the serial mode register (SMH), and receive data is input to the serial register at the rising edge of controlled SCK. When the serial register receives 8-bit data, data is transferred from the serial register to the receive buffer and the internal interrupt (INTSR) is generated. SCK can be selected as an internal clock or external clock by the serial mode register (SMH). Data transfer speed in reception is maximum 500 kbps when an internal clock is used for SCK and maximum 660 kbps when an external clock is used for SCK (12-MHz operation). 6 states or more is required in 8th SCK high-level width. 47 µPD78C17 PD78C17,78C18 78C18 Fig. 2-27 Serial Mode Register Format in I/O Interface Mode 7 SML 6 5 4 3 2 1 0 0 0 0 0 1 1 0 0 Synchronous Operation Character Length 8-Bit Fixed Parity Disable 7 SMH 6 5 4 3 2 1 0 0 TSK 1 0 RxE TxE SK 2 SK 1 SCK Selection 0 0 Internal clock (TO output) 0 1 Internal clock (384) 1 0 Internal clock (24) 1 1 External clock Transmission Enable 0 Disable 1 Enable Reception Enable 0 Disable 1 Enable I/O Interface Mode SCK Trigger 0 1 48 Disable Enable µPD78C17 PD78C17,78C18 78C18 (4) Serial mode register (SML, SMH) These are two 8-bit registers which control the serial interface operation (see Figs. 2-28 and 2-29). The serial mode low register (SML) bits 0 and 1 (B1, B2) control switchover of the asynchronous mode and synchronous operation and clock rate in the asynchronous mode, bits 2 and 3 (L1, L2) control character length, bit 4 (PEN) controls parity enable, bit 5 (EP) controls odd or even parity, and bits 6 and 7 (S1, S2) control a number of stop bits. After RESET input or in the hardware STOP mode, the serial mode low register (SML) is set to 48H. The serial mode high register (SMH) bits 0 and 1 (SK1, SK2) control whether an internal clock or external clock is used as the serial clock (SCK), bit 2 (TxE) controls the transmission operation, bit 3 (RxE) controls the reception operation, bit 4 (SE) controls whether or not the search mode is set in the synchronous mode. Bit 5 (IOE) controls whether the synchronous mode or I/O interface mode is set, and bit 6 (TSK) starts the serial clock when data is received using the internal clock in the I/O interface mode. The TSK bit is automatically reset (0) after the serial clock starts. When the serial clock is specified as an internal clock, the SCK value is determined by the following expressions. Internal clock (24): SCK = fXX/24 Internal clock (384): SCK = fXX/384 Internal clock (TO output): Timer input clock is 12: SCK = fXX/(24 x C) Timer input clock is 384: SCK = fXX/(768 x C) TIMER F/F input is 3: SCK = fXX/6 However, fXX is set in the oscillation frequency, SCK is set in the serial clock, and C is set in the timer count value. When TIMER F/F input is 3 in case of the internal clock (TO output), the asynchronous mode can only be used when the clock rate is 16 or 64. After RESET input or in the hardware STOP mode, the serial mode high register (SMH) is reset to 00H. 49 µPD78C17 PD78C17,78C18 78C18 Fig. 2-28 Serial Mode Low Register (SML) Format 7 6 5 4 3 2 1 S2 S1 EP PEN L2 L1 B2 0 B1 Clock Rate 0 0 0 1 x1 1 0 x 16 1 1 x 64 Synchronous Operation Character Length 0 0 Setting prohibited 0 1 Setting prohibited 1 0 7 bits 1 1 8 bits Parity Enable 0 Disable 1 Enable Even Parity Generation/Check 0 Odd number 1 Even number Number of Stop Bits 0 Setting prohibited 0 1 1 bit 1 0 Setting prohibited 1 50 0 1 2 bits µPD78C17 PD78C17,78C18 78C18 Fig. 2-29 Serial Mode High Register (SMH) Format 7 6 5 4 3 2 1 0 TSK IOE SE RxE TxE SK 2 0 SK 1 SCK Selection 0 0 Internal clock (TO output) 0 1 Internal clock (384) 1 0 Internal clock (24) 1 1 External clock Transmission Enable 0 Disable 1 Enable Reception Enable 0 Disable 1 Enable Search Mode 0 Disable 1 Enable I/O interface Mode 0 Disable 1 Enable SCK Trigger 0 Disable 1 Enable 51 µPD78C17 PD78C17,78C18 78C18 2.9 ANALOG/DIGITAL CONVERTER The µPD78C17 PD78C17 and 78C18 78C18 have on-chip 8-bit high-speed and high-resolution analog/digital (A/D) converter with 8-multiplexed analog input (AN7 to AN0), and 4 "Conversion Result" registers (CR0 to CR3) to retain a conversion result. This A/D converter uses the successive approximation method. In the A/D converter operation, either the scan mode or select mode can be selected by software. In the select mode, one of analog inputs is selected by the A/D channel mode register before starting A/D conversion. Conversion values are stored to CR0 through CR3 sequentially. In the scan mode, Analog conversion values AN0 to AN3 or AN4 to AN7 are stored to CR0 through CR3 sequentially. This mode switchover is specified by the A/D channel mode register. In case of the select mode, one of the analog inputs is selected by the A/D channel mode register and the A/ D conversion starts. Conversion values are stored to CR0 through CR3 sequentially. When four CR registers are set to conversion values, the internal interrupt (INTAD) is generated. The A/D converter continues A/D conversion and sequential storage of conversion values beginning with CR0 until the A/D channel mode register is changed. In case of the scan mode, the analog input AN0 to AN3 (ANI2 = 0) or AN4 to AN7 (ANI2 = 1) can be selected. If bit 3 (ANI2) of the A/D channel mode register is set to "0", analog inputs AN0, AN1, AN2, AN3 and AN0 are selected in that order. These input A/D conversion values CR0, CR1, CR2, CR3, and CR0 are stored in that order. If ANI2 of the A/D channel mode register is set to "1", analog inputs AN4, AN5, AN6, AN7, and AN4 are selected in that order, and these input A/D conversion values CR0, CR1, CR2, CR3, and CR0 in that order. In the scan mode, like in the select mode, when four CR registers are set to conversion values, the internal interrupt (INTAD) is generated. In the scan mode, too, the above-mentioned operation is repeated until the A/D channel mode register is changed. By setting (1) bit 0 (MKAD) of the interrupt mask register (MKH), the internal interrupt (INTAD) is disabled. 52 µPD78C17 PD78C17,78C18 78C18 Fig. 2-30 A/D Converter Block Diagram AV DD AV SS V AREF AN0 A/D CONVERTER AN1 AN3 AN4 AN5 MULTIPLEXER AN2 8 AN6 AN7 8 8 8 8 CR0 CR1 CR2 CR3 8 8 8 8 Internal Bus Caution Capacitors should be connected to the analog input pins and reference voltage input pins in order to prevent mulfunction due to noise. Analog Input AN n 100 to 1000 pF µPD78C17 PD78C17 µPD78C18 PD78C18 Reference Voltage Input 100 to 1000 pF V AREF V SS AV SS 53 µPD78C17 PD78C17,78C18 78C18 (1) A/D channel mode register (ANM) This is an 8-bit register which controls A/D converter operation. Bit 0 (MS) of the A/D channel mode register controls the operating mode, bits 1, 2, and 3 (ANI0, ANI1, ANI2) controls A/D conversion input, and bit 4 (FR) controls A/D operation according to change of the oscillator frequency. In the A/D channel mode register, the operating mode specification is written, and the contents of this register are read. Therefore, in the A/D interrupt generation, analog input data distinction is possible. After RESET input or in the hardware STOP mode, the A/D channel mode register is set to 00H. Fig. 2-31 A/D Channel Mode Register Format 7 6 5 4 3 2 1 FR ANI2 ANI1 ANI0 0 MS Operating Mode Specification 0 Scan mode 1 Select mode Analog Input Specification 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 0 Oscillator frequency > 9 MHz (192 states) 1 Oscillator frequency 9 MHz (144 states) (2) A/D converter operation control method The A/D converter can stop conversion operation by controlling the VAREF input voltage. If a voltage greater than VIH1 is input to the V AREF pin, the A/D converter starts conversion operation and the conversion results are guaranteed in VAREF = 3.4 V to AVDD. If the V AREF pin input voltage is set to less than VIL1 during the conversion operation, the A/D converter conversion operation stops. At this time, contents of CR0 to CR3 are undefined. Even if the VAREF input voltage is changed for A/D converter stop control, the A/D channel mode register (ANM) is not affected. Therefore, if the VAREF input voltage is greater than 3.4 V, the A/D converter restarts operation beginning with storage of conversion values to CR0 in the mode directly before the stop state is set. Even if the VAREF input voltage level is changed, the detection function of AN4 to AN7 input edge is not affected. Caution 54 When VAREF is low, inputs AN0 to AN7 in the range of AVSS to AVDD are necessary. µPD78C17 PD78C17,78C18 78C18 2.10 ZERO-CROSS DETECTOR The INT1 pin and INT2/TI (shared as PC3) pin can be made to execute zero-cross detection operations by setting the zero-cross mode register. The zero-cross detector has a self-bias type high-gain amplifier. It biases the input to the switching point and generates digital displacement in response to a small input displacement. Fig. 2-32 Zero-Cross Detector µ PD78C17 PD78C17, 78C18 78C18 External Capacitor INT 1 INT 2 / TI AC Input Signal To Internal Circuit 1 µF Self Bias Circuit enable The zero-cross detector detects a negative-to-positive or positive-to-negative transition of the AC signal input through an external capacitor and generates a digital pulse which changes from 0 to 1 or 1 to 0 at each transition point. Fig. 2-33 Zero-Cross Detection Signal AC Input signal Zero-Cross Detection Signal 55 µPD78C17 PD78C17,78C18 78C18 A digital pulse generated in the zero-cross detector of the INT1 pin is sent to the interrupt control circuit. The INTF1 interrupt request flag is set at the zero-cross point from the negative to the positive state of the AC signal (rising edge), and if INT1 interrupt is enabled, interrupt servicing is started. A digital pulse generated in the INT2/TI pin zero-cross detector is sent to the interrupt control circuit and interrupt servicing can be started at the zero-cross point from the positive to the negative state of the AC signal (falling edge) as with the INT1 pin, and can also be used as a timer input clock. The format of the zero-cross mode register (ZCM), which controls self-bias for zero-cross detection of the INT1 and INT2/TI pins, is shown in Fig. 2-34. Fig. 2-34 Zero-Cross Mode Register Format 7 ZCM 6 5 4 3 2 1 ZC2 0 ZC1 INT1 Pin 0 Does not generate self-bias 1 Generates self-bias INT2/T1 Pin 0 Does not generate self bias 1 Generates self-bias When the ZC1 and ZC2 bits of the zero-cross mode register are set to "0", a self-bias for zero-cross detection of each pin is not generated and each pin responds as a normal digital input. When the ZC1 and ZC2 bits are set to "1", a self-bias is generated and an AC input signal zero-cross can be detected by connecting a capacitor to each pin. Each pin with ZC1 and ZC2 bits set to "1" can be directly driven without the use of an external capacitor. In this case, each pin responds as a digital input. However, an input load current is necessary and an external circuit output driver must be considered. Thus, when no zero-cross detection is executed and each pin is used simply as an interrupt input or timer input, the ZC1 and ZC2 bits of the zero-cross mode register should be set to "0". RESET input sets both the ZC1 and ZC2 bits to "1" and a self-bias is generated. The zero-cross function of the INT2/TI (shared as PC3) pin can operate only when the control mode is specified by the MODE CONTROL C register (MCC). In the port mode, the zero-cross detection function does not operate. Caution Unlike other CMOS circuits, a supply current is always present in the zero-cross detector because of its operation points. This also applies in the standby modes (HALT and software/hardware STOP modes). Thus, when the zero-cross detector is operated (with self-bias generation: ZCX = 1), slightly more current flows than without zero-cross detector operation, and its effect is greater in the software/hardware STOP mode. 56 µPD78C17 PD78C17,78C18 78C18 3. INTERRUPT FUNCTIONS There are 3 kinds of external interrupt request and 8 kinds of internal interrupt requests. The 11 kinds of interrupt requests are divided into 6 groups, each of which is assigned a different priority and interrupt address. The priority of these interrupt sources and interrupt addresses are as follows. Priority Interrupt Address 1 4 NMI Falling edge External 2 8 INTT0 Match signal from TIMER0 Internal INTT1 Match signal from TIMER1 INT1 Rising edge INT2 Falling edge INTE0 Match signal from timer/event counter INTE1 Match signal from timer/event counter 3 4 5 16 24 32 Interrupt Request INTEIN CI pin or TO fall signal INTAD 6 40 Serial reception interrupt INTST External Internal Internal A/D converter interrupt INTSR External/ Internal Serial transmission interrupt Internal 57 µPD78C17 PD78C17,78C18 78C18 3.1 INTERRUPT CONTROL CIRCUIT CONFIGURATION The interrupt control circuit consists of a request register, a mask register, a priority control, a test control, an interrupt enable F/F, and a test flag register (see Fig. 3-1). Fig. 3-1 Interrupt Control Circuit Block Diagram INTFNMI NMI INTT0 INT1 INT2 REQUEST INTT1 TEST CONTROL Skip Control INTFNMI T.F INTE0 INTEIN INTAD REGISTER INTE1 SOFTI MASK REGISTER Interrupt Generation ENABLE INTSR EI INTST PRIORITY CONTROL S DI Q R INTFNMI OV ER SB AN7 to AN4 58 TEST FLAG REGISTER T.F SOFTI INT. ADR Internal Bus µPD78C17 PD78C17,78C18 78C18 (a) REQUEST REGISTER This register consists of 11 interrupt request flags which are set by the different interrupt requests. A flag is reset when an interrupt request is acknowledged or a skip instruction (SKIT or SKNIT) is executed. RESET input resets all flags. There are 11 types of interrupt request flags. · INTFNMI Set (1) by a falling edge input to the NMI pin. Unlike other interrupt request flags, this flag cannot be tested by a skip instruction. · INTFT0 Set (1) by TIMER0 COMPARATOR match signal. · INTFT1 Set (1) by TIMER1 COMPARATOR match signal. · INTF1 Set (1) by a rising edge input to the INT1 pin. · INTF2 Set (1) by a falling edge input to the INT2 pin. · INTFE0 Set (1) by a match signal when timer/event counter ECNT and ETM0 register contents match. · INTFE1 Set (1) by a match signal when timer/event counter ECNT and ETM1 register contents match. · INTFEIN Set (1) by a falling edge of the timer/event counter CI input or timer output (TO). · INTFAD Set (1) when A/D converter conversion values are transferred to the four registers CR0 to CR3. · INTFSR Set (1) when the serial interface receive buffer becomes full. · INTFST Set (1) when the serial interface transmit buffer becomes empty. (b) MASK REGISTER This is a 10-bit mask register which handles all interrupt requests except non-maskable interrupts (NMI). It can be set (1) or reset (0) bit-wise by an instruction. An interrupt request is masked (disabled) or enabled when the corresponding bit of the mask register is "1" or "0", respectively. All bits of the mask register are set by RESET input and all interrupt requests except non-maskable interrupts are masked. All bits of the mask register are set in the hardware STOP mode. 59 µPD78C17 PD78C17,78C18 78C18 Fig. 3-2 Mask Register (MKL, MKH) Format 7 MKL 6 5 4 3 2 1 0 MKEIN MKE1 MKE0 MK2 MK1 MKT1 MKT0 - 0 1 0 INTSR mask release 1 INTSR mask 0 INTST mask release 1 60 INTAD mask 0 MKSR INTAD mask release 1 MKST INTEIN mask INTST mask 0 - INTEIN mask release 1 - INTE1 mask 0 - INTE1 mask release 1 - INTE0 mask 0 - INTE0 mask release 1 MKH INT2 mask 0 1 INT2 mask release 1 2 INT1 mask 0 3 INT1 mask release 1 4 INTT1 mask 0 5 INTT1 mask release 1 6 INTT0 mask 0 7 INTT0 mask release MKAD µPD78C17 PD78C17,78C18 78C18 (c) PRIORITY CONTROL circuit This circuit controls the 6 priority levels described earlier. If two or more interrupt request flags are set simultaneously, the interrupt with the highest priority according to the priority is acknowledged. (d) TEST CONTROL circuit This circuit comes into operation when a skip instruction (SKIT or SKNIT) is executed to test interrupt request flags (except INTFNMI) for each interrupt source, NMI pin states, and test flags. (e) INTERRUPT ENABLE F/F (IE F/F) This is a flip-flop which is set by the EI instruction and reset by the DI instruction. This flip-flop is reset when an interrupt is acknowledged, and by RESET input, too. Interrupts are enabled when this flip-flop is set, and disabled when it is reset. (f) TEST FLAG REGISTER This register consists of 7 test flags which do not generate interrupt requests. These flags are tested or reset by the skip instructions (SKIT, SKNIT). · OV Set (1) when the timer/event counter ECNT overflows. · ER Set (1) in the event of a parity error, framing error or overrun error in serial interface. · SB Set (1) if VDD pin increases from a level lower than specified to a level higher than specified. · AN7 to AN4 Set (1) by a falling edge input to pins AN7 to AN4. 3.2 NON-MASKABLE INTERRUPT OPERATION When the interrupt request flag (INTFNMI) is set by a falling edge input to the NMI pin, a non-maskable interrupt is acknowledged by means of the following procedure irrespective of the EI/DI state (see Fig. 3-3). (i) A check is made to see if INTFNMI is set at the end of each instruction. If INTFNMI is set, a nonmaskable interrupt is acknowledged and INTFNMI is reset. (ii) When the non-maskable interrupt is acknowledged, the IE F/F is reset and all interrupts except for nonmaskable interrupts and the SOFTI instruction are placed in the disabled state (DI state). (iii) PSW, PC high byte, and PC low byte are saved into the stack memory in that order. (iv) The program jumps to the interrupt address (0004H 0004H). These interrupt operations are automatically carried out in 16 states. The interrupt request flag (INTFNMI) cannot be tested by the skip instruction. However, the NMI pin status can be tested by the skip instruction (SKIT NMI, SKNIT NMI). Therefore, by testing the NMI pin status with the skip instructions in several times in the non-maskable interrupt service routine, noise of comparatively long period or periodical noise can be removed. The NMI pin status is not changed even if the status is tested by the skip instruction. 61 µPD78C17 PD78C17,78C18 78C18 Fig. 3-3 Interrupt Operation Procedure Instruction End Y NMI? N DI status? Y N All masked? Y N INTFNMI reset Unmasked INTF× check 2 or more Number of set flags Other Interrupts 0 1 Priority check Hold Next Instruction Highest Priority Interrupt Both interrupts of the same level are non-masked? N Y INTF× reset IE F/F reset PSW and PC saved to stack memory PC Interrupt address 62 µPD78C17 PD78C17,78C18 78C18 3.3 MASKABLE INTERRUPT OPERATION Interrupt requests except non-maskable interrupts and the SOFTI instruction are maskable interrupts which can be enabled/disabled (IE F/F set/reset) by the EI/DI instructions and can be masked individually by means of the mask register. When an external maskable interrupt is recognized as a normal interrupt signal by an active level input for more than the specified time, an interrupt request flag is set. If an internal interrupt request is generated, an interrupt request flag is immediately set. Once the interrupt request flag is set, both the external and internal interrupts are serviced using the following procedure (see Fig. 3-3). (i) In the EI state (IE F/F = 1), a check is made to see if the interrupt request flag has been set at the end checked at end of each instruction. If the flag has been set, the interrupt cycle starts. However, interrupt requests masked by the mask register are not checked. (ii) If two or more interrupt request flags have been set simultaneously, their priorities are checked. The interrupt with the highest priority is acknowledged and the others are held pending. (iii) When an interrupt request is acknowledged, the interrupt request flag is automatically reset. If two types of interrupt requests with the same priority have both been unmasked by the mask register, the interrupt request flag is not reset. This is because the two types are identified by software at a later stage. (iv) When an interrupt request is acknowledged, the IE F/F is reset, and all interrupts except non-maskable interrupts and the SOFTI instruction are placed in the disabled state (DI state). (v) The PSW, upper PC byte, and lower PC byte are saved to the stack memory in that order. (vi) The program jumps to the interrupt address. These interrupt operations are automatically carried out in 16 states. The pending interrupt requests are acknowledged if there are no other interrupt requests of higher priority when interrupts are enabled by execution of the EI instruction. With maskable interrupts there are two types of interrupt requests with the same priority and same interrupt address. Unmasking both types, unmasking one type, or masking both kinds can be selected by setting the mask register. (1) When both types are unmasked The corresponding bits of the mask register for two types of interrupt requests are both set to "0". In this case, the interrupt request is the logical sum of the two interrupt request flags. If an interrupt request is acknowledged in accordance with the interrupt operation as a result of setting one or both interrupt request flags having the same priority and the program jumps to the interrupt address, the interrupt request flag is not reset. Therefore, the interrupt request is identified by executing a skip instruction which tests the interrupt request flag at the beginning of the interrupt service routine, and the interrupt request flag is reset. (2) When one type is unmasked For two types of interrupt requests having the same priority, the corresponding bit of the mask register for the interrupt request to be unmasked is set to "0" and the other bit is set to "1". In this case, if an interrupt request is generated by setting the unmasked interrupt request flag and that interrupt request is acknowledged in accordance with the interrupt operation, the interrupt request flag is automatically reset. When the masked interrupt request flag is set, that interrupt request is held pending. When the pending interrupt request is unmasked, it is acknowledged if there are no other interrupt requests of higher priority in the interrupt enable state. (3) When both types are masked The corresponding bits of the mask register for two types of interrupt request are both set to "1". In this case, the interrupt requests are held pending are not acknowledged when the interrupt request flag is set. When the pending interrupt requests are unmasked, they are acknowledged if there are no other interrupt requests of higher priority in the interrupt enabled state. 63 µPD78C17 PD78C17,78C18 78C18 3.4 INTERRUPT OPERATION BY SOFTI INSTRUCTION When the SOFTI instruction is executed, the program jumps unconditionally to the interrupt address (0060H 0060H). The SOFTI instruction interrupt is not affected by the IE F/F, and the IE F/F is not affected when this instruction is executed. The servicing procedure for an interrupt generated by the SOFTI instruction is as follows: (i) The PSW, upper PC byte, and lower PC byte are saved to the stack memory in that order. (ii) The program jumps to the interrupt address (0060H 0060H). Caution If the skip condition is satisfied by the instruction (arithmetic or logical operation, increment/ decrement, shift, skip, or RETS instruction) immediately before the SOFTI instruction, the SOFTI instruction is executed and not skipped. When SOFTI instruction is executed, the SK flag of the PSW is saved as set (1) to the stack area. Thus, when the return is made from the SOFTI service routine, the PSW SK flag remains set and the instruction following the SOFTI instruction is skipped. 64 µPD78C17 PD78C17,78C18 78C18 4. STANDBY FU