PD789826 78K0S PD789828 U11047 RA78K0S U11622 U11599 CC78K0S U11623 U11816 - Datasheet Archive

 

78K0S family 8-bit Security Cryptocontroller Product Letter Description The µPD789826 is a single-chip security

 

µPD789826 PD789826 78K0S 78K0S family 8-bit Security Cryptocontroller Product Letter Description The µPD789826 PD789826 is a single-chip security microcontroller with the built-in SuperMAP (Super Modular Arithmetic Processor) dedicated to public key encryption. It is designed around a 78K0S 78K0S CPU core and includes the following on-chip memory: 16 Kbytes of EEPROM, 1536 bytes of RAM and 44 Kbytes of ROM. The µPD789826 PD789826 supports most public key encryption algorithms: RSA, DSA, and Elliptic curve. Supplied in a standard package with the necessary cryptographic libraries, it also offers access to primitive functions for custom algorithm implementation. The µPD789826 PD789826 has the following dedicated features: ISO 7816 port structure, random number generator, parallel EEPROM writing and security circuits to protect data against external attack. The peripherals are managed by means of 7 maskable and non-maskable interrupt signals. Applications The µPD789826 PD789826 features the new generation SuperMAP to provide computing power for cryptographic algorithms that is second to none. The device is perfectly placed for a wide range of present and future applications requiring public key encryption such as RSA with key length up to 2048 bits, or ECC. Features · General registers: 8 x 8 bits or 4 x 16 bits · Three CPU speeds selectable by software · Instruction set: 1/8/16 bits manipulation instructions · 7 interrupt vectors · Three levels of power-saving standby modes · SuperMAP: high performance modular arithmetical processor · ROM: 44 Kbytes · RAM: 1536 bytes · EEPROM: 16 Kbytes, 10 years data retention, 100K erase/write cycles per byte, 2 ms programming time, 32 bytes protected OTP block, multiplex propgramming (1 to 32 bytes) · Basic interval timer/watchdog timer · 16-bit random number generator (8 or 16 bits read/write access) · VDD, GND: 2.7 to 5.5 V · CLK: 1 to 5 MHz · Two communication ports Block Diagram Watchdog Timer ROM 44 Kbytes Port G CPU 78K0S 78K0S 8-bit RAM 1536 bytes Random Number Generator Interrupt Control · INTPG EEPROM 16 Kbytes Multi Programming · INTWD · INTEE · INTS0 · INTS1 Security Circuits SuperMAP Co-Processor PG1 PG0 · INTSN Power On/Off Reset Circuit Clock Generator VDD GND RESET CLK Standby Control Functional Block Description CPU The 78K0S 78K0S CPU core, based on NEC's 78K0 market standard, is a compact 8-bit CISC engine with a powerful instruction set (including complex bit and word manipulation) combined with a wide range of memory addressing modes. The minimum instruction clock cycle is 0.2 µs at 5 MHz. Most instructions are executed in two or three clock cycles. Peripherals are easily accessed via a set of special function registers. Pinout The µPD789826 PD789826 device has 6 pins complying with the ISO 7816 standard: clock (CLK), ground (GND), voltage supply (VDD), reset (RST), input/output pin (PG0). An additional I/O pin (PG1) is available to manage custom communication protocols (eg, asynchronous full duplex protocol). The permissible operating voltage range is 2.7 to 5.5 V. The permissible external clock frequency range is 1 to 5 MHz. SuperMAP Coprocessor The SuperMAP enables high-speed parallel multiplication and exponentiation on large numbers up to 2048 bits long. The high level cryptographic libraries, supplied with the device and using the SuperMAP, include RSA, DSA and ECC as standard functions. For custom designs, SuperMAP can reference low-level primitives instead. Performance Table @ 5 MHz, 5 V RSA Signature 1024 bit with CRT 100 ms RSA Signature 1024 bit without CRT 360 ms RSA Authentication 2048 bit (e = 010001h) 36 ms SHA Hardware Accelerator (512 bits)