NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
PD780822B PD780821B PD78F0822B U17681EE2V0UD00 78K/0 RA78K/0 CC78K/0 U16985E - Datasheet Archive
µPD780822B Subseries 8-bit Single-Chip Microcontroller Hardware µPD780821B (A) µPD780822B (A) µPD78F0822B
User's Manual µPD780822B PD780822B Subseries 8-bit Single-Chip Microcontroller Hardware µPD780821B PD780821B (A) µPD780822B PD780822B (A) µPD78F0822B PD78F0822B (A) Document No. U17681EE2V0UD00 U17681EE2V0UD00 Date Published July 2007 © NEC Electronics Corporation 2007 Printed in Germany NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. All (other) product, brand, or trade names used in this pamphlet are the trademarks or registered trademarks of their respective owners. Product specifications are subject to change without notice. To ensure that you have the latest product data, please contact your local NEC Electronics sales office. 2 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 · The information in this document is current as of July, 2006. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. · No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. · NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. · Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. · While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. · NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 3 For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [America] [Europe] [Asia & Oceania] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ NEC Electronics (Europe) GmbH Arcadiastrasse 10 40472 Düsseldorf, Germany Tel: 0211-65030 http://www.eu.necel.com/ NEC Electronics (China) Co., Ltd 7th Floor, Quantum Plaza, No. 27 ZhiChunLu Haidian District, Beijing 100083, P.R.China Tel: 010-8235-1155 http://www.cn.necel.com/ Hanover Office Podbielski Strasse 166 B 30177 Hanover Tel: 0 511 33 40 2-0 NEC Electronics Shanghai Ltd. Room 2509-2510, Bank of China Tower, 200 Yincheng Road Central, Pudong New Area, Shanghai P.R. China P.C:200120 Tel: 021-5888-5400 http://www.cn.necel.com/ Munich Office Werner-Eckert-Strasse 9 81829 München Tel: 0 89 92 10 03-0 Stuttgart Office Industriestrasse 3 70565 Stuttgart Tel: 0 711 99 01 0-0 United Kingdom Branch Cygnus House, Sunrise Parkway Linford Wood, Milton Keynes MK14 6NP, U.K. Tel: 01908-691-133 Succursale Française 9, rue Paul Dautier, B.P. 52180 78142 Velizy-Villacoublay Cédex France Tel: 01-3067-5800 Sucursal en España Juan Esplandiu, 15 28007 Madrid, Spain Tel: 091-504-2787 NEC Electronics Hong Kong Ltd. 12/F., Cityplaza 4, 12 Taikoo Wan Road, Hong Kong Tel: 2886-9318 http://www.hk.necel.com/ Seoul Branch 11F., Samik Lavied'or Bldg., 720-2, Yeoksam-Dong, Kangnam-Ku, Seoul, 135-080, Korea Tel: 02-558-3737 NEC Electronics Taiwan Ltd. 7F, No. 363 Fu Shing North Road Taipei, Taiwan, R. O. C. Tel: 02-8175-9600 http://www.tw.necel.com/ NEC Electronics Singapore Pte. Ltd. 238A Thomson Road, #12-08 Novena Square, Singapore 307684 Tel: 6253-8311 http://www.sg.necel.com/ Tyskland Filial Täby Centrum Entrance S (7th floor) 18322 Täby, Sweden Tel: 08 638 72 00 Filiale Italiana Via Fabio Filzi, 25/A 20124 Milano, Italy Tel: 02-667541 Branch The Netherlands Steijgerweg 6 5616 HS Eindhoven The Netherlands Tel: 040 265 40 10 G06.7A 4 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 Preface Readers This manual has been prepared for engineers who want to understand the functions of the µPD780822B PD780822B Subseries and design and develop its application systems and programs. µPD780822B PD780822B Subseries: µPD780821B PD780821B(A), µPD780822B PD780822B(A), µPD78F0822B PD78F0822B(A) Purpose Organization This manual is intended for users to understand the functions of the µPD780822B PD780822B Subseries. The µPD780822B PD780822B Subseries manual is separated into two parts: this manual and the instruction edition (common to the 78K/0 78K/0 series). µPD780822B PD780822B Subseries This Manual · · · · Pin functions Internal block functions Interrupt Other on-chip peripheral functions 78K/0 78K/0 series User's Manual Instruction · CPU functions · Instruction set · Explanation of each instruction How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. · When using this manual as the manual for (A) products: Read the part number as follows: µPD780821B PD780821B µPD780821B PD780821B(A) µPD780822B PD780822B µPD780822B PD780822B(A) µPD78F0822B PD78F0822B µPD78F0822B PD78F0822B(A) · When you want to understand the function in general: Read this manual in the order of the contents. · How to interpret the register format: For the bit number enclosed in square, the bit name is defined as a reserved word in RA78K/0 RA78K/0, and in CC78K/0 CC78K/0 and defined in the header file of hte IAR compiler. · To make sure the details of the registers when you know the register name. Refer to Appendix C. User's Manual U17681EE2V0UD00 U17681EE2V0UD00 5 Preface Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. · Related documents for µPD780822B PD780822B Subseries Document No. Document name Japanese English µPD780822B PD780822B Subseries User's Manual Planned U16985E U16985E 78K/0 78K/0 Series User's Manual-Instruction IEU-849 IEU-849 U12326E U12326E 78K/0 78K/0 Series Instruction Table U10903J U10903J - 78K/0 78K/0 Series Instruction Set U10904J U10904J - · Related documents for development tools (User's Manuals) Document No. Document name Japanese English Operation EEU-809 EEU-809 EEU-1399 EEU-1399 Language EEU-815 EEU-815 EEU-1404 EEU-1404 EEU-817 EEU-817 EEU-1402 EEU-1402 Operation EEU-656 EEU-656 EEU-1280 EEU-1280 Language EEU-655 EEU-655 EEU-1284 EEU-1284 Operation U11517J U11517J - Language U11518J U11518J - Programming Note EEA-618 EEA-618 EEA-1208 EEA-1208 CC78K CC78K Series Library Source File EEU-777 EEU-777 - QB-780822 QB-780822 Planned U17172E U17172E RA78K RA78K Series Assembler Package RA78K RA78K Series Structured Assembler Preprocessor CC78K CC78K Series C Compiler CC78K/0 CC78K/0 C Compiler CC78K/0 CC78K/0 C Compiler Application Note SM78K0 SM78K0 System Simulator WindowsTM Base Reference U15373J U15373J U15373E U15373E SM78K0 SM78K0 Series System Simulator External part user open Interface U15802J U15802J U15802E U15802E U15185J U15185J U15185E U15185E ID78K0-NS ID78K0-NS Integrated Debugger 6 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 Preface · Related documents for embedded software (User's Manual) Document name Document No. Japanese English Basics U11536J U11536J - Technical U11538J U11538J - Basics 78K/0 78K/0 Series OS MX78K0 MX78K0 - Installation 78K/0 78K/0 Series Real-Time OS U11537J U11537J EEU-5010 EEU-5010 - EEU-829 EEU-829 EEU1438 EEU1438 Fuzzy Knowledge Data Creation Tool 78K/0 78K/0, 78K/II 78K/II, 87AD Series Fuzzy Inference Development Support SysEEU-862 tem-Translator EEU-1444 EEU-1444 78K/0 78K/0 Series Fuzzy Inference Development Support System- Fuzzy Inference Module EEU-858 EEU-858 EEU-1441 EEU-1441 78K/0 78K/0 Series Fuzzy Inference Development Support System- Fuzzy Inference Debugger EEU-921 EEU-921 EEU-1458 EEU-1458 · Other Documents Document name Document No. Japanese English IC Package Manual C10943X C10943X IEI-1213 IEI-1213 Semiconductor Device Mounting Technology Manual C10535J C10535J C10535E C10535E Quality Grade on NEC Semiconductor Devices C11531J C11531J C11531E C11531E Reliability Quality Control on NEC Semiconductor Devices C10983J C10983J C10983E C10983E Electric Static Discharge (ESD) Test MEM-539 MEM-539 - Semiconductor Devices Quality Assurance Guide MEI-603 MEI-603 MEI-1202 MEI-1202 Microcontroller Related Product Guide - Third Party Manufacturers U11416J U11416J - Caution: The above documents are subject to change without prior notice. Be sure to use the latest version document when starting design. User's Manual U17681EE2V0UD00 U17681EE2V0UD00 7 Preface Legend Symbols and notation are used as follows: Weight in data notation : Left is high-order column, right is low order column Active low notation : xxx (pin or signal name is over-scored) or /xxx (slash before signal name) Memory map address: : High order at high stage and low order at low stage Note : Explanation of (Note) in the text Caution : Item deserving extra attention Remark : Supplementary explanation to the text Numeric notation : Binary . . . XXXX or XXXB Decimal . . . XXXX Hexadecimal . . . XXXXH or 0x XXXX Prefixes representing powers of 2 (address space, memory capacity) K (kilo): 210 = 1024 M (mega): 220 = 10242 = 1,048,576 G (giga): 230 = 10243 = 1,073,741,824 8 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 Table of Contents Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Chapter 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Chapter 2 Outline (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Application fields . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Quality Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Pin Configuration (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 78K/0 78K/0 CAN Products Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Overview of Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Pin Functions (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.1 2.2 2.3 List of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Non-port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Description of Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.3.1 P00 to P03 (Port 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 2.3.2 P10 to P17 (Port 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 2.3.3 P20 to P27 (Port 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 2.3.4 P30 to P33 (Port 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.3.5 P70 to P77 (Port 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.3.6 P80 to P87 (Port 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.3.7 P90 to P97 (Port 9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 2.3.8 P100 to P105 (Port 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 2.3.9 P110 to P113 (Port 11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 2.3.10 P120 (Port 12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.3.11 P130 (Port 13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.3.12 P140 to P147 (Port 14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.3.13 P150 to P157 (Port 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 2.3.14 COM0 to COM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.15 VLCD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.16 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.17 X1 and X2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.18 XT1, XT2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.19 VDD0 to VDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.20 VSS0 to VSS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.21 AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.22 AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.23 AVREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.24 SMVDD0, SMVDD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 2.3.25 SMVSS0, SMVSS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.26 FLMD0, FLMD1 (Flash ROM version only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.3.27 IC (Mask ROM version only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 2.4 Pin I/O Circuits and Recommended Connection of Unused Pins . . . . . . . . . . . . . . . 58 Chapter 3 CPU Architecture (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . . 63 3.1 Memory Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.1.1 Internal program memory space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 3.1.2 Internal data memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.1.3 Special function register (SFR) area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 3.1.4 Data memory addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 3.2 Processor Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.2.1 Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 3.2.2 General registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 3.2.3 Special function register (SFR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 9 3.3 Instruction Address Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.3.1 Relative addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 3.3.2 Immediate addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 3.3.3 Table indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 3.3.4 Register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 3.4 Operand Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.4.1 Implied addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.4.2 Register addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.4.3 Direct addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 3.4.4 Short direct addressing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 3.4.5 Special function register (SFR) addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.4.6 Register indirect addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.4.7 Based addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.4.8 Based indexed addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.4.9 Stack addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Chapter 4 Port Functions (µPD780822B PD780822B Subseries). . . . . . . . . . . . . . . . . . . . . . . . . . . 97 4.1 4.2 Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Port Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 4.2.1 Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4.2.2 Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 4.2.3 Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 4.2.4 Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 4.2.5 Port 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 4.2.6 Port 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 4.2.7 Port 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 4.2.8 Port 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4.2.9 Port 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4.2.10 Port 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 4.2.11 Port 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 4.2.12 Port 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 4.2.13 Port 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.3 Port Function Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.4 Port Function Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.4.1 Writing to input/output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.4.2 Reading from input/output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 4.4.3 Operations on input/output port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Chapter 5 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 10 Clock Generator (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . . 125 Clock Generator Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Clock Generator Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Clock Generator Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 System Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.4.1 Main system clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 5.4.2 Subsystem clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 5.4.3 When subsystem clock is not used. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.4.4 Internal low-speed oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 5.4.5 Prescaler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Clock Generator Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Time Required to Switch Between Internal Low-speed Oscillator Clock and X1 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Time Required for CPU Clock Switchover. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Clock Switching Flowchart and Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 5.8.1 Switching from internal low-speed oscillator clock to X1 input clock . . . . . . . . 151 5.8.2 Switching from X1 input clock to internal low-speed oscillator clock . . . . . . . . 152 5.8.3 Switching from X1 input clock to subsystem clock . . . . . . . . . . . . . . . . . . . . . . 153 5.8.4 Switching from subsystem clock to X1 input clock . . . . . . . . . . . . . . . . . . . . . . 154 5.8.5 Register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 Chapter 6 16-Bit Timer 2 (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . . . . 157 6.1 6.2 6.3 6.4 16-Bit Timer 2 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 16-Bit Timer 2 Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 16-Bit Timer 2 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 16-Bit Timer 2 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.4.1 Pulse width measurement operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 6.5 16-Bit Timer 2 Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Chapter 7 16-Bit Timer/Event Counter P (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . 173 7.1 7.2 7.3 7.4 7.5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Functional Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 7.5.1 Anytime write and reload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 7.5.2 Interval timer mode (TPnMD2 to TPnMD0 = 000) . . . . . . . . . . . . . . . . . . . . . . 191 7.5.3 One-shot pulse mode (TPnMD2 to TPnMD0 = 011). . . . . . . . . . . . . . . . . . . . . 194 7.5.4 PWM mode (TPnMD2 to TPnMD0 = 100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 7.5.5 Free-running mode (TPnMD2 to TPnMD0 = 101) . . . . . . . . . . . . . . . . . . . . . . 202 7.5.6 Pulse width measurement mode (TPnMD2 to TPnMD0 = 110) . . . . . . . . . . . . 207 7.6 Timer Synchronized Operation Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Chapter 8 8-Bit Timer/Event Counters 50 and 51 (µPD780822B PD780822B Subseries) . . . . . . 213 8.1 8.2 8.3 8.4 8-Bit Timer/Event Counters 50 and 51 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 8-Bit Timer/Event Counters 50 and 51 Configurations. . . . . . . . . . . . . . . . . . . . . . . 215 8-Bit Timer/Event Counters 50 and 51 Control Registers . . . . . . . . . . . . . . . . . . . . 218 8-Bit Timer/Event Counters 50 and 51 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . 224 8.4.1 Interval timer operations (8-bit timer/event counter mode) . . . . . . . . . . . . . . . . 224 8.4.2 External event counter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 8.4.3 Square-wave output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 8.4.4 PWM output operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 8.5 Cautions on 8-Bit Timer/Event Counters 50 and 51 . . . . . . . . . . . . . . . . . . . . . . . . . 235 Chapter 9 Watch Timer (µPD780822B PD780822B Subseries). . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 9.1 9.2 Watch Timer Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Watch Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 9.2.1 Input Switch Control Register (ISC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 9.2.2 Watch Timer Mode Register (WTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 9.3 Watch Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 9.3.1 Watch timer operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 9.3.2 Interval timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 9.4 Cautions for Watch Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Chapter 10 Watchdog Timer (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . . 247 10.1 10.2 10.3 10.4 Watchdog Timer Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Watchdog Timer Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 Watchdog Timer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 10.4.1 Interval timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 10.4.2 Watchdog timer mode 1 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 10.4.3 Watchdog timer mode 2 operation when "Internal low-speed oscillator cannot be stopped" is selected by mask option . . . . . . . . . . . . . . . . . . . . . . . . 258 10.4.4 Watchdog timer mode 2 operation when "Internal low-speed oscillator can be stopped by software" is selected by mask option . . . . . . . . . . . . . . . . . 259 Chapter 11 Clock Output / Buzzer Output Controller (µPD780822B PD780822B Subseries) . . . . 263 11.1 11.2 Functions of Clock Output/Buzzer Output Controller . . . . . . . . . . . . . . . . . . . . . . . 263 Configuration of Clock Output/Buzzer Output Controller . . . . . . . . . . . . . . . . . . . . 264 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 11 11.3 11.4 Register Controlling Clock Output/Buzzer Output Controller . . . . . . . . . . . . . . . . . 264 Clock Output/Buzzer Output Controller Operations. . . . . . . . . . . . . . . . . . . . . . . . . 267 11.4.1 Clock output operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 11.4.2 Operation as buzzer output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 Chapter 12 A/D Converter (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . . . . 269 12.1 12.2 12.3 Functions of A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Configuration of A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Registers Used in A/D Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 12.3.1 A/D converter mode register (ADM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 12.3.2 Analog input channel specification register (ADS) . . . . . . . . . . . . . . . . . . . . . . 275 12.3.3 A/D conversion result register (ADCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 12.3.4 Power-fail comparison mode register (PFM) . . . . . . . . . . . . . . . . . . . . . . . . . . 277 12.3.5 Power-fail comparison threshold register (PFT) . . . . . . . . . . . . . . . . . . . . . . . . 277 12.4 A/D Converter Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 12.4.1 Basic operations of A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 12.4.2 Input voltage and conversion results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 12.4.3 A/D converter operation mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 12.5 How to Read A/D Converter Characteristics Table. . . . . . . . . . . . . . . . . . . . . . . . . . 284 12.6 Cautions for A/D Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 12.7 Cautions on Emulation performed with IE-78K0-NS-A IE-78K0-NS-A Emulator and IE-780822-NS-EM1 IE-780822-NS-EM1 Emulation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Chapter 13 Serial Interfaces CSI10 CSI10 and CSI11 CSI11 (µPD780822B PD780822B Subseries). . . . . . . . . . 295 13.1 13.2 13.3 Functions of Serial Interfaces CSI10 CSI10 and CSI11 CSI11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Configuration of Serial Interfaces CSI10 CSI10 and CSI11 CSI11 . . . . . . . . . . . . . . . . . . . . . . . . . 296 Registers Controlling Serial Interfaces CSI10 CSI10 and CSI11 CSI11 . . . . . . . . . . . . . . . . . . . . 298 13.3.1 Serial operation mode register 1n (CSIM1n) . . . . . . . . . . . . . . . . . . . . . . . . . . 298 13.3.2 Serial clock selection register 1n (CSIC1n) . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 13.3.3 Port mode registers 10 and 11 (PM10, PM11) . . . . . . . . . . . . . . . . . . . . . . . . . 304 13.4 Operation of Serial Interfaces CSI10 CSI10 and CSI11 CSI11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 13.4.1 Operation stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 13.4.2 3-wire serial I/O mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306 Chapter 14 Serial Interface UART6 (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . 315 14.1 14.2 14.3 Functions of Serial Interface UART6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Configuration of Serial Interface UART6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 Registers Controlling Serial Interface UART6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 14.3.1 Asynchronous serial interface operation mode register 6 (ASIM6) . . . . . . . . . 322 14.3.2 Asynchronous serial interface reception error status register 6 (ASIS6) . . . . . 324 14.3.3 Asynchronous serial interface transmission status register 6 (ASIF6) . . . . . . . 325 14.3.4 Clock selection register 6 (CKSR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 14.3.5 Baud rate generator control register 6 (BRGC6) . . . . . . . . . . . . . . . . . . . . . . . 327 14.3.6 Asynchronous serial interface control register 6 (ASICL6) . . . . . . . . . . . . . . . . 328 14.3.7 Input switch control register (ISC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 14.3.8 Port mode register 1 (PM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 14.4 Operation of Serial Interface UART6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 14.4.1 Operation stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 14.4.2 Asynchronous serial interface (UART) mode . . . . . . . . . . . . . . . . . . . . . . . . . . 332 14.4.3 Dedicated baud rate generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 Chapter 15 CAN Controller (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . . . 355 15.1 12 CAN Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 15.1.1 Protocol Mode Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 15.1.2 Message Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356 15.1.3 Data Frame / Remote Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 15.1.4 Description of each field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 15.1.5 Error Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 15.1.6 Overload Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 15.2.1 Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 15.2.2 Bit Stuffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 15.2.3 Multi Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 15.2.4 Multi Cast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 15.2.5 Sleep Mode/Stop Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 15.2.6 Error Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 15.2.7 Baud Rate Control Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 15.2.8 State Shift Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 15.3 Outline Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 15.4 Connection with Target System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 15.5 CAN Controller Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 15.6 Special Function Register for CAN-module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 15.7 Message and Buffer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 15.8 Transmit Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 15.9 Transmit Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 15.10 Receive Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 15.11 Receive Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 15.12 Mask Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 15.13 Operation of the CAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 15.13.1 DCAN control register (DCANC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 15.13.2 CAN control register (CANC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 15.13.3 DCAN Error Status Register (CANES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 15.13.4 CAN Transmit Error Counter (TEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 15.13.5 CAN Receive Error Counter (REC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404 15.13.6 Message Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 15.14 Baudrate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 15.15 Function Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 15.15.1 Transmit Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 15.15.2 Receive Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 15.15.3 Mask Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 15.15.4 Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 15.16 Interrupt Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 15.16.1 Interrupt Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 15.16.2 Transmit Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 15.16.3 Receive Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 15.16.4 Error Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 15.17 Influence of the standby Function of the CAN Controller . . . . . . . . . . . . . . . . . . . . 423 15.17.1 CPU Halt Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 15.17.2 CPU Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 15.17.3 DCAN Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 15.17.4 DCAN Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 15.18 Functional Description by Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 15.18.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 15.18.2 Transmit Preparation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 15.18.3 Abort Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 15.18.4 Handling by the DCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 15.18.5 Receive Event Oriented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 15.18.6 Receive Task Oriented . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 15.19 CAN Controller Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 15.2 Chapter 16 LCD Controller/Driver (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . 433 16.1 16.2 16.3 16.4 16.5 LCD Controller/Driver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 LCD Controller/Driver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 LCD Controller/Driver Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 LCD Controller/Driver Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 LCD Display Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 13 16.6 16.7 16.8 Common Signals and Segment Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 Supplying LCD Drive Voltage VLC0, VLC1, and VLC2 . . . . . . . . . . . . . . . . . . . . . . . . 440 Display Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 16.8.1 4-time-division display example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 16.9 Cautions on Emulation performed with IE-78K0-NS-A IE-78K0-NS-A Emulator and IE-780822-NS-EM1 IE-780822-NS-EM1 Emulation Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 Chapter 17 Sound Generator (µPD780822B PD780822B Subseries). . . . . . . . . . . . . . . . . . . . . . . . 449 17.1 17.2 17.3 17.4 Sound Generator Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 Sound Generator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 Sound Generator Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 Sound Generator Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 17.4.1 Sound generator settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 17.4.2 To output basic cycle signal SGOF (without amplitude) . . . . . . . . . . . . . . . . . . 456 17.4.3 To output basic cycle signal SGO (with amplitude) . . . . . . . . . . . . . . . . . . . . . 457 Chapter 18 Meter Controller / Driver (µPD780822B PD780822B Subseries). . . . . . . . . . . . . . . . . . 459 18.1 18.2 18.3 18.4 Meter Controller/Driver Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 Meter Controller/Driver Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461 Meter Controller/Driver Control Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 Meter Controller/Driver Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 18.4.1 Basic operation of free-running up counter (SMCNT) . . . . . . . . . . . . . . . . . . . 468 18.4.2 Update of PWM data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 18.4.3 Operation of 1-bit addition circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 18.4.4 PWM output operation (output with 1 clock shifted) . . . . . . . . . . . . . . . . . . . . . 471 Chapter 19 Interrupt Functions (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . 473 19.1 19.2 19.3 19.4 Interrupt Function Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 Interrupt Sources and Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 Interrupt Function Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 Interrupt Servicing Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 19.4.1 Non-maskable interrupt request acknowledge operation . . . . . . . . . . . . . . . . . 483 19.4.2 Maskable interrupt request acknowledge operation . . . . . . . . . . . . . . . . . . . . . 485 19.4.3 Software interrupt request acknowledge operation . . . . . . . . . . . . . . . . . . . . . 488 19.4.4 Multiple interrupt servicing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 19.4.5 Interrupt request reserve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 Chapter 20 Standby Function (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . 495 20.1 Standby Function and Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 20.1.1 Standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 20.1.2 Registers controlling standby function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 20.2 Standby Function Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 20.2.1 HALT mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 20.2.2 STOP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 Chapter 21 Reset Function (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . . . 511 21.1 Register for Confirming Reset Source. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 Chapter 22 Clock Monitor (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . . . . 519 22.1 22.2 22.3 22.4 Functions of Clock Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 Configuration of Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 Registers Controlling Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 Operation of Clock Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 Chapter 23 Flash Memory (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . . . . 527 23.1 23.2 23.3 14 Internal Memory Size Switching Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 Internal Expansion RAM Size Switching Register . . . . . . . . . . . . . . . . . . . . . . . . . . 529 Writing with Flash Programmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 23.4 23.5 23.6 Programming Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 Communication Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 Processing of Pins on Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 23.6.1 FLMD0 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 23.6.2 FLMD1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 23.6.3 Serial interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538 23.6.4 RESET pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 23.6.5 Port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 23.6.6 Other signal pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 23.6.7 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 23.7 Programming Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 23.7.1 Controlling flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 23.7.2 Flash memory programming mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 23.7.3 Selecting communication mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 23.7.4 Communication commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 23.8 Flash Memory Programming by Self-Programming . . . . . . . . . . . . . . . . . . . . . . . . . 545 23.9 Boot Swap Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 23.9.1 Outline of boot swap function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 Chapter 24 Mask Options / Option Bytes (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . 549 24.1 24.2 Mask Options (Mask ROM Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549 Option Bytes (Flash Memory Version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 Chapter 25 Instruction Set (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . . . . 551 25.1 Legends Used in Operation List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 25.1.1 Operand identifiers and description methods . . . . . . . . . . . . . . . . . . . . . . . . . . 551 25.1.2 Description of "operation" column. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 25.2 Operation List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 25.3 Instructions Listed by Addressing Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 Chapter 26 Electrical Specifications (µPD780822B PD780822B Subseries). . . . . . . . . . . . . . . . . . 565 26.1 26.2 26.3 26.4 26.5 26.6 26.7 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 Main System Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . 568 Internal Low-speed Oscillator Oscillation Circuit Characteristics . . . . . . . . . . . . . 569 Subsystem Clock Oscillation Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . 570 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 26.7.1 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 26.7.2 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 26.7.3 Sound Generator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 26.7.4 Meter Controller/Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 26.7.5 A/D Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 26.7.6 Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics 583 26.8 Flash Memory Programming Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 Chapter 27 Package Drawing (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . 587 Chapter 28 Recommended Soldering Conditions (µPD780822B PD780822B Subseries) . . . . . . . 589 Chapter 29 Cautions For Wait (µPD780822B PD780822B Subseries) . . . . . . . . . . . . . . . . . . . . . . . 591 29.1 29.2 29.3 Cautions for Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 Peripheral Hardware That Generates Wait . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 Example of Wait Occurrence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 Appendix A Development Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 15 Appendix B Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 Appendix C Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 16 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 List of Figures Figure 1-1: Figure 1-2: Figure 1-3: Figure 1-4: Figure 2-1: Figure 2-2: Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 3-6: Figure 3-7: Figure 3-8: Figure 3-9: Figure 3-10: Figure 3-11: Figure 3-12: Figure 3-13: Figure 3-14: Figure 3-15: Figure 3-16: Figure 3-17: Figure 3-18: Figure 3-19: Figure 3-20: Figure 3-21: Figure 3-22: Figure 3-23: Figure 3-24: Figure 3-25: Figure 4-1: Figure 4-2: Figure 4-3: Figure 4-4: Figure 4-5: Figure 4-6: Figure 4-7: Figure 4-8: Figure 4-9: Figure 4-10: Figure 4-11: Figure 4-12: Figure 4-13: Figure 4-14: Figure 4-15: Figure 4-16: Figure 4-17: Figure 5-1: Figure 5-2: Figure 5-3: Figure 5-4: Figure 5-5: Figure 5-6: Figure 5-7: Pin Configuration . 31 Pin Configuration . 32 78K/0 78K/0 CAN Products Expansion . 34 Function Block Diagram . 36 Pin Configuration . 57 Terminal I/O types (1/2). 60 Memory Map of the µPD780821 PD780821 . 63 Memory Map of the µPD780822B PD780822B . 64 Memory Map of the µPD78F0822 PD78F0822 . 65 Program memory common area mapping . 68 BANK: bank switching register format (µPD780821 PD780821) . 69 BANK: bank switching register format (µPD780822B PD780822B, µPD78F0822 PD78F0822) . 70 Data Memory Addressing of the µPD780822B PD780822B Subseries. 72 Program Counter Configuration . 73 Program Status Word Configuration . 73 Stack Pointer Configuration. 75 Data to be Saved to Stack Memory. 75 Data to be Restored from Stack Memory . 75 General Register Configuration . 76 Relative Addressing . 83 Immediate Addressing. 84 Table Indirect Addressing. 85 Register Addressing . 86 Register Addressing . 88 Direct addressing . 89 Short direct addressing . 90 Special-Function Register (SFR) Addressing. 91 Register indirect addressing . 92 Based addressing description example. 93 Based indexed addressing description example . 94 Stack addressing description example . 95 Port Types . 97 P00 to P03 Configuration . 101 Port 1 Configuration (1/2) . 102 P20 to P27 Configurations . 104 P30 to P33 Configurations . 105 P70 to P77 Configuration . 106 P80 to P87 Configuration . 107 Port 9 Configuration (1/2) . 108 Port 10 Configuration (1/2) . 110 Port 11 Configuration (1/2) . 112 P120 Configuration. 114 P130 Configuration. 115 P140 to P147 Configuration . 116 P150 to P157 Configuration . 117 Port Mode Register Format (1/2) . 118 Pull-Up Resistor Option Register (PU0, PU1, PU3, PU7 to PU12) Format . 120 Port Function Register (PF7, PF8, PF9, PF10 and PF11) Format . 121 Block Diagram of Clock Generator . 126 Processor Control Register (PCC) Format (1/2) . 127 Internal Low-speed Oscillator Mode Register (RCM) Format . 129 Main Clock Mode Register (MCM) Format . 130 Main OSC Control Register (MOC) Format . 131 Oscillation Stabilization Time Counter Status Register (OSTC) Format . 132 Oscillation Stabilization Time Select Register (OSTS) Format . 133 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 17 Figure 5-8: Figure 5-9: Figure 5-10: Figure 5-11: Figure 5-12: Figure 5-13: Figure 5-14: Figure 5-15: Figure 5-16: Figure 5-17: Figure 5-18: Figure 6-1: Figure 6-2: Figure 6-3: Figure 6-4: Figure 6-5: Figure 6-6: Figure 6-7: Figure 6-8: Figure 6-9: Figure 6-10: Figure 6-11: Figure 7-1: Figure 7-2: Figure 7-3: Figure 7-4: Figure 7-5: Figure 7-6: Figure 7-7: Figure 7-8: Figure 7-9: Figure 7-10: Figure 7-11: Figure 7-12: Figure 7-13: Figure 7-14: Figure 7-15: Figure 7-16: Figure 7-17: Figure 7-18: Figure 7-19: Figure 7-20: Figure 7-21: Figure 7-22: Figure 7-23: Figure 7-24: Figure 7-25: Figure 7-26: Figure 7-27: Figure 7-28: Figure 8-1: Figure 8-2: Figure 8-3: Figure 8-4: Figure 8-5: 18 Input Switch Control Register (ISC) Format (1/2) . 134 External circuit of Main System Clock Oscillator . 136 External circuit of Subsystem Clock Oscillator . 137 Examples of oscillator with Bad Connection (1/3) . 138 Subsystem Clock Feedback Resistor. 141 Timing Diagram of CPU Default Start Using Internal Low-speed Oscillator. 143 Status Transition Diagram (1/4). 144 Switching from Internal Low-speed Oscillator Clock to X1 Input Clock (Flowchart) . 151 Switching from X1 Input Clock to Internal Low-speed Oscillator Clock (Flowchart) . 152 Switching from X1 Input Clock to Subsystem Clock (Flowchart). 153 Switching from Subsystem Clock to X1 Input Clock (Flowchart). 154 Timer 2 (TM2) Block Diagram . 157 16-Bit Timer Mode Control Register (TMC2) Format . 161 Capture Pulse Control Register (CRC2) Format . 162 Prescaler Mode Register (PRM2) Format . 163 Input Switch Control Register (ISC) Format . 164 Configuration Diagram for Pulse Width Measurement by Using the Free Running Counter . 166 Timing of Pulse Width Measurement Operation by Using the Free Running Counter and One Capture Register (with Both Edges Specified). 167 CR2m Capture Operation with Rising Edge Specified . 168 Timing of Pulse Width Measurement Operation by Free Running Counter (with Both Edges Specified) . 169 16-Bit Timer Register Start Timing . 170 Capture Register Data Retention Timing. 170 Block Diagram of Timer P. 175 TMPn capture/compare register 0 (TPnCCR0) Format . 176 TMPn capture/compare register 1 (TPnCCR1) Format . 177 TMPn counter read buffer register (TPnCNT) Format . 178 TMPn control register 0 (TPnCTL0) Format) . 179 TMPn timer control register 1 (TPnCTL1) Format . 181 TMPn I/O control register 0 (TPnIOC0) Format . 182 TMPn I/O control register 1 (TPnIOC1) Format . 183 TMPn option register 0 (TPnOPT0) Format . 184 Input Switch Control Register (ISC) Format . 185 Flowchart of Basic Operation of Anytime Write . 187 Timing Chart of Anytime Write. 188 Flowchart of Basic Operation of Reload . 189 Timing Chart of Reload. 190 Flowchart of Basic Operation in Interval Timer Mode. 191 Timing of Basic Operation in Interval Timer Mode (1/2) . 192 Flowchart of Basic Operation in One-Shot Pulse Mode . 195 Timing of Basic Operation in One-Shot Pulse Mode . 196 Flowchart of Basic Operation in PWM Mode (1/2) . 198 Timing of Basic Operation in PWM Mode (1/2) . 200 Flowchart of Basic Operation in Free-Running Mode. 203 Timing of Basic Operation in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 0) . 204 Timing of Basic Operation in Free-Running Mode (TPnCCS1 = 1, TPnCCS0 = 1) . 205 Timing of Basic Operation in Free-Running Mode (TPnCCS1 = 0, TPnCCS0 = 1) . 206 Flowchart of Basic Operation in Pulse Width Measurement Mode . 207 Timing of Basic Operation in Pulse Width Measurement Mode . 208 Tuned Operation Image (TMP0, TMP1, TMP2) . 211 Basic Operation Timing of Tuned PWM Function (TMP0, TMP1, TMP2) . 212 8-Bit Timer/Event Counter 50 Block Diagram. 215 8-Bit Timer/Event Counter 51 Block Diagram. 216 Block Diagram of 8-Bit Timer/Event Counters 50 and 51 Output Control Circuit . 217 Timer Clock Select Register 50 (TLC50 TLC50) Format . 218 Timer Clock Select Register 51 (TLC51 TLC51) Format . 219 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 Figure 8-6: Figure 8-7: Figure 8-8: Figure 8-9: Figure 8-10: Figure 8-11: Figure 8-12: Figure 8-13: Figure 8-14: Figure 8-15: Figure 8-16: Figure 8-17: Figure 8-18: Figure 8-19: Figure 8-20: Figure 8-21: Figure 8-22: Figure 8-23: Figure 8-24: Figure 9-1: Figure 9-2: Figure 9-3: Figure 9-4: Figure 9-5: Figure 10-1: Figure 10-2: Figure 10-3: Figure 10-4: Figure 11-1: Figure 11-2: Figure 11-3: Figure 11-4: Figure 12-1: Figure 12-2: Figure 12-3: Figure 12-4: Figure 12-5: Figure 12-6: Figure 12-7: Figure 12-8: Figure 12-9: Figure 12-10: Figure 12-11: Figure 12-12: Figure 12-13: Figure 12-14: Figure 12-15: Figure 12-16: Figure 12-17: Figure 12-18: Figure 12-19: Figure 12-20: Figure 12-21: Figure 12-22: Figure 12-23: Figure 13-1: Figure 13-2: 8-Bit Timer Mode Control Register 50 (TMC50 TMC50) Format . 220 8-Bit Timer Mode Control Register 51 (TMC51 TMC51) Format . 221 Port Mode Register 1 (PM1) Format . 222 Port Mode Register 11 (PM11) Format . 222 Port Function Register 11 (PF11) Format . 223 8-Bit Timer Mode Control Register Settings for Interval Timer Operation . 224 Interval Timer Operation Timings (1/3). 225 8-Bit Timer Mode Control Register Setting for External Event Counter Operation. 229 External Event Counter Operation Timings (with Rising Edge Specified) . 229 8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation . 230 Square-wave Output Operation Timing . 231 8-Bit Timer Control Register Settings for PWM Output Operation . 232 PWM Output Operation Timing (Active high setting). 233 PWM Output Operation Timings (CRn = 00H, active high setting) . 233 PWM Output Operation Timings (CRn = FFH, active high setting) . 234 PWM Output Operation Timings (CRn changing, active high setting). 234 8-bit Timer Registers 50 and 51 Start Timings . 235 External Event Counter Operation Timings . 235 Timings after Compare Register Change during Timer Count Operation . 236 Block Diagram of Watch Timer. 237 Input Switch Control Register (ISC) Format . 239 Watch Timer Mode Control Register (WTM) Format (1/2) . 240 Operation Timing of Watch Timer/Interval Timer. 244 Example of Generation of Watch Timer Interrupt Request (INTWT) (When Interrupt Period = 0.5 s) . 245 Watchdog Timer Block Diagram. 248 Watchdog Timer Enable Register (WDTE) Format . 250 Watchdog Timer Mode Register (WDTM) Format (1/2) . 251 Input Switch Control Register (ISC) Format . 253 Block Diagram of Clock Output/Buzzer Output Controller. 263 Format of Clock Output Selection Register (CKS) . 265 Format of Port Mode Register 3 (PM3) . 266 Remote Control Output Application Example . 267 Block Diagram of A/D Converter . 269 Format of A/D Converter Mode Register (ADM) . 273 Timing Chart When Boost Reference Voltage Generator Is Used . 274 Format of Analog Input Channel Specification Register (ADS) . 275 Format of A/D Conversion Result Register (ADCR). 276 Format of Power-Fail Comparison Mode Register (PFM) . 277 Format of Power-Fail Comparison Threshold Register (PFT) . 277 Basic Operation of A/D Converter . 279 Relationship Between Analog Input Voltage and A/D Conversion Result . 280 A/D Conversion Operation . 281 Power-Fail Detection (When PFEN = 1 and PFCM = 0) . 282 Overall Error . 284 Quantization Error . 285 Zero-Scale Error . 285 Full-Scale Error . 286 Integral Linearity Error . 286 Differential Linearity Error. 287 Sampling time. 287 Circuit Configuration of Series Resistor String . 288 Analog Input Pin Connection . 289 Timing of A/D Conversion End Interrupt Request Generation. 290 Timing of A/D Converter Sampling and A/D Conversion Start Delay . 291 Internal Equivalent Circuit of ANIn Pin . 292 Block Diagram of Serial Interface CSI10 CSI10 . 296 Block Diagram of Serial Interface CSI11 CSI11 . 297 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 19 Figure 13-3: Figure 13-4: Figure 13-5: Figure 13-6: Figure 13-7: Figure 13-8: Figure 13-9: Figure 13-10: Figure 13-11: Figure 14-1: Figure 14-2: Figure 14-3: Figure 14-4: Figure 14-5: Figure 14-6: Figure 14-7: Figure 14-8: Figure 14-9: Figure 14-10: Figure 14-11: Figure 14-12: Figure 14-13: Figure 14-14: Figure 14-15: Figure 14-16: Figure 14-17: Figure 14-18: Figure 14-19: Figure 14-20: Figure 14-21: Figure 14-22: Figure 14-23: Figure 14-24: Figure 14-25: Figure 14-26: Figure 14-27: Figure 15-1: Figure 15-2: Figure 15-3: Figure 15-4: Figure 15-5: Figure 15-6: Figure 15-7: Figure 15-8: Figure 15-9: Figure 15-10: Figure 15-11: Figure 15-12: Figure 15-13: Figure 15-14: Figure 15-15: Figure 15-16: Figure 15-17: Figure 15-18: Figure 15-19: Figure 15-20: Figure 15-21: Figure 15-22: 20 Format of Serial Operation Mode Register 10 (CSIM10 CSIM10) (1/2) . 298 Format of Serial Operation Mode Register 11 (CSIM11 CSIM11) . 300 Format of Serial Clock Selection Register 10 (CSIC10 CSIC10) (1/2) . 301 Format of Serial Clock Selection Register 11 (CSIC11 CSIC11) (1/2) . 303 Serial operation mode register 1n (CSIM1n) Format. 305 Timing in 3-Wire Serial I/O Mode (1/2) . 309 Timing of Clock/Data Phase . 311 Output Operation of First Bit. 312 Output Value of SO1n Pin (Last Bit). 313 LIN Transmission Operation. 316 LIN Reception Operation . 317 Port Configuration for LIN Reception Operation. 318 Block Diagram of Serial Interface UART6 . 320 Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) Format(1/2) . 322 Asynchronous Serial Interface Reception Error Status Register 6 (ASIS6) Format . 324 Asynchronous Serial Interface Transmission Status Register 6 (ASIF6) Format . 325 Clock Selection Register 6 (CKSR6) Format . 326 Baud Rate Generator Control Register 6 (BRGC6) Format . 327 Asynchronous Serial Interface Control Register 6 (ASICL6) Format (1/2) . 328 Input Switch Control Register (ISC) Format . 330 Port Mode Register 1 (PM1) Format . 330 Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) Format . 331 Format of Normal UART Transmit/Receive Data . 334 Example of Normal UART Transmit/Receive Data Waveform . 335 Normal Transmission Completion Interrupt Request Timing. 337 Example of Continuous Transmission Processing Flow. 339 Timing of Starting Continuous Transmission. 340 Timing of Ending Continuous Transmission . 341 Reception Completion Interrupt Request Timing. 342 Reception Error Interrupt . 343 Noise Filter Circuit . 344 SBF Transmission . 345 SBF Reception . 346 Configuration of Baud Rate Generator . 348 Permissible Baud Rate Range During Reception. 351 Data Frame Length During Continuous Transmission . 353 Data Frame. 357 Remote Frame. 357 Data Frame. 358 Arbitration Field/Standard Format Mode . 358 Arbitration Field/Extended Format Mode. 359 Control Field (Standard Format Mode). 360 Control Field (Extended Format Mode) . 360 Data Field . 361 CRC Field . 361 ACK Field . 362 End of Frame. 362 Interframe Space/Error Active . 363 Interframe Space/Error Passive . 363 Error Frame . 364 Overload Frame. 365 Nominal Bit Time (8 to 25 Time Quanta) . 371 Adjusting Synchronization of the Data Bit . 372 Bit Synchronization. 373 Transmission State Shift Chart. 374 Reception State Shift Chart . 375 Error State Shift Chart . 376 Structural Block Diagram. 377 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 Figure 15-23: Figure 15-24: Figure 15-25: Figure 15-26: Figure 15-27: Figure 15-28: Figure 15-29: Figure 15-30: Figure 15-31: Figure 15-32: Figure 15-33: Figure 15-34: Figure 15-35: Figure 15-36: Figure 15-37: Figure 15-38: Figure 15-39: Figure 15-40: Figure 15-41: Figure 15-42: Figure 15-43: Figure 15-44: Figure 15-45: Figure 15-46: Figure 15-47: Figure 15-48: Figure 15-49: Figure 15-50: Figure 15-51: Figure 15-52: Figure 15-53: Figure 15-54: Figure 15-55: Figure 16-1: Figure 16-2: Figure 16-3: Figure 16-4: Figure 16-5: Figure 16-6: Figure 16-7: Figure 16-8: Figure 16-9: Figure 16-10: Figure 16-11: Figure 16-12: Figure 16-13: Figure 17-1: Figure 17-2: Figure 17-3: Figure 17-4: Figure 17-5: Figure 17-6: Figure 17-7: Figure 18-1: Figure 18-2: Figure 18-3: Figure 18-4: Connection to the CAN Bus . 378 Transmit Message Definition Bits . 382 Transmit Identifier (IDTX0 to IDTX4) Registers . 383 Transmit Data . 384 Control bits for Receive Identifier . 387 Receive Status Bits (1/2) . 388 Receive Identifier (IDREC0 to IDREC4) Registers . 390 Receive Data . 391 Identifier Compare with Mask . 393 Control Bits for Mask Identifier . 394 Mask Identifier . 395 DCAN Control Register (DCANC) Format . 396 CAN Control Register (1/2) . 397 DCAN Support. 398 Time Stamp Function . 400 SOFOUT Toggle Function. 400 Global Time System Function . 400 CAN Error Status Register (1/3) . 401 Transmit Error Counter . 404 Receive Error Counter . 404 Message Count Register (MCNT) (1/2) . 405 Bit Rate Prescaler (1/2) . 407 Synchronization Control Registers 0 and 1 (1/2) . 409 Transmit Control Register (1/2) . 413 Receive Message Register . 415 Mask Control Register (1/2) . 416 Redefinition Control Register (1/2) . 419 Initialization Flow Chart . 426 Transmit Preparation . 427 Transmit Abort . 428 Handling of Semaphore Bits by DCAN-Module. 429 Receive with Interrupt, Software Flow . 430 Receive, Software Polling . 431 LCD Controller/Driver Block Diagram. 434 LCD Clock Select Circuit Block Diagram. 434 LCD Display Mode Register (LCDM) Format . 435 LCD Display Control Register (LCDC) Format . 436 Relationship between LCD Display Data Memory Contents and Segment/Common Outputs . 437 Common Signal Waveform . 439 Common Signal and Segment Signal Voltages and Phases . 439 Example of Connection of LCD Drive Power Supply (1/2) . 440 4-Time-Division LCD Display Pattern and Electrode Connections. 442 4-Time-Division LCD Panel Connection Example . 443 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) . 444 LCD Display Mode Register 3(LCDM3) Format . 446 LCD Clock Control Register 3 (LCDC3) Format. 447 Sound Generator Block Diagram . 449 Concept of Each Signal . 450 Sound Generator Control Register (SGCR) Format (1/2) . 451 Sound Generator Buzzer Control Register (SGBR) Format . 453 Sound Generator Amplitude Register (SGAM) Format . 454 Sound Generator Output Operation Timing . 456 Sound Generator Output Operation Timing . 457 Meter Controller/Driver Block Diagram. 459 1-bit Addition Circuit Block Diagram . 460 Timer Mode Control Register (MCNTC) Format . 463 Compare Control Register n (MCMPCn) Format . 464 User's Manual U17681EE2V0UD00 U17681EE2V0UD00 21 Figure 18-5: Figure 18-6: Figure 18-7: Figure 18-8: Figure 18-9: Figure 18-10: Figure 19-1: Figure 19-2: Figure 19-3: Figure 19-4: Figure 19-5: Figure 19-6: Figure 19-7: Figure 19-8: Figure 19-9: Figure 19-10: Figure 19-11: Figure 19-12: Figure 19-13: Figure 19-14: Figure 20-1: Figure 20-2: Figure 20-3: Figure 20-4: Figure 20-5: Figure 20-6: Figure 20-7: Figure 21-1: Figure 21-2: Figure 21-3: Figure 21-4: Figure 21-5: Figure 22-1: Figure 22-2: Figure 22-3: Figure 23-1: Figure 23-2: Figure 23-3: Figure 23-4: Figure 23-5: Figure 23-6: Figure 23-7: Figure 23-8: Figure 23-9: Figure 23-10: Figure 23-11: Figure 23-12: Figure 23-13: Figure 23-14: Figure 23-15: Figure 23-16: Figure 23-17: Figure 23-18: Figure 23-19: Figure 23-20: 22 Port Mode Control Register (PMC) Format (1/2) . 465 Meter Controller/Driver Clock Register (SMSWI) Format . 467 Restart Timing after Count Stop (Count Start Æ Count Stop Æ Count Start) . 468 Update of PWM data . 469 Timing in 1-bit Addition Circuit Operation . 470 Timing of Output with 1 Clock Shifted . 471 Basic Configuration of Interrupt Function (1/2). 475 Interrupt Request Flag Register Format . 478 Interrupt Mask Flag Register Format . 479 Priority Specify Flag Register Format . 480 Formats of External Interrupt Rising Edge Enable Register and External Interrupt Falling Edge Enable Register . 481 Program Status Word Format. 482 Flowchart from Non-Maskable Interrupt Generation to Acknowledge . 483 Non-Maskable Interrupt Request Acknowledge Timing . 484 Non-Maskable Interrupt Request Acknowledge Operation . 484 Interrupt Request Acknowledge Processing Algorithm . 486 Interrupt Request Acknowledge Timing (Minimum Time). 487 Interrupt Request Acknowledge Timing (Maximum Time). 487 Multiple Interrupt Example (1/2) . 490 Interrupt Request Hold . 493 Format of Oscillation Stabilization Time Counter Status Register (OSTC) . 497 Format of Oscillation Stabilization Time Select Register (OSTS) . 498 HALT Mode Release by Interrupt Request Generation. 502 HALT Mode Release by RESET Input (1/2) . 503 Operation Timing When STOP Mode Is Released. 507 STOP Mode Release by Interrupt Request Generation . 508 STOP Mode Release by RESET Input. 509 Block Diagram of Reset Function . 511 Timing of Reset by RESET Input. 512 Timing of Reset Due to Watchdog Timer Overflow . 512 Timing of Reset in STOP Mode by RESET Input . 513 Reset Control Flag Register (RESF) Format . 517 Block Diagram of Clock Monitor . 519 Format of Clock Monitor Mode Register (CLM) . 520 Timing of Clock Monitor (1/4) . 52