78064Y IEU-1364B IEU-817C HP9000 78P064YKL-T 78062YGC- 78062YGF- 78063YGC- - Datasheet Archive

 

8-BIT SINGLE-CHIP MICROCONTROLLER mPD78062 mPD78063 mPD78064 mPD78P064 mPD78062Y mPD78063Y mPD78064Y mPD78P064Y © 1993

 

mPD78064, 78064Y 78064Y SUBSERIES 8-BIT SINGLE-CHIP MICROCONTROLLER mPD78062 mPD78063 mPD78064 mPD78P064 mPD78062Y mPD78063Y mPD78064Y mPD78P064Y © 1993 Document No. IEU-1364B IEU-1364B (O. D. No. IEU-817C IEU-817C) Date Published July 1995 P Printed in Japan NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after poweron for devices having reset function. FIP is a trademark of NEC Corporation. IEBus, QTOP are trademarks of NEC Corporation. MS-DOS and Windows are trademarks of Microsoft Corporation. IBM DOS, PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 HP9000 Series 300, HP9000 HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. SunOS is a trademark of Sun Microsystems, Inc. TRON is an abbreviation of The Realtime Operating system Nucleus. ITRON is an abbreviation of Industrial TRON. The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: mPD78P064KL-T, 78P064YKL-T 78P064YKL-T The customer must judge the need for license: mPD78062GC- x x x -7EA, 78062YGC- 78062YGC- x x x -7EA, mPD78062GF- x x x -3BA, 78062YGF- 78062YGF- x x x -3BA, mPD78063GC- x x x -7EA, 78063YGC- 78063YGC- x x x -7EA, mPD78063GF- x x x -3BA, 78063YGF- 78063YGF- x x x -3BA, mPD78064GC- x x x -7EA, 78064YGC- 78064YGC- x x x -7EA, mPD78064GF- x x x -3BA, 78064YGF- 78064YGF- x x x -3BA, mPD78P064GC-7EA, 78P064YGC-7EA 78P064YGC-7EA, mPD78P064GF-3BA, 78P064YGF-3BA 78P064YGF-3BA The application circuits and their parameters are for references only and are not intended for use in actual design-in's. Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M7 94.11 Major Revised Points (1/2) Page Revisions Throughout µPD78064Y PD78064Y subseries has been added for target devices. p.8 Section 1.5 "78K/0 78K/0 Series Expansion" has been modified. p.36 Table 3-1. "Pin Input/Output Circuit Types" has beem modified. · Recommended connections of the following unused pins P07/XT1 P07/XT1, P110 to P117, VPP · Input/output circuit type of the following pins P110 to P117 p.108 PM2 given in Figure 6-17. "Port Mode Register Format" has been modified. p.117 A caution given in Figure 7-4. "Oscillation Mode Selection Register Format" has been modified and added. p.118 A caution given in Figure 7-6. "External Circuit of Main System Clock Oscillator" has been modified. p.121 Section 7.4.4 "When no subsystem clocks are used" has been modified. Connection of XT1 pin: Connect to VSS -> Connect to VDD. p.197 Figure 10-1. "Watch Timer Block Diagram" has been modified. p.223 Figure 14-2. "A/D Converter Mode Register Format" has been modified. p.233 Section 14.5(7) "AVDD pin" has been modified and Figure 14-12. "Handling of AVDD Pin" has been added. p.244 Figure 15-4. "Serial Operating Mode Register 0 Format" has been modified. p.261 Figure 15-18. "Acknowledge Signal" has been modified. p.267 Figure 15-21. "RELD and CMDD Operations (Slave)" has been modified. p.284 Section 15.4.4(c) "Interrupt timing specify register (SINT)" has been modified. p.287 Figure 15-34. "SCK0/P27 SCK0/P27 Pin Configuration" has been modified. p.339 Figure 17-1. "Serial Interface Channel 2 Block Diagram" has been modified. p.348 Range of baud rate transmit/receive clock generated by main systm clock has been changed. 75 bps to 38400 bps -> 75 bps to 76800 bps p.429 Table 20-1. "HALT Mode Operating Status" has been modified. Description of HALT mode operating status has been separated to those during main system clock execution and during sub-system clock execution. p.432 Cautions given in Section 20.2.2(1) "STOP Mode Set and Operating Status" have been modified. p.432 Table 20-3. "STOP Mode Operating Status" has been modified. Description of STOP mode operating status has been separated to those during main system clock execution and during sub-system clock execution. (2/2) Page Revisions p.448 Description of QTOP microcontroller has been added to Section 22.5 "Screening of One-Time PROM Versions". p.465, 475, HP9000 HP9000 series 700 has been added for the host machine of development tools and embedded software. p.469 System simulator (SM78K0 SM78K0) has been added for development tools. p.470 Section A.4 "Operating System for IBM PC" has been added. p.476 OS(MX78K0 MX78K0) has been added for embedded software. The asterisks on page margins show revised points. PREFACE Readers This manual has been prepared for user engineers who want to understand the functions of the mPD78064 and 78064Y 78064Y subseries and design and develop its application systems and programs. l mPD78064 subseries : mPD78062, 78063, 78064, 78P064 78P064 l mPD78064Y subseries : mPD78062Y, 78063Y 78063Y, 78064Y 78064Y, 78P064Note Note Under development Purpose This manual is intended for users to understand the functions described in the Organization below. Organization The mPD78064, 78064Y 78064Y subseries manual is separated into two parts: this manual and the instruction edition (common to the 78K/0 78K/0 series). mPD78064, 78064Y 78064Y 78K/0 78K/0 series subseries User's Manual User's Manual Instruction l l CPU functions Internal block functions l Instruction set l Interrupt l Explanation of each instruction l How to Read This Manual Pin functions l Other on-chip peripheral functions Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers. l When you want to understand the functions in general: Æ Read this manual in the order of the contents. l How to interpret the register format: Æ For the circled bit number, the bit name is defined as a reserved word in RA78K/0 RA78K/0, and in CC78K/0 CC78K/0, already defined in the header file named sfrbit.h. l When you know a register name and want to confirm its details: Æ Read APPENDIX C REGISTER INDEX. l To know the mPD78064 and 78064Y 78064Y subseries instruction function in detail: Æ Refer to the 78K/0 78K/0 series User's Manual: Instructions (IEU-1372 IEU-1372) l To know the electrical specifications of the mPD78064 and 78064Y 78064Y subseries: Æ Refer to separately available Data Sheet m PD78062 PD78062, 78063 and 78064 (IC-3244 IC-3244), mPD78P064 Data Sheet (IC-3224 IC-3224) mPD78062Y, 78063Y 78063Y, 78064Y 78064Y Data Sheet (IC-3235 IC-3235) l To know the application example of each function of the mPD78064 and 78064Y 78064Y subseries: Æ Refer to separately available Application Note 78K/0 78K/0 Series: Basic (III) (In preparation), 78K/0 78K/0 series Application Note: Floating-Point Operation Program (IEA1289 IEA1289) Chapter Organization: This manual divides the descriptions for the mPD78064 and 78064Y 78064Y subseries into different chapters as shown below. Read only the chapters related to the device you use. mPD78064 mPD78064Y Subseries Chapter Subseries Chapter 1 Outline (mPD78064 Subseries) " - Chapter 2 Outline (mPD78064Y Subseries) - " Chapter 3 Pin Function (mPD78064 Subseries) " - Chapter 4 Pin Function (mPD78064Y Subseries) - " Chapter 5 CPU Architecture " " Chapter 6 Port Functions " " Chapter 7 Clock Generator " " Chapter 8 16-Bit Timer/Event Counter " " Chapter 9 8-Bit Timer/Event Counters 1 and 2 " " Chapter 10 Watch Timer " " Chapter 11 Watchdog Timer " " Chapter 12 Clock Output Control Circuit " " Chapter 13 Buzzer Output Control Circuit " " Chapter 14 A/D Converter " " Chapter 15 Serial Interface Channel 0 (mPD78064 Subseries) " - Chapter 16 Serial Interface Channel 0 (mPD78064Y Subseries) - " Chapter 17 Serial Interface Channel 2 " " Chapter 18 LCD Controller / Driver " " Chapter 19 Interrupt and Test Functions " " Chapter 20 Standby Function " " Chapter 21 Reset Function " " Chapter 22 mPD78P064, mPD78P064Y " " Chapter 23 Instruction Set " " Differences between mPD78064 and mPD78064Y subseries: The mPD78064 and mPD78064Y subseries are different in the following functions of the serial interface channel 0. mPD78064 mPD78064Y Subseries Subseries 3-wire serial I/O mode " " 2-wire serial I/O mode " " SBI (serial bus interface) mode " - - " Modes of serial interface channel 0 2 I C (Inter IC) bus mode " : Supported - : Not supported Legend Data representation weight : High digits on the left and low digits on the right Active low representations : ¥¥¥ (line over the pin and signal names) Note : Description of note in the text. Caution : Information requiring particular attention Remarks : Additional explanatory material Numeral representations : Binary . ¥¥¥¥ or ¥¥¥¥B Decimal . ¥¥¥¥ Hexadecimal . ¥¥¥¥H Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. l Related documents for mPD78064 subseries Document name Document No. Japanese English mPD78062, 78063, 78064 Data Sheet IC-8632 IC-8632 IC-3244 IC-3244 mPD78P064 Data Sheet IC-8636 IC-8636 IC-3224 IC-3224 mPD78064, 78064Y 78064Y Subseries User's Manual IEU-817 IEU-817 This manual 78K/0 78K/0 Series User's Manual-Instruction IEU-849 IEU-849 IEU-1372 IEU-1372 78K/0 78K/0 Series Instruction Table IEM-5522 IEM-5522 - 78K/0 78K/0 Series Instruction Set IEM-5521 IEM-5521 - mPD78064 Subseries Special Function Register Table IEM-5568 IEM-5568 - Basics III IEA-767 IEA-767 In preparation Floating-point operation program IEA-718 IEA-718 IEA-1289 IEA-1289 78K/0 78K/0 Series Application Note l Related documents for mPD78064Y subseries Document name Document No. Japanese English mPD78062Y, 78063Y 78063Y, 78064Y 78064Y Data Sheet IC-8704 IC-8704 IC-3235 IC-3235 mPD78P064Y Preliminary Product Information IP-8703 IP-8703 IP-3236 IP-3236 mPD78064, 78064Y 78064Y Subseries User's Manual IEU-817 IEU-817 This manual 78K/0 78K/0 Series User's Manual-Instruction IEU-849 IEU-849 IEU-1372 IEU-1372 78K/0 78K/0 Series Instruction Table IEM-5522 IEM-5522 - 78K/0 78K/0 Series Instruction Set IEM-5521 IEM-5521 - mPD78064Y Subseries Special Function Register Table IEM-5583 IEM-5583 - Basics III IEA-767 IEA-767 In preparation Floating-point operation program IEA-718 IEA-718 IEA-1289 IEA-1289 78K/0 78K/0 Series Application Note Caution The above documents are subject to change without prior notice. Be sure to use the latest version document when starting design. l Development Tool Documents (User's Manuals) Document Name Document No. Japanese English Operation EEU-809 EEU-809 EEU-1399 EEU-1399 Language EEU-815 EEU-815 EEU-1404 EEU-1404 EEU-817 EEU-817 EEU-1402 EEU-1402 Operation EEU-656 EEU-656 EEU-1280 EEU-1280 Language EEU-655 EEU-655 EEU-1284 EEU-1284 Programming Know-How EEA-618 EEA-618 Planned EEU-777 EEU-777 - EEU-651 EEU-651 EEU-1355 EEU-1355 EEU-704 EEU-704 Planned PG-1500 PG-1500 Controller IBM PC Series (PC DOS ) Base EEU-5008 EEU-5008 EEU-1291 EEU-1291 IE-78000-R IE-78000-R EEU-810 EEU-810 EEU-1398 EEU-1398 IE-78000-R-BK IE-78000-R-BK EEU-867 EEU-867 EEU-1427 EEU-1427 IE-78064-R-EM IE-78064-R-EM EEU-905 EEU-905 EEU-1443 EEU-1443 EP-78064 EP-78064 EEU-934 EEU-934 EEU-1469 EEU-1469 RA78K RA78K Series Assembler Package RA78K RA78K Series Structured Assembler Preprocessor CC78K CC78K Series C Compiler CC78K CC78K C Compiler Application Note CC78K CC78K Series Library Source File PG-1500 PG-1500 PROM Programmer TM PG-1500 PG-1500 Controller PC-9800 PC-9800 Series (MS-DOS ) Base TM SM78K0 SM78K0 System Simulator Reference EEU-5002 EEU-5002 Planned SD78K/0 SD78K/0 Screen Debugger Introduction EEU-852 EEU-852 - PC-9800 PC-9800 Series (MS-DOS) Base Reference EEU-816 EEU-816 - SD78K/0 SD78K/0 Screen Debugger Introduction EEU-5024 EEU-5024 EEU-1414 EEU-1414 Reference EEU-993 EEU-993 EEU-1413 EEU-1413 TM IBM PC/AT (PC DOS) Base Caution The above documents are subject to change without prior notice. Be sure to use the latest version document when starting design. l Documents for Embedded Software (User's Manual) Document Name Document No. Japanese English Basics EEU-912 EEU-912 - Installation EEU-911 EEU-911 - Technicals EEU-913 EEU-913 - Basics EEU-5010 EEU-5010 - Fuzzy Knowledge Data Creation Tool EEU-829 EEU-829 EEU-1438 EEU-1438 78K/0 78K/0, 78K/II 78K/II, 87AD Series Fuzzy Inference Development Support System-Translator EEU-862 EEU-862 EEU-1444 EEU-1444 78K/0 78K/0 Series Fuzzy Inference Development Support System-Fuzzy Inference Module EEU-858 EEU-858 EEU-1441 EEU-1441 78K/0 78K/0 Series Fuzzy Inference Development Support System-Fuzzy Inference Debugger EEU-921 EEU-921 EEU-1458 EEU-1458 78K/0 78K/0 Series Real-Time OS 78K/0 78K/0 Series OS MX78K0 MX78K0 l Other Documents Document Name Document No. Japanese English Package Manual IEI-635 IEI-635 IEI-1213 IEI-1213 Semiconductor Device Mounting Technology Manual IEI-616 IEI-616 IEI-1207 IEI-1207 Quality Grade on NEC Semiconductor Devices IEI-620 IEI-620 IEI-1209 IEI-1209 Reliability Quality Control on NEC Semiconductor Devices IEM-5068 IEM-5068 - Electric Static Discharge (ESD) Test MEM-539 MEM-539 - Semiconductor Devices Quality Assurance Guide MEI-603 MEI-603 MEI-1202 MEI-1202 Microcontroller Related Product Guide-Third Party Manufacturers MEI-604 MEI-604 - Caution The above documents are subject to change without prior notice. Be sure to use the latest version document when starting design. CONTENTS CHAPTER 1 OUTLINE (mPD78064 Subseries) . 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1 Features . Applications . Ordering Information . Pin Configuration (Top View) . 78K/0 78K/0 Series Expansion . Block Diagram . Outline of Function . Mask Options . 1 2 2 3 8 10 11 12 CHAPTER 2 OUTLINE (mPD78064Y Subseries) . 13 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 Features . Applications . Ordering Information . Pin Configuration (Top View) . 78K/0 78K/0 Series Expansion . Block Diagram . Outline of Function . Mask Options . 13 14 14 15 20 22 23 24 CHAPTER 3 PIN FUNCTION (mPD78064 Subseries) . 25 3.1 25 3.1.1 Normal operating mode pins . 25 3.1.2 3.2 Pin Function List . PROM programming mode pins (mPD78P064 only) . 28 Description of Pin Functions . 29 3.2.1 P00 to P05, P07 (Port 0) . 29 3.2.2 P10 to P17 (Port 1) . 30 3.2.3 P25 to P27 (Port 2) . 30 3.2.4 P30 to P37 (Port 3) . 31 3.2.5 P70 to P72 (Port 7) . 32 3.2.6 P80 ­ P87 (Port 8) . 33 3.2.7 P90 ­ P97 (Port 9) . 33 3.2.8 P100 ­ P103 (Port 10) . 33 3.2.9 P110 ­ P117 (Port 11) . 33 3.2.10 COM0 to COM3 . 34 3.2.11 VLC0 ­ VLC2 . 34 3.2.12 BIAS . 34 3.2.13 AVREF . 34 3.2.14 AVDD . 34 3.2.15 AVSS . 34 3.2.16 RESET . 34 ­i­ 3.2.17 X1 and X2 . 34 3.2.18 XT1 and XT2 . 34 3.2.19 VDD . 35 3.2.20 VSS . 35 3.2.21 VPP (mPD78P064 only) . 35 3.2.22 IC (Mask ROM version only) . 35 Input/output Circuits and Recommended Connection of Unused Pins . 36 CHAPTER 4 PIN FUNCTION (mPD78064Y Subseries) . 41 3.3 4.1 41 4.1.1 Normal operating mode pins . 41 4.1.2 4.2 Pin Function List . PROM programming mode pins (mPD78P064Y only) . 44 Description of Pin Functions . 45 4.2.1 P00 to P05, P07 (Port 0) . 45 4.2.2 P10 to P17 (Port 1) . 46 4.2.3 P25 to P27 (Port 2) . 46 4.2.4 P30 to P37 (Port 3) . 47 4.2.5 P70 to P72 (Port 7) . 48 4.2.6 P80 ­ P87 (Port 8) . 49 4.2.7 P90 ­ P97 (Port 9) . 49 4.2.8 P100 ­ P103 (Port 10) . 49 4.2.9 P110 ­ P117 (Port 11) . 49 4.2.10 COM0 to COM3 . 50 4.2.11 VLC0 ­ VLC2 . 50 4.2.12 BIAS . 50 4.2.13 AVREF . 50 4.2.14 AVDD . 50 4.2.15 AVSS . 50 4.2.16 RESET . 50 4.2.17 X1 and X2 . 50 4.2.18 XT1 and XT2 . 50 4.2.19 VDD . 51 4.2.20 VSS . 51 4.2.21 VPP (mPD78P064Y only) . 51 4.2.22 IC (Mask ROM version only) . 51 Input/output Circuits and Recommended Connection of Unused Pins . 52 CHAPTER 5 CPU ARCHITECTURE . 57 4.3 5.1 Memory Spaces . 57 5.1.1 61 Internal data memory space . 62 5.1.3 Special Function Register (SFR) area . 62 5.1.4 5.2 Internal program memory space . 5.1.2 Data memory addressing . 63 Processor Registers . 67 5.2.1 Control registers . 67 5.2.2 General registers . 69 5.2.3 Special Function Register (SFR) . 71 ­ ii ­ 5.3 Instruction Address Addressing . 75 5.3.1 75 Immediate addressing . 76 5.3.3 Table indirect addressing . 77 5.3.4 5.4 Relative Addressing . 5.3.2 Register addressing . 78 Operand Address Addressing . 79 5.4.1 Implied addressing . 79 5.4.2 Register addressing . 80 5.4.3 Direct addressing . 81 5.4.4 Short direct addressing . 82 5.4.5 Special-Function Register (SFR) addressing . 84 5.4.6 Register indirect addressing . 85 5.4.7 Based addressing . 86 5.4.8 Based indexed addressing . 87 5.4.9 Stack addressing . 87 CHAPTER 6 PORT FUNCTIONS . 89 6.1 6.2 Port Functions . Port Configuration . 89 92 6.2.1 92 Port 0 . 6.2.2 Port 1 . 94 6.2.3 Port 2 (mPD78064 Subseries) . 95 6.2.4 Port 2 (mPD78064Y Subseries) . 97 6.2.5 Port 3 . 99 6.2.6 Port 7 . 100 6.2.7 Port 8 . 102 6.2.8 Port 9 . 103 6.2.9 Port 10 . 104 6.2.10 Port 11 . 105 Port Function Control Registers . Port Function Operations . 106 111 6.4.1 Writing to input/output port . 111 6.4.2 Reading from input/output port . 111 6.4.3 Operations on input/output port . 111 CHAPTER 7 CLOCK GENERATOR . 113 6.3 6.4 7.1 7.2 7.3 7.4 113 113 115 118 7.4.1 Main system clock oscillator . 118 7.4.2 Subsystem clock oscillator . 119 7.4.3 Scaler . 121 7.4.4 7.5 Clock Generator Functions . Clock Generator Configuration . Clock Generator Control Register . System Clock Oscillator . When no subsystem clocks are used . 121 Clock Generator Operations . 122 7.5.1 Main system clock operations . 123 7.5.2 Subsystem clock operations . 124 ­ iii ­ 7.6 Changing System Clock and CPU Clock Settings . 125 7.6.1 Time required for switchover between system clock and CPU clock . 125 7.6.2 System clock and CPU clock switching procedure . 126 CHAPTER 8 16-BIT 16-BIT TIMER/EVENT COUNTER . 127 8.1 8.2 8.3 8.4 16-Bit Timer/Event Counter Functions . 16-Bit Timer/Event Counter Configuration . 16-Bit Timer/Event Counter Control Registers . 16-Bit Timer/Event Counter Operations . 129 131 135 144 8.4.1 Interval timer operations . 144 8.4.2 PWM output operations . 146 8.4.3 PPG output operations . 149 8.4.4 Pulse width measurement operations . 150 8.4.5 External event counter operation . 157 8.4.6 Square-wave output operation . 159 8.4.7 One-shot pulse output operation . 161 16-Bit Timer/Event Counter Operating Precautions . 165 CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1 AND 2 . 169 8.5 9.1 169 8-bit timer/event counter mode . 169 9.1.2 9.2 9.3 9.4 8-Bit Timer/Event Counters 1 and 2 Functions . 9.1.1 16-bit timer/event counter mode . 172 8-Bit Timer/Event Counters 1 and 2 Configurations . 8-Bit Timer/Event Counters 1 and 2 Control Registers . 8-Bit Timer/Event Counters 1 and 2 Operations . 174 178 183 9.4.1 8-bit timer/event counter mode . 183 9.4.2 16-bit timer/event counter mode . 188 Cautions on 8-Bit Timer/Event Counters 1 and 2 . 192 CHAPTER 10 WATCH TIMER . 195 9.5 10.1 10.2 10.3 10.4 Watch Timer Functions . Watch Timer Configuration . Watch Timer Control Registers . Watch Timer Operations . 195 196 196 200 10.4.1 Watch timer operation . 200 10.4.2 Interval timer operation . 200 CHAPTER 11 WATCHDOG TIMER . 201 11.1 11.2 11.3 11.4 Watchdog Timer Functions . Watchdog Timer Configuration . Watchdog Timer Control Registers . Watchdog Timer Operations . 201 203 204 207 11.4.1 Watchdog timer operation . 207 11.4.2 Interval timer operation . 208 ­ iv ­ CHAPTER 12 CLOCK OUTPUT CONTROL CIRCUIT . 209 12.1 Clock Output Control Circuit Functions . 12.2 Clock Output Control Circuit Configuration . 12.3 Clock Output Function Control Registers . 209 210 211 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT . 215 13.1 Buzzer Output Control Circuit Functions . 13.2 Buzzer Output Control Circuit Configuration . 13.3 Buzzer Output Function Control Registers . 215 215 216 CHAPTER 14 A/D CONVERTER . 219 14.1 14.2 14.3 14.4 A/D Converter Functions . A/D Converter Configuration . A/D Converter Control Registers . A/D Converter Operations . 219 219 222 226 14.4.1 Basic operations of A/D converter . 226 14.4.2 Input voltage and conversion results . 228 14.4.3 A/D converter operating mode . 229 14.5 A/D Converter Cautions . 231 CHAPTER 15 SERIAL INTERFACE CHANNEL 0 (mPD78064 Subseries) . 235 15.1 15.2 15.3 15.4 Serial Interface Channel 0 Functions . Serial Interface Channel 0 Configuration . Serial Interface Channel 0 Control Registers . Serial Interface Channel 0 Operations . 236 238 242 249 15.4.1 Operation stop mode . 249 15.4.2 3-wire serial I/O mode operation . 250 15.4.3 SBI mode operation . 255 15.4.4 2-wire serial I/O mode operation . 281 15.4.5 SCK0/P27 SCK0/P27 pin output manipulation . 287 CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (mPD78064Y Subseries) . 289 16.1 16.2 16.3 16.4 Serial Interface Channel 0 Functions . Serial Interface Channel 0 Configuration . Serial Interface Channel 0 Control Registers . Serial Interface Channel 0 Operations . 290 292 296 303 16.4.1 Operation stop mode . 303 16.4.2 3-wire serial I/O mode operation . 304 16.4.3 2-wire serial I/O mode operation . 308 16.4.4 I2C bus mode operation . 314 16.4.5 Cautions on use of I2 C bus mode . 331 16.4.6 SCK0/SCL/P27 SCK0/SCL/P27 pin output manipulation . 334 ­v­ CHAPTER 17 SERIAL INTERFACE CHANNEL 2 . 17.1 17.2 17.3 17.4 337 Serial Interface Channel 2 Functions . Serial Interface Channel 2 Configuration . Serial Interface Channel 2 Control Registers . Serial Interface Channel 2 Operation . 337 338 342 350 17.4.1 Operation stop mode . 350 17.4.2 Asynchronous serial interface (UART) mode . 352 17.4.3 3-wire serial I/O mode . 365 LCD CONTROLLER/DRIVER . 371 LCD Controller/Driver Functions . LCD Controller/Driver Configuration . LCD Controller/Driver Control Registers . LCD Controller/Driver Settings . LCD Display Data Memory . Common Signals and Segment Signals . Supply of LCD Drive Voltages VLC0, VLC1, VLC2 . Display Modes . 371 372 374 377 378 379 383 387 18.8.1 Static Display Example . 387 18.8.2 2-Time-Division Display Example . 390 18.8.3 3-Time-Division Display Example . 393 18.8.4 4-Time-Division Display Example . 397 CHAPTER 19 INTERRUPT AND TEST FUNCTIONS . 401 CHAPTER 18 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 19.1 19.2 19.3 19.4 Interrupt Function Types . Interrupt Sources and Configuration . Interrupt Function Control Registers . Interrupt Servicing Operations . 401 402 405 414 19.4.1 Non-maskable interrupt acknowledge operation . 414 19.4.2 Maskable interrupt acknowledge operation . 417 19.4.3 Software interrupt acknowledge operation . 420 19.4.4 Multiple interrupt servicing . 420 19.4.5 Interrupt reserve . 422 19.5 Test Functions . 423 19.5.1 Registers controlling the test function . 423 19.5.2 Test input signal acknowledge operation . 426 CHAPTER 20 STANDBY FUNCTION . 427 20.1 Standby Function and Configuration . 427 20.1.1 Standby function . 427 20.1.2 Standby function control register . 428 20.2 Standby Function Operations . 429 20.2.1 HALT mode . 429 20.2.2 STOP mode . 432 ­ vi ­ CHAPTER 21 RESET FUNCTION . 435 21.1 Reset Function . 435 CHAPTER 22 mPD78P064, 78P064Y 78P064Y . 439 22.1 Memory Size Switching Register . 22.2 PROM Programming . 440 441 22.2.1 Operating modes . 441 22.2.2 PROM write procedure . 443 22.2.3 PROM reading procedure . 447 22.3 Erasure Procedure (mPD78P064KL-T and 78P064YKL-T 78P064YKL-T Only) . 22.4 Opaque Film Masking the Window (mPD78P064KL-T and 78P064YKL-T 78P064YKL-T Only) . 22.5 Screening of One-Time PROM Versions . 448 448 448 CHAPTER 23 INSTRUCTION SET . 449 23.1 Legends Used in Operation List . 450 23.1.1 Operand identifiers and description methods . 450 23.1.2 Description of "operation" column . 451 23.1.3 Description of "flag operation" column . 451 23.2 Operation List . 23.3 Instructions Listed by Addressing Type . 452 460 ­ vii ­ APPENDIX A DEVELOPMENT TOOLS . A.1 A.2 A.3 Language Processing Software . PROM Programming Tools . Debugging Tool . 465 466 467 468 A.3.1 Hardware . 468 A.3.2 Software . 469 Operating Systems for IBM PC . 470 APPENDIX B EMBEDDED SOFTWARE . 475 A.4 B.1 B.2 Real-time OS . Fuzzy Inference Development Support System . 475 477 APPENDIX C REGISTER INDEX . 479 C.1 C.2 Register Name Index . Register Symbol Index . 479 482 APPENDIX D REVISION HISTORY . 485 ­ viii ­ LIST OF FIGURES (1/8) Figure No. Title Page 3-1 Pin Input/Output Circuit of List . 38 4-1 Pin Input/Output Circuit of List . 54 5-1 Memory Map (mPD78062, 78062Y 78062Y) . 57 5-2 Memory Map (mPD78063, 78063Y 78063Y) . 58 5-3 Memory Map (mPD78064, 78064Y 78064Y) . 59 5-4 Memory Map (mPD78P064, 78P064Y 78P064Y) . 60 5-5 Data Memory Addressing (mPD78062, 78062Y 78062Y) . 63 5-6 Data Memory Addressing (mPD78063, 78063Y 78063Y) . 64 5-7 Data Memory Addressing (mPD78064, 78064Y 78064Y) . 65 5-8 Data Memory Addressing (mPD78P064, 78P064Y 78P064Y) . 66 5-9 Program Counter Configuration . 67 5-10 Program Status Word Configuration . 67 5-11 Stack Pointer Configuration . 68 5-12 Data to be Saved to Stack Memory . 68 5-13 Data to be Reset from Stack Memory . 69 5-14 General Register Configuration . 70 6-1 Port Types . 89 6-2 P00 and P07 Configurations . 93 6-3 P01 to P05 Configurations . 93 6-4 P10 to P17 Configurations . 94 6-5 P25, P26 Configurations (mPD78064 subseries) . 95 6-6 P27 Configuration (mPD78064 subseries) . 96 6-7 P25, P26 Configurations (mPD78064Y subseries) . 97 6-8 P27 Configuration (mPD78064Y subseries) . 98 6-9 P30 to P37 Configurations . 99 6-10 P70 Configuration . 100 6-11 P71 and P72 Configurations . 101 6-12 P80 to P87 Configurations . 102 6-13 P90 to P97 Configurations . 103 6-14 P100 to P103 Configurations . 104 6-15 P110 to P117 Configurations . 105 6-16 Block Diagram of Falling Edge Detection Circuit . 105 6-17 Port Mode Register Format . 108 6-18 Pull-Up Resistor Option Register Format . 109 6-19 Key Return Mode Register Format . 110 ­ ix ­ LIST OF FIGURES (2/8) Figure No. Title Page 7-1 Block Diagram of Clock Generator . 7-2 Subsystem Clock Feedback Resistor . 114 115 7-3 Processor Clock Control Register Format . 116 7-4 Oscillation Mode Selection Register Format . 117 7-5 Main System Clock Waveform due to Writing to OSMS . 117 7-6 External Circuit of Main System Clock Oscillator . 118 7-7 External Circuit of Subsystem Clock Oscillator . 119 7-8 Examples of Oscillator with Bad Connection . 119 7-9 Main System Clock Stop Function . 123 7-10 System Clock and CPU Clock Switching . 126 8-1 16-Bit Timer/Event Counter Block Diagram . 132 8-2 16-Bit Timer/Event Counter Output Control Circuit Block Diagram . 133 8-3 Timer Clock Selection Register 0 Format . 136 8-4 16-Bit Timer Mode Control Register Format . 138 8-5 Capture/Compare Control Register 0 Format . 139 8-6 16-Bit Timer Output Control Register Format . 140 8-7 Port Mode Register 3 Format . 141 8-8 External Interrupt Mode Register 0 Format . 142 8-9 Sampling Clock Select Register Format . 143 8-10 Control Register Settings for Interval Timer Operation . 144 8-11 Interval Timer Configuration Diagram . 145 8-12 Interval Timer Operation Timings . 145 8-13 Control Register Settings for PWM Output Operation . 147 8-14 Example of D/A Converter Configuration with PWM Output . 148 8-15 TV Tuner Application Circuit Example . 148 8-16 Control Register Settings for PPG Output Operation . 149 8-17 Control Register Settings for Pulse Width Measurement with Free-Running Counter and One Capture Register . 150 8-18 Configuration Diagram for Pulse Width Measurement by Free-Running Counter . 151 8-19 Timing of Pulse Width Measurement Operation by Free-Running Counter and One Capture Register (with Both Edges Specified) . 8-20 with Free-Running Counter . 8-21 153 Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers . 8-23 152 Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) . 8-22 151 Control Register Settings for Two Pulse Width Measurements 154 Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) . 155 8-24 Control Register Settings for Pulse Width Measurement by Means of Restart . 156 8-25 Timing of Pulse Width Measurement Operation by Means of Restart (with Rising Edge Specified) . ­x­ 156 LIST OF FIGURES (3/8) Figure No. 8-26 Title Control Register Settings in External Event Counter Mode . Page 157 8-27 External Event Counter Configuration Diagram . 158 8-28 External Event Counter Operation Timings (with Rising Edge Specified) . 158 8-29 Control Register Settings in Square-Wave Output Mode . 159 8-30 Square-Wave Output Operation Timing . 160 8-31 Control Register Settings for One-Shot Pulse Output Operation Using Software Trigger . 161 8-32 Timing of One-Shot Pulse Output Operation Using Software Trigger . 162 8-33 Control Register Settings for One-Shot Pulse Output Operation Using External Trigger . 8-34 163 Timing of One-Shot Pulse Output Operation Using External Trigger (With Rising Edge Specified) . 164 8-35 16-Bit Timer Register Start Timing . 165 8-36 Timings After Change of Compare Register During Timer Count Operation . 165 8-37 Capture Register Data Retention Timing . 166 8-38 Operation Timing of OVF0 Flag . 167 9-1 8-Bit Timer/Event Counters 1 and 2 Block Diagram . 175 9-2 Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 1 . 176 9-3 Block Diagram of 8-Bit Timer/Event Counter Output Control Circuit 2 . 176 9-4 Timer Clock Select Register 1 Format . 179 9-5 8-Bit Timer Mode Control Register Format . 180 9-6 8-Bit Timer Output Control Register Format . 181 9-7 Port Mode Register 3 Format . 182 9-8 Interval Timer Operation Timings . 183 9-9 External Event Counter Operation Timings (with Rising Edge Specified) . 186 9-10 Interval Timer Operation Timing . 188 9-11 External Event Counter Operation Timings (with Rising Edge Specified) . 190 9-12 8-Bit Timer Registers 1 and 2 Start Timing . 192 9-13 External Event Counter Operation Timing . 192 9-14 Timing after Compare Register Change during Timer Count Operation . 193 10-1 Watch Timer Block Diagram . 197 10-2 Timer Clock Select Register 2 Format . 198 10-3 Watch Timer Mode Control Register Format . 199 11-1 Watchdog Timer Block Diagram . 203 11-2 Timer Clock Select Register 2 Format . 205 11-3 Watchdog Timer Mode Register Format . 206 ­ xi ­ LIST OF FIGURES (4/8) Figure No. Title Page 12-1 Remote Controlled Output Application Example . 209 12-2 Clock Output Control Circuit Block Diagram . 210 12-3 Timer Clock Select Register 0 Format . 212 12-4 Port Mode Register 3 Format . 213 13-1 Buzzer Output Control Circuit Block Diagram . 215 13-2 Timer Clock Select Register 2 Format . 217 13-3 Port Mode Register 3 Format . 218 14-1 A/D Converter Block Diagram . 220 14-2 A/D Converter Mode Register Format . 223 14-3 A/D Converter Input Select Register Format . 224 14-4 External Interrupt Mode Register 1 Format . 225 14-5 A/D Converter Basic Operation . 227 14-6 Relations between Analog Input Voltage and A/D Conversion Result . 228 14-7 A/D Conversion by Hardware Start . 229 14-8 A/D Conversion by Software Start . 230 14-9 Example of Method of Reducing Current Consumption in Standby Mode . 231 14-10 Analog Input Pin Disposition . 232 14-11 A/D Conversion End Interrupt Generation Timing . 233 14-12 Handling of AVDD Pin . 233 15-1 Serial Bus Interface (SBI) System Configuration Example . 237 15-2 Serial Interface Channel 0 Block Diagram . 239 15-3 Timer Clock Select Register 3 Format . 243 15-4 Serial Operating Mode Register 0 Format . 244 15-5 Serial Bus Interface Control Register Format . 246 15-6 Interrupt Timing Specify Register Format . 248 15-7 3-Wire Serial I/O Mode Timings . 253 15-8 RELT and CMDT Operations . 253 15-9 Circuit of Switching in Transfer Bit Order . 254 15-10 Example of Serial Bus Configuration with SBI . 255 15-11 SBI Transfer Timings . 257 15-12 Bus Release Signal . 258 15-13 Command Signal . 258 15-14 Addresses . 259 15-15 Slave Selection with Address . 259 15-16 Commands . 260 15-17 Data . 260 15-18 Acknowledge Signal . 261 15-19 BUSY and READY Signals . 262 15-20 RELT, CMDT, RELD, and CMDD Operations (Master) . 267 ­ xii ­ LIST OF FIGURES (5/8) Figure No. Title Page 15-21 RELD and CMDD Operations (Slave) . 267 15-22 ACKT Operation . 268 15-23 ACKE Operations . 269 15-24 ACKD Operations . 270 15-25 BSYE Operation . 270 15-26 Pin Configuration . 273 15-27 Address Transmission from Master Device to Slave Device (WUP = 1) . 275 15-28 Command Transmission from Master Device to Slave Device . 276 15-29 Data Transmission from Master Device to Slave Device . 277 15-30 Data Transmission from Slave Device to Master Device . 278 15-31 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode . 281 15-32 2-Wire Serial I/O Mode Timings . 285 15-33 RELT and CMDT Operations . 286 15-34 SCK0/P27 SCK0/P27 Pin Configuration . 287 16-1 Serial Bus Configuration Example Using I2C Bus . 291 16-2 Serial Interface Channel 0 Block Diagram . 293 16-3 Timer Clock Select Register 3 Format . 297 16-4 Serial Operating Mode Register 0 Format . 298 16-5 Serial Bus Interface Control Register Format . 299 16-6 Interrupt Timing Specify Register Format . 301 16-7 3-Wire Serial I/O Mode Timings . 306 16-8 RELT and CMDT Operations . 306 16-9 Circuit of Switching in Transfer Bit Order. 307 16-10 Serial Bus Configuration Example Using 2-Wire Serial I/O Mode . 308 16-11 2-Wire Serial I/O Mode Timings . 312 16-12 RELT and CMDT Operations . 313 2 16-13 Example of Serial Bus Configuration Using I C Bus . 314 16-14 I2C Bus Serial Data Transfer Timing . 315 16-15 Start Condition . 316 16-16 Address . 316 16-17 Transfer Direction Specification . 316 16-18 Acknowledge Signal . 317 16-19 Stop Condition . 317 16-20 Wait Signal . 318 16-21 Pin Configuration . 323 16-22 Data Transmission from Master to Slave 16-23 Data Transmission from Slave to Master (Both Master and Slave Selected 9-Clock Wait) . 328 16-24 Start Condition Output . 331 16-25 Slave Wait Release (Transmission) . 332 (Both Master and Slave Selected 9-Clock Wait) . ­ xiii ­ 325 LIST OF FIGURES (6/8) Figure No. Title Page 16-26 Slave Wait Release (Reception) . 333 16-27 SCK0/SCL/P27 SCK0/SCL/P27 Pin Configuration . 334 16-28 SCK0/SCL/P27 SCK0/SCL/P27 Pin Configuration . 335 16-29 Logic Circuit of SCL Signal . 335 17-1 Serial Interface Channel 2 Block Diagram . 339 17-2 Baud Rate Generator Block Diagram . 340 17-3 Serial Operating Mode Register 2 Format . 342 17-4 Asynchronous Serial Interface Mode Register Format . 343 17-5 Asynchronous Serial Interface Status Register Format . 345 17-6 Baud Rate Generator Control Register Format . 346 17-7 Asynchronous Serial Interface Transmit/Receive Data Format . 359 17-8 Asynchronous Serial Interface Transmission Completion Interrupt Timing . 361 17-9 Asynchronous Serial Interface Reception Completion Interrupt Timing . 362 17-10 Receive Error Timing . 363 17-11 3-Wire Serial I/O Mode Timing . 370 18-1 LCD Controller/Driver Block Diagram . 372 18-2 LCD Clock Select Circuit Block Diagram . 373 18-3 LCD Display Mode Register Format . 374 18-4 LCD Display Control Register Format . 376 18-5 Relationship between LCD Display Data Memory Contents and Segment/Common Outputs . 378 18-6 Common Signal Waveform . 381 18-7 Common Signal and Static Signal Voltages and Phases . 382 18-8 LCD Drive Power Supply Connection Examples (with On-Chip Split Resistor) . 384 18-9 LCD Drive Power Supply Connection Examples (with External Split Resistor) . 385 18-10 Example of LCD Drive Voltage Supply from Off-Chip . 386 18-11 Static LCD Display Pattern and Electrode Connections . 387 18-12 Static LCD Panel Connection Example . 388 18-13 Static LCD Drive Waveform Examples . 389 18-14 2-Time-Division LCD Display Pattern and Electrode Connections . 390 18-15 2-Time-Division LCD Panel Connection Example . 391 18-16 2-Time-Division LCD Drive Waveform Examples (1/2 Bias Method) . 392 18-17 3-Time-Division LCD Display Pattern and Electrode Connections . 393 18-18 3-Time-Division LCD Panel Connection Example . 394 18-19 3-Time-Division LCD Drive Waveform Examples (1/2 Bias Method) . 395 18-20 3-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) . 396 18-21 4-Time-Division LCD Display Pattern and Electrode Connections . 397 18-22 4-Time-Division LCD Panel Connection Example . 398 18-23 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method) . 399 ­ xiv ­ LIST OF FIGURES (7/8) Figure No. Title Page 19-1 Basic Configuration of Interrupt Function . 403 19-2 Interrupt Request Flag Register Format . 406 19-3 Interrupt Mask Flag Register Format . 407 19-4 Priority Specify Flag Register Format . 408 19-5 External Interrupt Mode Register 0 Format . 409 19-6 External Interrupt Mode Register 1 Format . 410 19-7 Sampling Clock Select Register Format . 411 19-8 Noise Remover Input/Output Timing (during rising edge detection) . 412 19-9 Program Status Word Format . 413 19-10 Non-Maskable Interrupt Acknowledge Flowchart . 415 19-11 Non-Maskable Interrupt Acknowledge Timing . 415 19-12 Non-Maskable Interrupt Request Acknowledge Operation . 416 19-13 Interrupt Acknowledge Processing Algorithm . 418 19-14 Interrupt Acknowledge Timing (Minimum Time) . 419 19-15 Interrupt Acknowledge Timing (Maximum Time) . 419 19-16 Multiple Interrupt Example . 421 19-17 Interrupt Request Hold . 422 19-18 Basic Configuration of Test Function . 423 19-19 Format of Interrupt Request Flag Register 1L . 424 19-20 Format of Interrupt Mask Flag Register 1L . 424 19-21 Key Return Mode Register Format . 425 20-1 Oscillation Stabilization Time Select Register Format . 428 20-2 HALT Mode Clear upon Interrupt Generation . 430 20-3 HALT Mode Release by RESET Input . 431 20-4 STOP Mode Release by Interrupt Generation . 433 20-5 Release by STOP Mode RESET Input . 434 21-1 Block Diagram of Reset Function . 435 21-2 Timing of Reset Input by RESET Input . 436 21-3 Timing of Reset due to Watchdog Timer Overflow . 436 21-4 Timing of Reset Input in STOP Mode by RESET Input . 436 22-1 Memory Size Switching Register Format . 440 22-2 Page Program Mode Flowchart . 443 22-3 Page Program Mode Timing . 444 22-4 Byte Program Mode Flowchart . 445 22-5 Byte Program Mode Timing . 446 22-6 PROM Read Timing . 447 ­ xv ­ LIST OF FIGURES (8/8) Figure No. Title Page A-1 Development Tool Configuration . 465 A-2 EV-9500GC-100 EV-9500GC-100 Drawing (For Reference Only) (Unit: mm) . 472 A-3 EV-9200GF-100 EV-9200GF-100 Drawing (For Reference Only) . 473 A-4 EV-9200GF-100 EV-9200GF-100 Footprint (For Reference Only) . 474 ­ xvi ­ LIST OF TABLES (1/3) Table No. Title Page 1-1 Mask Options of Mask ROM Versions . 12 2-1 Mask Options of Mask ROM Versions . 24 3-1 Pin Input/Output Circuit Types . 36 4-1 Pin Input/Output Circuit Types . 52 5-1 Internal ROM Capacity . 61 5-2 Vector Table . 61 5-3 Internal High-Speed RAM Capacity . 62 5-4 Special-Function Register List . 73 6-1 Port Functions (mPD78064 subseries) . 90 6-2 Port Functions (mPD78064Y subseries) . 91 6-3 Port Configuration . 92 6-4 Port Mode Register and Output Latch Settings when Using Dual-Functions . 107 7-1 Clock Generator Configuration . 113 7-2 Maximum Time Required for CPU Clock Switchover . 125 8-1 Timer/Event Counter Types and Functions . 128 8-2 16-Bit Timer/Event Counter Interval Times . 129 8-3 16-Bit Timer/Event Counter Square-Wave Output Ranges . 130 8-4 16-Bit Timer/Event Counter Configuration . 131 8-5 INTP0/TI00 INTP0/TI00 Pin Valid Edge and CR00 Capture Trigger Valid Edge . 134 8-6 16-Bit Timer/Event Counter Interval Times . 146 8-7 16-Bit Timer/Event Count Square-Wave Output Ranges . 160 9-1 8-Bit Timer/Event Counters 1 and 2 Interval Times . 170 9-2 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges . 171 9-3 Interval Times when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters . 9-4 172 Square-Wave Output Ranges when 8-Bit Timer/Event Counters 1 and 2 are Used as 16-Bit Timer/Event Counters . 173 9-5 8-Bit Timer/Event Counters 1 and 2 Configurations . 174 9-6 8-Bit Timer/Event Counter 1 Interval Time . 184 9-7 8-Bit Timer/Event Counter 2 Interval Time . 185 9-8 8-Bit Timer/Event Counters 1 and 2 Square-Wave Output Ranges . 187 9-9 Interval Times when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter . 9-10 189 Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Timer/Event Counter . ­ xvii ­ 191 LIST OF TABLES (2/3) Table No. Title Page 10-1 Interval Timer Interval Time . 195 10-2 Watch Timer Configuration . 196 10-3 Interval Timer Interval Time . 200 11-1 Watchdog Timer Inadvertent Program Overrun Detection Times . 201 11-2 Interval Times . 202 11-3 Watchdog Timer Configuration . 203 11-4 Watchdog Timer Overrun Detection Time . 207 11-5 Interval Timer Interval Time . 208 12-1 Clock Output Control Circuit Configuration . 210 13-1 Buzzer Output Control Circuit Configuration . 215 14-1 A/D Converter Configuration . 219 15-1 Differences between Channels 0 and 2 . 235 15-2 Serial Interface Channel 0 Configuration . 238 15-3 Various Signals in SBI Mode . 271 16-1 Differences between Channels 0 and 2 . 289 16-2 Serial Interface Channel 0 Configuration . 292 16-3 Serial Interface Channel 0 Interrupt Request Signal Generation . 295 16-4 Signals in I2C Bus Mode . 322 17-1 Serial Interface Channel 2 Configuration . 338 17-2 Serial Interface Channel 2 Operating Mode Settings . 344 17-3 Relation between Main System Clock and Baud Rate . 348 17-4 Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) . 349 17-5 Relation between Main System Clock and Baud Rate . 357 17-6 Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H) . 358 17-7 Receive Error Causes . 363 18-1 Maximum Number of Display Pixels . 371 18-2 LCD Controller/Driver Configuration . 372 18-3 Frame Frequencies (Hz) . 375 18-4 COM Signals . 379 18-5 LCD Drive Voltages . 380 18-6 LCD Drive Voltages (with On-Chip Split Resistor) . 383 18-7 Selection and Non-Selection Voltages (COM0) . 387 18-8 Selection and Non-Selection Voltages (COM0, COM1) . 390 18-9 Selection and Non-Selection Voltages (COM0 to COM2) . 393 18-10 Selection and Non-Selection Voltages (COM0 to COM3) . 397 ­ xviii ­ LIST OF TABLES (3/3) Table No. 19-1 Title Interrupt Source List .