NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
78K/0 PD78054 PD78064 PD78078 PD78083 PD780018 PD780058 PD780308 PD78058F - Datasheet Archive
78K/0 Series 8-bit Single-chip Microcontroller Basic (III) µPD78054 subseries µPD78064 subseries µPD78078
Application Note 78K/0 78K/0 Series 8-bit Single-chip Microcontroller Basic (III) µPD78054 PD78054 subseries µPD78064 PD78064 subseries µPD78078 PD78078 subseries µPD78083 PD78083 subseries µPD780018 PD780018 subseries µPD780058 PD780058 subseries µPD780308 PD780308 subseries µPD78058F PD78058F subseries µPD78064B PD78064B subseries µPD78075B PD78075B subseries µPD78098B PD78098B subseries Document No. U10182EJ2V0AN00 U10182EJ2V0AN00 (2nd edition) Date Published October 1997 N © Printed in Japan 1995 µPD78054Y PD78054Y subseries µPD78064Y PD78064Y subseries µPD78078Y PD78078Y subseries µPD78098 PD78098 subseries µPD780018Y PD780018Y subseries µPD780058Y PD780058Y subseries µPD780308Y PD780308Y subseries µPD78058FY PD78058FY subseries µPD78070A PD78070A, 78070AY 78070AY µPD78075BY PD78075BY subseries [MEMO] NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. FIP, EEPROM, and IEBus are trademarks of NEC Corporation. Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The application circuits and their parameters are for reference only and are not intended for use in actual design-ins. The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product. M7 96.5 Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: · Device availability · Ordering information · Product release schedule · Availability of related technical literature · Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) · Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics Inc. (U.S.) NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288 Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580 Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 NEC Electronics (Germany) GmbH Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490 NEC Electronics Hong Kong Ltd. Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 NEC Electronics (France) S.A. NEC Electronics Singapore Pte. Ltd. Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860 United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583 NEC Electronics (France) S.A. NEC Electronics (UK) Ltd. Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Italiana s.r.1. Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Taiwan Ltd. NEC Electronics (Germany) GmbH Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951 NEC do Brasil S.A. Sao Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689 J96. 8 Major Revisions in This Edition Page Throughout Description Addition of following products as target products: µPD780018 PD780018, 780018Y 780018Y, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY, 78098B 78098B subseries, µPD78070A PD78070A, 78070AY 78070AY µPD78052 PD78052(A), 78053(A), 78054(A) µPD78062 PD78062(A), 78063(A), 78064(A) µPD78081 PD78081(A), 78082(A), 78P083 78P083(A), 78081(A2) µPD78058F PD78058F(A), 78058FY 78058FY(A) µPD78064B PD78064B(A) Deletion of following products as target products: µPD78P054Y PD78P054Y, 78P064Y 78P064Y, 78074, 78075, 78075, 78074Y 78074Y, 78075Y 78075Y p.100 Addition of Note 2 and Caution 2 to Figure 4-5 Format of Watchdog Timer Mode Register p.113 Addition of Caution to Figure 5-8 Format of External Interrupt Mode Register 0 p.196 Addition of Table 8-2 Items Supported by Each Subseries p.197 Addition of Table 8-3 Registers of Serial Interface p.204, p206 Addition of note on using wake-up function and note on changing operation mode to Figures 8-7 and 8-8 Format of Serial Operating Mode Register 0 p.218, p.224 Addition of Caution to Figures 8-16 and 8-17 Format of Automatic Data Transfer/Reception Interval Specification Register p.239 Addition of Figures 8-23 and 8-24 Format of Serial Interface Pin Select Register p.240 µPD6252 PD6252 as maintenance product in 8.1 Interface with EEPROMTM (µPD6252 PD6252) p.250 Addition of (5) Limitations when using I2C bus mode to 8.1.2 Communication in I2C bus mode p.286 Addition of (f) Limitations when using UART mode to 8.5 Interface in Asynchronous Serial Interface (UART) Mode p.347 Addition of Figure 11-3 Format of Port Mode Register 12 p.216, p.217 Description of following register formats and tables for each subseries: p.229-p.232 Figures 8-14 and 8-15 Format of Automatic Data Transmission/Reception Control Register p.352, p.353 Tables 8-4, 8-5, and 8-6 Setting of Operation Modes of Serial Interface Channel 2 Figures 12-1 and 12-2 Format of LCD Display Mode Register p.387 Addition of APPENDIX B REVISION HISTORY The mark shows major revised points. INTRODUCTION Readers This Application Note is intended for use by engineers who understand the functions of the 78K/0 78K/0 series and wish to design application programs with the following subseries products: · Subseries µPD78054 PD78054 subseries : µPD78052 PD78052, 78053, 78054, 78P054 78P054, 78055, 78056, 78058, 78P058 78P058, 78052(A), 78053(A), 78054(A) µPD78054Y PD78054Y subseries : µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y, 78P058Y 78P058Y µPD78064 PD78064 subseries : µPD78062 PD78062, 78063, 78064, 78P064 78P064, 78062(A), 78063(A), 78064(A) µPD78064Y PD78064Y subseries : µPD78062Y PD78062Y, 78063Y 78063Y, 78064Y 78064Y µPD78078 PD78078 subseries µPD78076 PD78076, 78078, 78P078 78P078 : µPD78078Y PD78078Y subseries : µPD78076Y PD78076Y, 78078Y 78078Y, 78P078Y 78P078Y µPD78083 PD78083 subseries : µPD78081 PD78081, 78082, 78P083 78P083, 78081(A), 78082(A), µPD78098 PD78098 subseries : 78P83 78P83(A), 78081(A2) µPD78094 PD78094, 78095, 78096, 78098ANote 1, 78P098ANote 1 µPD780018 PD780018 subseries : µPD780016Note 2, 780018Note 2, 78P0018Note 2 µPD780018Y PD780018Y subseries : µPD780016YNote 2, 780018YNote 2, 78P0018YNote 2 µPD780058 PD780058 subseries : µPD780053Note 1, 780054Note 1, 780055Note 1, 780056Note 1, 780058Note 1, 78F0058Note 1 µPD780058Y PD780058Y subseries : µPD780053YNote 2, 780054YNote 2, 780055YNote 2, 780056YNote 2, 780058YNote 2, 78F0058YNote 2 µPD780308 PD780308 subseries : µPD780306Note 1, 780308Note 1, 78P0308Note 1 µPD780308Y PD780308Y subseries : µPD780306YNote 1, 780308YNote 1, 78P0308YNote 1 µPD78058F PD78058F subseries : µPD78056F PD78056F, 78058F 78058F, 78P058F 78P058F, 78058F 78058F(A) µPD78058FY PD78058FY subseries : µPD78056FY PD78056FY, 78058FY 78058FY, 78P058FY 78P058FY, 78P058FY 78P058FY(A) µPD78064B PD78064B subseries : µPD78064B PD78064B, 78P064B 78P064B, 78064B 78064B(A) µPD78070A PD78070A, 78070AY 78070AY µPD78075B PD78075B subseries : µPD78074B PD78074B, 78075B 78075B µPD78075BY PD78075BY subseries: µPD78074BYNote 1, 78075BYNote 1 µPD78098B PD78098B subseries : µPD78095BNote 2, 78096BNote 2, 78098BNote 2, 78P098BNote 2 Notes 1. Under development 2. Planned Remarks 1. The µPD78052 PD78052(A), 78053(A), and 78054(A) have higher reliability than the µPD78052 PD78052, 78053, and 78054. 2. The µPD78062 PD78062(A), 78063(A), and 78064(A) have higher reliability than the µPD78062 PD78062, 78063, and 78064. 3. The µPD78081 PD78081(A), 78082(A), 78P083 78P083(A), and 78081(A2) have higher reliability than the µPD78081 PD78081, 78082, and 78P083 78P083. 4. The µPD78058F PD78058F(A) and 78058FY 78058FY(A) have higher reliability than the µPD78058F PD78058F and 78058FY 78058FY. 5. The µPD78064B PD78064B(A) has higher reliability than the µPD78064B PD78064B. Purpose This Application Note is to deepen your understanding of the basic functions of the 78K/0 78K/0 series by using program examples. Note that the programs and hardware configuration shown in this document are only examples and not subject to mass production. Organization This Application Note consists of the following contents: · General · Software · Hardware In addition to this Application Note, the following Application Notes are also available: Document Name Document Number Japanese IEA-715 IEA-715 IEA-1288 IEA-1288 Targeted Subseries Contents English µPD78002 PD78002, 78002Y 78002Y Explains basic functions of Application Note µPD78014 PD78014, 78014Y 78014Y products in 78K/0 78K/0 series by Basic (I) µPD78018F PD78018F, 78018FY 78018FY using program examples 78K/0 78K/0 Series 78K/0 78K/0 Series U10121J U10121J U10121E U10121E µPD78044 PD78044 Application Note µPD78044H PD78044H Basic (II) µPD780208 PD780208 µPD780228 PD780228 78K/0 78K/0 Series This µPD78054 PD78054, 78054Y 78054Y document U10182J U10182J Application Note µPD78064 PD78064, 78064Y 78064Y µPD78078 PD78078, 78078Y 78078Y Basic (III) µPD78083 PD78083 µPD78098 PD78098 µPD780018 PD780018, 780018Y 780018Y µPD780058 PD780058, 780058Y 780058Y µPD780308 PD780308, 780308Y 780308Y µPD78058F PD78058F, 78058FY 78058FY µPD78064B PD78064B µPD78070A PD78070A, 78070AY 78070AY µPD78075B PD78075B, 78075BY 78075BY µPD78098B PD78098B 78K/0 78K/0 Series IEA-1289 IEA-1289 Application Note All subseries in 78K/0 78K/0 Explains floating-point operation series IEA-718 IEA-718 programs of products in 78K/0 78K/0 Floating-Point except µPD78002 PD78002 and Operation Program 78002Y 78002Y subseries µPD78014 PD78014 Series IEA-744 IEA-744 IEA-1301 IEA-1301 µPD78014 PD78014 series Explains how to organize Application Note only µPD78014 PD78014 and electronic pocketbook by using Electronic Pocketbook 78P014 78P014 µPD78014 PD78014 subseries Caution The application examples and program lists shown in this Application Note assume that the main system clock operates at 4.19 MHz, not at 5.0 MHz. How to Read This Manual Although this Application Note explains the functions of the 78K/0 78K/0 series products, the functions of some products in each subseries differ from those of the others. (1/2) Subseries µPD78054 PD78054 µPD78064 PD78064 µPD78078 PD78078 µPD78083 PD78083 Chapter µPD78054Y PD78054Y µPD78064Y PD78064Y µPD78078Y PD78078Y CHAPTER 1 GENERAL CHAPTER 2 FUNDAMENTALS OF SOFTWARE CHAPTER 3 APPLICATIONS OF SYSTEM CLOCK SELECTION CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER CHAPTER 5 APPLICATIONS OF 16-BIT 16-BIT TIMER/EVENT COUNTER CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER CHAPTER 7 APPLICATIONS OF WATCH TIMER CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE CHAPTER 9 APPLICATIONS OF A/D CONVERTER CHAPTER 10 APPLICATIONS OF D/A CONVERTER CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER CHAPTER 13 APPLICATIONS OF KEY INPUT µPD78098 PD78098 µPD780018 PD780018 µPD780058 PD780058 µPD780018Y PD780018Y µPD780058Y PD780058Y (2/2) Subseries µPD780308 PD780308 µPD78058F PD78058F Chapter µPD780308Y PD780308Y µPD78058FY PD78058FY CHAPTER 1 GENERAL CHAPTER 2 FUNDAMENTALS OF SOFTWARE CHAPTER 3 APPLICATIONS OF SYSTEM CLOCK SELECTION CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER CHAPTER 5 APPLICATIONS OF 16-BIT 16-BIT TIMER/EVENT COUNTER CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER CHAPTER 7 APPLICATIONS OF WATCH TIMER CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE CHAPTER 9 APPLICATIONS OF A/D CONVERTER CHAPTER 10 APPLICATIONS OF D/A CONVERTER CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER CHAPTER 13 APPLICATIONS OF KEY INPUT µPD78064B PD78064B µPD78070A PD78070A µPD78075B PD78075B µPD78098B PD78098B µPD78070AY PD78070AY µPD78075BY PD78075BY The (A)-model and standard models differ only in quality grade. The µPD78081 PD78081(A2) differs from standard models and (A)-models in terms of supply voltage and operating temperature range. For details, refer to the individual Data Sheet. In this document, read (A)-models and (A2)-model as follows: µPD78052 PD78052 µPD78052 PD78052(A) µPD78053 PD78053 µPD78053 PD78053(A) µPD78054 PD78054 µPD78054 PD78054(A) µPD78062 PD78062 µPD78062 PD78062(A) µPD78063 PD78063 µPD78063 PD78063(A) µPD78064 PD78064 µPD78064 PD78064(A) µPD78081 PD78081 µPD78081 PD78081(A) µPD78082 PD78082 µPD78082 PD78082(A) µPD78P083 PD78P083 µPD78P083 PD78P083(A) µPD78081 PD78081 µPD78081 PD78081(A2) µPD78058F PD78058F µPD78058F PD78058F(A) µPD78058FY PD78058FY µPD78058FY PD78058FY(A) µPD78064B PD78064B µPD78064B PD78064B(A) Legend Data significance : Left: higher digit, right: lower digit Low active : ××× (top bar over pin or signal name) Note : Description of Note in the text Caution : Important information Remark : Supplement Numeric representation : Binary . ×××× or ××××B Decimal . ×××× Hexadecimal . ××××H Quality Grade · Standard µPD78052 PD78052, 78053, 78054, 78055, 78056, 78058, 78P058 78P058 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y, 78P058Y 78P058Y µPD78062 PD78062, 78063, 78064, 78P064 78P064 µPD78062Y PD78062Y, 78063Y 78063Y, 78064Y 78064Y µPD78076 PD78076, 78078, 78P078 78P078 µPD78076Y PD78076Y, 78078Y 78078Y, 78P078Y 78P078Y µPD78081 PD78081, 78082, 78P083 78P083 µPD78094 PD78094, 78095, 78096, 78098A, 78P098A 78P098A µPD780016 PD780016, 780018, 78P0018 78P0018 µPD780016Y PD780016Y, 780018Y 780018Y, 78P0018Y 78P0018Y µPD780053 PD780053, 780054, 780055, 780056, 780058, 78F0058 78F0058 µPD780053Y PD780053Y, 780054Y 780054Y, 780055Y 780055Y, 780056Y 780056Y, 780058Y 780058Y, 78F0058Y 78F0058Y µPD780306 PD780306, 780308, 78P0308 78P0308 µPD780306Y PD780306Y, 780308Y 780308Y, 78P0308Y 78P0308Y µPD78056F PD78056F, 78058F 78058F, 78P058F 78P058F µPD78056FY PD78056FY, 78058FY 78058FY, 78P058FY 78P058FY µPD78064B PD78064B, 78P064B 78P064B µPD78070A PD78070A, 78070AY 78070AY µPD78074B PD78074B, 78075B 78075B µPD78074BY PD78074BY, 78075BY 78075BY µPD78095B PD78095B, 78096B 78096B, 78098B 78098B, 78P098B 78P098B · Special µPD78052 PD78052(A), 78053(A), 78054(A) µPD78062 PD78062(A), 78063(A), 78064(A) µPD78082 PD78082(A), 78083(A), 78P083 78P083(A), 78081(A2) µPD78058F PD78058F(A), 78058FY 78058FY(A) µPD78064B PD78064B(A) Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. · Consumer appliances Application Field Related documents Some of the related documents listed below are preliminary versions but not so specified here. · Common related documents Document Number Document Name Japanese English 78K/0 78K/0 Series Application Note - Basic (III) U10182J U10182J This document 78K/0 78K/0 Series Application Note - Floating-Point Operation Program IEA-718 IEA-718 IEA-1289 IEA-1289 78K/0 78K/0 Series User's Manual - Instruction U12326J U12326J U12326E U12326E 78K/0 78K/0 Series Instruction Set U10904J U10904J 78K/0 78K/0 Series Instruction Table U10903J U10903J · Documents dedicated to product (1) µPD78054 PD78054 subseries Document Number Document Name Japanese English µPD78052 PD78052, 78053, 78054, 78055, 78056, 78058 Data Sheet U12327J U12327J IC-3403 IC-3403 µPD78P054 PD78P054 Data Sheet U12346J U12346J U12346E U12346E µPD78P058 PD78P058 Data Sheet IC-8884 IC-8884 U10417E U10417E µPD78054 PD78054, µPD78054Y PD78054Y Subseries User's Manual U11747J U11747J U11747E U11747E µPD78054 PD78054 Subseries Special Function Register Table U10102J U10102J µPD78052 PD78052(A), 78053(A), 78054(A) Data Sheet U12171J U12171J U12171E U12171E (2) µPD78054Y PD78054Y subseries Document Number Document Name Japanese English µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78056Y 78056Y, 78058Y 78058Y Data Sheet U10906J U10906J U10906E U10906E µPD78P058Y PD78P058Y Data Sheet U10907J U10907J U10907E U10907E µPD78054 PD78054, 78054Y 78054Y Subseries User's Manual U11747J U11747J U11747E U11747E µPD78054Y PD78054Y Subseries Special Function Register Table U10087J U10087J (3) µPD78064 PD78064 subseries Document Number Document Name Japanese English µPD78062 PD78062, 78063, 78064 Data Sheet U12238J U12238J U12338E U12338E µPD78P064 PD78P064 Data Sheet U12589J U12589J U12589E U12589E µPD78062 PD78062(A), 78063(A), 78064(A) Data Sheet U10335J U10335J U10335E U10335E µPD78064 PD78064, 78064Y 78064Y Subseries User's Manual U10105J U10105J U10105E U10105E µPD78064 PD78064 Subseries Special Function Register Table IEM-5568 IEM-5568 (4) µPD78064Y PD78064Y subseries Document Number Document Name Japanese English µPD78062Y PD78062Y, 78063Y 78063Y, 78064Y 78064Y Data Sheet U10330J U10330J U10330E U10330E µPD78064 PD78064, 78064Y 78064Y Subseries User's Manual U10105J U10105J U10105E U10105E µPD78064Y PD78064Y Subseries Special Function Register Table IEM-5583 IEM-5583 (5) µPD78078 PD78078 subseries Document Number Document Name Japanese English µPD78076 PD78076, 78078 Data Sheet U10167J U10167J U10167E U10167E µPD78P078 PD78P078 Data Sheet U10168J U10168J U10168E U10168E µPD78078 PD78078 Subseries User's Manual U10641J U10641J U10641E U10641E µPD78078 PD78078 Subseries Special Function Register Table IEM-5607 IEM-5607 (6) µPD78078Y PD78078Y subseries Document Number Document Name Japanese English µPD78076Y PD78076Y, 78078Y 78078Y Data Sheet U10605J U10605J U10605E U10605E µPD78P078Y PD78P078Y Data Sheet U10606J U10606J U10606E U10606E µPD78078 PD78078, 78078Y 78078Y Subseries User's Manual U10641J U10641J U10641E U10641E µPD78078Y PD78078Y Subseries Special Function Register Table U10257J U10257J (7) µPD78083 PD78083 subseries Document Number Document Name Japanese English µPD78081 PD78081, 78082 Data Sheet U11415J U11415J U11415E U11415E µPD78P083 PD78P083 Data Sheet U11006J U11006J U11006E U11006E uPD78081 uPD78081(A), 78082(A) Data Sheet U12436J U12436J To be released soon uPD78P083 uPD78P083(A) Data Sheet U12175J U12175J U12175E U12175E µPD78083 PD78083 Subseries User's Manual U12176J U12176J U12176E U12176E µPD78083 PD78083 Subseries Special Function Register Table IEM-5599 IEM-5599 (8) µPD78098 PD78098 subseries Document Number Document Name Japanese English µPD78094 PD78094, 78095, 78096, 78098A Data Sheet U10146J U10146J U10146E U10146E µPD78P098A PD78P098A Data Sheet U10203J U10203J U10203E U10203E µPD78098 PD78098 Subseries User's Manual IEU-854 IEU-854 IEU-1381 IEU-1381 µPD78098 PD78098 Subseries Special Function Register List IEM-5591 IEM-5591 (9) µPD780018 PD780018 subseries Document Number Document Name Japanese English µPD780016 PD780016, 780018 Preliminary Product Information Plan to prepare Plan to prepare µPD78P0018 PD78P0018 Preliminary Product Information Plan to prepare Plan to prepare µPD780018 PD780018, 780018Y 780018Y Subseries User's Manual Plan to prepare Plan to prepare (10) µPD780018Y PD780018Y subseries Document Number Document Name Japanese English µPD780016Y PD780016Y, 780018Y 780018Y Preliminary Product Information U11810J U11810J U11810E U11810E µPD78P0018Y PD78P0018Y Preliminary Product Information Plan to prepare Plan to prepare µPD780018 PD780018, 780018Y 780018Y Subseries User's Manual Plan to prepare Plan to prepare (11) µPD780058 PD780058 subseries Document Number Document Name Japanese µPD780053 PD780053, 780054, 780055, 780056, 780058 English U12182J U12182J U12182E U12182E µPD78F0058 PD78F0058 Preliminary Product Information U12092J U12092J U12092E U12092E µPD780058 PD780058, 780058Y 780058Y Subseries User's Manual U12013J U12013J U12013E U12013E Preliminary Product Information (12) µPD780058 PD780058, 780058Y 780058Y subseries Document Number Document Name Japanese µPD780053Y PD780053Y, 780054Y 780054Y, 780055Y 780055Y, 780056Y 780056Y, 780058Y 780058Y English Plan to prepare Plan to prepare µPD78F0058Y PD78F0058Y Preliminary Product Information U12324J U12324J U12324E U12324E µPD780058 PD780058, 780058Y 780058Y Subseries User's Manual U12013J U12013J U12013E U12013E Preliminary Product Information (13) µPD780308 PD780308 subseries Document Number Document Name Japanese English µPD780306 PD780306, 780308 Data Sheet U11105J U11105J U11105E U11105E µPD78P0308 PD78P0308 Preliminary Product Information U11776J U11776J U11776E U11776E µPD780308 PD780308, 780308Y 780308Y Subseries User's Manual U11377J U11377J U11377E U11377E (14) µPD780308Y PD780308Y subseries Document Number Document Name Japanese English µPD780306Y PD780306Y, 780308Y 780308Y Data Sheet U12251J U12251J U12251E U12251E µPD78P0308Y PD78P0308Y Preliminary Product Information U11832J U11832J U11832E U11832E µPD780308 PD780308, 780308Y 780308Y Subseries User's Manual U11377J U11377J U11377E U11377E (15) µPD78058F PD78058F subseries Document Number Document Name Japanese English µPD78056F PD78056F, 78058F 78058F Data Sheet U11795J U11795J U11795E U11795E µPD78P058F PD78P058F Data Sheet U11796J U11796J U11796E U11796E µPD78058F PD78058F(A) Data Sheet To be released soon Plan to prepare µPD78058F PD78058F, 78058FY 78058FY Subseries User's Manual U12068J U12068J U12068E U12068E (16) µPD78058FY PD78058FY subseries Document Number Document Name Japanese English µPD78056FY PD78056FY, 78058FY 78058FY Data Sheet U12142J U12142J U12142E U12142E µPD78P058FY PD78P058FY Data Sheet U12076J U12076J U12076E U12076E µPD78058F PD78058F, 78058FY 78058FY Subseries User's Manual U12068J U12068J To be released soon (17) µPD78064B PD78064B subseries Document Number Document Name Japanese English µPD78064B PD78064B Data Sheet U11590J U11590J U11590E U11590E µPD78064B PD78064B(A) Data Sheet U11597J U11597J U11597E U11597E µPD78P064B PD78P064B Data Sheet U11598J U11598J U11598E U11598E µPD780308 PD780308, 780308Y 780308Y User's Manual U10785J U10785J U10785E U10785E (18) µPD78070A PD78070A, 78070AY 78070AY subseries Document Number Document Name Japanese English µPD78070A PD78070A Data Sheet U10326J U10326J U10326E U10326E µPD78070AY PD78070AY Data Sheet U10542J U10542J U10542E U10542E µPD78070A PD78070A, 78070AY 78070AY User's Manual IEU-907 IEU-907 U10200E U10200E µPD78070A PD78070A U10133J U10133J µPD78070AY PD78070AY U10134J U10134J (19) µPD78075B PD78075B subseries Document Number Document Name Japanese English µPD78074B PD78074B, 78075B 78075B Data Sheet U12017J U12017J U12017E U12017E µPD78075B PD78075B, 78075BY 78075BY Subseries User's Manual U12560J U12560J To be released soon (20) µPD78075BY PD78075BY subseries Document Number Document Name Japanese English µPD78074BY PD78074BY, 78075BY 78075BY Data Sheet Plan to prepare Plan to prepare µPD78075B PD78075B, 78075BY 78075BY Subseries User's Manual U12560J U12560J To be released soon (21) µPD78098B PD78098B subseries Document Number Document Name Japanese English µPD78095B PD78095B, 78096B 78096B, 78098B 78098B Data Sheet Plan to prepare Plan to prepare µPD78P098B PD78P098B Data Sheet Plan to prepare Plan to prepare µPD78098B PD78098B Subseries User's Manual To be released soon Plan to prepare The contents of the above related documents are subject to change without notice. Be sure to use the latest edition when you design your system. CONTENTS CHAPTER 1 GENERAL . 1.1 Product Development of 78K/0 78K/0 Series . 1.2 Features of 78K/0 78K/0 Series . 1 1 3 CHAPTER 2 FUNDAMENTALS OF SOFTWARE . 2.1 Data Transfer . 2.2 Data Comparison . 2.3 Decimal Addition . 2.4 Decimal Subtraction . 2.5 Binary-to-Decimal Conversion . 2.6 Bit Manipulation Instruction . 2.7 Binary Multiplication (16 bits × 16 bits) . 2.8 Binary Division (32 bits ÷ 16 bits) . 57 57 58 59 66 68 70 71 75 CHAPTER 3 APPLICATION OF SYSTEM CLOCK SELECTION . 3.1 Changing PCC Immediately after RESET . 3.2 Selecting Power ON/OFF . 79 89 91 CHAPTER 4 APPLICATIONS OF WATCHDOG TIMER . 4.1 Setting Watchdog Timer Mode . 4.2 Setting Interval Timer Mode . 95 101 103 CHAPTER 5 APPLICATIONS OF 16-BIT 16-BIT TIMER/EVENT COUNTER . 5.1 Setting of Interval Timer . 5.2 PWM Output . 5.3 Remote Controller Signal Reception . 105 116 118 121 5.3.1 Remote controller signal reception by counter clearing . 5.3.2 123 Remote controller signal reception by PWM output and free running mode . 137 One-Shot Pulse Output . PPG Output . 152 156 CHAPTER 6 APPLICATIONS OF 8-BIT TIMER/EVENT COUNTER . 6.1 Setting of Interval Timer . 163 171 5.4 5.5 6.1.1 Setting of 8-bit timers . 172 6.1.2 Setting of 16-bit timer . 173 Musical Scale Generation . 174 CHAPTER 7 APPLICATIONS OF WATCH TIMER . 7.1 Watch and LED Display Program . 181 187 CHAPTER 8 APPLICATIONS OF SERIAL INTERFACE . 8.1 Interface with EEPROMTM (µPD6252 PD6252) . 195 240 6.2 8.1.1 8.1.2 Communication in 2-wire serial I/O mode . Communication in I2 C bus mode . i 242 250 Interface with OSD LSI (µPD6451A PD6451A) . Interface in SBI Mode . 260 265 8.3.1 Application as master CPU . 267 8.3.2 8.2 8.3 Application as slave CPU . 276 Interface in 3-Wire Serial I/O Mode . 279 8.4.1 Application as master CPU . 280 8.4.2 Application as slave CPU . 283 Interface in Asynchronous Serial Interface (UART) Mode . 286 CHAPTER 9 APPLICATIONS OF A/D CONVERTER . 9.1 Level Meter . 9.2 Thermometer . 9.3 Analog Key Input . 9.4 4-Channel Input A/D Conversion . 299 307 316 326 332 CHAPTER 10 APPLICATIONS OF D/A CONVERTER . 10.1 SIN Wave Output . 337 338 CHAPTER 11 APPLICATION OF REAL-TIME OUTPUT PORT . 11.1 Stepping Motor . 345 348 CHAPTER 12 APPLICATIONS OF LCD CONTROLLER/DRIVER . 12.1 Static Display . 12.2 4-Time Division Display . 351 360 366 CHAPTER 13 APPLICATIONS OF KEY INPUT . 373 APPENDIX A DESCRIPTION OF SPD CHART . 379 APPENDIX B REVISION HISTORY . 387 8.4 8.5 ii LIST OF FIGURES (1/6) Fig. No. Title Page 1-1. Block Diagram of µPD78054 PD78054 Subseries . 4 1-2. Block Diagram of µPD78054Y PD78054Y Subseries . 7 1-3. Block Diagram of µPD78064 PD78064 Subseries . 10 1-4. Block Diagram of µPD78064Y PD78064Y Subseries . 12 1-5. Block Diagram of µPD78078 PD78078 Subseries . 14 1-6. Block Diagram of µPD78078Y PD78078Y Subseries . 16 1-7. Block Diagram of µPD78083 PD78083 Subseries . 18 1-8. Block Diagram of µPD78098 PD78098 Subseries . 20 1-9. Block Diagram of µPD780018 PD780018 Subseries . 23 1-10. Block Diagram of µPD780018Y PD780018Y Subseries . 26 1-11. Block Diagram of µPD780058 PD780058 Subseries . 29 1-12. Block Diagram of µPD780058Y PD780058Y Subseries . 32 1-13. Block Diagram of µPD780308 PD780308 Subseries . 35 1-14. Block Diagram of µPD780308Y PD780308Y Subseries . 37 1-15. Block Diagram of µPD78058F PD78058F Subseries . 39 1-16. Block Diagram of µPD78058FY PD78058FY Subseries . 42 1-17. Block Diagram of µPD78064B PD78064B Subseries . 45 1-18. Block Diagram of µPD78070A PD78070A . 47 1-19. Block Diagram of µPD78070AY PD78070AY . 49 1-20. Block Diagram of µPD78075B PD78075B Subseries . 51 1-21. Block Diagram of µPD78075BY PD78075BY Subseries . 53 1-22. Block Diagram of µPD78098B PD78098B Subseries . 55 2-1. Data Exchange . 57 2-2. Data Comparison . 58 2-3. Decimal Addition . 59 2-4. Decimal Subtraction . 66 2-5. Binary-to-Decimal Conversion . 68 2-6. Bit Operation . 70 2-7. Binary Multiplication . 71 2-8. Binary Division . 75 3-1. Format of Processor Clock Control Register (µPD78054 PD78054, 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY subseries, µPD78070A PD78070A,78070AY 78070AY) . 81 3-2. Format of Processor Clock Control Register (µPD78083 PD78083 subseries) . 82 3-3. Format of Processor Clock Control Register (µPD78098 PD78098, 78098B 78098B subseries) . 83 3-4. Format of Processor Clock Control Register (µPD780018 PD780018, 780018Y 780018Y subseries) . 84 3-5. Format of Oscillation Mode Select Register (µPD78054 PD78054, 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 78083, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY subseries, µPD78070A PD78070A, 78070AY 78070AY) . 3-6. 85 Format of Oscillation Mode Select Register (µPD78098 PD78098, 78098B 78098B subseries) . 85 iii LIST OF FIGURES (2/6) Fig. No. 3-7. Title Page Format of Oscillation Mode Select Register (µPD780018 PD780018, 780018Y 780018Y subseries) . 86 3-8. Format of Clock Select Register 1 (µPD78098 PD78098, 78098B 78098B subseries) . 86 3-9. Format of Clock Select Register 2 (µPD78098 PD78098, 78098B 78098B subseries) . 86 3-10. Example of Selecting CPU Clock after RESET (with µPD78054 PD78054 subseries) . 89 3-11. Example of System Clock Changing Circuit . 90 3-12. Example of Changing System Clock on Power Failure (µPD78054 PD78054 subseries) . 90 4-1. Format of Timer Clock Select Register 2 (µPD78054 PD78054 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY subseries, µPD78070A PD78070A, 78070AY 78070AY) . 96 4-2. Format of Timer Clock Select Register 2 (µPD78083 PD78083 subseries) . 97 4-3. Format of Timer Clock Select Register 2 (µPD78098 PD78098, 78098B 78098B subseries) . 98 4-4. Format of Timer Clock Select Register 2 (µPD780018 PD780018, 780018Y 780018Y subseries) . 99 4-5. Format of Watchdog Timer Mode Register . 100 4-6. Count Timing of Watchdog Timer . 103 5-1. Format of Timer Clock Select Register 0 (µPD78054 PD78054, 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY subseries, µPD78070A PD78070A, 78070AY 78070AY) . 106 5-2. Format of Timer Clock Select Register 0 (µPD78098 PD78098, 78098B 78098B subseries) . 108 5-3. Format of Timer Clock Select Register 0 (µPD780018 PD780018, 780018Y 780018Y subseries) . 109 5-4. Format of 16-Bit Timer Mode Control Register . 110 5-5. Format of Capture/Compare Control Register . 111 5-6. Format of 16-Bit Timer Output Control Register . 112 5-7. Format of Port Mode Register 3 . 113 5-8. Format of External Interrupt Mode Register 0 . 113 5-9. Format of Sampling Clock Select Register (µPD78054 PD78054, 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY subseries, µPD78070A PD78070A, 78070AY 78070AY) . 114 5-10. Format of Sampling Clock Select Register (µPD78098 PD78098, 78098B 78098B subseries) . 115 5-11. Format of Sampling Clock Select Register (µPD780018 PD780018, 780018Y 780018Y subseries) . 115 5-12. Example of Remote Controller Signal Receiver Circuit . 121 5-13. Remote Controller Signal Transmitter IC Output Signal . 122 5-14. Output Signal of Receiver Preamplifier . 122 5-15. Sampling of Remote Controller Signal . 123 5-16. Timing of One-Shot Pulse Output Operation by Software Trigger . 153 5-17. PPG Output Waveform Changing Timing . 156 6-1. Format of Timer Clock Select Register 1 (µPD78054 PD78054, 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY subseries, µPD78070A PD78070A, 78070AY 78070AY) . 6-2. 164 Format of Timer Clock Select Register 1 (µPD78098 PD78098, 78098B 78098B subseries) . 166 iv LIST OF FIGURES (3/6) Fig. No. Title Page 6-3. Format of Timer Clock Select Register 1 (µPD780018 PD780018, 780018Y 780018Y subseries) . 167 6-4. Format of 8-Bit Timer Mode Control Register . 168 6-5. Format of 8-Bit Timer Output Control Register . 169 6-6. Format of Port Mode Register 3 . 170 6-7. Count timing of 8-Bit Timers . 171 6-8. Musical Scale Generation Circuit . 174 6-9. Timer Output and Interval . 174 7-1. Format of Timer Clock Select Register 2 (µPD78054 PD78054, 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY subseries, µPD78070A PD78070A, 78070AY 78070AY) . 182 7-2. Format of Timer Clock Select Register 2 (µPD78098 PD78098, 78098B 78098B subseries) . 183 7-3. Format of Timer Clock Select Register 2 (µPD780018 PD780018, 780018Y 780018Y subseries) . 184 7-4. Format of Watch Timer Mode Control Register (µPD78054 PD78054, 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 780018, 780018Y 780018Y, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY subseries, µPD78070A PD78070A, 78070AY 78070AY) . 185 7-5. Format of Watch Timer Mode Control Register (µPD78098 PD78098, 78098B 78098B subseries) . 186 7-6. Concept of Watch Data . 187 7-7. LED Display Timing . 188 7-8. Circuit Example of Watch Timer . 188 8-1. Format of Timer Clock Select Register 3 (µPD78054 PD78054, 78078, 780058, 78058F 78058F, 78075B 78075B subseries, µPD78070A PD78070A) . 8-2. 198 Format of Timer Clock Select Register 3 (µPD78054Y PD78054Y, 78078Y 78078Y, 780058Y 780058Y, 78058FY 78058FY, 78075BY 78075BY subseries, µPD78070AY PD78070AY) . 199 8-3. Format of Timer Clock Select Register 3 (µPD78064 PD78064, 780308, 78064B 78064B subseries) . 200 8-4. Format of Timer Clock Select Register 3 (µPD78064Y PD78064Y, 780308Y 780308Y subseries) . 201 8-5. Format of Timer Clock Select Register 3 (µPD78098 PD78098, 78098B 78098B subseries) . 202 8-6. Format of Timer Clock Select Register 3 (µPD780018 PD780018, 780018Y 780018Y subseries) . 203 8-7. Format of Serial Operating Mode Register 0 (µPD78054 PD78054, 78064, 78078, 78098, 780058, 780308, 78058F 78058F, 78064B 78064B, 78075B 78075B, 78098B 78098B subseries, µPD78070A PD78070A) . 8-8. 204 Format of Serial Operating Mode Register 0 (µPD78054Y PD78054Y, 78064Y 78064Y, 78078Y 78078Y, 780058Y 780058Y, 780308, 78058FY 78058FY, 78075BY 78075BY subseries, µPD78070AY PD78070AY) . 8-9. 206 Format of Serial Bus Interface Control Register (µPD78054 PD78054, 78064, 78078, 78098, 780058, 780308, 78058F 78058F, 78064B 78064B, 78075B 78075B, 78098B 78098B subseries, µPD78070A PD78070A) . 8-10. 208 Format of Serial Bus Interface Control Register (µPD78054Y PD78054Y, 78064Y 78064Y, 78078Y 78078Y, 780058Y 780058Y, 780308Y 780308Y, 78058FY 78058FY, 78075BY 78075BY subseries, µPD78070AY PD78070AY) . v 210 LIST OF FIGURES (4/6) Fig. No. 8-11. Title Page Format of Interrupt Timing Specification Register (µPD78054 PD78054, 78064, 78078, 78098, 780058, 780308, 78058F 78058F, 78064B 78064B, 78075B 78075B, 78098B 78098B subseries, µPD78070A PD78070A) . 8-12. 212 Format of Interrupt Timing Specification Register (µPD78054Y PD78054Y, 78064Y 78064Y, 78078Y 78078Y, 780058Y 780058Y, 78008Y 78008Y, 78058FY 78058FY, 78075BY 78075BY subseries, µPD78070AY PD78070AY) . 8-13. 213 Format of Serial Operating Mode Register 1 (µPD78054 PD78054, 78054Y 78054Y, 78078, 78078Y 78078Y, 78098, 780018, 780018Y 780018Y, 780058, 780058Y 780058Y, 78058F 78058F, 78058FY 78058FY, 78075B 78075B, 78075BY 78075BY, 78098B 78098B subseries, µPD78070A PD78070A, 78070AY 78070AY) . 8-14. 215 Format of Automatic Data Transfer/Reception Control Register (µPD78054 PD78054, 78054Y 78054Y, 78078, 78078Y 78078Y, 78098, 780018, 780018Y 780018Y, 78058F 78058F, 78058FY 78058FY, 78075B 78075B, 78075BY 78075BY, 78098B 78098B subseries, µPD78070A PD78070A, 78070AY 78070AY) . 8-15. Format of Automatic Data Transfer/Reception Control Register (µPD780058 PD780058, 780058Y 780058Y subseries) . 8-16. 216 217 Format of Automatic Data Transfer/Reception Interval Specification Register (µPD78054 PD78054, 78054Y 78054Y, 78078, 78078Y 78078Y, 780018, 780018Y 780018Y, 780058, 780058Y 780058Y, 78058F 78058F, 78058FY 78058FY, 78075B 78075B, 78075BY 78075BY subseries, µPD78070A PD78070A, 78070AY 78070AY) . 8-17. (µPD78098 PD78098, 78098B 78098B subseries) . 8-18. 218 Format of Automatic Data Transfer/Reception Interval Specification Register 224 Format of Serial Operating Mode Register 2 (µPD78054 PD78054, 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 78083, 78098, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY, 78098B 78098B subseries, µPD78070A PD78070A, 78070AY 78070AY) . 8-19. 227 Format of Asynchronous Serial Interface Mode Register (µPD78054 PD78054, 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 78083, 78098, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY, 78098B 78098B subseries, µPD78070A PD78070A, 78070AY 78070AY) . 8-20. 228 Format of Asynchronous Serial Interface Status Register (µPD78054 PD78054, 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 78083, 78098, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY, 78098B 78098B subseries, µPD78070A PD78070A, 78070AY 78070AY) . 8-21. 234 Format of Baud Rate Generator Control Register (µPD78054 PD78054, 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 78083, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY subseries, µPD78070A PD78070A, 78070AY 78070AY) . 235 Format of Baud Rate Generator Control Register (µPD78098 PD78098, 78098B 78098B subseries) . 237 8-23. Format of Serial Interface Pin Select Register (µPD780058 PD780058 and 780058Y 780058Y Subseries) . 239 8-24. Format of Serial Interface Pin Select Register 8-22. (µPD780308 PD780308 and 780308Y 780308Y Subseries) . 239 8-25. Pin Configuration of µPD6252 PD6252 . 240 8-26. Example of Connection of µPD6252 PD6252 . 242 8-27. Communication Format of µPD6252 PD6252 . 243 8-28. Example of Connection between µPD6252 PD6252 and 250 I2C vi Bus Mode . LIST OF FIGURES (5/6) Fig. No. Title Page 8-29. µPD6252 PD6252 Operation Timing . 251 8-30. Example of Connecting µPD6451A PD6451A . 260 8-31. Communication Format of µPD6451A PD6451A . 260 8-32. Example of Connection in SBI Mode . 265 8-33. Communication Format in SBI Mode . 266 8-34. ACK Signal in Case of Time out . 267 8-35. Testing Bus Line . 267 8-36. Example of Connection in 3-Wire Serial I/O Mode . 279 8-37. Communication Format in 3-Wire Serial I/O Mode . 279 8-38. Output of Busy Signal . 283 8-39. Communication Block Diagram . 288 8-40. Communication Format . 289 8-41. Reception Format . 289 8-42. Timing of Reception Completion Interrupt (when ISRM = 1) . 295 8-43. Receive Buffer Register Reading Disabled Period . 296 9-1. Format of A/D Converter Mode Register (µPD78054 PD78054, 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 78083, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY subseries, µPD78070A PD78070A, 78070AY 78070AY) . 300 9-2. Format of A/D Converter Mode Register (µPD78098 PD78098, 78098B 78098B subseries) . 301 9-3. Format of A/D Converter Mode Register (µPD780018 PD780018, 780018Y 780018Y subseries) . 302 9-4. Format of A/D Converter Input Select Register . 303 9-5. Format of External Interrupt Mode Register 1 . (µPD78054 PD78054, 78054Y 78054Y, 78078, 78078Y 78078Y, 78098, 780018, 780018Y 780018Y, 78058F 78058F, 78058FY 78058FY, 78075B 78075B, 78075BY 78075BY, 78098B 78098B subseries, µPD78070A PD78070A, 78070AY 78070AY) . 9-6. 304 Format of External Interrupt Mode Register 1 (µPD78064 PD78064, 78064Y 78064Y, 780058, 780058Y 780058Y, 780308, 780308Y 780308Y, 78064B 78064B subseries) . 305 9-7. Format of External Interrupt Mode Register 1 (µPD78083 PD78083 subseries) . 306 9-8. Format of A/D Current Cut Select Register (µPD78098 PD78098, 78098B 78098B subseries) . 306 9-9. Example of Level Meter Circuit . 307 9-10. A/D Conversion Result and Display . 307 9-11. Concept of Peak Hold . 308 9-12. Circuit Example of Thermometer . 316 9-13. Temperature vs. Output Characteristic . 317 9-14. Example of Analog Key Input Circuit . 327 9-15. Timing Chart in 4-Channel Scan Mode . 332 10-1. Format of D/A Converter Mode Register . 337 10-2. Analog Output and Output Data Storage Timing . 338 10-3. D/A Output Waveform . 338 10-4. SIN Wave Conversion Circuit . 340 vii LIST OF FIGURES (6/6) Fig. No. Title Page 11-1. Format of Real-Time Output Port Mode Register . 346 11-2. Format of Real-Time Output Port Control Register . 346 11-3. Format of Port Mode Register 12 . 347 11-4. Phase Excitation Output Pattern and Output Timing . 348 12-1. Format of LCD Display Mode Register (µPD78064 PD78064, 78064Y 78064Y, 78064B 78064B subseries) . 352 12-2. Format of LCD Display Mode Register (µPD780308 PD780308, 780308Y 780308Y subseries) . 353 12-3. Format of LCD Display Control Register . 354 12-4. Relations between Contents of LCD Display Data Memory and Segment/Common Output . 356 12-5. Common Signal Waveform . 358 12-6. Phase Difference in Voltage between Command Signal and Segment Signal . 359 12-7. Display Pattern and Electrode Wiring of Static LCD . 360 12-8. Connection of Static LCD . 361 12-9. Example of Connecting LCD Driving Power in Static Display Mode (with external divider resistor, VDD = 5 V, and VLCD = 5 V) . 361 12-10. Example of Static LCD Driving Waveform . 362 12-11. Display Pattern of 4-Time Division LCD and Electrode Wiring . 366 12-12. Connections of 4-Time Division LCD Panel . 367 12-13. Example of Connecting LCD Drive Power in 4-Time Division Mode (with external divider resistor, VDD = 5 V, VLCD = 5 V) . 367 12-14. Example of 4-Time Division LCD Driving Waveform . 368 13-1. Key Matrix Circuit . 373 viii LIST OF TABLES (1/2) Table. No. Title Page 1-1. Functional Outline of µPD78054 PD78054 Subseries . 5 1-2. Functional Outline of µPD78054Y PD78054Y Subseries . 8 1-3. Functional Outline of µPD78064 PD78064 Subseries . 11 1-4. Functional Outline of µPD78064Y PD78064Y Subseries . 13 1-5. Functional Outline of µPD78078 PD78078 Subseries . 15 1-6. Functional Outline of µPD78078Y PD78078Y Subseries . 17 1-7. Functional Outline of µPD78083 PD78083 Subseries . 19 1-8. Functional Outline of µPD78098 PD78098 Subseries . 21 1-9. Functional Outline of µPD780018 PD780018 Subseries . 24 1-10. Functional Outline of µPD780018Y PD780018Y Subseries . 27 1-11. Functional Outline of µPD780058 PD780058 Subseries . 30 1-12. Functional Outline of µPD780058Y PD780058Y Subseries . 33 1-13. Functional Outline of µPD780308 PD780308 Subseries . 36 1-14. Functional Outline of µPD780308Y PD780308Y Subseries . 38 1-15. Functional Outline of µPD78058F PD78058F Subseries . 40 1-16. Functional Outline of µPD78058FY PD78058FY Subseries . 43 1-17. Functional Outline of µPD78064B PD78064B Subseries . 46 1-18. Functional Outline of µPD78070A PD78070A . 48 1-19. Functional Outline of µPD78070AY PD78070AY . 50 1-20. Functional Outline of µPD78075B8 PD78075B8 Subseries . 52 1-21. Functional Outline of µPD78075BY PD78075BY Subseries . 54 1-22. Functional Outline of µPD78098B PD78098B Subseries . 56 3-1. Maximum Time Required for Changing CPU Clock . 80 3-2. Relation between CPU Clock and Minimum Instruction Execution Time (other than µPD78098 PD78098 and 78098B 78098B subseries) . 87 3-3. CPU Clock (fCPU) List (µPD78098 PD78098 and 78098B 78098B Subseries) . 88 5-1. Valid Time of Input Signal . 123 5-2. Valid Time of Input Signal . 137 6-1. Musical Scale and Frequency . 17 8-1. Serial Interface Channel of Each Subseries . 195 8-2. Items Supported by Each Subseries . 196 8-3. Registers of Serial Interface . 197 8-4. Setting of Operation Modes of Serial Interface Channel 2 (µPD78054 PD78054, 78054Y 78054Y, 78064, 78064Y 78064Y, 78078, 78078Y 78078Y, 78083, 78098, 78058F 78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY, 78098B 78098B subseries, µPD78070A PD78070A, 78070AY 78070AY) . 8-5. 780058Y 780058Y Subseries) . 8-6. 229 Setting of Operation Modes of Serial Interface Channel 2 (µPD780058 PD780058 and 230 Setting of Operation Modes of Serial Interface Channel 2 (µPD780308 PD780308 and 780308Y 780308Y Subseries) . ix 232 LIST OF TABLES (2/2) Table. No. Title Page 8-7. Pin Function of µPD6252 PD6252 . 241 8-8. µPD6252 PD6252 Commands . 242 8-9. Signals in SBI Mode . 266 8-10. Relations between Main System Clock and Baud Rate (at fX = 4.19 MHz) . 287 9-1. A/D Conversion Value and Temperature . 318 9-2. Input Voltage and Key Code . 326 9-3. Resistances of R1 through R5 . 327 10-1. Voltage of SIN Wave Output and Preset Value . 339 11-1. Operation Mode and Output Trigger of Real-Time Output Port . 346 12-1. Maximum Number of Pixels for Display . 355 12-2. COM Signal . 357 12-3. Select and Unselect Voltages (COM0) . 360 12-4. Select and Unselect Voltages (COM0, 1, 2, 3) . 366 A-1. Comparison between SPD Symbols and Flowchart Symbol . 379 x CHAPTER 1 GENERAL 1.1 Product Development of 78K/0 78K/0 Series The following shows the products organized according to usage. The names in the parallelograms are subseries names. Products in mass production Products under development Y subseries products are compatible with I2C bus. Control 100-pin 100-pin 100-pin µ PD78075B PD78075B µ PD78078 PD78078 µ PD78070A PD78070A 100-pin 80-pin 80-pin µ PD780058 PD780058 µ PD78058F PD78058F µPD78075BY PD78075BY µPD78078Y PD78078Y µ PD78070AY PD78070AY µ PD780018AY PD780018AY µ PD780058YNote EMI-noise reduced version of the µ PD78078 PD78078 A timer was added to the µ PD78054 PD78054 and external interface was enhanced ROM-less version of the µPD78078 PD78078 Serial I/O of the µ PD78078Y PD78078Y was enhanced and the function is limited. Serial I/O of the µ PD78054 PD78054 was enhanced and EMI-noise was reduced. µ PD78058FY PD78058FY EMI-noise reduced version of the µ PD78054 PD78054 µ PD78054Y PD78054Y µPD780034Y PD780034Y µ PD780024Y PD780024Y UART and D/A converter were enhanced to the µ PD78014 PD78014 and I/O was enhanced 64-pin µPD78054 PD78054 µPD780034 PD780034 64-pin 64-pin µ PD780024 PD780024 µ PD78014H PD78014H 64-pin µ PD78014Y PD78014Y 64-pin µPD78018F PD78018F µPD78014 PD78014 µ PD780001 PD780001 An A/D converter and 16-bit timer were added to the µPD78002 PD78002 An A/D converter was added to the µPD78002 PD78002 64-pin µPD78002 PD78002 µ PD78002Y PD78002Y Basic subseries for control 42/44-pin µ PD78083 PD78083 64-pin µPD780964 PD780964 µPD780924 PD780924 80-pin 64-pin µPD78018FY PD78018FY A/D converter of the µ PD780024 PD780024 was enhanced Serial I/O of the µ PD78018F PD78018F was added and EMI-noise was reduced. EMI-noise reduced version of the µ PD78018F PD78018F Low-voltage (1.8 V) operation version of the µPD78014 PD78014, with larger selection of ROM and RAM capacities On-chip UART, capable of operating at low voltage (1.8 V) Inverter control 64-pin A/D converter of the µ PD780924 PD780924 was enhanced On-chip inverter control circuit and UART. EMI-noise was reduced. FIPTM drive µ PD780208 PD780208 µ PD780228 PD780228 The I/O and FIP C/D of the µ PD78044F PD78044F were enhanced, Display output total: 53 100-pin 80-pin µ PD78044H PD78044H An N-ch open drain I/O was added to the µ PD78044F PD78044F, Display output total: 34 80-pin µPD78044F PD78044F Basic subseries for driving FIP, Display output total: 34 100-pin 78K/0 78K/0 Series The I/O and FIP C/D of the µ PD78044H PD78044H were enhanced, Display output total: 48 LCD drive 100-pin µ PD780308 PD780308 µPD780308Y PD780308Y 100-pin µPD78064B PD78064B µPD78064 PD78064 The SIO of the µPD78064 PD78064 was enhanced, and ROM, RAM capacity increased EMI-noise reduced version of the µ PD78064 PD78064 µ PD78064Y PD78064Y Basic subseries for driving LCDs, On-chip UART 100-pin IEBusTM supported 80-pin µ PD78098B PD78098B EMI-noise reduced version of the µPD78098 PD78098 80-pin µ PD78098 PD78098 An IEBus controller was added to the µPD78054 PD78054 Meter control 80-pin µ PD780973 PD780973 On-chip automobile meter driving controller/driver LV 64-pin µ PD78P0914 PD78P0914 On-chip PWM output, LV digital code decoder, and Hsync counter Note Under planning 1 CHAPTER 1 GENERAL The following lists the main functional differences between subseries products. Function Subseries Name ROM Capacity µPD78075B PD78075B 32K-40K 32K-40K µPD78078 PD78078 Control Timer 8-bit 10-bit 8-bit 8-bit 16-bit Watch WDT A/D A/D D/A Serial Interface I/O VDD MIN. External Value Expansion 48K-60K 48K-60K µPD78070A PD78070A 4ch 1ch 1ch 1ch 8ch 2ch 3ch (UART: 1ch) µPD780058 PD780058 24K-60K 24K-60K µPD78058F PD78058F 48K-60K 48K-60K µPD78054 PD78054 8K-32K 8K-32K 2.7 V 68 1.8 V 69 2.7 V 16K-60K 16K-60K µPD780034 PD780034 1.8 V 61 88 2ch 2ch 3ch (time division UART: 1ch) 3ch (UART: 1ch) 2.0 V 8ch µPD78014H PD78014H µPD78018F PD78018F 8K µPD78002 PD78002 8K-16K 8K-16K 1.8 V 53 1.8 V 8K-32K 8K-32K µPD780001 PD780001 51 8K-60K 8K-60K µPD78014 PD78014 3ch (UART: 1ch, time division 3-wire: 1ch) 2ch µPD780024 PD780024 8ch 2.7 V 1ch 1ch µPD78083 PD78083 Inverter control µPD780964 PD780964 FIP drive µPD780208 PD780208 32K-60K 32K-60K 2ch 1ch µPD780228 PD780228 48K-60K 48K-60K 3ch µPD78044H PD78044H 32K-48K 32K-48K 2ch 1ch µPD78044F PD78044F 48K-60K 48K-60K µPD78064B PD78064B 1ch (UART: 1ch) 33 1.8 V 2ch (UART: 2ch) 47 2.7 V 2ch 74 2.7 V 1ch 72 4.5 V 68 2.7 V 57 2.0 V 69 2.7 V 32K µPD78064 PD78064 8ch 53 16K-40K 16K-40K µPD780308 PD780308 39 16K-32K 16K-32K LCD drive 8K-32K 8K-32K 3ch Note 8ch 8ch 1ch 1ch 8ch µPD780924 PD780924 IEBus µPD78098 PD78098 supported µPD78098B PD78098B µPD780973 PD780973 24K-32K 24K-32K LV µPD78P0914 PD78P0914 32K 1ch 2ch 2ch 1ch 1ch 1ch 8ch 3ch (time division UART: 1ch) 2ch (UART: 1ch) 32K-60K 32K-60K Meter control 1ch 40K-60K 40K-60K Note 10-bit timer: 1 channel 2 2ch 1ch 1ch 1ch 8ch 3ch 1ch 1ch 1ch 5ch 2ch (UART: 1ch) 56 4.5 V 2ch 54 4.5 V 6ch 1ch 8ch 2ch 3ch (UART: 1ch) CHAPTER 1 GENERAL 1.2 Features of 78K/0 78K/0 Series The 78K/0 78K/0 series is a collection of 8-bit single-chip microcontrollers ideal for commercial systems. The µPD78054 PD78054 and 78054Y 78054Y subseries are provided with peripheral hardware functions such as an A/D converter, D/A converter, timer, serial interface, real-time output port, and interrupt function. The µPD78064 PD78064 and 78064Y 78064Y subseries are provided with peripheral hardware functions such as an LCD controller/ driver, A/D converter, timer, serial interface, and interrupt function. The µPD78078 PD78078 and 78078Y 78078Y subseries are based on the µPD78054 PD78054 and 78054Y 78054Y subseries with a timer added and the external interface function reinforced. The µPD78083 PD78083 subseries is provided with peripheral hardware functions such as an A/D converter, timer, serial interface, and interrupt function. The µPD78098 PD78098 subseries is based on the µPD78054 PD78054 subseries with an IEBus controller added. The µPD780018 PD780018 and 780018Y 780018Y subseries are versions of the µPD78078 PD78078 and 78078Y 78078Y subseries (serial interface with time division transfer function) with an improved serial interface and a limited number of functions. The µPD780058 PD780058 and 780058Y 780058Y subseries are low-EMI noise versions of the µPD78054 PD78054 and 78054Y 78054Y subseries (serial interface with time division transfer function), with an improved serial interface. The µPD780308 PD780308 and 780308Y 780308Y subseries are versions of the µPD78064 PD78064 and 78064Y 78064Y subseries with increased ROM and RAM with an improved serial interface. The µPD78058F PD78058F, 78058FY 78058FY, 78064B 78064B, 78075B 78075B, 78075BY 78075BY, and 78098B 78098B subseries are low-EMI noise versions of the µPD78054 PD78054, 78054Y 78054Y, 78064, 78078, 78078Y 78078Y, and 78098 subseries. The µPD78070A PD78070A and 78070AY 78070AY subseries are the ROM-less versions of the µPD78078 PD78078 and 78078Y 78078Y subseries. The µPD78054Y PD78054Y, 78064Y 78064Y, 78078Y 78078Y, 780058Y 780058Y, 780308Y 780308Y, 78058FY 78058FY, 78075BY 78075BY subseries and µPD78070AY PD78070AY are provided with I2C bus control function instead of the SBI function of the µPD78054 PD78054, 78064, 78078, 780058, 780308, 78058F 78058F, 78075B 78075B subseries and µPD78070A PD78070A. In addition, one-time PROM, EPROM, or flash-memory models that can operate at the same operating voltage as the mask ROM models and that are ideal for early and small-scale production of the application system are also available. The block diagram and function outline of each series is shown on the following pages. 3 CHAPTER 1 GENERAL Figure 1-1. Block Diagram of µPD78054 PD78054 Subseries TO0/P30 TI00/INTP0/P00 TI00/INTP0/P00 TI01/INTP1/P01 TI01/INTP1/P01 16-bit TIMER/ EVENT COUNTER TO1/P31 TI1/P33 TI1/P33 8-bit TIMER/EVENT COUNTER 1 TO2/P32 TI2/P34 TI2/P34 8-bit TIMER/EVENT COUNTER 2 PORT0 P00 P01-P06 P01-P06 P07 PORT1 P10-P17 P10-P17 PORT2 P20-P27 P20-P27 PORT3 P30-P37 P30-P37 PORT4 P40-P47 P40-P47 PORT5 P50-P57 P50-P57 PORT6 P60-P67 P60-P67 PORT7 P70-P72 P70-P72 PORT12 PORT12 P120-P127 P120-P127 PORT13 PORT13 P130, P131 REAL-TIME OUTPUT PORT RTP0/P120RTP7/P127 RTP0/P120RTP7/P127 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SI0/SB0/P25 SO0/SB1/P26 SO0/SB1/P26 SCK0/P27 SCK0/P27 SERIAL INTERFACE 0 SI1/P20 SI1/P20 SO1/P21 SO1/P21 SCK1/P22 SCK1/P22 STB/P23 STB/P23 BUSY/P24 BUSY/P24 ROM SERIAL INTERFACE 1 SI2/RXD/P70 SI2/RXD/P70 SO2/TXD/P71 SO2/TXD/P71 SCK2/ASCK/P72 SCK2/ASCK/P72 78K/0 78K/0 CPU CORE SERIAL INTERFACE 2 RAM ANI0/P10ANI7/P17 ANI0/P10ANI7/P17 AVDD AVSS AVREF0 A/D CONVERTER ANO0/P130 ANO0/P130, ANO1/P131 ANO1/P131 AVSS AVREF1 D/A CONVERTER INTP0/P00INTP6/P06 INTP0/P00INTP6/P06 INTERRUPT CONTROL EXTERNAL ACCESS BUZ/P36 BUZ/P36 PCL/P35 PCL/P35 SYSTEM CONTROL RESET X1 X2 XT1/P07 XT1/P07 XT2 BUZZER OUTPUT CLOCK OUTPUT CONTROL AD0/P40AD7/P47 AD0/P40AD7/P47 A8/P50A15/P57 A8/P50A15/P57 RD/P64 RD/P64 WR/P65 WR/P65 WAIT/P66 WAIT/P66 ASTB/P67 ASTB/P67 VDD VSS IC (VPP) Remarks 1. The internal ROM and RAM capacities differ depending on the model. 2. ( ): µPD78P054 PD78P054, 78P058 78P058 4 CHAPTER 1 GENERAL Table 1-1. Functional Outline of µPD78054 PD78054 Subseries (1/2) Item µPD78052 PD78052 µPD78053 PD78053 µPD78054 PD78054 µPD78P054 PD78P054 Internal memory µPD78055 PD78055 µPD78056 PD78056 Note 1 Part Number ROM Mask ROM 16K bytes PROM 24K bytes High-speed RAM µPD78P058 PD78P058 Note 2 Mask ROM 40K bytes PROM 48K bytes 1024 bytesNote 3 1024 bytes 512 bytes 1024 bytes Buffer RAM 32K bytes 32K bytesNote 2 µPD78058 PD78058 60K bytes 60K bytesNote 3 1024 bytesNote 3 32 bytes 1024 bytes 1024 bytesNote 4 Expansion RAM None Memory space 64K bytes General-purpose register 8 bits × 8 × 4 banks Minimum 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0 MHz) With main instruction system clock execution With subsystem 122 µs (at 32.768 kHz) time clock Instruction set · · · · 16-bit operation Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. I/O port · · · · Total CMOS input CMOS I/O N-ch open-drain I/O A/D converter 8-bit resolution × 8 channels D/A converter 8-bit resolution × 2 channels Serial interface · 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel · 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel · 3-wire serial I/O/UART mode selectable : 1 channel Timer · · · · Timer output 3 (14-bit PWM output: 1) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) : : : : 69 2 63 4 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel Notes 1. The µPD78P054 PD78P054 is a PROM model of the µPD78052 PD78052, 78053, and 78054. 2. The µPD78P058 PD78P058 is a PROM model of the µPD78055 PD78055, 78056, and 78058. 3. The capacities of the internal PROM and internal high-speed RAM can be changed by using a memory size select register (IMS). 4. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS). 5 CHAPTER 1 GENERAL Table 1-1. Functional Outline of µPD78054 PD78054 Subseries (2/2) Item µPD78052 PD78052 µPD78053 PD78053 µPD78054 PD78054 µPD78P054 PD78P054 µPD78055 PD78055 µPD78056 PD78056 Note 1 Part Number Buzzer output Maskable Non-maskable Internal: 1 source Software Note 2 Internal: 13, external: 7 interrupt µPD78P058 PD78P058 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Vectored µPD78058 PD78058 1 Test input Internal: 1, external: 1 Supply voltage VDD = 2.0 to 6.0 V Package · 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm) · 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)Note 3 · 80-pin plastic TQFP (fine pitch) (12 × 12 mm) (µPD78052 PD78052, 78053, 78054, 78P054 78P054, 78058 only) · 80-pin ceramic WQFN (14 × 14 mm) (µPD78P054 PD78P054, 78P058 78P058 only) Notes 1. The µPD78P054 PD78P054 is a PROM model of the µPD78052 PD78052, 78053, and 78054. 2. The µPD78P058 PD78P058 is a PROM model of the µPD78055 PD78055, 78056, and 78058. 3. Under planning 6 CHAPTER 1 GENERAL Figure 1-2. Block Diagram of µPD78054Y PD78054Y Subseries TO0/P30 TI00/INTP0/P00 TI00/INTP0/P00 TI01/INTP1/P01 TI01/INTP1/P01 16-bit TIMER/ EVENT COUNTER TO1/P31 TI1/P33 TI1/P33 8-bit TIMER/EVENT COUNTER 1 TO2/P32 TI2/P34 TI2/P34 8-bit TIMER/EVENT COUNTER 2 PORT0 P00 P01-P06 P01-P06 P07 PORT1 P10-P17 P10-P17 PORT2 P20-P27 P20-P27 PORT3 P30-P37 P30-P37 PORT4 P40-P47 P40-P47 PORT5 P50-P57 P50-P57 PORT6 P60-P67 P60-P67 PORT7 P70-P72 P70-P72 PORT12 PORT12 P120-P127 P120-P127 PORT13 PORT13 P130, P131 REAL-TIME OUTPUT PORT RTP0/P120RTP7/P127 RTP0/P120RTP7/P127 WATCHDOG TIMER WATCH TIMER SI0/SB0/SDA0/P25 SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SCK0/SCL/P27 SERIAL INTERFACE 0 SI1/P20 SI1/P20 SO1/P21 SO1/P21 SCK1/P22 SCK1/P22 STB/P23 STB/P23 BUSY/P24 BUSY/P24 ROM SERIAL INTERFACE 1 SI2/RXD/P70 SI2/RXD/P70 SO2/TXD/P71 SO2/TXD/P71 SCK2/ASCK/P72 SCK2/ASCK/P72 78K/0 78K/0 CPU CORE SERIAL INTERFACE 2 ANI0/P10ANI7/P17 ANI0/P10ANI7/P17 AVDD AVSS AVREF0 RAM A/D CONVERTER ANO0/P130 ANO0/P130, ANO1/P131 ANO1/P131 AVSS AVREF1 D/A CONVERTER INTP0/P00INTP6/P06 INTP0/P00INTP6/P06 INTERRUPT CONTROL EXTERNAL ACCESS BUZ/P36 BUZ/P36 PCL/P35 PCL/P35 SYSTEM CONTROL RESET X1 X2 XT1/P07 XT1/P07 XT2 BUZZER OUTPUT CLOCK OUTPUT CONTROL AD0/P40AD7/P47 AD0/P40AD7/P47 A8/P50A15/P57 A8/P50A15/P57 RD/P64 RD/P64 WR/P65 WR/P65 WAIT/P66 WAIT/P66 ASTB/P67 ASTB/P67 VDD VSS IC (VPP) Remarks 1. The capacities of the internal ROM and RAM differ depending on the model. 2. ( ): µPD78P058Y PD78P058Y 7 CHAPTER 1 GENERAL Table 1-2. Functional Outline of µPD78054Y PD78054Y Subseries (1/2) Item Part Number Internal memory ROM µPD78052Y PD78052Y µPD78053Y PD78053Y µPD78054Y PD78054Y µPD78055Y PD78055Y µPD78056Y PD78056Y µPD78058Y PD78058Y µPD78P058Y PD78P058Y Mask ROM PROM 16K bytes 24K bytes High-speed RAM 512 bytes 1024 bytes Buffer RAM 32K bytes 40K bytes 48K bytes 60K bytes 60K bytesNote 1 1024 bytesNote 1 32 bytes Expansion RAM None 1024 bytes Memory space 64K bytes General-purpose register 8 bits × 8 × 4 banks Minimum 1024 bytesNote 2 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0 MHz) With main instruction system clock execution With subsystem 122 µs (at 32.768 kHz) time clock Instruction set · · · · 16-bit operation Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. I/O port · · · · Total CMOS input CMOS I/O N-ch open-drain I/O A/D converter 8-bit resolution × 8 channels D/A converter 8-bit resolution × 2 channels Serial interface · 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable : 1 channel · 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel · 3-wire serial I/O/UART mode selectable : 1 channel Timer · · · · Timer output 3 (14-bit PWM output: 1) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with : : : : 69 2 63 4 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Notes 1. The capacities of the internal PROM and internal high-speed RAM can be changed by using a memory size select register (IMS). 2. The internal expansion RAM capacity can be changed by using an internal expansion RAM size select register (IXS). 8 CHAPTER 1 GENERAL Table 1-2. Functional Outline of µPD78054Y PD78054Y Subseries (2/2) Item Part Number µPD78052Y PD78052Y µPD78053Y PD78053Y µPD78054Y PD78054Y µPD78055Y PD78055Y µPD78056Y PD78056Y µPD78058Y PD78058Y µPD78P058Y PD78P058Y Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Vectored Maskable Internal: 13, external: 7 interrupt Non-maskable Internal: 1 source Software 1 Test input Internal: 1, external: 1 Supply voltage VDD = 2.0 to 6.0 V Package · 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm) · 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm)Note · 80-pin ceramic WQFN (14 × 14 mm)(µPD78P058Y PD78P058Y only) Note Under planning 9 CHAPTER 1 GENERAL Figure 1-3. Block Diagram of µPD78064 PD78064 Subseries TO0/P30 TI00/INTP0/P00 TI00/INTP0/P00 TI01/INTP1/P01 TI01/INTP1/P01 16-bit TIMER/ EVENT COUNTER TO1/P31 TI1/P33 TI1/P33 8-bit TIMER/EVENT COUNTER 1 P10-P17 P10-P17 PORT2 P25-P27 P25-P27 PORT3 P30-P37 P30-P37 PORT7 P70-P72 P70-P72 PORT8 P80-P87 P80-P87 PORT9 P90-P97 P90-P97 PORT10 PORT10 P100-P103 P100-P103 PORT11 PORT11 8-bit TIMER/EVENT COUNTER 2 P00 P01-P05 P01-P05 P07 PORT1 TO2/P32 TI2/P34 TI2/P34 PORT0 P110-P117 P110-P117 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SI0/SB0/P25 SO0/SB1/P26 SO0/SB1/P26 SCK0/P27 SCK0/P27 ROM SERIAL INTERFACE 0 SI2/RXD/P70 SI2/RXD/P70 SO2/TXD/P71 SO2/TXD/P71 SCK2/ASCK/P72 SCK2/ASCK/P72 78K/0 78K/0 CPU CORE SERIAL INTERFACE 2 ANI0/P10ANI7/P17 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP0/P00INTP5/P05 INTP0/P00INTP5/P05 RAM S0-S23 S0-S23 S24/P97S31/P90 S24/P97S31/P90 A/D CONVERTER LCD CONTROLLER/ DRIVER INTERRUPT CONTROL S32/P87S39/P80 S32/P87S39/P80 COM0-COM3 VLC0-VLC2 BIAS fLCD BUZ/P36 BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL PCL/P35 PCL/P35 CLOCK OUTPUT CONTROL VDD VSS IC (VPP) Remarks 1. The internal ROM and RAM capacities differ depending on the model. 2. ( ): µPD78P064 PD78P064 10 RESET X1 X2 XT1/P07 XT1/P07 XT2 CHAPTER 1 GENERAL Table 1-3. Functional Outline of µPD78064 PD78064 Subseries Item µPD78062 PD78062 Part Number Internal memory ROM µPD78063 PD78063 µPD78064 PD78064 Mask ROM 16K bytes High-speed RAM 512 bytes µPD78P064 PD78P064 PROM 24K bytes 32K bytes 1024 bytes 32K bytesNote 1 1024 bytesNote 1 LCD display RAM 40 × 4 bits Memory space 64K bytes General-purpose register 8 bits × 8 × 4 banks Minimum 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0 MHz) With main instruction system clock execution With subsystem 122 µs (at 32.768 kHz) time clock · · · · Instruction set 16-bit operation Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. · Total : 57 I/O port (including pins multiplexed · CMOS input : 2 with segment signal output) · CMOS I/O : 55 A/D converter 8-bit resolution × 8 channels LCD controller/driver · Segment signal output : 40 max. · Common signal output : 4 max. · Bias : 1/2 or 1/3 bias selectable Serial interface · 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : 1 channel · 3-wire serial I/O/UART mode selectable : 1 channel Timer · · · · Timer output 3 (14-bit PWM output: 1) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Vectored Maskable Internal: 12, external: 6 interrupt Non-maskable Internal: 1 source Software 1 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : Test input VDD = 2.0 to 6.0 V Package · · · · channel channels channel channel Internal: 1, external: 1 Supply voltage 1 2 1 1 100-pin 100-pin 100-pin 100-pin plastic QFP (fine pitch) (14 × 14 mm, resin thickness 1.45 mm) plastic LQFP (fine pitch) (14 × 14 mm, resin thickness 1.4 mm) plastic QFP (14 × 20 mm) ceramic WQFN (14 × 20 mm)Note 2 (µPD78P064 PD78P064 only) Notes 1. The capacities of the internal PROM and internal high-speed RAM can be changed by using a memory size select register (IMS). 2. Under development 11 CHAPTER 1 GENERAL Figure 1-4. Block Diagram of µPD78064Y PD78064Y Subseries TO0/P30 TI00/INTP0/P00 TI00/INTP0/P00 TI01/INTP1/P01 TI01/INTP1/P01 16-bit TIMER/ EVENT COUNTER TO1/P31 TI1/P33 TI1/P33 8-bit TIMER/EVENT COUNTER 1 P10-P17 P10-P17 PORT2 P25-P27 P25-P27 PORT3 P30-P37 P30-P37 PORT7 P70-P72 P70-P72 PORT8 P80-P87 P80-P87 PORT9 P90-P97 P90-P97 PORT10 PORT10 P100-P103 P100-P103 PORT11 PORT11 8-bit TIMER/EVENT COUNTER 2 P00 P01-P05 P01-P05 P07 PORT1 TO2/P32 TI2/P34 TI2/P34 PORT0 P110-P117 P110-P117 WATCHDOG TIMER WATCH TIMER SI0/SB0/SDA0/P25 SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SO0/SB1/SDA1/P26 SCK0/SDL/P27 SCK0/SDL/P27 ROM SERIAL INTERFACE 0 SI2/RXD/P70 SI2/RXD/P70 SO2/TXD/P71 SO2/TXD/P71 SCK2/ASCK/P72 SCK2/ASCK/P72 78K/0 78K/0 CPU CORE SERIAL INTERFACE 2 ANI0/P10ANI7/P17 ANI0/P10ANI7/P17 AVDD AVSS AVREF INTP0/P00INTP5/P05 INTP0/P00INTP5/P05 RAM S0-S23 S0-S23 S24/P97S31/P90 S24/P97S31/P90 A/D CONVERTER LCD CONTROLLER/ DRIVER INTERRUPT CONTROL S32/P87S39/P80 S32/P87S39/P80 COM0-COM3 VLC0-VLC2 BIAS fLCD BUZ/P36 BUZ/P36 BUZZER OUTPUT SYSTEM CONTROL PCL/P35 PCL/P35 CLOCK OUTPUT CONTROL VDD VSS IC Remark The internal ROM and RAM capacities differ depending on the model. 12 RESET X1 X2 XT1/P07 XT1/P07 XT2 CHAPTER 1 GENERAL Table 1-4. Functional Outline of µPD78064Y PD78064Y Subseries Item µPD78062Y PD78062Y Part Number Internal memory ROM µPD78063Y PD78063Y µPD78064Y PD78064Y Mask ROM 16K bytes 24K bytes High-speed RAM 512 bytes 32K bytes 1024 bytes LCD display RAM 40 × 4 bits Memory space 64K bytes General-purpose register 8 bits × 8 × 4 banks Minimum 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0 MHz) With main instruction system clock execution With subsystem 122 µs (at 32.768 kHz) time clock Instruction set · · · · 16-bit operation Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. I/O port · Total : 57 (including pins multiplexed · CMOS input : 2 with segment signal output) · CMOS I/O : 55 A/D converter 8-bit resolution × 8 channels LCD controller/driver · Segment signal output : 40 max. · Common signal output : 4 max. · Bias : 1/2 or 1/3 bias selectable Serial interface · 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable : 1 channel · 3-wire serial I/O/UART mode selectable : 1 channel Timer · · · · Timer output 3 (14-bit PWM output: 1) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Vectored Maskable Internal: 12, external: 6 interrupt Non-maskable Internal: 1 source Software 1 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 2 1 1 channel channels channel channel Test input Internal: 1, external: 1 Supply voltage VDD = 2.0 to 6.0 V Package · 100-pin plastic QFP (fine pitch) (14 × 14 mm, resin thickness 1.45 mm) · 100-pin plastic LQFP (fine pitch) (14 × 14 mm, resin thickness 1.4 mm) · 100-pin plastic QFP (14 × 20 mm) 13 CHAPTER 1 GENERAL Figure 1-5. Block Diagram of µPD78078 PD78078 Subseries TO0/P30 TI00/INTP0/P00 TI00/INTP0/P00 TI01/INTP1/P01 TI01/INTP1/P01 16-bit TIMER/ EVENT COUNTER TO1/P31 TI1/P33 TI1/P33 8-bit TIMER/EVENT COUNTER 1 TO2/P32 TI2/P34 TI2/P34 8-bit TIMER/EVENT COUNTER 2 TI5/TO5/P100 TI5/TO5/P100 8-bit TIMER/EVENT COUNTER 5 TI6/TO6/P101 TI6/TO6/P101 8-bit TIMER/EVENT COUNTER 6 PORT1 SI1/P20 SI1/P20 SO1/P21 SO1/P21 SCK1/P22 SCK1/P22 STB/P23 STB/P23 BUSY/P24 BUSY/P24 SI2/RXD/P70 SI2/RXD/P70 SO2/TXD/P71 SO2/TXD/P71 SCK2/ASCK/P72 SCK2/ASCK/P72 ANI0/P10ANI7/P17 ANI0/P10ANI7/P17 AVDD AVSS AVREF0 PORT6 P60-P67 P60-P67 P70-P72 P70-P72 PORT8 P80-P87 P80-P87 P90-P96 P90-P96 PORT10 PORT10 P100-P103 P100-P103 PORT12 PORT12 P120-P127 P120-P127 PORT13 PORT13 P130, P131 REAL-TIME OUTPUT PORT SERIAL INTERFACE 1 P50-P57 P50-P57 PORT7 SERIAL INTERFACE 0 P40-P47 P40-P47 PORT9 SI0/SB0/P25 SI0/SB0/P25 SO0/SB1/P26 SO0/SB1/P26 SCK0/P27 SCK0/P27 P30-P37 P30-P37 PORT5 WATCH TIMER P20-P27 P20-P27 PORT4 ROM P10-P17 P10-P17 PORT3 78K/0 78K/0 CPU CORE P00 P01-P06 P01-P06 P07 PORT2 WATCHDOG TIMER PORT0 RTP0/P120RTP7/P127 RTP0/P120RTP7/P127 RAM SERIAL INTERFACE 2 A/D CONVERTER ANO0/P130 ANO0/P130, ANO1/P131 ANO1/P131 AVSS AVREF1 INTP0/P00INTP6/P06 INTP0/P00INTP6/P06 EXTERNAL ACCESS SYSTEM CONTROL D/A CONVERTER AD0/P40AD7/P47 AD0/P40AD7/P47 A0/P80A7/P87 A0/P80A7/P87 A8/P50A15/P57 A8/P50A15/P57 RD/P64 RD/P64 WR/P65 WR/P65 WAIT/P66 WAIT/P66 ASTB/P67 ASTB/P67 RESET X1 X2 XT1/P07 XT1/P07 XT2 INTERRUPT CONTROL BUZ/P36 BUZ/P36 BUZZER OUTPUT PCL/P35 PCL/P35 CLOCK OUTPUT CONTROL VDD VSS IC (VPP) Remarks 1. The internal ROM capacitiy differs depending on the model. 2. ( ): µPD78P078 PD78P078 14 CHAPTER 1 GENERAL Table 1-5. Functional Outline of µPD78078 PD78078 Subseries Item µPD78076 PD78076 Part Number Internal memory ROM µPD78078 PD78078 Mask ROM µPD78P078 PD78P078 PROM 48K bytes 60K bytes 60K bytesNote 1 High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM 1024 bytes Memory space 64K bytes General-purpose register 8 bits × 8 × 4 banks Minimum 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0 MHz) With main instruction system clock execution With subsystem 122 µs (at 32.768 kHz) timon clock Instruction set · · · · 16-bit operation Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. I/O port · · · · Total CMOS input CMOS I/O N-ch open-drain I/O A/D converter 8-bit resolution × 8 channels D/A converter 8-bit resolution × 2 channels Serial interface · 3-wire serial I/O/SBI/2-wire serial I/O mode selectable : : : : 88 2 78 8 : 1 channel · 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel · 3-wire serial I/O/UART mode selectable : 1 channel Timer · · · · 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : Timer output 5 (14-bit PWM output: 1, 8-bit PWM output: 2) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Vectored Maskable Internal: 15, external: 7 interrupt Non-maskable Internal: 1 source Software 1 Test input VDD = 1.8 to 5.5 V Package · · · · channel channels channel channel Internal: 1, external: 1 Supply voltage 1 4 1 1 100-pin 100-pin 100-pin 100-pin plastic QFP (fine pitch) (14 × 14 mm, resin thickness 1.45 mm) plastic LQFP (fine pitch) (14 × 14 mm, resin thickness 1.4 mm)Note 2 plastic QFP (14 × 20 mm, resin thickness 2.7 mm) ceramic WQFN (14 × 20 mm) (µPD78P078 PD78P078 only) Notes 1. The internal ROM capacity can be changed by using a memory size select register (IMS). 2. Under planning 15 CHAPTER 1 GENERAL Figure 1-6. Block Diagram of µPD78078Y PD78078Y Subseries TO0/P30 TI00/INTP0/P00 TI00/INTP0/P00 TI01/INTP1/P01 TI01/INTP1/P01 16-bit TIMER/ EVENT COUNTER TO1/P31 TI1/P33 TI1/P33 8-bit TIMER/EVENT COUNTER 1 TO2/P32 TI2/P34 TI2/P34 8-bit TIMER/EVENT COUNTER 2 TI5/TO5/P100 TI5/TO5/P100 8-bit TIMER/EVENT COUNTER 5 TI6/TO6/P101 TI6/TO6/P101 8-bit TIMER/EVENT COUNTER 6 PORT1 SI2/RXD/P70 SI2/RXD/P70 SO2/TXD/P71 SO2/TXD/P71 SCK2/ASCK/P72 SCK2/ASCK/P72 ANI0/P10ANI7/P17 ANI0/P10ANI7/P17 AVDD AVSS AVREF0 PORT10 PORT10 P100-P103 P100-P103 P120-P127 P120-P127 PORT13 PORT13 P130, P131 RTP0/P120RTP7/P127 RTP0/P120RTP7/P127 INTERRUPT CONTROL BUZ/P36 BUZ/P36 CLOCK OUTPUT CONTROL EXTERNAL ACCESS AD0/P40AD7/P47 AD0/P40AD7/P47 A0/P80A7/P87 A0/P80A7/P87 A8/P50A15/P57 A8/P50A15/P57 RD/P64 RD/P64 WR/P65 WR/P65 WAIT/P66 WAIT/P66 ASTB/P67 ASTB/P67 SYSTEM CONTROL RESET X1 X2 XT1/P07 XT1/P07 XT2 BUZZER OUTPUT PCL/P35 PCL/P35 VDD VSS IC (VPP) Remarks 1. The internal ROM capacity differs depending on the model. 2. ( ): µPD78P078Y PD78P078Y 16 P90-P96 P90-P96 RAM D/A CONVERTER INTP0/P00INTP6/P06 INTP0/P00INTP6/P06 P80-P87 P80-P87 A/D CONVERTER ANO0/P130 ANO0/P130, ANO1/P131 ANO1/P131 AVSS AVREF1 P70-P72 P70-P72 PORT8 SERIAL INTERFACE 2 P60-P67 P60-P67 REAL-TIME OUTPUT PORT SERIAL INTERFACE 1 PORT6 PORT12 PORT12 SI1/P20 SI1/P20 SO1/P21 SO1/P21 SCK1/P22 SCK1/P22 STB/P23 STB/P23 BUSY/P24 BUSY/P24 P50-P57 P50-P57 PORT7 SERIAL INTERFACE 0 P40-P47 P40-P47 PORT9 SI0/SB0/SDA0/P25 SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SCK0/SCL/P27 P30-P37 P30-P37 PORT5 WATCH TIMER P20-P27 P20-P27 PORT4 ROM P10-P17 P10-P17 PORT3 78K/0 78K/0 CPU CORE P00 P01-P06 P01-P06 P07 PORT2 WATCHDOG TIMER PORT0 CHAPTER 1 GENERAL Table 1-6. Functional Outline of µPD78078Y PD78078Y Subseries Item µPD78076Y PD78076Y Part Number Internal memory ROM µPD78078Y PD78078Y Mask ROM µPD78P078Y PD78P078Y PROM 48K bytes 60K bytes 60K bytesNote 1 High-speed RAM 1024 bytes Buffer RAM 32 bytes Expansion RAM 1024 bytes Memory space 64K bytes General-purpose register 8 bits × 8 × 4 banks Minimum 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (at 5.0 MHz) With main instruction system clock execution With subsystem 122 µs (at 32.768 kHz) time clock Instruction set · · · · 16-bit operation Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. I/O port · · · · Total CMOS input CMOS I/O N-ch open-drain I/O A/D converter 8-bit resolution × 8 channels D/A converter 8-bit resolution × 2 channels Serial interface · 3-wire serial I/O/2-wire serial I/O/I2C bus mode selectable : 1 channel · 3-wire serial I/O mode (with function to automatically transfer/receive up to 32 bytes) : 1 channel · 3-wire serial I/O/UART mode selectable : 1 channel Timer · · · · Timer output 5 (14-bit PWM output: 1, 8-bit PWM output: 2) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz), 32.768 kHz (with subsystem clock of 32.768 kHz) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Vectored Maskable Internal: 15, external: 7 interrupt Non-maskable Internal: 1 source Software 1 : : : : 88 2 78 8 16-bit timer/event counter : 8-bit timer/event counter : Watch timer : Watchdog timer : 1 4 1 1 channel channels channel channel Test input Internal: 1, external: 1 Supply voltage VDD = 1.8 to 5.5 V Package · 100-pin plastic QFP (14 × 20 mm, resin thickness 2.7 mm) · 100-pin plastic LQFP (fine pitch) (14 × 14 mm, resin thickness 1.4 mm)Note 2 · 100-pin ceramic WQFN (14 × 20 mm) (µPD78P078Y PD78P078Y only) Notes 1. The internal ROM capacity can be changed by using a memory size select register (IMS). 2. Under development 17 CHAPTER 1 GENERAL Figure 1-7. Block Diagram of µPD78083 PD78083 Subseries TI5/TO5/P100 TI5/TO5/P100 TI6/TO6/P101 TI6/TO6/P101 P00 8-bit TIMER/ EVENT COUNTER 5 5-bit TIMER/ EVENT COUNTER 6 ANI0/P10ANI7/P17 ANI0/P10ANI7/P17 AVDD AVSS AVREF1 INTP1/P01INTP3/P03 INTP1/P01INTP3/P03 P10-P17 P10-P17 P30-P37 P30-P37 PORT5 P50-P57 P50-P57 PORT7 P70-P72 P70-P72 PORT10 PORT10 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 SCK2/ASCK/P72 PORT1 78K/0 78K/0 CPU CORE P01-P03 P01-P03 PORT3 WATCHDOG TIMER PORT0 P100, P101 ROM SERIAL INTERFACE 2 A/D CONVERTER RAM INTERRUPT CONTROL BUZ/P36 BUZ/P36 BUZZER OUTPUT PCL/P35 PCL/P35 CLOCK OUTPUT CONTROL VDD VSS IC (VPP) SYSTEM CONTROL Remarks 1. The internal ROM and RAM capacities differ depending on the model. 2. ( ): µPD78P083 PD78P083 18 RESET X1 X2 CHAPTER 1 GENERAL Table 1-7. Functional Outline of µPD78083 PD78083 Subseries Item µPD78081 PD78081 Part Number Internal memory ROM µPD78082 PD78082 Mask ROM 8K bytes High-speed RAM 256 bytes µPD78P083 PD78P083 PROM 16K bytes 24K bytesNote 1 384 bytes 512 bytesNote 1 Memory space 64K bytes General-purpose register 8 bits × 8 × 4 banks Minimum instruction execution time 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (with main system clock of 5.0 MHz) Instruction set · · · · I/O port · Total : 33 · CMOS input : 1 · CMOS I/O : 32 A/D converter 8-bit resolution × 8 channels Serial interface 3-wire serial I/O/UART mode selectable: 1 channel Timer · 8-bit timer/event counter : 2 channels · Watchdog timer : 1 channel Timer output 2 (8-bit PWM output) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (with main system clock of 5.0 MHz) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (with main system clock of 5.0 MHz) Vectored Maskable Internal: 8, external: 3 interrupt Non-maskable Internal: 1 source Software 1 16-bit operation Multiplication/division (8 bits × 8 bits, 16 bits ÷ 8 bits) Bit manipulation (set, reset, test, Boolean operation) BCD adjustment, etc. Supply voltage VDD = 1.8 to 5.5 VNote 2 Package · 42-pin plastic shrink DIP (600 mil) · 42-pin ceramic shrink DIP (with window) (600 mil) (µPD78P083 PD78P083 only) · 44-pin plastic QFP (10 × 10 mm) Notes 1. The capacities of the internal PROM and internal-high-speed RAM can be changed by using a memory size select register. (IMS) 2. The supply voltage (VDD) of the µPD78081 PD78081(A2) is 4.5 to 5.5 V. 19 CHAPTER 1 GENERAL Figure 1-8. Block Diagram of µPD78098 PD78098 Subseries TO0/P30 TI00/INTP0/P00 TI00/INTP0/P00 TI01/INTP1/P0 TI01/INTP1/P0