PD78052Y 78053Y 78054Y 78055Y 78056Y 78058Y PD78052 78P058Y PD78054 U11747E - Datasheet Archive

 

MOS INTEGRATED CIRCUIT µPD78052Y, 78053Y, 78054Y, 78055Y, 78056Y, 78058Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The

 

DATA SHEET MOS INTEGRATED CIRCUIT µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, and 78058Y 78058Y versions add the I2C bus control function to the µPD78052 PD78052, 78053, 78054, 78055, 78056, and 78058, and are suitable for application in AV products. Various peripheral hardware such as 8-bit resolution D/A converter, timer, serial interface, real-time output port and interrupt functions are incorporated. The 78P058Y 78P058Y, a one-time PROM or EPROM version which can be operated in the same supply voltage as for the mask ROM version, and various development tools are also available. Detailed function descriptions, etc., are provided in the following User's Manual. Be sure to read it when designing. µPD78054 PD78054, 78054Y 78054Y Subseries User's Manual : U11747E U11747E 78K/0 78K/0 Series User's Manual Instructions : U12326E U12326E FEATURES · Internal high-capacity ROM and RAM · External memory expansion space : 64 Kbytes Item Program memory Part number (ROM) Data memory Internal High-Speed RAM Internal Buffer RAM Internal Expanded RAM 32 bytes No µPD78052Y PD78052Y 16 Kbytes 512 bytes µPD78053Y PD78053Y 24 Kbytes 1024 bytes µPD78054Y PD78054Y 32 Kbytes µPD78055Y PD78055Y 40 Kbytes µPD78056Y PD78056Y 48 Kbytes µPD78058Y PD78058Y 60 Kbytes 1024 bytes · Minimum instruction execution time can be varied from high-speed (0.4 µs) to ultra-low-speed (122 µs) · I/O ports : 69 (N-ch open-drain : 4) · 8-bit resolution A/D converter: 8 channels · 8-bit resolution D/A converter: 2 channels · Serial interface : 3 channels (I2C bus mode : 1 channel) · Timer : 5 channels · Supply voltage : VDD = 2.0 to 6.0 V APPLICATIONS Cellular phones, pagers, printers, AV equipment, airconditioners, cameras, PPC, fuzzy home applicances, vending machines, etc. The information in this document is subject to change without notice. Document No. U10906EJ2V0DS00 U10906EJ2V0DS00 (2nd edition) Date Published September 1997 N Printed in Japan The mark shows major revised points. © 1993 1996 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y ORDERING INFORMATION Part Number Package µPD78052YGC-xxx-8BT 80-pin plastic QFP (14 x 14 mm) µPD78053YGC-xxx-8BT 80-pin plastic QFP (14 x 14 mm) µPD78054YGC-xxx-8BT 80-pin plastic QFP (14 x 14 mm) µPD78055YGC-xxx-8BT 80-pin plastic QFP (14 x 14 mm) µPD78056YGC-xxx-8BT 80-pin plastic QFP (14 x 14 mm) µPD78058YGC-xxx-8BT 80-pin plastic QFP (14 x 14 mm) Remark 2 xxx indicates the ROM code suffix. µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 78K/0 78K/0 SERIES DEVELOPMENT The following shows the 78K/0 78K/0 Series products development. Subseries names are shown inside frames. Under mass production Under development Controller Y subseries provide I2C bus interface function µ PD78075B PD78075B µ PD78075BY PD78075BY EMI noise reduced version of the µ PD78078 PD78078 100-pin µ PD78078 PD78078 µ PD78078Y PD78078Y Added a timer and enhanced external interface to the µ PD78054 PD78054 Subseries 100-pin µ PD78070A PD78070A µ PD78070AY PD78070AY ROM-less versions of the µPD78078 PD78078 µPD780018AY PD780018AY Enhanced serial I/O of the µ PD78078Y PD78078Y with limited number of functions 100-pin 100-pin Note 80-pin µ PD780058 PD780058 µPD780058Y PD780058Y Enhanced serial I/O of the µPD78054 PD78054, EMI noise reduced version 80-pin µ PD78058F PD78058F µPD78058FY PD78058FY EMI noise reduced version of the µPD78054 PD78054 80-pin µ PD78054 PD78054 µ PD78054Y PD78054Y Added UART, and D/A to the µ PD78014 PD78014 and enhanced I/O ports 64-pin µPD780034 PD780034 µPD780034Y PD780034Y Enhanced A/D of the µ PD780024 PD780024 64-pin µ PD780024 PD780024 µ PD780024Y PD780024Y Enhanced serial I/O of the µ PD78018F PD78018F, EMI noise reduced version 64-pin µ PD78014H PD78014H EMI noise reduced version of the µPD78018F PD78018F 64-pin µ PD78018F PD78018F µ PD78018FY PD78018FY Low voltage (1.8 V) operation version of the µ PD78014 PD78014, enhanced ROM and RAM variation 64-pin µPD78014 PD78014 µPD78014Y PD78014Y 64-pin µPD780001 PD780001 64-pin µ PD78002 PD78002 42/44-pin µ PD78083 PD78083 Added an A/D and 16-bit timer/event to the µ PD78002 PD78002 Added A/D to the µPD78002 PD78002 µ PD78002Y PD78002Y Basic subseries for controller On-chip UART, operatable at a low-voltage (1.8 V) Inverter controller 64-pin µ PD780988 PD780988 Enhanced the inverter control, timer, and SIO of the µPD78064 PD78064. Expanded ROM and RAM. 64-pin µ PD780964 PD780964 Enhanced A/D of the µ PD780924 PD780924 64-pin µ PD780924 PD780924 On-chip inverter control circuit and UART, EMI noise reduced version FIP driver 100-pin µ PD780228 PD780228 µ PD78044H PD78044H 80-pin Enhanced I/O ports, FIP controller/driver of the µPD78044F PD78044F, Total display outputs: 53 Enhanced I/O ports, FIP controller/driver of the µ PD78044H PD78044H, Total display outputs: 48 Added an N-ch open-drain input/output to the µ PD78044F PD78044F, Total display outputs: 34 µ PD780208 PD780208 80-pin 78K/0 78K/0 Series 100-pin µ PD78044F PD78044F Basic subseries for FIP drive, Total display outputs: 34 LCD driver 100-pin µ PD780308 PD780308 100-pin µ PD78064 PD78064 Enhanced SIO to the µPD78064 PD78064 and expanded ROM and RAM EMI noise reduced version of the µPD78064 PD78064 µPD78064B PD78064B 100-pin µ PD780308Y PD780308Y µ PD78064Y PD78064Y Basic subseries for LCD driving, on-chip UART IEBus supported 80-pin µPD78098B PD78098B EMI noise reduced version of the µPD78098 PD78098 80-pin µ PD78098 PD78098 Added an IEBus controller to the µPD78054 PD78054 Meter controller 80-pin µ PD780973 PD780973 Automobile meter drive controller/driver incorporated LV 64-pin µPD78P0914 PD78P0914 Note Under planning Incorporated PWM output, LV digital code decorder, and Hsync counter 3 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y The major functional differences among the subseries are shown below. Function Subseries Name ROM Capacity µPD78075BY PD78075BY 32 K to 40 K I/O Serial Interface VDD MIN. Value 3-wire/2-wire/I2C With automatic transmit/receive function, 3-wire 3-wire/UART : 1 ch : 1 ch : 1 ch 88 1.8 V 61 2.7 V µPD780018AY PD780018AY 48 K to 60 K With automatic transmit/receive function, 3-wire Time division 3-wire I2C bus (multi master supported) : 1 ch : 1 ch : 1 ch 88 µPD780058Y PD780058Y 24 K to 60 K 3-wire/2-wire/I2C With automatic transmit/receive function, 3-wire 3-wire/Time division UART : 1 ch : 1 ch : 1 ch 68 1.8 V µPD78058FY PD78058FY 48 K to 60 K Control 3-wire/2-wire/I2C With automatic transmit/receive function, 3-wire : 1 ch : 1 ch 69 2.7 V 3-wire/UART : 1 ch UART 3-wire I2C bus (multi master supported) : 1 ch : 1 ch µPD78078Y PD78078Y µPD78070AY PD78070AY µPD78054Y PD78054Y 48 K to 60 K ­ 16 K to 60 K µPD780034Y PD780034Y 8 K to 32 K µPD780024Y PD780024Y 51 1.8 V : 1 ch µPD78018FY PD78018FY 8 K to 60 K 3-wire/2-wire/I C With automatic transmit/receive function, 3-wire : 1 ch : 1 ch µPD78014Y PD78014Y 8 K to 32 K 3-wire/2-wire/SBI/I2C With automatic transmit/receive function, 3-wire : 1 ch : 1 ch µPD78002Y PD78002Y 8 K to 16 K 3-wire/2-wire/SBI/I2C : 1 ch 2 µPD780308Y PD780308Y 48 K to 60 K 3-wire/2-wire/I C 3-wire/Time division UART 3-wire : 1 ch : 1 ch : 1 ch µPD78064Y PD78064Y LCD 2.0 V 3-wire/2-wire/I2C 3-wire/UART 53 2.7 V : 1 ch : 1 ch driver 16 K to 32 K 2 57 2.0 V Remark The functions other than the serial interface are the same as those of Subseries products without the suffix Y. 4 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y OVERVIEW OF FUNCTION Product Name µPD78052Y PD78052Y µPD78053Y PD78053Y µPD78054Y PD78054Y µPD78055Y PD78055Y µPD78056Y PD78056Y µPD78058Y PD78058Y ROM 16 Kbytes 24 Kbytes 32 Kbytes 40 Kbytes 48 Kbytes 60 Kbytes High-speed RAM 512 bytes Item Internal Memory 1024 bytes Buffer RAM 32 bytes Expanded RAM None Memory space 64 Kbytes General registers 8 bits × 32 registers (8 bits × 8 registers × 4 banks) Minimum instruction execution time 1024 bytes On-chip minimum instruction execution time cycle modification function When main system clock selected 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@ 5.0-MHz operation) When subsystem clock selected 122 µs (@ 32.768-kHz operation) Instruction set · · · · I/O ports Total · CMOS input · CMOS I/O · N-ch open-drain I/O A/D converter · 8-bit resolution × 8 channels D/A converter · 8-bit resolution × 2 channels Serial interface · 3-wire serial I/O/2-wire serial I/O mode/I2C bus mode selectable: 1 channel · 3-wire serial I/O mode (on-chip max. 32-byte automatic data transmit/receive function): 1 channel · 3-wire serial I/O/UART mode selectable : 1 channel Timer · · · · Timer output 3 (14-bit PWM output × 1) Clock output 19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz, 5.0 MHz (@ 5.0-MHz operation with main system clock) 32.768 kHz (@ 32.768-kHz operation with subsystem clock) Buzzer output 1.2 kHz, 2.4 kHz, 4.9 kHz, 9.8 kHz (@ 5.0-MHz operation with main system clock) Vectored interrupt sources 16-bit operation Multiplication/division (8 bits × 8 bits,16 bits ÷ 8 bits) Bit manipulation (set, reset, test, boolean operation) BCD adjustment, etc. 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer : : : : : : : : 1 2 1 1 69 02 63 4 channel channels channel channel Maskable Internal interrupt : 13, external interrupt : 7 Non-maskable Internal interrupt : 1 Software 1 Test input Internal : 1, external : 1 Supply voltage VDD = 2.0 to 6.0 V Operating ambient temperature TA = ­40 to +85°C Package · 80-pin plastic QFP (14 × 14 mm) 5 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y CONTENTS 1. PIN CONFIGURATION (TOP VIEW) . 7 2. BLOCK DIAGRAM . 9 3 PIN FUNCTIONS . 10 10 3.1 Port Pins . 3.2 Non-port Pins . 12 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins . 14 4. MEMORY SPACE . 18 5. PERIPHERAL HARDWARE FUNCTION FEATURES . 19 5.1 5.2 Clock Generator . 20 5.3 Timer/Event Counter . 20 5.4 Clock Output Control Circuit . 23 5.5 Buzzer Output Control Circuit . 23 5.6 A/D Converter . 24 5.7 D/A Converter . 25 5.8 Serial Interfaces . 25 5.9 6. Ports . 19 Real-Time Output Port Functions . 27 INTERRUPT FUNCTIONS AND TEST FUNCTIONS . 28 6.1 Interrupt Functions . 6.2 Test Functions . 32 28 7. EXTERNAL DEVICE EXPANSION FUNCTIONS . 33 8. STANDBY FUNCTION . 33 9. RESET FUNCTION . 33 10. INSTRUCTION SET . 34 11. ELECTRICAL SPECIFICATIONS . 37 12. CHARACTERISTIC CURVES (REFERENCE VALUE) . 64 13. PACKAGE DRAWING . 66 14. RECOMMENDED SOLDERING CONDITIONS . 67 APPENDIX A. DEVELOPMENT TOOLS . 68 APPENDIX B. 6 RELATED DOCUMENTS . 70 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 1. PIN CONFIGURATION (TOP VIEW) · 80-pin plastic QFP (14 × 14 mm) µPD78052YGC-xxx-8BT µPD78053YGC-xxx-8BT µPD78054YGC-xxx-8BT µPD78055YGC-xxx-8BT µPD78056YGC-xxx-8BT P00/INTP0/TI00 P00/INTP0/TI00 P01/INTP1/TI01 P01/INTP1/TI01 P02/INTP2 P02/INTP2 P03/INTP3 P03/INTP3 P04/INTP4 P04/INTP4 P05/INTP5 P05/INTP5 P06/INTP6 P06/INTP6 VDD X2 X1 IC XT2 XT1/P07 XT1/P07 AVDD AVREF0 P10/ANI0 P10/ANI0 P11/ANI1 P11/ANI1 P12/ANI2 P12/ANI2 P13/ANI3 P13/ANI3 P14/ANI4 P14/ANI4 µPD78058YGC-xxx-8BT P15/ANI5 P15/ANI5 1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 P16/ANI6 P16/ANI6 2 59 P127/RTP7 P127/RTP7 P17/ANI7 P17/ANI7 3 58 P126/RTP6 P126/RTP6 AVSS 4 57 P125/RTP5 P125/RTP5 P130/ANO0 P130/ANO0 5 56 P124/RTP4 P124/RTP4 P131/ANO1 P131/ANO1 6 55 P123/RTP3 P123/RTP3 AVREF1 7 54 P122/RTP2 P122/RTP2 P70/SI2/RxD 8 53 P121/RTP1 P121/RTP1 P71/SO2/TxD RESET 9 52 P120/RTP0 P120/RTP0 P72/SCK2/ASCK P72/SCK2/ASCK 10 51 P37 P20/SI1 P20/SI1 11 50 P36/BUZ P36/BUZ P21/SO1 P21/SO1 12 49 P35/PCL P35/PCL P22/SCK1 P22/SCK1 13 48 P34/TI2 P34/TI2 P23/STB P23/STB 14 47 P33/TI1 P33/TI1 P65/WR P65/WR P64/RD P64/RD P63 P62 P61 P60 P57/A15 P57/A15 P56/A14 P56/A14 41 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VSS P66/WAIT P66/WAIT P41/AD1 P41/AD1 P55/A13 P55/A13 P67/ASTB P67/ASTB 42 P54/A12 P54/A12 43 19 P53/A11 P53/A11 18 P40/AD0 P40/AD0 P52/A10 P52/A10 P27/SCK0/SCL P27/SCK0/SCL P51/A9 P51/A9 P30/TO0 P30/TO0 P50/A8 P50/A8 44 P47/AD7 P47/AD7 17 P46/AD6 P46/AD6 P31/TO1 P31/TO1 P26/SO0/SB1/SDA1 P26/SO0/SB1/SDA1 P45/AD5 P45/AD5 P32/TO2 P32/TO2 45 P44/AD4 P44/AD4 46 16 P43/AD3 P43/AD3 15 P42/AD2 P42/AD2 P24/BUSY P24/BUSY P25/SI0/SB0/SDA0 P25/SI0/SB0/SDA0 Cautions 1. IC (Internally Connected) pin should be connected directly to VSS. 2. AVDD pin should be connected to VDD pin. 3. AVSS pin should be connected to VSS pin. 7 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y A8 to A15 : Address Bus PCL : Programmable Clock AD0 to AD7 : Address/Data Bus RD : Read Strobe ANI0 to ANI7 : Analog Input RESET : Reset ANO0, ANO1 : Analog Output RTP0 to RTP7 : Real-Time Output Port ASCK : Asynchronous Serial Clock R XD : Receive Data ASTB : Address Strobe SB0, SB1 : Serial Bus AVDD : Analog Power Supply SCK0 to SCK2 : Serial Clock AVREF0, AVREF1 : Analog Reference Voltage SCL : Serial Clock AVSS : Analog Ground SDA0, SDA1 : Serial Data BUSY : Busy SI0 to SI2 : Serial Input BUZ : Buzzer Clock SO0 to SO2 : Serial Output IC : Internally Connected : Strobe TI00, TI01 : Timer Input P00 to P07 : Port0 TI1, TI2 : Timer Input P10 to P17 : Port1 TO0 to TO2 : Timer Output P20 to P27 : Port2 TX D : Transmit Data P30 to P37 : Port3 VDD : Power Supply P40 to P47 : Port4 VSS : Ground P50 to P57 : Port5 WAIT : Wait P60 to P67 : Port6 WR : Write Strobe P70 to P72 : Port7 X1, X2 : Crystal (Main System Clock) P120 to P127 : Port12 XT1, XT2 : Crystal (Subsystem Clock) P130, P131 8 STB INTP0 to INTP6 : Interrupt from Peripherals : Port13 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 2. BLOCK DIAGRAM PORT0 TI01/INTP1/P01 TI01/INTP1/P01 TO1/P31 TI1/P33 TI1/P33 TO2/P32 TI2/P34 TI2/P34 P10 to P17 PORT2 P20 to P27 PORT3 TI00/INTP0/P00 TI00/INTP0/P00 P30 to P37 PORT4 P40 to P47 PORT5 P50 to P57 PORT6 P60 to P67 PORT7 P70 to P72 PORT12 PORT12 P120 to P127 PORT13 PORT13 16-bit TIMER/ EVENT COUNTER P00 P01 to P06 P07 PORT1 TO0/P30 P130, P131 8-bit TIMER/ EVENT COUNTER 1 8-bit TIMER/ EVENT COUNTER 2 WATCHDOG TIMER WATCH TIMER SI0/SB0/SDA0/P25 SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SCK0/SCL/P27 SERIAL INTERFACE 0 78K/0 78K/0 CPU CORE ROM SI1/P20 SI1/P20 SO1/P21 SO1/P21 SCK1/P22 SCK1/P22 SERIAL INTERFACE 1 STB/P23 STB/P23 BUSY/P24 BUSY/P24 SI2/RxD/P70 SO2/TxD/P71 SERIAL INTERFACE 2 SCK2/ASCK/P72 SCK2/ASCK/P72 RAM ANI0/P10 ANI0/P10 to ANI7/P17 ANI7/P17 AVDD REAL-TIME OUTPUT PORT A/D CONVERTER RTP0/P120 RTP0/P120 to RTP7/P127 RTP7/P127 AVSS AVREF0 ANO0/P130 ANO0/P130, ANO1/P131 ANO1/P131 AVSS EXTERNAL ACCESS D/A CONVERTER AVREF1 AD0/P40AD7/P47 AD0/P40AD7/P47 A8/P50 A8/P50 to A15/P57 A15/P57 RD/P64 RD/P64 WR/P65 WR/P65 WAIT/P66 WAIT/P66 INTP0/P00 INTP0/P00 to INTP6/P06 INTP6/P06 BUZ/P36 BUZ/P36 ASTB/P67 ASTB/P67 INTERRUPT CONTROL RESET BUZZER OUTPUT X1 SYSTEM CONTROL PCL/P35 PCL/P35 CLOCK OUTPUT CONTROL VDD VSS IC X2 XT1/P07 XT1/P07 XT2 Remark The internal ROM and RAM capacity depends on the product. 9 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 3. PIN FUNCTIONS 3.1 Port Pins (1/2) Pin Name P00 Input P01 Input/ output P02 After Reset Alternate Function Input only Input INTP0/TI00 INTP0/TI00 Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor Input INTP1/TI01 INTP1/TI01 I/O Function Port 0 8-bit I/O port INTP2 can be used by software. P03 INTP3 P04 INTP4 P05 INTP5 P06 INTP6 P07 Note 1 Input Input only Input XT1 P10 to P17 Input/ output Port 1 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software.Note 2 Input ANI0 to ANI7 P20 Input/ output Port 2 8-bit input/output port. Input SI1 P21 P22 P23 SO1 Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. SCK1 STB P24 BUSY P25 SI0/SB0/SDA0 P26 SO0/SB1/SDA1 P27 SCK0/SCL P30 Input/ output P31 Port 3 8-bit input/output port. Input TO1 Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. P32 P33 TO0 TO2 TI1 P34 TI2 P35 PCL P36 BUZ P37 - P40 to P47 Input/ output Port 4 8-bit input/output port. Input/output can be specified in 8-bit unit. When used as an input port, on-chip pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection. Input AD0 to AD7 Notes 1. When using the P07/XT1 P07/XT1 pins as an input port, set 1 in bit 6 (FRC) of the processor clock control register (PCC). On-chip feedback resistor of the subsystem clock oscillator should not be used. 2. When using the P10/ANI0 P10/ANI0 to P17/ANI7 P17/ANI7 pins as the A/D converter analog input pins, set port 1 to the input mode. The pull-up resistor is disabled automatically. 10 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 3.1 Port Pins (2/2) Pin Name P50 to P57 Input/ output After Alternate Reset Function Port 5 8-bit input/output port. LED can be driven directly. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input A8 to A15 Input - Input RD I/O Function P60 Input/ Port 6 N-ch open-drain input/output port. P61 output 8-bit input/outport port. Input/output can be specified bit-wise. On-chip pull-up resistor can be specified by mask option. LED can be driven directly. P62 P63 P64 When used as an input port, P65 on-chip pull-up resistor can be used by software. P66 WR WAIT P67 P70 P71 ASTB Input/ output P72 P120 to P127 Input/ output P130, P131 Input/ output Port 7 3-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input Port 12 8-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input RTP0 to RTP7 Port 13 2-bit input/output port. Input/output can be specified bit-wise. When used as an input port, on-chip pull-up resistor can be used by software. Input ANO0, ANO1 SI2/RxD SO2/TxD SCK2/ASCK 11 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 3.2 Non-port Pins (1/2) Pin Name INTP0 I/O Input INTP1 Function External interrupt request input for which the effective edge (rising edge, falling edge, or both rising edge and falling edge) can be After Reset Alternate Function Input P00/TI00 P00/TI00 P01/TI01 P01/TI01 specified. INTP2 P02 INTP3 P03 INTP4 P04 INTP5 P05 INTP6 P06 SI0 Input Serial interface serial data input. Input SI1 P20 SI2 SO0 P70/RxD Output Serial interface serial data output. Input SO1 SB1 P71/TxD Input/ output Serial interface serial data input/output. Input P25/SI0/SB0 P25/SI0/SB0 SDA1 SCK1 P25/SI0/SDA0 P25/SI0/SDA0 P26/SO0/SDA1 P26/SO0/SDA1 SDA0 SCK0 P26/SB1/SDA1 P26/SB1/SDA1 P21 SO2 SB0 P25/SB0/SDA0 P25/SB0/SDA0 P26/SO0/SB1 P26/SO0/SB1 Input/ output Serial interface serial clock input/ output Input P27/SCL P27/SCL P22 SCK2 P72/ASCK P72/ASCK SCL P27/SCK0 P27/SCK0 STB Output Serial interface automatic transmit/receive strobe output. Input P23 BUSY Input Serial interface automatic transmit/receive busy input. Input P24 RxD Input Asynchronous serial interface serial data input. Input P70/SI2 P70/SI2 TxD Output Asynchronous serial interface serial data output. Input P71/SO2 P71/SO2 ASCK Input Asynchronous serial interface serial clock input. Input P72/SCK2 P72/SCK2 TI00 Input External count clock input to the 16-bit timer (TM0) Input TI01 Capture trigger signal input to the capture register (CR00) TI1 External count clock input to the 8-bit timer (TM1) TI2 TO0 P33 External count clock input to the 8-bit timer (TM2) Output 16-bit timer (TM0) output (dual-function as 14-bit PWM output) P00/INTP0 P00/INTP0 P01/INTP1 P01/INTP1 P34 Input P30 TO1 8-bit timer (TM1) output P31 TO2 8-bit timer (TM2) output P32 PCL Output Clock output (for main system clock, subsystem clock trimming). Input P35 BUZ Output Buzzer output. Input P36 RTP0 to RTP7 Output Real-time output port by which data is output in synchronization with a trigger. Input P120 to P127 AD0 to AD7 Input/ output Low-order address/data bus at external memory expansion. Input P40 to P47 A8 to A15 Output High-order address bus at external memory expansion. Input P50 to P57 RD Output External memory read operation strobe signal output. Input P64 WR 12 External memory write operation strobe signal output. P65 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 3.2 Non-port Pins (2/2) Pin Name After Reset DualFunction Pin Wait insertion at external memory access. Input P66 Strobe output which latches the address information output at port 4 and port 5 to access external memory. Input P67 A/D converter analog input. Input P10 to P17 D/A converter analog output. I/O Function WAIT Input ASTB Output ANI0 to ANI7 Input ANO0, ANO1 Output Input P130, P131 AVREF0 Input A/D converter reference voltage input. - - AVREF1 Input D/A converter reference voltage input. - - AVDD - A/D converter analog power supply. Connect to VDD - - AVSS - Ground potential of A/D converter and D/A converter. Connect to VSS - - RESET Input System reset input. - - X1 Input Main system clock oscillation crystal connection. - - X2 - XT1 Input - XT2 - - Input P07 - VDD - Positive power supply. VSS - Ground potential. - - IC - Internally connected. Connect directly to VSS. - - Subsystem clock oscillation crystal connection. - - - 13 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the input/output circuit configuration of each type, see Figure 3-1. Table 3-1. Input/Output Circuit Type of Each Pin (1/2) Input/output Circuit Type I/O P00/INTP0/TI00 P00/INTP0/TI00 2 Input P01/INTP1/TI01 P01/INTP1/TI01 8-A Input/output P07/XT1 P07/XT1 16 Input P10/ANI0 P10/ANI0 to P17/ANI7 P17/ANI7 11 Input/output P20/SI1 P20/SI1 8-A P21/SO1 P21/SO1 5-A P22/SCK1 P22/SCK1 8-A P23/STB P23/STB 5-A P24/BUSY P24/BUSY 8-A P25/SI0/SB0/SDA0 P25/SI0/SB0/SDA0 10-A Pin Name Recommended Connection when Used Connect to VSS . Independently connect to VSS through resistor. P02/INTP2 P02/INTP2 P03/INTP3 P03/INTP3 P04/INTP4 P04/INTP4 P05/INTP5 P05/INTP5 P06/INTP6 P06/INTP6 Connect to VDD. Independently connect to VDD or VSS through resistor. P26/SO0/SB1/SDA1 P26/SO0/SB1/SDA1 P27/SCK0/SCL P27/SCK0/SCL P30/TO0 P30/TO0 5-A P31/TO1 P31/TO1 P32/TO2 P32/TO2 P33/TI1 P33/TI1 8-A P34/TI2 P34/TI2 P35/PCL P35/PCL 5-A P36/BUZ P36/BUZ P37 P40/AD0 P40/AD0 to P47/AD7 P47/AD7 5-E Independently connect to VDD through resistor. P50/A8 P50/A8 to P57/A15 P57/A15 5-A Independently connect to VDD or VSS through resistor. P60 to P63 13-B Independently connect to VDD through resistor. P64/RD P64/RD 5-A Independently connect to VDD or VSS through resistor. P65/WR P65/WR P66/WAIT P66/WAIT P67/ASTB P67/ASTB 14 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Table 3-1. Input/Output Circuit Type of Each Pin (2/2) Input/output Circuit Type I/O P70/SI2/RxD 8-A Input/output P71/SO2/TxD 5-A P72/SCK2/ASCK P72/SCK2/ASCK 8-A Pin Name P120/RTP0 P120/RTP0 to P127/RTP7 P127/RTP7 12-A Independently connect to VDD or VSS through resistor. 5-A P130/ANO0 P130/ANO0 , P131/ANO1 P131/ANO1 Recommended Connection when Used Independently connect to VSS through resistor. RESET 2 Input XT2 16 - AVREF0 - AVREF1 - Leave open. Connect to VSS . Connect to VDD . AVDD AVSS Connect to VSS . IC Connect directly to VSS. 15 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Figure 3-1. Pin Input/Output Circuits (1/2) Type 2 Type 8-A V DD pull-up enable P-ch IN V DD data P-ch IN/OUT Schmitt-Triggered Input with Hysteresis Characteristic V DD Type 5-A pull-up enable output disable N-ch V DD Type 10-A pul-lup enable P-ch P-ch V DD data V DD data P-ch P-ch IN/OUT output disable IN/OUT open drain output disable N-ch N-ch input enable Type 5-E pull-up enable pull-up enable P-ch P-ch IN/OUT P-ch IN/OUT output disable P-ch VDD data V DD data VDD Type 11 V DD N-ch output disable Comparator N-ch P-ch + N-ch VREF (Threshold Voltage) input enable 16 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Figure 3-1. Pin Input/Output Circuits (2/2) V DD Type 12-A pull-up enable Type 16 feed back P-ch cut-off V DD data P-ch P-ch IN/OUT output disable input enable N-ch P-ch XT1 Analog Output Voltage XT2 N-ch Type 13-B V DD Mask Option IN/OUT data output disable N-ch V DD RD P-ch Middle-High Voltage Input Buffer 17 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 4. MEMORY SPACE Figure 4-1 shows the µPD78052Y/78053Y/78054Y/78055Y/78056Y/78058Y memory map. Figure 4-1. Memory Map FFFFH Special Function Registers (SFR) 256 x 8 bits FF00H FF00H FEFFH FEE0H FEDFH 7A7FH General Registers 32 x 8 bits Use Prohibited F800H F800H F7FFH Internal Expanded RAM 1024 x 8 bits Internal High-Speed RAM Note3 F400H F400H F3FFH mmmmH mmmmH - 1 Use Prohibited Note2 F000H F000H Use Prohibited Data Memory Space Note1 FAE0H FADFH nnnnH Buffer RAM 32 x 8 bits Program Area FAC0H FABFH 1000H 1000H 0FFFH Use Prohibited CALLF Entry Area FA80H FA80H FA7FH 0800H 0800H 07FFH 07FFH Program Area External Memory 0080H 0080H 007FH 007FH Program Memory Space nnnnH + 1 nnnnH CALLT Table Area Internal ROM 0040H 0040H 003FH 003FH Note3 Vector Table Area 0000H 0000H 0000H 0000H Notes 1. Provided in the µPD78058Y PD78058Y only 2. When the external device expansion function is used with the µPD78058Y PD78058Y, set the internal ROM capacity to 56 Kbytes or less using the internal memory size switching register (IMS). 3. The internal ROM capacity and internal high-speed RAM capacity depend on the products (see the next table). Relevant Product Name Internal High-Speed RAM First Address mmmmH µPD78052Y PD78052Y µPD78053Y PD78053Y µPD78054Y PD78054Y µPD78055Y PD78055Y µPD78056Y PD78056Y µPD78058Y PD78058Y 18 Internal ROM Last Address nnnnH 3FFFH 5FFFH 7FFFH 9FFFH BFFFH EFFFH FD00H FD00H FB00H FB00H µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 5. PERIPHERAL HARDWARE FUNCTION FEATURES 5.1 Ports The following 3 types of I/O ports are available. · CMOS input (P00, P07) : 2 · CMOS input/output (P01 to P06, port 1 to port 5, P64 to P67, port 7, port 12, port 13) : 63 · N-channel open-drain input/output (P60 to P63) : Total : 69 4 Table 5-1. Port Functions Name Port 0 Pin Name Function P00, P07 Dedicated input port pins P01 to P06 Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Port 1 P10 to P17 Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Port 2 P20 to P27 Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Port 3 P30 to P37 Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Port 4 P40 to P47 Input/output port pins. Input/output specifiable in 8-bit units. When used as input port pins, on-chip pull-up resistor can be used by software. Test input flag (KRIF) is set to 1 by falling edge detection. Port 5 P50 to P57 Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. LED direct drive capability. Port 6 P60 to P63 N-channel open-drain input/output port pins. Input/output specifiable bit-wise. On-chip pull-up resistor can be used by mask option. LED direct drive capability. P64 to P67 Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Port 7 P70 to P72 Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Port 12 P120 to P127 Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. Port 13 P130, P131 Input/output port pins. Input/output specifiable bit-wise. When used as input port pins, on-chip pull-up resistor can be used by software. 19 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 5.2 Clock Generator Two types of generators, a main system clock generator and a subsystem clock generator, are avaibable. The minimum instruction execution time can also be changed. · 0.4 µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 µs (@5.0-MHz operation with main system clock) · 122 µs (@32.768-kHz operation with subsystem clock) Figure 5-1. Clock Generator Block Diagram XT1/P07 XT1/P07 Subsystem Clock Oscillator XT2 fXT Watch Timer, Clock Output Function Prescaler 1 X1 X2 Main System fX Clock Oscillator Selector STOP Clock to Peripheral Hardware Prescaler fXX Scaler 2 fXX fXX fXX fXX fXT 2 22 23 24 2 fX 2 Selector Standby Control Circuit Wait Control Circuit CPU Clock (fCPU) To INTP0 Sampling Clock 5.3 Timer/Event Counter 5 timer/event counter channels are incorporated. · 16-bit timer/event counter : 1 channel · 8-bit timer/event counter : 2 channels · Watch timer : 1 channel · Watchdog timer : 1 channel Table 5-2. Operation of Timer/Event Counter 16-Bit Timer/Event Counter 8-Bit Timer/Event Counter Watch Timer Watchdog Timer Operation mode Interval timer 1 channel 2 channels 1 channel 1 channel External event counter 1 channel 2 channels - - Timer output 1 output 2 outputs - - PWM output 1 output - - - Function Pulse amplitude measurement 2 inputs Square wave output 1 output 2 outputs - - One-shot pulse output 1 output - - - Interrupt source 20 2 2 1 1 Test input - - 1 input - µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Figure 5-2. 16-Bit Timer/Event Counter Block Diagram Internal Bus INTP1 TI01/P01/INTP1 TI01/P01/INTP1 16-Bit Capture/ Compare Register (CR00) Selector INTTM00 INTTM00 PWM pulse Output Control Circuit Match Watch Timer Output Output Control Circuit TO0/P30 2fXX fXX Selector fXX/2 fXX/2 16-Bit Timer Register (TM0) 2 TI00/P00/INTP0 TI00/P00/INTP0 Clear Edge Detector Selector Match INTTM01 INTTM01 INTP0 16-Bit Capture/ Compare Register (CR01) Internal Bus Figure 5-3. 8-Bit Timer/Event Counter Block Diagram Internal Bus INTTM1 8-Bit Compare Register (CR10) 8-Bit Compare Register (CR20) Selector Match Match Output Control Circuit INTTM2 fxx/2 to fxx/29 fxx/211 Selector 8-Bit Timer Register 1 (TM1) Selector TI1/P33 TI1/P33 Clear 8-Bit Timer Register 2 (TM2) Clear fxx/2 to fxx/29 fxx/211 TO2/P32 Selector Selector TI2/P34 TI2/P34 Output Control Circuit TO1/P31 Internal Bus 21 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Figure 5-4. Watch Timer Block Diagram fW 214 Selector fXX/2 7 Selector fW 5-Bit Counter Selector Prescaler fXT fW 24 fW 25 fW 26 fW 27 fW 28 INTWT fW 213 fW 29 INTTM3 Selector To 16-Bit Timer/ Event Counter Figure 5-5. Watchdog Timer Block Diagram fXX 23 Prescaler fXX 4 2 fXX 5 2 fXX 6 2 fXX 7 2 fXX 8 2 fXX 9 2 fXX 11 2 INTWDT Maskable Interrupt Request Selector 8-Bit Counter Control Circuit RESET INTWDT Non-Maskable Interrupt Request 22 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 5.4 Clock Output Control Circuit A clock with the following frequencies can be output as the clock output. · 19.5 kHz/39.1 kHz/78.1 kHz/156 kHz/313 kHz/625 kHz/1.25 MHz/2.5 MHz/5.0 MHz (@5.0-MHz operation with main system clock) · 32.768 kHz (@32.768-kHz operation with subsystem clock) Figure 5-6. Clock Output Control Circuit Block Diagram fXX fXX/2 fXX/22 fXX/23 fXX/24 Synchronization Circuit Selector Output Control Circuit PCL/P35 PCL/P35 fXX/25 fXX/26 fXX/27 fXT 5.5 Buzzer Output Control Circuit A clock with the following frequencies can be output as the buzzer output. · 1.2 kHz/2.4 kHz/4.9 kHz/9.8 kHz (@5.0-MHz operation with main system clock) Figure 5-7. Buzzer Output Control Circuit Block Diagram fXX/29 fXX/210 Selector Output Control Circuit BUZ/P36 BUZ/P36 fXX/211 23 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 5.6 A/D Converter An A/D converter of 8-bit resolution x 8 channels is incorporated. The following two A/D conversion operation start-up methods are available. · Hardware start · Software start Figure 5-8. A/D Converter Block Diagram Series Resistor String AVDD Sample & Hold Circuit ANI0/P10 ANI0/P10 AVREF0 ANI1/P11 ANI1/P11 Voltage Comparator ANI2/P12 ANI2/P12 Tap Selector ANI3/P13 ANI3/P13 ANI4/P14 ANI4/P14 Selector ANI5/P15 ANI5/P15 ANI6/P16 ANI6/P16 Successive Approximation Register (SAR) ANI7/P17 ANI7/P17 INTP3/P03 INTP3/P03 Edge Detection Circuit Control Circuit AVSS INTAD INTP3 A/D Conversion Result Register (ADCR) Internal Bus 24 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 5.7 D/A Converter A D/A converter of 8-bit resolution × 2 channels is available. Conversion method is R-2R resistor ladder method. Figure 5-9. D/A Converter Block Diagram AVREF1 ANOn Selector DACSn Write AVSS INTTMX D/A Conversion Value Set Register n (DACSn) DAMm D/A Converter Mode Register Internal Bus n = 0, 1 m = 4, 5 x = 1, 2 5.8 Serial Interfaces 3 channels of the clocked serial interface are incorporated. · Serial interface channel 0 · Serial interface channel 1 · Serial interface channel 2 Table 5-3. Types and Functions of Serial Interface Function 3-wire serial I/O made 3-wire serial I/O mode with automatic transmit/receive function Serial Interface Channel 0 Serial Interface Channel 1 Serial Interface Channel 2 (MSB/LSB first switchable) (MSB/LSB first switchable) (MSB/LSB first switchable) - (MSB/LSB first switchable) - 2-wire serial I/O mode (MSB first) - - I2C bus mode (MSB first) - - Asynchronous serial interface (UART) mode - - (Dedicated baud rate generator incorporated) 25 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Figure 5-10. Serial Interface Channel 0 Block Diagram Internal Bus SI0/SB0/SDA0/P25 SI0/SB0/SDA0/P25 Selector Serial I/O Shift Register 0 (SIO0) Output Latch SO0/SB1/SDA1/P26 SO0/SB1/SDA1/P26 Selector Acknowledge Output Circuit Stop Condition/Start Condition/Acknowledge Detection Circuit Interrupt Request Signal Generator Serial Clock Counter SCK0/SCL/P27 SCK0/SCL/P27 INTCSI0 fXX/2 to fXX/28 Serial Clock Control Circuit Selector TO2 Figure 5-11. Serial Interface Channel 1 Block Diagram Internal Bus Automatic Data Transmit/ Receive Address Pointer (ADTP) Buffer RAM Automatic Data Transmit/Receive Interval Specification Register (ADTI) Match SI1/P20 SI1/P20 Serial I/O Shift Register 1 (SIO1) SO1/P21 SO1/P21 5-Bit Counter STB/P23 STB/P23 BUSY/P24 BUSY/P24 SCK1/P22 SCK1/P22 Handshake Control Circuit Serial Clock Counter Interrupt Request Signal Generator INTCSI1 fXX/2 to fXX/2 Serial Clock Control Circuit 26 Selector TO2 8 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Figure 5-12. Serial Interface Channel 2 Block Diagram Internal Bus Receive Buffer Register (RXB/SIO2) Direction Control Circuit Transmit Shift Register (TXS/SIO2) Receive Shift Register (RXS) RxD/SI2/P70 Direction Control Circuit Transmit Control Circuit INTST TXD/SO2/P71 TXD/SO2/P71 INTSER Receive Control Circuit INTSR/INTCSI2 SCK Output Control Circuit ASCK/SCK2/P72 ASCK/SCK2/P72 Baud Rate Generator 5.9 fXX to fXX/210 Real-time Output Port Functions Data set previously in the real-time output buffer register is transferred to the output latch by hardware concurrently with timer interrupt or external interrupt generation in order to output to off-chip. This is a real-time output function. Pins used to output data to off-chip are called real-time output ports. By using a real-time output port, a signal which has no jitter can be output. This is most applicable to control stepping motors, etc. Figure 5-13. Real-Time Output Port Block Diagram Internal Bus INTP2 INTTM1 INTTM2 Output Trigger Control Circuit Real-Time Output Real-Time Output Buffer Register Buffer Register Higher 4 Bits Lower 4 Bits (RTBH) (RTBL) Real-Time Output Port Mode Register (RTPM) Output Latch P127 P120 27 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 6. INTERRUPT FUNCTIONS AND TEST FUNCTIONS 6.1 Interrupt Functions There are interrupt functions, 22 sources of three different types, as shown below. · Non-maskable interrupt: 1 · Maskable interrupts: 20 · Software interrupt: 1 The following table shows the interrupt source list. Table 6-1. Interrupt Source List (1/2) Interrupt Type Interrupt Source DefaultNote 1 Priority Name Trigger Internal/ External Basic Configuration TypeNote 2 0004H 0004H (A) Non-maskable - INTWDT Watchdog timer overflow (watchdog timer mode 1 selected) Maskable 0 INTWDT Watchdog timer overflow (interval timer mode selected) 1 INTP0 2 INTP1 3 INTP2 000AH 000AH 4 INTP3 000CH 000CH 5 INTP4 000EH 000EH 6 INTP5 0010H 0010H Pin input edge detection Internal Vector Table Address (B) External 0006H 0006H (C) 0008H 0008H (D) 7 INTP6 8 INTCSI0 End of serial interface channel 0 transfer 9 INTCSI1 End of serial interface channel 1 transfer 0016H 0016H 10 INTSER Generation of serial interface channel 2 UART receive error 0018H 0018H 11 INTSR End of serial interface channel 2 UART reception 001AH 001AH INTCSI2 End of serial interface channel 2 3-wire transfer INTST End of serial interface channel 2 UART transmission 12 0012H 0012H Internal 0014H 0014H (B) 001CH 001CH Notes 1. The default priority is a priority order when two or more maskable interrupt requests are generated simultaneously. 0 is the highest order and 18, the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively. 28 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Table 6-1. Interrupt Source List (2/2) Interrupt Type Maskable Interrupt Source DefaultNote 1 Priority Name Trigger Internal/ External Basic Configuration TypeNote 2 001EH 001EH (B) 13 INTTM3 Reference time interval signal from watch timer 14 INTTM00 INTTM00 Generation of match signal of 16-bit timer register and capture/compare register (CR00) 0020H 0020H 15 INTTM01 INTTM01 Generation of match signal of 16-bit timer register and capture/compare register (CR01) 0022H 0022H 16 INTTM1 Generation of match signal of 8-bit timer/event counter 1 0024H 0024H 17 INTTM2 Generation of match signal of 8-bit timer/event counter 2 0026H 0026H 18 Software INTAD End of conversion by A/D converter 0028H 0028H - BRK BRK instruction execution Internal Vector Table Address - 003EH 003EH (E) Notes 1. The default priority is a priority order when two or more maskable interrupts are generated simultaneously. 0 is the highest order and 18, the lowest. 2. Basic configuration types (A) to (E) correspond to (A) to (E) in Figure 6-1, respectively. 29 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Figure 6-1. Interrupt Function Basic Configuration(1/2) (A) Internal non-maskable interrupt Internal Bus Interrupt Request Vector Table Address Generator Priority Control Circuit Standby Release Signal (B) Internal maskable interrupt Internal Bus MK Interrupt Request PR IE ISP Vector Table Address Generator Priority Control Circuit IF Standby Release Signal (C) External maskable interrupt (INTP0) Internal Bus Sampling Clock Select Register (SCS) Interrupt Request External Interrupt Mode Register (INTM0) Sampling Clock Edge Detection Circuit MK IF IE PR Priority Control Circuit ISP Vector Table Address Generator Standby Release Signal 30 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Figure 6-1. Interrupt Function Basic Configuration(2/2) (D) External maskable interrupt (except INTP0) Internal Bus External Interrupt Mode Register (INTM0 and INTM1) Interrupt Request Edge Detection Circuit MK IE PR Priority Control Circuit IF ISP Vector Table Address Generator Standby Release Signal (E) Software interrupt Internal Bus Interrupt Request Priority Control Circuit Vector Table Address Generator IF : Interrupt request flag IE : Interrupt enable flag ISP : In-service priority flag MK : Interrupt mask flag PR : Priority specification flag 31 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 6.2 Test Functions There are two test functions as shown in Table 6-2. Table 6-2. Test Input Source List Test Input Source Internal/External Name Trigger INTWT Watch timer overflow Internal INTPT4 Port 4 falling edge detection External Figure 6-2. Test Function Basic Configuration Internal Bus MK Test Input IF : Test input flag MK : Test mask flag 32 IF Standby Release Signal µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 7. EXTERNAL DEVICE EXPANSION FUNCTIONS The external device expansion functions connect external devices to areas other than the internal ROM, RAM, and SFR. Ports 4 to 6 are used for external device connection. 8. STANDBY FUNCTION There are the following two standby functions to reduce the system current consumption. · HALT mode : The CPU operating clock is stopped. The average current consumption can be reduced by intermittent operation in combination with the normal operating mode. · STOP mode : The main system clock oscillation is stopped. The whole operation by the main system clock is stopped, so that the system operates with ultra-low current consumption using only the subsystem clock. Figure 8-1. Standby Function CSS=1 Main System Clock Operation Interrupt Request CSS=0 HALT Instruction STOP Instruction Interrupt Request STOP Mode (Main system clock oscillation stopped) Subsystem Clock Operation Note Interrupt Request HALT Mode (Clock supply to CPU is stopped, oscillation) HALT Instruction HALT Mode Note (Clock supply to CPU is stopped, oscillation) Note The current consumption can be reduced by stopping the main system clock. When the CPU is operating on the subsystem clock, set bit 7 (MCC) of processor clock control register (PCC) to stop the main system clock. The STOP instruction cannot be used. Caution When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. 9. RESET FUNCTION There are the following two reset methods. · External reset input by RESET pin · Internal reset by watchdog time runaway time detection 33 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 10. INSTRUCTION SET (1) 8-bit instructions MOV, XCH, ADD ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, ROR4, ROL4, PUSH, POP, DBNZ Second Operand First Operand [HL + Byte] #byte A r Note sfr saddr !addr16 [DE] [HL] [HL + B] $addr16 1 ADD MOV MOV MOV MOV XCH XCH XCH XCH MOV MOV MOV MOV ROR XCH XCH XCH ROL SUB ADD ADD ADD ADD ADD RORC SUBC ADDC ADDC ADDC ADDC ADDC ROLC AND SUB SUB SUB SUB SUB SUBC OR SUBC SUBC SUBC SUBC XOR AND AND AND AND AND CMP OR OR OR OR OR XOR XOR XOR XOR XOR CMP r None [HL + C] ADDC A PSW CMP CMP CMP CMP MOV INC DEC MOV ADD ADDC SUB SUBC AND OR XOR CMP DBNZ B, C sfr MOV MOV saddr MOV ADD MOV DBNZ INC DEC ADDC SUB SUBC AND OR XOR CMP !addr16 PSW MOV MOV MOV PUSH POP [DE] MOV [HL] MOV ROR4 ROL4 [HL + Byte] MOV [HL + B] [HL + C] X MULU C DIVUW Note Except r = A 34 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y (2) 16-bit instructions MOV, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand First Operand AX ADDW SUBW CMPW rp Note sfrp saddrp !addr16 SP MOVW AX #word MOVW MOVW MOVW MOVW None XCHW rp MOVW MOVW Note sfrp MOVW MOVW saddrp MOVW MOVW !addr16 SP INCW DECW PUSH POP MOVW MOVW MOVW Note Only when rp = BC, DE, or HL (3) Bit manipulate instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand First Operand A.bit sfr.bit saddr.bit PSW.bit [HL].bit CY $addr16 None A.bit MOV1 BT BF BTCLR SET1 CLR1 sfr.bit MOV1 BT BF BTCLR SET1 CLR1 saddr.bit MOV1 BT BF BTCLR SET1 CLR1 PSW.bit MOV1 BT BF BTCLR SET1 CLR1 [HL].bit MOV1 BT BF BTCLR SET1 CLR1 CY MOV1 AND1 MOV1 AND1 MOV1 AND1 MOV1 AND1 MOV1 AND1 SET1 CLR1 OR1 XOR1 OR1 XOR1 OR1 XOR1 OR1 XOR1 OR1 XOR1 NOT1 35 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y (4) Call instruction/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand First Operand Basic instruction Compound instruction AX BR !addr16 CALL BR !addr11 CALLF [addr5] CALLT $addr16 BR BC BNC BZ BNZ BT BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 36 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 11. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol Test Conditions Rating VDD Unit ­0.3 to +7.0 V AVDD ­0.3 to VDD + 0.3 V AVREF0 ­0.3 to VDD + 0.3 V AVREF1 ­0.3 to VDD + 0.3 V AVSS Input voltage ­0.3 to +0.3 V ­0.3 to V DD + 0.3 V N-ch Open-drain ­0.3 to +16 V ­0.3 to VDD + 0.3 V Analog input pin AVSS ­ 0.3 to AVREF0 + 0.3 V VI1 P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131, X1, X2, XT2, RESET VI2 P60 to P63 Output voltage VO Analog input voltage VAN P10 to P17 Output current high IOH 1 pin ­10 mA P01 to P06, P30 to P37, P56, P57, P60 to P67, P120 to P127 total ­15 mA P10 to P17, P20 to P27, P40 to P47, P50 to P55, P70 to P72, P130, P131 total ­15 mA 1 pin Peak value 30 mA r.m.s. value 15 mA Peak value 100 mA r.m.s. value 70 mA Peak value 100 mA r.m.s. value 70 mA P10 to P17, P20 to P27, P40 to P47, P70 to P72, P130, P131 total Peak value 50 mA r.m.s. value 20 mA P01 to P06, P30 to P37, P64 to P67, P120 to P127 total Peak value 50 mA Output current low IOL Note 2 P50 to P55 total P56, P57, P60 to P63 total 20 mA Operating ambient temperature TA r.m.s. value ­40 to +85 °C Storage temperature Tstg ­65 to +150 °C Note The r.m.s. should be calculated as follows: [r.m.s.] = [Peak value] × duty Caution If any of the parameters exceed the absolute maximum ratings, even momentarily, device reliability may be impaired. The absolute maximum ratings are values that may physically damage the product. Be sure to use the product within the ratings. Remark The characteristics of dual-function pins and port pins are the same unless otherwise specified. 37 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Main System Clock Oscillation Circuit Characteristics (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) Recommended Circuit Resonator X2 Ceramic resonator X1 IC Oscillator frequency (fx) C2 Test Conditions Parameter Note 1 stabilization time X2 X1 IC R1 C2 C1 Note 2 MAX. Unit 5.0 MHz 4 ms 5.0 MHz 10 ms 1.0 After VDD reaches oscillation voltage range MIN. 1.0 Oscillator frequency (fx) Note 1 V DD = 4.5 to 6.0 V Oscillation stabilization time External clock V DD = Oscillator voltage range TYP. C1 Oscillation Crystal resonator MIN. Note 2 1.0 X1 input X2 X1 frequency (fx) 5.0 MHz 85 500 ns Note 1 X1 input µPD74HCU04 PD74HCU04 30 high/low level width (tXH , tXL) Notes 1. Indicates only oscillation circuit characteristics. Refer to "AC Characteristics" for instruction execution time. 2. Time required to stabilize oscillation after reset or STOP mode release. Cautions 1. When using the main system clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid adverse effects from wiring capacitance. · Wiring should be as short as possible. · Wiring should not cross other signal lines. · Wiring should not be placed close to a varying high current. · The potential of the oscillator capacitor ground should be the same as VSS. · Do not ground wiring to a ground pattern in which a high current flows. · Do not fetch a signal from the oscillator. 2. When the main system clock is stopped and the system is operated by the subsystem clock, the subsystem clock should be switched again to the main system clock after the oscillation stabilization time is secured by the program. 38 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Subsystem Clock Oscillation Circuit Characteristics (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) Resonator Recommended Circuit IC XT2 Crystal resonator XT1 R2 C4 C3 Parameter Test Conditions MIN. TYP. MAX. Unit 32 32.768 35 kHz 1.2 2 s Oscillator frequency (fXT) Note 1 VDD = 4.5 to 6.0 V Oscillation Note 2 stabilization time 10 XT2 XT1 XT1 input frequency (fXT) Note 1 32 100 kHz XT1 input high/low level width (tXTH , tXTL) External clock 5 15 µs Notes 1. Indicates only oscillation circuit characteristics. Refer to AC Characteristics for instruction execution time. 2. Time required to stabilize oscillation after VDD reaches MIN. in the oscillation voltage range. Cautions 1. When using the subsystem clock oscillator, wiring in the area enclosed with the broken line should be carried out as follows to avoid an adverse effect from wiring capacitance. · Wiring should be as short as possible. · Wiring should not cross other signal lines. · Wiring should not be placed close to a varying high current. · The potential of the oscillator capacitor ground should be the same as VSS. · Do not ground wiring to a ground pattern in which a high current flows. · Do not fetch a signal from the oscillator. 2. The subsystem clock oscillation circuit is a circuit with a low amplification level, more prone to misoperation due to noise than the main system clock. When using the subsystem clock, pay special attention to wiring as described above. 39 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Recommended Oscillator Constant (1) µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y Main System Clock: Ceramic Resonator (TA = ­40 to +85°C) Manufacturer Product Name Frequency (MHz) Murata Mfg. Co., Ltd. Recommended Circuit consonant C1 (pF) C2 (pF) Oscillator Voltage range MIN. (V) Remarks MAX. (V) 30 30 2.0 6.0 5.00 On-chip On-chip 2.0 6.0 Capacitor on chip 5.00 33 33 2.0 6.0 Lead type KBR-5.0MKS 5.00 On-chip On-chip 2.0 6.0 Capacitor on chip, lead type KBR-5.0MWS 5.00 On-chip On-chip 2.0 6.0 Capacitor on chip, lead type PBRC 5.00A 5.00 33 33 2.0 6.0 Chip type CCR4.0MC3 4.00 On-chip On-chip 2.0 6.0 Capacitor on chip CCR5.0MC3 TDK Corp. 5.00 KBR-5.0MSA Kyocera Corp. CSA5.00MG CST5.00MGW 00MGW 5.00 On-chip On-chip 2.0 6.0 Capacitor on chip Main System Clock: Crystal Resonator (TA = ­10 to +70°C) Manufacturer Product Name Oscillator Voltage Range Recommended Circuit Constant Frequency (MHz) C1 (pF) Daishinku Corp. SMD-49 SMD-49 3.579545 C2 (pF) R1 (k) MIN. (V) MAX. (V) 27 27 1.5 2.0 6.0 Subsystem Clock: Crystal Resonator (TA = ­10 to +70°C) Manufacturer Product Name Oscillator Voltage Range Recommended Circuit Constant Frequency (MHz) C3 (pF) Daishinku Corp. DT-38 DT-38 (1TA252E00 1TA252E00) Caution 32.768 C4 (pF) R2 (k) MIN. (V) MAX. (V) 27 20 330 2.0 6.0 The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation. However, they do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. 40 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y (2) µPD78058Y PD78058Y Main System Clock: Ceramic Resonator (TA = ­40 to +85°C) Manufacturer Product Name Frequency (MHz) Kyocera Corp. C1 (pF) C2 (pF) Oscillator Voltage range MIN. (V) Remarks MAX. (V) 4.19 33 33 2.0 6.0 PBRC4.19B 4.19 On-chip On-chip 2.0 6.0 KBR-4.19MSA 19MSA 4.19 33 33 2.0 6.0 KBR-4.19MKS 19MKS 4.19 On-chip On-chip 2.0 6.0 PBRC4.91A 4.91 33 33 2.0 6.0 PBRC4.91B 4.91 On-chip On-chip 2.0 6.0 KBR-4.91MSA 91MSA 4.91 33 33 2.0 6.0 KBR-4.91MKS 91MKS Caution PBRC4.19A Recommended Circuit consonant 4.91 On-chip On-chip 2.0 6.0 Capacitor on chip Capacitor on chip Capacitor on chip Capacitor on chip The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation. However, they do not guarantee accuracy of the oscillation frequency. If the application circuit requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency in the application circuit. For this, it is necessary to directly contact the manufacturer of the resonator being used. Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz Measured pins retured to 0 V. 15 pF Input/output capacitance CIO f = 1 MHz Measured pins retured to 0 V. P01 to P06, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 15 pF P60 to P63 20 pF Remark The characteristics of the dual-function pins and port pins are the same unless otherwise specified. 41 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y DC Characteristics (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) Parameter VIH1 VIH2 Test Conditions MIN. VDD = 2.7 to 6.0 V P33, P34, P70, P72, RESET VIH3 P60 to P63 VDD = 2.7 to 6.0 V (N-ch open-drain) VIH4 X1, X2 VDD = 2.7 to 6.0 V VDD V VDD V 0.8 VDD VDD V VDD V 0.7 VDD 15 V 0.8 VDD P00 to P06, P20, P22, P24 to P27, 0.7 VDD 0.85 VDD VDD = 2.7 to 6.0 V Unit 0.8 VDD P10 to P17, P21, P23, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P64 to P67, P71, P120 to P127, P130, P131 MAX 15 V VDD ­ 0.5 VDD V VDD ­ 0.2 Input voltage, high Symbol TYP. VDD V VIL1 VIL2 VIL3 0.8 VDD VDD V 0.9 VDD VDD V 2.0 V VDD < 2.7 Input voltage, low 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V VIH5 0.9 VDD VDD V P10 to P17, P21, P23, P30 to P32, VDD = 2.7 to 6.0 V P35 to P37, P40 to P47, P50 to P57, P64 to P67, P71, P120 to P127, P130, P131 0 0.3 VDD V 0 0.2 VDD V P00 to P06, P20, P22, P24 to P27, P33, P34, P70, P72, RESET VDD = 2.7 to 6.0 V 0 0.2 VDD V 0 0.15 VDD V P60 to P63 4.5 V VDD 6.0 V 0 0.3 VDD V XT1/P07 XT1/P07, XT2 VNote 2.7 V VDD < 4.5 V 0 0.2 VDD V 0 0.1 VDD V 0 0.4 V VIL4 VDD = 2.7 to 6.0 V 0 0.2 V VIL5 XT1/P07 XT1/P07, XT2 4.5 V VDD 6.0 V 0 0.2 VDD V 2.7 V VDD < 4.5 V 0 0.1 VDD V 2.0 V VDD < 2.7 Output voltage, X1, X2 0 0.1 VDD V VOH VOL1 VDD = 4.5 to 6.0 V, IOH = ­1 mA VDD ­ 1.0 V IOH = ­100 µA high Output voltage, low VNote VDD ­ 0.5 V P50 to P57, P60 to P63 VDD = 4.5 to 6.0 V, IOL = 15 mA P01 to P06, P10 to P17, P20 to P27, VDD = 4.5 to 6.0 V, P30 to P37, P40 to P47, P64 to P67, IOL = 1.6 mA P70 to P72, P120 to P127, P130, P131 VOL2 SB0, SB1, SCK0 VOL3 VDD = 4.5 to 6.0 V, open-drain, pulled-up (R = 1 K) IOL = 400 µA 0.4 2.0 V 0.4 V 0.2 VDD V 0.5 V Note For use the P07/XT1 P07/XT1 pin as P07, input the reverse phase of P07 to the XT2 pin. Remark The characteristics of dual-function pins and port pins are the same unless otherwise specified. 42 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y DC Characteristics (TA = ­40 to +85°C, VDD = 2.7 to 6.0 V) Parameter Input leakage current, high Symbol ILIH1 Test Conditions ILIH2 MAX Unit P00 to P06, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P72, P120 to P127, P130, P131, RESET 3 µA X1, X2, XT1/P07 XT1/P07, XT2 VIN = VDD MIN. TYP. 20 µA ILIH3 Input leakage current, low VIN = 15 V P60 to P63 80 µA ILIL1 VIN = 0 V P00 to P06, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131, RESET ­3 µA X1, X2, XT1/P07 XT1/P07, XT2 ­20 µA ­3 Note 1 µA ILIL2 ILIL3 P60 to P63 Output leakage current, high ILOH VOUT = VDD 3 µA Output leakage current, low ILOL VOUT = 0 V ­3 µA Mask option R1 VIN = 0 V, P60 to P63 R2 VIN = 0 V, P01 to P06, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P64 to P67, P70 to P72, P120 to P127, P130, P131 20 40 90 k 4.5 V VDD 6.0 V 15 40 90 k 2.7 V VDD < 4.5 V 20 500 k pull-up resistor Software pull-up resistor Note 2 Notes 1. If no pull-up resistor is connected in P60 to P63 (specified with mask option), a ­200 µA (MAX.) low-level input leak current flows only during the 1.5-clock interval (no wait interval) during which a read instruction is executed for port 6 (P6) and port mode register (PM6). The leak current is ­3 µA (MAX.) at all times other than the 1.5-clock interval during which the read instruction is executed. 2. A software pull-up resistor can be used only in the range of VDD = 2.7 to 6.0 V. Remark The characteristics of dual-function pins and port pins are the same unless otherwise specified. 43 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y DC Characteristics (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) Parameter Symbol Test Conditions MIN. TYP. MAX Unit IDD2 VDD = 5.0 V ±10 % 4 12 mA VDD = 3.0 V ±10 % Note 2 0.6 1.8 mA VDD = 2.2 V ±10 % Note 2 0.35 1.05 mA VDD = 5.0 V ±10 % Note 1 6.5 19.5 mA operating mode (fXX = 5.0 MHz) Note 4 IDD1 5.0 MHz Crystal oscillation operating mode (fXX = 2.5 MHz) Note 3 5.0 MHz Crystal oscillation Power supply current Note 5 Note 1 VDD = 3.0 V ±10 % Note 2 0.8 2.4 mA 1.4 4.2 mA VDD = 5.0 V ±10 % 0.5 1.5 mA VDD = 2.2 V ±10 % 280 840 µA 5.0 MHz Crystal oscillation VDD = 5.0 V ±10 % 1.6 4.8 mA VDD = 3.0 V ±10 % 0.65 1.95 mA VDD = 5.0 V ±10 % 60 120 µA VDD = 3.0 V ±10 % 32 64 µA VDD = 2.2 V ±10 % IDD4 VDD = 3.0 V ±10 % HALT mode (fXX = 5.0 MHz) IDD3 5.0 MHz Crystal oscillation HALT mode (fXX = 2.5 MHz) Note 3 24 48 µA VDD = 5.0 V ±10 % 25 55 µA Note 4 32.768 kHz Crystal oscillation operating mode Note 6 32.768 kHz Crystal oscillation HALT mode Note 6 15 µA 2.5 12.5 µA XT1 = VDD STOP mode VDD = 5.0 V ±10 % 1 30 µA VDD = 3.0 V ±10 % 0.5 10 µA When feedback resistor is used VDD = 2.2 V ±10 % 0.3 10 µA XT1 = VDD STOP mode VDD = 5.0 V ±10 % 0.1 30 µA VDD = 3.0 V ±10 % 0.05 10 µA When feedback resistor is unused IDD6 5 VDD = 2.2 V ±10 % IDD5 VDD = 3.0 V ±10 % VDD = 2.2 V ±10 % 0.05 10 µA Notes 1. The on-chip pull-up resistor, AVREF0, AVREF1, AVDD current, and port current are not included. 2. Operation with main system clock fXX = fX/2 (when oscillation mode selection register (OSMS) is set to 00H) 3. Operation with main system clock fXX = fX (when OSMS is set to 01H) 4. When the main system clock operation is halted. 5. Operating in high-speed mode (when the processor clock control register (PCC) is set to 00H.) 6. Operating in low-speed mode (when PCC is set to 04H) 44 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y AC Characteristics (1) Basic Operation (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) Parameter Cycle time (Min. instruction Symbol TCY Test Conditions MIN. MAX. Unit 0.8 64 µs Operating on main system clock (fXX = 2.5 MHz)Note 1 VDD = 2.7 to 6.0 V 2.2 64 µs Operating on main system clock (fXX = 5.0 MHz)Note 2 execution time) 4.5 V VDD 6.0 V 0.4 32 µs 2.7 V VDD < 4.5 V 0.8 32 µs 125 µs 40Note 3 Operating on sub system clock TI00 input high-/low-level width TYP. tTIH00, tTIL00 122 3.5 V VDD 6.0 V 2/fsam + 0.1Note4 µs 2.7 V VDD < 3.5 V 2/fsam + 0.2Note4 µs Note4 µs 2/fsam + 0.5 10 µs 20 µs TI01 input high-/low-level width tTIH01, tTIL01 VDD = 2.7 to 6.0 V TI1, TI2 input frequency fTI1 VDD = 4.5 to 6.0 V 0 4 MHz 0 275 kHz TI1, TI2 input high-/low-level width tTIH1, tTIL1 VDD = 4.5 to 6.0 V 100 ns µs 1.8 INTP1 to INTP6, KR0 to KR7 RESET low level width tRSL µs 2.7 V VDD < 3.5 V 2/fsam + 0.2 INTP0 Note4 µs 2/fsam + 0.5 Note4 tINTH, tINTL 3.5 V VDD 6.0 V 2/fsam + 0.1 µs 10 µs 20 Interrupt request input high-/ low-level width Note4 µs 10 µs 20 µs VDD = 2.7 to 6.0 V VDD = 2.7 to 6.0 V Notes 1. Main system clock fXX = fX/2 operation (when an oscillation mode selection register (OSMS) is set to 00H) 2. Main system clock fXX = fX operation (when OSMS is set to 01H) 3. On an external clock. When a crystal resonator is used, the minimum value is 114 µs. 4. In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock selection register, fsam is selectable between fXX/2N, fXX/32, fXX/64, and fXX/128 (when N= 0 to 4). 45 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y TCY vs VDD (At fXX = fX/2 main system clock operation) TCY vs VDD (At fXX = fX main system clock operation) 60 60 10 Operation Guaranteed Range Cycle Time TCY [µs] Cycle Time TCY [µs] 10 2.0 1.0 0.5 0.4 0 2.0 1.0 0.5 0.4 1 2 3 4 5 Supply Voltage VDD [V] 46 Operation Guaranteed Range 6 0 1 2 3 4 5 Supply Voltage VDD [V] 6 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y (2) Read/write Operation (a) When MCS = 1, PCC2 to PCC0 = 000B (TA = ­40 to +85°C, VDD = 4.5 to 6.0 V) Parameter Symbol Test Conditions MIN. MAX. Unit ASTB high-level width tASTH 0.85tCY ­ 50 ns Address setup time tADS 0.85tCY ­ 50 ns Address hold time tADH 50 ns Data input time from address tADD1 (2.85 + 2n)tCY ­ 80 ns tADD2 (4 + 2n)tCY ­ 100 ns tRDD1 (2 + 2n)tCY ­ 100 ns tRDD2 (2.85 + 2n)tCY ­ 100 ns Data input time from RD Read data hold time tRDH 0 ns RD low-level width tRDL1 (2 + 2n)tCY ­ 60 ns tRDL2 (2.85 + 2n)tCY ­ 60 ns WAIT input time from RD tRDWT1 0.85tCY ­ 50 ns tRDWT2 2tCY ­ 60 ns WAIT input time from WR tWRWT 2tCY ­ 60 ns WAIT low-level width tWTL (1.15 + 2n)tCY (2 + 2n)tCY ns Write data setup time tWDS (2.85 + 2n)tCY ­ 100 ns Write data hold time tWDH 20 ns WR low-level width tWRL (2.85 + 2n)tCY ­ 60 ns RD delay time from ASTB tASTRD 25 ns WR delay time from ASTB tASTWR 0.85tCY + 20 ns ASTB delay time from RD in external fetch tRDAST 0.85tCY ­ 10 1.15tCY + 20 ns Address hold time from tRDADH 0.85tCY ­ 50 1.15tCY + 50 ns Write data output time from RD tRDWD 40 Write data output time from WR tRDWD 0 50 ns Address hold time from WR tWRADH 0.85tCY 1.15tCY + 40 ns RD delay time from WAIT tWTRD 1.15tCY + 40 3.15tCY + 40 ns WR delay time from WAIT tWTWR 1.15tCY + 30 3.15tCY + 30 ns RD in external fetch ns Remarks 1. MCS: Oscillation mode selection register (OSMS) bit 0 2. PCC2 to PCC0: Processor clock control register (PCC) bit 2 to 0 3. tCY = TCY/4 4. n indicates number of waits. 47 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y (b) Except when MCS = 1, PCC2 to PCC0 = 000B (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) (1/2) Parameter ASTB high-level width Symbol tASTH Test Conditions MIN. Unit ns Data input time from address tADD1 VDD = 2.7 to 6.0 V tCY ­ 80 ns ns 0.4tCY ­ 10 ns 0.37tCY ­ 40 tADH VDD = 2.7 to 6.0 V ns tCY ­ 150 Address hold time tADS tCY ­ 80 tCY ­ 150 Address setup time VDD = 2.7 to 6.0 V MAX. ns VDD = 2.7 to 6.0 V (3 + 2n)tCY ­ 160 ns (3 + 2n)tCY ­ 320 ns tADD2 (4 + 2n)tCY ­ 200 ns (4 + 2n)tCY ­ 300 ns tRDD1 VDD = 2.7 to 6.0 V (1.4 + 2n)tCY ­ 70 ns (1.37 + 2n)tCY ­ 120 Data input time from RD VDD = 2.7 to 6.0 V ns (2.4 + 2n)tCY ­ 70 ns tRDD2 VDD = 2.7 to 6.0 V (2.37 + 2n)tCY ­ 120 Read data hold time tRDH RD low-level width tRDL1 VDD = 2.7 to 6.0 V tRDL2 VDD = 2.7 to 6.0 V ns 0 ns (1.4 + 2n)tCY ­ 20 ns (1.37 + 2n)tCY ­ 20 tRDWT1 ns (2.37 + 2n)tCY ­ 20 WAIT input time from RD ns (2.4 + 2n)tCY ­ 20 ns WAIT low-level width tWTL Write data setup time tWDS (1 + 2n)tCY VDD = 2.7 to 6.0 V ns 2tCY ­ 100 VDD = 2.7 to 6.0 V ns ns 2tCY ­ 200 tWRWT ns 2tCY ­ 100 VDD = 2.7 to 6.0 V ns 2tCY ­ 200 WAIT input time from WR tCY ­ 100 tCY ­ 200 tRDWT2 VDD = 2.7 to 6.0 V ns (2 + 2n)tCY ns tWRL VDD = 2.7 to 6.0 V RD delay time from ASTB tASTRD VDD = 2.7 to 6.0 V ns ns (2.4 + 2n)tCY ­ 20 ns tWDH WR low-level width ns 20 Write data hold time (2.4 + 2n)tCY ­ 60 (2.37 + 2n)tCY ­ 100 (2.37 + 2n)tCY ­ 20 VDD = 2.7 to 6.0 V ns 1.4tCY ­ 30 ns 1.37tCY ­ 50 tASTWR ns 0.37tCY ­ 50 WR delay time from ASTB ns 0.4tCY ­ 30 ns Remarks 1. MCS: Oscillation mode selection register (OSMS) bit 0 2. PCC2 to PCC0: Processor clock control register (PCC) bit 2 to 0 3. tCY = TCY/4 4. n indicates the number of waits. 48 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y (b) Except when MCS = 1, PCC2 to PCC0 = 000B (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) (1/2) Parameter Symbol Test Conditions MIN. MAX. Unit ASTB delay time from RD in external fetch tRDAST tCY ­ 10 tCY + 20 ns Address hold time from RD in external fetch tRDADH tCY ­ 50 tCY + 50 ns Write data output time from RD tRDWD ns ns RD delay time from WAIT ns tCY + 60 ns tCY + 120 ns VDD = 2.7 to 6.0 V 0.6tCY + 180 2.6tCY + 180 ns 2.63tCY + 350 ns 0.6tCY + 120 2.6tCY + 120 ns 0.63tCY + 240 tWTWR VDD = 2.7 to 6.0 V ns tCY VDD = 2.7 to 6.0 V 60 0.63tCY + 350 WR delay time from WAIT tWTRD VDD = 2.7 to 6.0 V 120 tCY tWRADH 0 0 Address hold time from WR tWRWD 0.4tCY ­ 20 0.37tCY ­ 40 Write data output time from WR VDD = 2.7 to 6.0 V 2.63tCY + 240 ns Remarks 1. MCS: Oscillation mode selection register (OSMS) bit 0 2. PCC2 to PCC0: Processor clock control register (PCC) bit 2 to 0 3. tCY = TCY/4 4. n indicates number of waits. 49 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y (3) Serial Interface (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V) (a) Serial interface channel 0 (i) 3-wire serial I/O mode (SCK0. Internal clock output) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit tSIK1 (to SCK0) SI0 hold time (from SCK0) tKSO1 ns VDD = 4.5 to 6.0 V tKCY1/2 ­ 50 ns ns 4.5 V VDD 6.0 V 100 ns 150 ns ns 400 ns tKSI1 SO0 output delay time from SCK0 ns 300 SI0 setup time 1600 2.7 V VDD < 4.5 V tKH1, tKL1 ns tKCY1/2 ­ 100 SCK0 high-/low-level width 800 3200 tKCY1 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V SCK0 cycle time C = 100 pF Note 300 ns MAX. Unit Note C is the load capacitance of SCK0, SO0 output line. (ii) 3-wire serial I/O mode (SCK0. External clock input) Parameter Symbol tKCY2 Test Conditions MIN. TYP. 4.5 V VDD 6.0 V 800 ns 2.7 V VDD < 4.5 V SCK0 cycle time 1600 ns 3200 ns 400 ns 2.7 V VDD < 4.5 V tKH2, tKL2 4.5 V VDD 6.0 V 800 ns 1600 SCK0 high-/low-level width ns SI0 setup time (to SCK0) tSIK2 100 ns SI0 hold time (from tKSI2 400 ns SCK0) SO0 output delay time from SCK0 tKSO2 C = 100 pF Note 300 ns SCK0 rise, fall time tR2, tF2 When using external device expansion function 160 ns When not using external device expansion function 1000 ns Note C is the load capacitance of SO0 output line. 50 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y (iii) 2-wire serial I/O mode (SCK0. Internal clock output) Parameter SCK0 cycle time Symbol tKCY3 Test Conditions R = 1 k, MIN. VDD = 2.7 to 6.0 V TYP. MAX. Unit 1600 ns 3200 ns tKCY3/2 ­ 160 ns tKCY3/2 ­ 190 ns tKCY3/2 ­ 50 ns tKCY3/2 ­ 100 ns 4.5 V VDD 6.0 V 300 ns 2.7 V VDD < 4.5 V 350 ns 400 ns ns C = 100 pF Note SCK0 high-level width tKH3 VDD = 2.7 to 6.0 V SCK0 low-level width tKL3 VDD = 4.5 to 6.0 V SB0, SB1 setup time tSIK3 (to SCK0) SB0, SB1 hold time (from SCK0) tKSI3 600 SB0, SB1 output delay time from SCK0 tKSO3 0 300 ns Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output line. (iv) 2-wire serial I/O mode (SCK0. External clock input) Parameter Symbol Test Conditions SCK0 high-level width tKCY4 tKH4 VDD = 2.7 to 6.0 V MIN. TYP. MAX. Unit ns ns VDD = 2.7 to 6.0 V ns ns 800 ns 1600 tKL4 650 1300 SCK0 low-level width VDD = 2.7 to 6.0 V 1600 3200 SCK0 cycle time ns SB0, SB1 setup time (to SCK0) tSIK4 100 ns SB0, SB1 hold time (from SCK0) tKSI4 tKCY4/2 ns SB0, SB1 output delay time from SCK0 tKSO4 SCK0 rise, fall time tR4, tF4 R = 1 k, C = 100 pF VDD = 4.5 to 6.0 V Note When using external device expansion function When not using external device expansion function 0 300 ns 0 500 ns 160 ns 1000 ns Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output line. 51 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y (v) I2C Bus mode (SCL.Internal clock output) Parameter SCL cycle time Symbol tKCY5 Test Conditions R = 1 k C = 100pF MIN. TYP. MAX. Unit Note SCL high-level width tKH5 VDD = 2.7 to 6.0 V SCL low-level width tKL5 VDD = 4.5 to 6.0 V 10 µs 20 VDD = 2.7 to 6.0 V µs tKCY5 ­ 160 ns tKCY5 ­ 190 ns ns ns 0 tKSI5 200 300 SDA0, SDA1 setup time tSIK5 (to SCL) SDA0, SDA1 hold time ns tKCY5 ­ 100 VDD = 2.7 to 6.0 V ns tKCY5 ­ 50 ns (to SCL) SDA0, SDA1 output delay time from SCL tKSO5 VDD = 4.5 to 6.0 V 0 300 ns 0 500 ns SCLSDA0, SDA1 tKSB or SCLSDA0, SDA1 200 ns SDA0, SDA1SCL tSBK 400 ns SDA0, SDA1 high-level width tSBH 500 ns Note R and C are the load resistance and load capacitance of the SCK0, SB0, and SB1 output line. (vi) I2C Bus mode (SCL.External clock input) Parameter SCL cycle time Symbol Test Conditions tKCY6 MIN. TYP. MAX. Unit 1000 ns SCL high-/low-level width tKH6, tKL6 400 ns SDA0, SDA1 setup time tSIK6 (to SCL) 200 ns 0 ns SDA0, SDA1 hold time (to SCL) tKSI6 SCL SDA0, SDA1 output delay time tKSO6 R = 1 k, C = 100 pF VDD = 4.5 to 6.0 V Note 0 300 ns 0 500 ns SCLSDA0, SDA1 tKSB or SCLSDA0, SDA1 200 ns SDA0, SDA1 SCL tSBK 400 ns SDA0, SDA1 high-level width tSBH 500 ns SCL rise, fall time tR6, tF6 When using external device expansion function 160 ns When not using external device expansion function 1000 ns Note R and C are the load resistance and load capacitance of the SDA0, SDA1 output line. 52 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y (b) Serial interface channel 1 (i) 3-wire serial I/O mode (SCK1. Internal clock output) Parameter SCK1 cycle time Symbol tKCY7 Test Conditions MIN. 4.5 V VDD 6.0 V TYP. MAX. 800 2.7 V VDD < 4.5 V Unit ns 1600 ns 3200 ns tKCY7/2 ­ 50 ns tKCY7/2 ­ 100 ns 4.5 V VDD 6.0 V 100 ns 2.7 V VDD < 4.5 V 150 ns 300 ns 400 ns SCK1 high-/low-level width tKH7, tKL7 VDD = 4.5 to 6.0 V SI1 setup time (to SCK1) tSIK7 SI1 hold time (from SCK1) tKSI7 SO1 output delay time from SCK1 tKSO7 C = 100 pF Note 300 ns MAX. Unit Note C is the load capacitance of the SCK1 and SO1 output lines. (ii) 3-wire serial I/O mode (SCK1. External clock input) Parameter Symbol Test Conditions MIN. TYP. tKCY8 4.5 V VDD 6.0 V 800 ns 2.7 V VDD < 4.5 V SCK1 cycle time 1600 ns 3200 ns tKH8, tKL8 4.5 V VDD 6.0 V 400 ns 2.7 V VDD < 4.5 V 800 ns 1600 SCK1 high-/low-level width ns SI1 setup time (to SCK1) tSIK8 100 ns SI1 hold time (from SCK1) tKSI8 400 ns SO1 output delay time from SCK1 tKSO8 C = 100 pF SCK1 rise, fall time tR8, tF8 When using external device expansion function Note When not using external device expansion function 300 ns 160 ns 1000 ns Note C is the load capacitance of the SO1 output line. 53 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y (iii) 3-wire serial I/O mode with automatic transmit/receive function (SCK1.Internal clock output) Parameter SCK1 high-/low-level width tKH9, MIN. 4.5 V VDD 6.0 V 800 ns 1600 ns 3200 tKCY9 Test Conditions 2.7 V VDD < 4.5 V SCK1 cycle time Symbol ns tKCY9/2 ­ 50 ns VDD = 4.5 to 6.0 V tKL9 TYP. MAX. Unit SI1 hold time (from SCK1) tKSO9 STB from SCK1 tSBW ns 150 ns ns tSBD Strobe signal high-level width ns 100 tKSI9 SO1 output delay time from SCK1 tKCY9/2 ­ 100 300 tSIK9 4.5 V VDD 6.0 V 2.7 V VDD < 4.5 V SI1 setup time (to SCK1) 400 ns C = 100 pF Note tBYS Busy signal hold time (from busy signal detection timing) tBYH tKCY9/2 + 100 ns tKCY9 ­ 30 tKCY9 + 30 ns tKCY9 ­ 60 Busy signal setup time (to busy signal detection timing) ns tKCY9/2 ­ 100 VDD = 2.7 to 6.0V 300 tKCY9 + 60 ns ns 4.5 V VDD 6.0 V 100 ns 2.7 V VDD < 4.5 V 150 ns 200 SCK1 from busy inactive 100 ns tSPS 2tKCY9 ns Note C is the load capacitance of the SCK1, SO1 output line. (iv) 3-wire serial I/O mode with automatic transmit/receive function (SCK1.External clock input) Parameter Symbol tKCY10 Test Conditions MIN. 4.5 V VDD 6.0 V 800 ns 2.7 V VDD < 4.5 V SCK1 cycle time TYP. MAX. Unit 1600 ns 3200 ns tKH10, 4.5 V VDD 6.0 V 400 ns tKL10 2.7 V VDD < 4.5 V 800 ns 1600 SCK1 high-/low-level width ns SI1 setup time (to SCK1) tSIK10 100 ns SI1 hold time (from SCK1) tKIS10 400 ns SO1 output delay time from SCK1 tKSO10 C = 100 pF SCK1 rise, fall time tR10, tF10 Note 300 ns When using external device expansion function 160 ns When not using external device expansion function 1000 ns Note C is the load capacitance of the SO1 output line. 54 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y (c) Serial interface channel 2 (i) 3-wire serial I/O mode (SCK2. Internal clock output) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit tKCY11 4.5 V VDD 6.0 V 800 ns 2.7 V VDD < 4.5 V SCK2 cycle time 1600 ns 3200 width tSIK11 ns tKCY11/2 ­ 100 ns 4.5 V VDD 6.0 V 100 ns 150 ns ns 400 ns tKL11 SI2 setup time ns 300 tKH11, tKCY11/2 ­ 50 2.7 V VDD < 4.5 V SCK2 high-/low-level (to SCK2) SI2 hold time (to SCK2) tKSI11 SO2 output delay time from SCK2 tKSO11 VDD = 4.5 to 6.0 V C = 100 pF Note 300 ns MAX. Unit 4.5 V VDD 6.0 V 78125 bps 2.7 V VDD < 4.5 V 39063 bps 19531 bps MAX. Unit Note C is the load capacitance of the SCK2, SO2 output line. (ii) UART mode (Dedicated baud rate generator output) Parameter Symbol Transfer rate Test Conditions MIN. TYP. (iii) UART mode (External clock input) Parameter Symbol tKCY12 Test Conditions MIN. TYP. 4.5 V VDD 6.0 V 800 ns 2.7 V VDD < 4.5 V ASCK cycle time 1600 ns 3200 tKH12, tKL12 ns 4.5 V VDD 6.0 V 400 ns 2.7 V VDD < 4.5 V 800 ns 1600 ASCK high-/low-level width ns 4.5 V VDD 6.0 V tR12, tF12 bps 19531 bps 9766 ASCK rise, fall time 39063 2.7 V VDD < 4.5 V Transfer rate bps 1000 ns 160 ns VDD = 4.5 to 6.0 V, when not using external device expansion function. 55 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y AC Timing Test Point (Excluding X1, XT1 Input) 0.8 VDD 0.2 VDD 0.8 VDD 0.2 VDD Test Points Clock Timing 1/fX tXL tXH VIH4 (MIN.) VIL4 (MAX.) X1 Input 1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.) XT1 Input TI Timing tTIL00, tTIL01 tTIH00, tTIH01 TI00, TI01 1/fTI1 tTIL1 TI1, TI2 56 tTIH1 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Read/Write Operation External Fetch (No Wait) : A8 to A15 Higher 8-Bit Address Lower 8-Bit Address tADD1 Hi-z AD0 to AD7 tADS tASTH Operation Code tRDADH tRDD1 tADH tRDAST ASTB RD tRDL1 tASTRD tRDH External Fetch (Wait Insertion) : A8 to A15 Higher 8-Bit Address Lower 8-Bit Address tADD1 Hi-z AD0 to AD7 Operation Code tRDADH tRDD1 tADS tASTH tADH tRDAST ASTB RD tASTRD tRDL1 tRDH WAIT tRDWT1 tWTL tWTRD 57 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y External Data Access (No Wait) : A8 to A15 Higher 8-Bit Address Lower 8-Bit Address tADD2 Hi-z AD0 to AD7 Read Data Hi-z Hi-z Write Data tRDD2 tADS tADH tRDH tASTH ASTB RD tASTRD tRDWD tRDL2 tWDH tWDS tWDWR WR tASTWR tWRL tWRADH External Data Access (Wait Insertion) : A8 to A15 Higher 8-Bit Address Lower 8-Bit Address tADD2 Hi-z AD0 to AD7 Read Data Hi-z Hi-z Write Data tRDD2 tADS tADH tRDH tASTH ASTB tASTRD RD tRDWD tRDL2 tWDH tWDS tWDWR WR tASTWR tWRL tWRADH WAIT tRDWT2 tWTRD tWTL 58 tWRWT tWTL tWTWR µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Serial Transfer Timing 3-wire Serial I/O Mode : tKCYm tKLm tKHm tRn tFn SCK0 to SCK2 tSIKm SI0 to SI2 tKSIm Input Data tKSOm Output Data SO0 to SO2 m = 1, 2, 7, 8, 11 n = 2, 8 2-wire Serial I/O Mode : tKCY3, 4 tKL3, 4 tR4 tKH3, 4 tF4 SCK0 tSIK3, 4 tKSO3, 4 tKSI3, 4 SB0, SB1 I2C Bus Mode: tF6 tR6 tKCY5, 6 SCL tKL5, 6 tKSI5, 6 tKH5, 6 tSIK5, 6 tKSO5, 6 tKSB tKSB tSBK SDA0, SDA1 tSBH tSBK 59 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 3-wire Serial I/O Mode with Automatic Transmit/Receive Function : SO1 SI1 D2 D1 D2 D0 D1 D7 D0 D7 tKSI9, 10 tSIK9, 10 tKH9, 10 tKSO9, 10 tF10 SCK1 tR10 tKL9, 10 tKCY9, 10 tSBD tSBW STB 3-wire Serial I/O Mode with Automatic Transmit/Receive Function (Busy processing) : 7 SCK1 8 9 Note 10 Note tBYS 10+n Note tBYH tSPS BUSY (Active high) Note The signal is not actually driven low here; it is shown as such to indicate the timing. UART Mode (External Clock Input) : t KCY12 KCY12 t KL12 t KH12 tR12 ASCK 60 1 tF12 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y A/D Converter Characteristics (TA = ­40 to +85°C, AVDD = VDD = 2.0 to 6.0 V, AVSS = VSS = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 8 8 8 bit 2.7 V AVREF0 AVDD ±0.6 % 2.0 V AVREF0 < 2.7 V ±1.4 % 200 µs Resolution Overall error Note Conversion time tCONV 19.1 Sampling time tSAMP 12/fxx Analog input voltage VIAN AVSS Reference voltage AVREF0 2.0 Resistance between AVREF0 and AVSS RAIREF0 4 µs AVREF0 AVDD V V k 14 Note Overall error excluding quantization error (±1/2 LSB). It is indicated as a ratio to the full-scale value. fXX : Main system clock frequency (fX or fX/2) fX : Main system clock oscillation frequency D/A Converter Characteristics (TA = ­40 to +85°C, VDD = 2.0 to 6.0 V, AVSS = VSS = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit 8 bit R = 2 M Note1 1.2 % R = 4 M Note1 0.8 % 0.6 % Resolution Overall error R = 10 M Note1 C=30pF 4.5 V AVREF1 6.0 V 10 µs Note1 Settling time 2.7 V AVREF1 < 4.5 V 15 µs 2.0 V AVREF1 < 2.7 V Output resistance RO Analog reference voltage AVREF1 AVREF1 current IREF1 20 DACS0, DACS1 = 55H Note 2 10 2.0 Note2 µs k VDD V 1.5 mA Notes 1. R and C denote D/A converter output pin load resistance and load capacitance, respectively. 2. Value for one D/A converter channel DACS0, DACS1: D/A conversion value setting register. 61 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics (TA = ­40 to +85°C) Parameter Data retention power Symbol Test Conditions MIN. VDDDR TYP. Unit 6.0 1.8 MAX. V 10 µA supply voltage Data retention power supply current IDDDR Release signal set time tSREL Oscillation stabiliation wait time tWAIT VDDDR = 1.8 V Subsystem clock stop and feedback resistor disconnected 0.1 µs 0 217/fx ms Release by interrupt request Note Release by RESET Note ms In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time selection register (OSTS), selection of 212/fXX and 214/fXX to 217/fXX is possible. fXX : Main system clock frequency (fX or fX/2) fX : Main system clock oscillation frequency Data Retention Timing (STOP Mode Release by RESET) Internal Reset Operation HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution RESET tWAIT Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Request Signal) HALT Mode Operating Mode STOP Mode Data Retention Mode VDD VDDDR tSREL STOP Instruction Execution Standby Release Signal (Interrupt Request) tWAIT 62 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Interrupt Request Input Timing tINTL tINTH INTP0 to INTP6 RESET Input Timing tRSL RESET 63 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 12. CHARACTERISTIC CURVES (REFERENCE VALUE) IDD vs VDD (fx = fxx = 5.0 MHz) (TA = 25°C) 10.0 PCC = 00H PCC = 01H 5.0 PCC = 02H PCC = 03H PCC = 04H PCC = 30H HALT (X1 oscillation, XT1 oscillation) 1.0 Supply Current IDD (mA) 0.5 0.1 PCC = B0H 0.05 HALT (X1 stop, XT1 oscillation) 0.01 0.005 0.001 0 2 3 4 5 6 Supply Voltage VDD (V) 64 7 8 9 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y IDD vs VDD (fx = 5.0 MHz, fxx = 2.5 MHz) (TA = 25°C) 10.0 PCC = 00H 5.0 PCC = 01H PCC = 02H PCC = 03H PCC = 04H PCC = 30H HALT (X1 oscillation, XT1 oscillation) 1.0 Supply Current IDD (mA) 0.5 0.1 PCC = B0H 0.05 HALT (X1 Stop, XT1 oscillation) 0.01 0.005 0.001 0 2 3 4 5 6 7 8 9 Supply Voltage VDD (V) 65 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 13. PACKAGE DRAWING 80 PIN PLASTIC QFP (14×14) A B 60 61 41 40 detail of lead end C S D R Q 80 1 21 20 F G H I M J P K M N NOTE L ITEM MILLIMETERS INCHES A 17.20±0.20 0.677±0.008 B 14.00±0.20 0.551 +0.009 ­0.008 C 14.00±0.20 0.551 +0.009 ­0.008 D 17.20±0.20 0.677±0.008 F 0.825 0.032 G 0.825 0.032 H Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition. 0.32±0.06 0.013 +0.002 ­0.003 I 0.13 0.005 J 0.65 (T.P.) 0.026 (T.P.) K 1.60±0.20 0.063±0.008 L 0.80±0.20 0.031 +0.009 ­0.008 M 0.17 +0.03 ­0.07 0.007 +0.001 ­0.003 N 0.10 0.004 P 1.40±0.10 0.055±0.004 Q 0.125±0.075 0.005±0.003 R 3° +7° ­3° 3° +7° ­3° S 1.70 MAX. 0.067 MAX. P80GC-65-8BT P80GC-65-8BT Remark Dimensions and materials of ES product are the same as those of mass-production products. 66 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y 14. RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the conditions recommended in the table below. For a detailed description of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 14-1. Surface Mounting Type Soldering Conditions µPD78052YGC-xxx-8BT : 80-pin plastic QFP (14 × 14 mm) µPD78053YGC-xxx-8BT : 80-pin plastic QFP (14 × 14 mm) µPD78054YGC-xxx-8BT : 80-pin plastic QFP (14 × 14 mm) µPD78055YGC-xxx-8BT : 80-pin plastic QFP (14 × 14 mm) µPD78056YGC-xxx-8BT : 80-pin plastic QFP (14 × 14 mm) µPD78058YGC-xxx-8BT : 80-pin plastic QFP (14 × 14 mm) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow Package peak temperature: 235 °C, Duration: 30 sec. max. (at 210°C or above), Number of times: Twice max. IR35-00-2 IR35-00-2 VPS Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200°C or above), Number of times: Twice max. VP15-00-2 VP15-00-2 Wave soldering Solder bath temperature : 260°C max., Duration : 10 sec. max., Number of times: once, Preheating temperature : 120°C max. (package surface temperature) WS60-00-1 WS60-00-1 Partial heating Pin temperature: 300°C max. Duration: 3 sec. max. (per pin row) Caution - Avoid as much as possible combining two or more soldering methods (except for the partial heating method). 67 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y APPENDIX A. DEVELOPMENT TOOLS The following development tools are available for system development using µPD78054Y PD78054Y subseries. Language Processing Software RA78K/0 RA78K/0 Notes 1, 2, 3, 4 78K/0 78K/0 series common assembler package CC78K/0 CC78K/0 Notes 1, 2, 3, 4 78K/0 78K/0 series common C compiler package DF78054 DF78054 Notes 1, 2, 3, 4 Device file common to µPD78054 PD78054 subseries CC78K/0-L CC78K/0-L Notes 1, 2, 3, 4 78K/0 78K/0 series common C compiler library source file PROM Writing Tools PG-1500 PG-1500 PROM programmer PA-78P054GC PA-78P054GC PA-78P054KK-T PA-78P054KK-T Programmer adapters connected to PG-1500 PG-1500 PG-1500 PG-1500 controller Notes 1, 2 PG-1500 PG-1500 control program Debugging Tools IE-78000-R IE-78000-R In-circuit emulator common to 78K/0 78K/0 series IE-78000-R-A IE-78000-R-A In-circuit emulator common to 78K/0 78K/0 series (for integrated debugger) IE-78000-R-BK IE-78000-R-BK Break board common to 78K/0 78K/0 series IE-780308-R-EM IE-780308-R-EM Emulation board common to µPD780308 PD780308 subseries IE-78000-R-SV3 IE-78000-R-SV3 Interface adapter and cable when using EWS for the host machine (for IE-78000-R-A IE-78000-R-A) IE-78000-98-IF-B IE-78000-98-IF-B Interface adapter when using the PC-9800 PC-9800 series (except for notebook computers) for the host machine (for IE-78000-R-A IE-78000-R-A) IE-78000-98N-IF IE-78000-98N-IF Interface adapter and cable when using the PC-9800 PC-9800 series notebook computers for the host machine (for IE-78000-R-A IE-78000-R-A) IE-78000-PC-IF-B IE-78000-PC-IF-B Interface adapter when using IBM/PC ATTM and its compatibles for the host machine (for IE-78000-R-A IE-78000-R-A) EP-78230GC-R EP-78230GC-R Emulation probe common to µPD78234 PD78234 subseries EV-9200GC-80 EV-9200GC-80 Socket to be mounted in the target system board manufactured for 80-pin plastic QFP (GC-8BT type) SM78K0 SM78K0 ID78K0 ID78K0 Notes 5, 6, 7 Notes 4, 5, 6, 7 SD78K/0 SD78K/0 Notes 1, 2 DF78054 DF78054 Notes 1, 2, 4, 5, 6, 7 System simulator common to 78K/0 78K/0 series Integrated debugger for IE-78000-R-A IE-78000-R-A Screen debugger for IE-78000-R IE-78000-R Device file common to µPD78054 PD78054 subseries Notes 1. PC-9800 PC-9800 series (MS-DOSTM) based 2. IBM PC/AT and compatible computer (PC DOSTM/IBM DOSTM/MS-DOS) based 3. HP9000 HP9000 series 300TM 300TM (HP-UXTM) based 4. HP9000 HP9000 series 700TM 700TM (HP-UX) based, SPARCstationTM (Sun OSTM) based, EWS4800 EWS4800 series (EWS-UX/ V) based 5. PC-9800 PC-9800 series (MS-DOS + WindowsTM) based 6. IBM PC/AT and compatible computer (PC DOS/IBM DOS/MS-DOS + Windows) based 7. NEWSTM (NEWS-OSTM) based 68 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Real-Time OS RX78K/0 RX78K/0 Notes 1, 2, 3, 4 Real-time OS for 78K/0 78K/0 series MX78K0 MX78K0 Notes 1, 2, 3, 4 OS for 78K/0 78K/0 series Fuzzy Inference Development Support System FE9000 FE9000 Note 1 FT9080 FT9080 Note 1 FI78K0 FI78K0 / FE9200 FE9200 Note 5 Fuzzy knowledge data creation tool / FT9085 FT9085 Note 2 Translator Notes 1, 2 FD78K0 FD78K0 Notes 1, 2 Fuzzy inference module Fussy inference debugger Notes 1. PC-9800 PC-9800 series (MS-DOS) based 2. IBM PC/AT and its compatible computers (PC DOS/IBM DOS/MS-DOS) based 3. HP9000 HP9000 series 300 (HP-UX) based 4. HP9000 HP9000 series 700 (HP-UX) based, SPARCstation (Sun OS) based, EWS4800 EWS4800 series (EWS-UX/V) based 5. IBM PC/AT and its compatible computers (PC DOS/IBM DOS/MS-DOS + Windows) based Remarks 1. For third party development tools, see the 78K/0 78K/0 Series Selection Guide (U11126E U11126E). 2. RA78K/0 RA78K/0, CC78K/0 CC78K/0, SM78K0 SM78K0, ID78K0 ID78K0, SD78K/0 SD78K/0, and RX78K/0 RX78K/0 are used in combination with DF78054 DF78054. 69 µPD78052Y PD78052Y, 78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y APPENDIX B. RELATED DOCUMENTS Device Related Documents Document No. (English) Document Name µPD78052Y PD78052Y,78053Y 78053Y, 78054Y 78054Y, 78055Y 78055Y, 78056Y 78056Y, 78058Y 78058Y Data Sheet Document No. (Japanese) This document U10906J U10906J µPD78P058Y PD78P058Y Data Sheet U10907E U10907E U10907J U10907J µPD78054 PD78054 and µPD78054Y PD78054Y Subseries User's Manual IEU-1356 IEU-1356 U11747J U11747J 78K/0 78K/0 Series User's Manual Instructions U12326E U12326E U12326J U12326J 78K/0 78K/0 Series Instruction Set ­ U10904J U10904J 78K/0 78K/0 Series Instruction Table ­ U10903J U10903J µPD78054Y PD78054Y Special Function Register Table ­ U10087J U10087J U10182E U10182E U10182J U10182J Document No. (English) Document No. (Japanese) Operation EEU-1399 EEU-1399 EEU-809 EEU-809 Language EEU-1404 EEU-1404 EEU-815 EEU-815 EEU-1402 EEU-1402 U12323J U12323J 78K/0 78K/0 Series Application Note Basics (III) Development Tool Related Documents (User's Manual) Document Name RA78K RA78K Series Assembler Package RA78K RA78K Series Structured Assembler Preprocessor CC78K0 CC78K0 C Assembler Package Operation U11802E U11802E U11802J U11802J Assembly Language U11801E U11801E U11801J U11801J Structured Assembly Language CC78K0 CC78K0 C Compiler U11789E U11789E U11789J U11789J Operation EEU-1280 EEU-1280 EEU-656 EEU-656 Language CC78K CC78K Series C Compiler EEU-1284 EEU-1284 EEU-655 EEU-655 CC78K/0 CC78K/0 C Compiler Application Note Operation U11517E U11517E U11517J U11517J Language U11518E U11518E U11518J U11518J Programming Know-How EEA-1208 EEA-1208 EEA-618 EEA-618 U12322E U12322E U12322J U12322J CC78K CC78K Series Library Source File PG-1500 PG-1500 PROM Programmer U11940E U11940E U11940J U11940J PG-1500 PG-1500 Controller PC-9800 PC-9800 Series (MS-DOS) Based EEU-1291 EEU-1291 EEU-704 EEU-704 PG-1500 PG-1500 Controller IBM PC Series (PC DOS) Based U10540E U10540E EEU-5008 EEU-5008 IE-78000-R IE-78000-R U11376E U11376E U11376J U11376J IE-78000-R-A IE-78000-R-A U10057E U10057E U10057J U10057J IE-78000-R-BK IE-78000-R-BK EEU-1427 EEU-1427 EEU-867 EEU-867 IE-780308-R-EM IE-780308-R-EM U11362E U11362E U11362J U11362J EP-78230 EP-78230 EEU-1515 EEU-1515 EEU-985 EEU-985 SM78K0 SM78K0 System Simulator WIndows based Reference U10181E U10181E U10181J U10181J SM78K SM78K Series