PD77115 PD77115A PD77111 U14623J PD77016 U13116J RAM11 RAM16 PD77115F1-CN6

2010 4 1 NEC http://www.renesas.com 2010 4 1 http://www.renesas.com http://japan.renesas.com/inquiry 1. 2. 3. 4.

2010 4 1 NEC http://www.renesas.com 2010 4 1 http://www.renesas.com http://japan.renesas.com/inquiry 1. 2. 3. 4. 5. 6. 7. OA AV 8. 9. 10. RoHS 11. 12. 1. 2. 1 MOS MOS Integrated Circuit µ PD77115 PD77115, 77115A 16 µ PD77115 PD77115, 77115A16DSPDigital Signal Processor µ PD77115 PD77115 RAMDSP MPEG1 Audio Layer 3 MP3 AACMPEG2 Advanced Audio Coding1 µ PD77115 PD77115, µ PD77115A PD77115Aµ PD77115 PD77115 µ PD77111 PD77111 U14623J U14623J µ PD77016 PD77016 U13116J U13116J 13.3 ns75 MHz · RAM11 RAM11.5 K×32 · RAM16 RAM16 K×16×2 · · SDSecure Digital · 16 · 16 · 8 · DSP 2.02.7 V50 MHz 2.32.7 V75 MHz I/O 2.73.6V · TYP. 50 mW2.0 V50 MHz µ PD77115F1-CN6 PD77115F1-CN6 80FBGA9 80FBGA9×9 µ PD77115GK-9EU PD77115GK-9EU 80TQFP12 80TQFP12×12 µ PD77115AF1- PD77115AF1-×××-CN6 80FBGA9 80FBGA9×9 ×××ROM U14867JJ5V0DS005 U14867JJ5V0DS005 August 2004 NS CP(K) 2000, 2004 2 X Y X U14867JJ5V0DS U14867JJ5V0DS SD X Y R0-R7 Y DMA MAC 16 x 16 + 40 -> 40 ALU(40) BSFT PC CPU PLL RESET WAKEUP CLKOUT CLKIN PLL0-PLL3 P4-P7 PLL0-PLL3 µ PD77115 PD77115, 77115A INT1-INT4 µ PD77115 PD77115, 77115A + 2.5 V IVDD (8) (2) (16) RESET INT1-INT4 SDDAT SDCR SDCLK SD EVDD SO SOEN/LRCLK SCK/BCLK SI SIEN/MCLK +3V (2) (4) CLKIN CLKOUT WAKEUP (4) P0-P3,P4/PLL0-P7/PLL3 HCS HA0,HA1 HRD HRE HWR HWE HD0-HD15 HD0-HD15 TDO,TICE TCK,TDI,TMS,TRST GND PLL0-PLL3P4-P7 U14867JJ5V0DS U14867JJ5V0DS 3 4 DSP µ PD77110 PD77110 µ PD77111 PD77111 µ PD77112 PD77112 µ PD77113A PD77113A µ PD77114 PD77114 RAM 35.5 K×32 1 K×32 × ROM 31.75 K×32 3K×16 16K×16 16 K×16 µ PD77213 PD77213 31.5 K×32 15.5 K×32 48 K×32 24 K×16 µ PD77210 PD77210 11.5 K×32 3.5 K×32 µ PD77115 PD77115,77115A 32 K×16 RAM 64 K×32 16 K×16 30 K×16 18 K×16 X/Y ROM 32 K×16 X/Y 32 K×16 16 K×16 8 K×16 1 M×16 U14867JJ5V0DS U14867JJ5V0DS 1 M×16SD I/F 8 K×16 X/Y 6.25 ns 13.3 ns75 MHz 65 MHz 8.33 ns 160 MHz 15.3 ns 120 MHz ×18 ×116 ×116 ×1064 2 1 2 CODEC CODEC 16 8 8 16 1 16 216 - - - - - SDI/F - SDI/F DSP2.5 V 100TQFP 100TQFP 80FBGA 80FBGA 80TQFP 80TQFP DSP1.5 V I/O3 V I/O3 V 100TQFP 100TQFP 80FBGA 80FBGA 100TQFP 100TQFP 80FBGA 80FBGA 161FBGA 161FBGA 80TQFP 80TQFP 144LQFP 144LQFP µ PD77115 PD77115, 77115A 4 µ PD77115 PD77115, 77115A 80FBGA9 80FBGA9×9 µ PD77115F1-CN6 PD77115F1-CN6 µ PD77115AF1- PD77115AF1-×××-CN6 (Bottom View) (Top View) 9 8 7 6 5 4 3 2 1 J H G F E D C B A A B C D E F G H J A1 EVDD C3 SDDAT E6 GND G8 HRE A2 NC C4 GND E7 HWR G9 EVDD A3 EVDD C5 INT3 E8 EVDD H1 GND A4 IVDD C6 TRST E9 CLKOUT H2 EVDD A5 INT2 C7 TICE F1 EVDD H3 HD12 A6 RESET C8 TDO F2 P0 H4 EVDD A7 TDI C9 HA0 F3 P3 H5 GND A8 I.C. D1 SOEN/LRCLK F4 HD9 H6 HD2 A9 I.C. D2 P5/PLL1 F5 HD4 H7 IVDD B1 NC D3 SO F6 HRD H8 HD0 B2 SI D4 P7/PLL3 F7 HWE H9 GND B3 SDCR D5 SDCLK F8 CLKIN J1 NC B4 GND D6 INT4 F9 HCS J2 GND B5 WAKEUP D7 IVDD G1 P1 J3 HD13 B6 INT1 D8 HA1 G2 HD15 J4 HD10 B7 TMS D9 GND G3 HD14 J5 HD7 B8 TCK E1 P6/PLL2 G4 HD11 J6 HD6 B9 I.C. E2 P4/PLL0 G5 HD8 J7 HD3 C1 SIEN/MCLK E3 GND G6 HD5 J8 GND C2 SCK/BCLK E4 P2 G7 HD1 J9 I.C. U14867JJ5V0DS U14867JJ5V0DS 5 µ PD77115 PD77115, 77115A 80TQFP12 80TQFP12×12Top View 62 61 TRST TMS TDI I.C. TCK 71 70 69 68 67 66 65 64 63 SDDAT NC SDCR GND EVDD SDCLK GND IVDD WAKEUP INT1 INT2 INT3 INT4 RESET 80 79 78 77 76 75 74 73 72 EVDD µ PD77115GK-9EU PD77115GK-9EU SIEN/MCLK SCK/BCLK 3 4 58 57 I.C. I.C. SO 5 56 HA1 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 HA0 GND IVDD GND EVDD CLKIN CLKOUT HWR HRD HCS HWE HRE EVDD SOEN/LRCLK P7/PLL3 GND P6/PLL2 P5/PLL1 P4/PLL0 EVDD EVDD GND HD13 HD12 HD11 HD10 HD9 HD8 HD7 EVDD GND HD6 HD5 HD4 HD3 HD2 IVDD GND I.C. HD1 P3 P2 P1 P0 HD15 GND NC HD14 38 39 40 TICE 59 36 37 60 2 27 28 29 30 31 32 33 34 35 1 21 22 23 24 25 26 SI NC 6 U14867JJ5V0DS U14867JJ5V0DS TDO GND HD0 µ PD77115 PD77115, 77115A 1 SI 21 EVDD 41 HD0 61 TCK 2 NC 22 GND 42 GND 62 I.C. 3 SIEN/MCLK 23 HD13 43 EVDD 63 TDI 4 SCK/BCLK 24 HD12 44 HRE 64 TMS 5 SO 25 HD11 45 HWE 65 TRST 6 SOEN/LRCLK 26 HD10 46 HCS 66 RESET 7 P7/PLL3 27 HD9 47 HRD 67 INT4 8 GND 28 HD8 48 HWR 68 INT3 9 P6/PLL2 29 HD7 49 CLKOUT 69 INT2 10 P5/PLL1 30 EVDD 50 CLKIN 70 INT1 11 P4/PLL0 31 GND 51 EVDD 71 WAKEUP 12 EVDD 32 HD6 52 GND 72 IVDD 13 P3 33 HD5 53 IVDD 73 GND 14 P2 34 HD4 54 GND 74 SDCLK 15 P1 35 HD3 55 HA0 75 EVDD 16 P0 36 HD2 56 HA1 76 GND 17 HD15 37 IVDD 57 TDO 77 SDCR 18 GND 38 GND 58 I.C. 78 NC 19 NC 39 I.C. 59 I.C. 79 SDDAT 20 HD14 40 HD1 60 TICE 80 EVDD U14867JJ5V0DS U14867JJ5V0DS 7 µ PD77115 PD77115, 77115A CLKIN : Clock Input CLKOUT : Clock Output EVDD : Power Supply for I/O Pins GND : Ground HA0, HA1 : Host Data Access HCS : Host Chip Select HD0-HD15 HD0-HD15 : Host Data Bus HRD : Host Read HRE : Host Read Enable HWE : Host Write Enable HWR : Host Write I.C. : Internally Connected INT1-INT4 : Interrupt IVDD : Power Supply for DSP Core NC : Non-Connection P0-P3 : Port P4/PLL0-P7/PLL3 : Port/ PLL Setting Input RESET : Reset SCK/BCLK : Serial Clock Input/ Output SDCLK : SD Card Clock Output SDCR : SD Card Command Output/ Response Input SDDAT : SD Card Data Input/ Output SI : Serial Data Input SIEN/MCLK : Serial Input Enable/ Master Clock Input SO : Serial Data Output SOEN/LRCLK : Serial Output Enable/ Left Right Clock Input/ Output TCK : Test Clock Input TDI : Test Data Input TDO : Test Data Output TICE : Test In-Circuit Emulator TMS : Test Mode Select TRST : Test Reset WAKEUP : Wakeup from STOP Mode 8 U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A 1 10 . 1. 1 10 . 1. 2 2 . 14 15 . 2. 1 2. 2 16 . 2. 3 2. 4 3 . 16 . 17 18 . 3. 1 3. 2 PLL . 18 . 18 4ROM . 4. 1 4. 2 15 . . 18 19 . 4. 3 5 18 . 19 20 . 5. 1 HALT . 20 5. 2 STOP . 20 6 21 . 6. 1 . 21 6. 2 . 7 . 23 25 7. 1 25 . 7. 2 8 9 26 32 . . . 50 10 . 52 U14867JJ5V0DS U14867JJ5V0DS 9 µ PD77115 PD77115, 77115A 1 1. 1 80FBGA 80FBGA A4, D7, H7 EVDD A1, A3, E8, F1, 12, 21, 30, 43, GND 80TQFP 80TQFP IVDD 37, 53, 72 G9, H2, H4 - DSP2.5 V - - I/O3 V - - - 51, 75, 80 B4, C4, D9, E3, 8, 18, 22, 31, E6, H1, H5, H9, 38, 42, 52, 54, J2, J8 73, 76 80FBGA 80FBGA 80TQFP 80TQFP CLKIN F8 50 - CLKOUT E9 49 - RESET A6 66 - PLL0-PLL3 E2, D2, E1, D4 11-9, 7 PLL P4-P7 PLL3-PLL0 0000×16 0001×1 0010×2 0011×3 0100×4 0101×5 0110×6 0111×7 1000×8 1001×9 1010×10 1011×11 1100×12 1101×13 1110×14 1111×15 WAKEUP B5 71 - 80 FBGA INT1-INT4 B6, A5, C5, D6 80 TQFP 70-67 10 U14867JJ5V0DS U14867JJ5V0DS - µ PD77115 PD77115, 77115A 80 FBGA SCK/BCLK C2 80 TQFP 4 - SCK BCLK SOEN/ D1 6 - LRCLK SOEN LRCLK SO D3 5 - - 3S SIEN/MCLK C1 3 SIEN MCLK SI B2 1 - "3S"RESET SD 80 FBGA 80 TQFP SD - SD - 3S SDCLK D5 74 SDCR B3 77 C3 79 SD 3S SDDAT - "3S" SDI/F U14867JJ5V0DS U14867JJ5V0DS 11 µ PD77115 PD77115, 77115A 80 FBGA HA1 D8 80 TQFP 56 HD15-HD0 HD15-HD0 - 1 HST 0HRD= 0 HDTout HWR = 0 HDT in HA0 C9 55 HD15-HD0 HD15-HD0 - 1HSTHDTin HDTout 15-8 0HSTHDTin HDTout 7-0 8 16 HCS F9 46 - HRD F6 47 - HWR E7 48 - HRE G8 44 - HWE F7 45 - HD0-HD15 HD0-HD15 H8, G7, H6, J7, 41, 40, 36-32, 16 - F5, G6, J6, J5, 29-23, 20 ,17 3S G5, F4, J4, G4, H3, J3, G3, G2 "3S" I/F 80 FBGA 80 TQFP P0 F2 16 P1 G1 15 - P2 E4 14 - P3 F3 13 - P4 E2 11 PLL0 P5 D2 10 PLL1 P6 E1 9 PLL2 7 PLL3 P7 12 D4 U14867JJ5V0DS U14867JJ5V0DS - µ PD77115 PD77115, 77115A 80 FBGA 80 TQFP TDO C8 57 TICE C7 60 - TCK B8 61 - TDI A7 63 - TMS B7 64 - 65 - TRST C6 - 80 FBGA I.C. NC A8, A9, B9, J9 A2, B1, J1 39, 58, 59, 62 - - 2, 19, 78 - - 80 TQFP µ PD77115 PD77115 U14867JJ5V0DS U14867JJ5V0DS 13 µ PD77115 PD77115, 77115A 1. 2 1. 2. 1 INT1 - INT4 SCLK/BCLK SI EVDD EVDDGND SIEN/MCLK GND SOEN/LRCLK SO SDCLK SDCR EVDDGND SDDAT HA0,HA1 EVDDGND HCS, HRD, HWR EVDD HRE, HWE HD0-HD15 HD0-HD15 P0-P3 EVDDGND TCK GND TDO, TICE TMS, TDI TRST CLKOUT WAKEUP EVDD HCS, HRD, HWR 1. 2. 2 I.C. - NC - 14 U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A 2 2. 1 DSP 2. 1. 1 CPU 31 2. 1. 2 INT1-INT4 2. 1. 3 4 2. 1. 4 PC 15PC 2. 1. 5 PLL PLLDSP ×116PLL0-PLL3 116PLL0-PLL3 2DSP HALTmA STOPµ A WAKEUP 2. 1. 6 RAM64 RAM64 RAMROM RAM µ PD7711511 PD7711511.5 KRAM U14867JJ5V0DS U14867JJ5V0DS 15 µ PD77115 PD77115, 77115A 2. 2 4040 ALU40840 ALU40840 2. 2. 1 R0-R7 840 R0-R7R0L-R7L15-0R0H-R7H31-16R0E-R7E39-32 R0-R7R0L-R7L15-0R0H-R7H31-16R0E-R7E39-32 3RnL, RnH, RnE1 2. 2. 2 MACMultiply Accumulator 21614040 MACMSFTMAC Shifter40 116 2. 2. 3 ALUArithmetic Logic Unit 1240 40 2. 2. 4 BSFTBarrel Shifter 4040 MSB0 2. 3 22 2. 3. 1 2X Y64 µ PD7711516 PD7711516 K×2RAM 2. 3. 2 XY 4 DPn 4 DNn 1DMXDMYALU 16 U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A 2. 4 XY I/O 2. 4. 1 ASIO 1 PD77115 PD77115 µ 2 µ PD77111 PD77111 1 MCLK, BCLK, LRCLK, 256, 384, 512 fs MCLKBCLKLRCLK 3264MSB 3264MSB LRCLK 2 816MSBLSB 816MSBLSB 2. 4. 2 HIO CPUDMA16 CPUDMA16 DSP16 DSP16 2. 4. 3 PIO 8 2. 4. 4 SDSDCIF µ PD77115SDSecure DigitalSD RAMDMA SDROM 2. 4. 5 16SD INT4 U14867JJ5V0DS U14867JJ5V0DS 17 µ PD77115 PD77115, 77115A 3 RESET 3. 1 RESET DSP P0, P1RAM 0x200 3. 2 PLL PLLPLL0-PLL3 350PLL 350PLL 100 µ sPLLCLKINDSP PLL 4ROM ROM RAM µ PD77115RAM PD77115RAM 4. 1 P0, P1 0x200 P0, P13 12CLKIN 12CLKIN P1 0 0 0x200 0 1 0x200 1 0 1 P0 1 0x200 DSP RAM 18 U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A 4. 2 RAM RAM 0x6 R7L DP3 4. 3 RAM RAM RAM 0x9 R7 R7L DP3 U14867JJ5V0DS U14867JJ5V0DS 19 µ PD77115 PD77115, 77115A 5 5. 1 HALT HALTHALTPLL HALT HALT DSP CLKOUT CLKOUT1 50 % µ PD771151/ll = 1-16 5. 2 STOP STOPSTOPSTOPPLL µ PD77115 PD77115 STOPWAKEUP WAKEUP µ s 20 U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A 6 6. 1 6. 1. 1 64 K×32 0xFFFF 0xA000 0x9FFF RAM (8K ) 0x8000 0x7FFF 0x1000 0x0FFF RAM (3.5K ) 0x0240 0x023F (64 ) 0x0200 0x01FF ROM (512 ) 0x0000 U14867JJ5V0DS U14867JJ5V0DS 21 µ PD77115 PD77115, 77115A 6. 1. 2 0x2000x23F 4 0x200 0x204 0x208 0x20C 0x210 INT1 0x214 INT2 0x218 INT3 0x21C INT4 0x220 SI 0x224 SO 0x228 SDDAT/PBU 0x22C SDDAT 0x230 HI 0x234 HO 0x238 SDCR 0x23C 1 2 22 U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A 6. 2 6. 2. 1 64 K×16XY 0xFFFF 0x6000 0x5FFF RAM (8K ) 0x4000 0x3FFF 0x3840 0x383F 0x3800 (64 ) 0x37FF 0x3000 0x2FFF RAM (4K 0x2000 0x1FFF 0x1000 0x0FFF RAM (4K) 0x0000 U14867JJ5V0DS U14867JJ5V0DS 23 µ PD77115 PD77115, 77115A 6. 2. 2 XY 0x3800 SDT/ASDT 0x3801 SST 0x3802 ASST 0x3803 0x3804 PDT 0x3805 PCD 0x3806 HDT 0x3807 HST 0x3808-0x380F 0x3810 SDDR SD 0x3811 SDCMD_IDX SD 0x3812 SDCMD_AGH SD 0x3813 SDCMD_AGL SD 0x3814 SDCTL SD 0x3815 SDRPR SD 0x3816 SDSBR SDCRC 0x3817-0x381F 0x3820 TIR 0x3821 TCR 0x3822 TCSR 0x3823 TENR 0x3824-0x382D 0x382E CLKCNTL 0x382F 0x3830 PSAR DMA 0x3831 PSR DMA 0x3832 PRR DMA 0x3833 PCR DMA 0x3834-0x383F ASIO - PIO HIO - SDCIF - Timer - PLL - SDCIF - 1C C 2XY 3XY 24 U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A 7 7. 1 132 1µ PD7711513 PD7711513.3 ns 9 13 MAC3 22 MAC, ALUBSFT 2 1 3 ALU1 4 16 5 6 7 8 9 U14867JJ5V0DS U14867JJ5V0DS 25 µ PD77115 PD77115, 77115A 7. 2 1 a ro, ro ro , R0-R7 rl, rl R0L-R7L rh, rh R0H-R7H re R0E-R7E reh R0EH-R7EH dp DP0-DP7 dn DN0-DN7 dm DMX, DMY dpx DP0-DP3 dpy DP4-DP7 dpx_mod DPn, DPnDPn-DPnDPn!DPnn = 0-3 dpy_mod DPn, DPnDPn-DPnDPn!DPnn = 4-7 dp_imm DPnimmn = 0-7 ××× ××× DP01000DP01000 DP01000DP01000 26 U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A b DPn DPn DPn DPnDPn1 DPn- DPnDPn-1 DPn DPnDPnDNn DP0-DP7DN0-DN7 DP0DP0DN0 DPn n = 0-3DPn =DPLDNnmodDMX1DPH n = 4-7DPn =DPLDNnmodDMY1DPH !DPn DPn DPnimm DPnDPnDNn DPnDPnimm c dOV 1 U14867JJ5V0DS U14867JJ5V0DS 27 µ PD77115 PD77115, 77115A OV 3 ro = rorhrh rororhrh ro = ro-rhrh roro-rhrh rororhrl rororlrl ro ro rhrh ro rhrh 216 ro = rorhrl (rl) ro = rorlrl (rl, rl ) 1 ro = (ro1)rhrh 2 16 ro = (ro16)rhrh ro 2 ro = rhrh rorhrh ro roro = ro roro ro roimm = ro roimm (imm1) ro ro-ro = ro ro-ro ro ro-imm = ro ro-imm (imm1) ro ro SRA rl = ro rorl ro ro SRA imm = ro roimm ro ro SRL rl = ro rorl ro ro SRL imm = ro roimm ro ro SLL rl = ro rorl ro ro SLL imm = ro roimm ro ro & ro = ro ro & ro ro ro & imm = ro ro & imm ro roro = ro roro ro roimm = ro roimm ro ro^ro = ro ro^ro ro ro^imm = ro ro^imm ro LT(ro, ro = ) if(roro ) ro 0x0000000001 else ro 0x0000000000 28 U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A OV CLR(ro) ro0x0000000000 ro ro1 = ro ro1 ro ro-1 = ro ro-1 ro ABS(ro) = if(ro0) ro -ro else ro ro 1 ro ~ro = ro ~ro 2 ro -ro = ro -ro ro CLIP(ro) = if(ro0x007FFFFFFF) ro 0x007FFFFFFF elseif(ro0xFF80000000) ro 0xFF80000000 else ro ro ro ROUND(ro) = if(ro0x007FFF0000) ro 0x007FFF0000 elseif(ro0xFF80000000) ro 0xFF80000000 else ro (ro0x8000) & 0xFFFFFF0000 1 ) ro ro EXP(ro) = log2( ro ro ro = ro ro ro = ro ro ro ro ro = ro - ro ro -ro ro = ro / if(sign(ro = sign(ro) )= ro (ro -ro)1 else ro (ro ro)1 if(sign(ro = 0) )= ro ro 1 U14867JJ5V0DS U14867JJ5V0DS 29 µ PD77115 PD77115, 77115A OV ro = dpx_mod ro dpy_mod rodpx, ro = dpy 1, 2 ro = dpx_mod dpy_mod = rh rodpx, dpyrh dpx_mod = rh ro = dpy_mod dpxrh, rodpy dpx_mod = rh dpy_mod = rh dpxrh, dpyrh dest = dpx_mod dest = dpx_mod destdpx, dpysource dpx_mod = source dpxsource, dest = dpy_mod destdpy dpx_mod = source dpxsource, dpy_mod = source 1, 2, 3 destdpy dpy_mod = source destdpx, dest dpy_mod = dpysource dest = addr destaddr addr = source addrsource 4 dest = dp_imm destdp dp_imm = source 6 dest = rl destrl rlsource rl = imm rlimm dpsource rl = source 5 imm = 0-0xFFFF dpimm dp = imm imm = 0-0xFFFF dnimm dn = imm imm = 0-0xFFFF dmimm dm = imm imm = 1-0xFFFF 121 2mod 3dest, dest=ro, reh, re, rh, rl, source, source=re, rh, rl 0X-0xFFFFXX 4dest =ro, reh, re, rh, rl, source =re, rh, rl, addr = 0Y-0xFFFFYY 5dest =ro, reh, re, rh, rl, source =re, rh, rl 6dest, source 30 U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A JMP imm JMP dp CALL imm OV PCimm PCdp SPSP1 STKPC1 PCimm CALL dp SPSP1 STKPC1 PCdp RET PCSTK SPSP-1 RETI PCSTK STKSP-1 REP count RCcount RF0 PCPC RCRC-1 PCPC1 RF1 LOOP count RCcount RF0 2 PCPC RCRC-1 PCPC1 RF1 LPOP LCLSR3 LELSR2 LSLSR1 LSPLSP-1 NOP PCPC1 HALT CPU STOP CPU, PLL, OSC IF(ro cond) FINT U14867JJ5V0DS U14867JJ5V0DS 31 µ PD77115 PD77115, 77115A 8 TA = 25 IVDD DSP -0.53.6 V EVDD I/O -0.54.6 V VI VIEVDD0.5 V -0.54.1 V VO -0.54.1 V Tstg -65150 TA -4085 1 MIN. TYP. MAX. IVDD DSP 2.0 2.7 V EVDD I/O 2.7 3.6 V 0 EVDD V VI TA = 25 IVDD = 0 V, EVDD = 0 V MIN. TYP. MAX. CI f = 1 MHz, 10 pF CO 0 V 10 pF CIO 10 pF 32 U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A DCTA = -4085 IVDDEVDD MIN. TYP. MAX. VIHN 0.7 EVDD EVDD V VIHS RESET, INT1-INT4, 0.8 EVDD EVDD V 0.5 EVDD EVDD V SCK, SIEN, SOEN VIHC CLKIN VIL 0 0.2 EVDD V VIC CLKIN 0 0.5 EVDD V 0.25 -0.25 VOH IOH = -2.0 mA 0.7 EVDD V IOH = -100 µ A 0.8 EVDD V VOL IOL = 2.0 mA 0.2 EVDD ILH TDI, TMS, TRST V 0 10 µA -10 0 µA -250 0 µA 0 250 µA TBD 75 mA TBD 10 mA 100 µA VI = EVDD ILL TDI, TMS, TRST VI = 0 V IPUI TDI, TMS, 0 VVIEVDD IPDI TRST, 0 VVIEVDD IDD tcC = 30 ns, IVDD = 2.7 V VIHN = VIHS = EVDD, VIL = 0 V, IDDH tcC = 30 ns, 8IVDD = 2.7 V IDDS 0 TA60 TYP. MAX. 0.8 EVDD 0.5 EVDD 0.2 EVDD 0.8 EVDD 0.5 EVDD 0.2 EVDD 0.5 EVDD+0.25 0.5 EVDD 0.5 EVDD-0.25 0.5 EVDD+0.25 0.5 EVDD 0.5 EVDD-0.25 () 0.7 EVDD 0.5 EVDD 0.2 EVDD 0.7 EVDD 0.5 EVDD 0.2 EVDD 0.5 EVDD 0.5 EVDD RESET, INT1 - INT4, SCK, SIEN, SOEN CLKIN U14867JJ5V0DS U14867JJ5V0DS 33 µ PD77115 PD77115 , 77115A ACTA = -4085 IVDDEVDD CLKIN 1 tcCX MIN. TYP. MAX. 25 ns 2 IVDD2.0~2.7V 15×m 50×m ns IVDD2.3~2.7V PLL 10×m 50×m ns CLKIN twCXH 12.5 ns CLKIN twCXL 12.5 ns CLKIN trfCX tcC(R) 5 ns IVDD = 2.02.7 V 20 ns IVDD = 2.32.7 V 3 13.3 ns 1m 2. PLLtcCX 3tcCX÷m×ntcCXmn tcC MIN. TYP. MAX. tcCX ns PLL CLKOUT twCO ns (tcCX÷m)×n×l ns tcC ns tcCO CLKOUT (tcCX÷m)×n HALT n = 1 tcC÷2-3 ns n =1 tcC÷n-3 ns tcC÷n-3 ns HALT CLKOUT trfCO 5 ns IVDD = 2.02.7 V 20 ns IVDD = 2.32.7 V 15 ns CLKOUT 34 tdCO mnlHALT U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A tcCX twCXH trfCX twCXL trfCX CLKIN tcC, tcC(R) tcCO tdCO twCO twCO trfCO trfCO CLKOUT U14867JJ5V0DS U14867JJ5V0DS 35 µ PD77115 PD77115 , 77115A RESET tw(RL) WAKEUP tw(WAKEUPL) 6 tcC INT1-INT4 TYP. MAX. trec(INT) 3 tcC ns ns HALTtcCll = 1-16 tw(RL) RESET WAKEUP tw (WAKEUPL) WAKEUP trec(INT) INT1 - INT4 36 U14867JJ5V0DS U14867JJ5V0DS µs 3 tcC tw(INTL) ns 6 tcC tw(INTL) INT1-INT4 MIN. µ PD77115 PD77115, 77115A MIN. TYP. MAX. MCLK tcMC 40 ns MCLK twMC 0.4 × tcMC ns MCLK trfMC 50.1 × tcMC ns BCLK tcBC 300 ns BCLK twBC 120 ns BCLK trfBC LRCLK tsu(BC-LR) SI SI 20 ns 50 ns tsuSI 50 ns thSI 50 ns BCLK tcBC MIN. TYP. MAX. 1/64 fs ns 1/32 fs ns 64 32 BCLK twBC BCLK trfBC LRCLK td(BC-LR) SO tdSO 0.4 tcBC ns ns -40 40 ns -40 U14867JJ5V0DS U14867JJ5V0DS 20 40 ns 37 µ PD77115 PD77115 , 77115A tcMC twMC trfMC twMC trfMC MCLK tcBC twBC trfBC trfBC twBC BCLK td(BC-LR) td(BC-LR) LRCLK tdSO SO tsuSI thSI SI tcBC twBC trfBC trfBC twBC BCLK tsu(BC-LR) LRCLK tdSO SO tsuSI thSI SI 38 U14867JJ5V0DS U14867JJ5V0DS tsu(BC-LR) µ PD77115 PD77115, 77115A MIN. TYP. MAX. SCK tcSC 602tcC ns SCK twSC 25 ns SCK trfSC SOEN tsuSOE 20 ns ns 5 ns 15 ns 10 ns 10 ns 5 ns IVDD = 2.02.7 V 15 ns IVDD = 2.32.7 V thSI 10 IVDD = 2.32.7 V SI ns IVDD = 2.02.7 V tsuSI 10 IVDD = 2.32.7 V SI ns IVDD = 2.02.7 V thSIE 15 IVDD = 2.32.7 V SIEN ns IVDD = 2.02.7 V tsuSIE 5 IVDD = 2.32.7 V SIEN ns IVDD = 2.02.7 V thSOE 10 IVDD = 2.32.7 V SOEN IVDD = 2.02.7 V 10 ns SO MIN. TYP. MAX. IVDD = 2.02.7 V 30 ns IVDD = 2.32.7 V SO tdSO 25 ns thSO 0 U14867JJ5V0DS U14867JJ5V0DS ns 39 µ PD77115 PD77115 , 77115A 1 tcSC twSC trfSC trfSC twSC SCK tsuSOE tsuSOE thSOE thSOE SOEN tdSO Hi-Z thSO tdSO 1st SO Last 2 tcSC twSC trfSC trfSC twSC SCK tsuSOE thSOE SOEN tdSO SO 40 Last thSO 1st U14867JJ5V0DS U14867JJ5V0DS Last µ PD77115 PD77115, 77115A 1 tcSC twSC trfSC twSC trfSC SCK tsuSIE tsuSIE thSIE thSIE SIEN tsuSI thSI 3rd 2nd 1st SI 2 tcSC twSC trfSC twSC trfSC SCK tsuSIE thSIE SIEN tsuSI SI Last1 Last thSI 1st U14867JJ5V0DS U14867JJ5V0DS 2nd 3rd 41 µ PD77115 PD77115 , 77115A SCK SCK111 SCK111 × 42 U14867JJ5V0DS U14867JJ5V0DS × µ PD77115 PD77115, 77115A HRD tdHR MIN. TYP. MAX. IVDD = 2.02.7 V 15 ns IVDD = 2.32.7 V 5 ns HRD twHR 40 ns HCS, HA0, HA1 thHCAR 0 ns thHCAW 0 ns HRD, HWR trecHS 3tcC ns HWR tdHW IVDD = 2.02.7 V 15 ns IVDD = 2.32.7 V 10 ns HCS, HA0, HA1 HWR twHW 40 ns HWR thHDW 0 ns HWR tsuHDW IVDD = 2.02.7 V 15 ns IVDD = 2.32.7 V 10 ns MIN. TYP. MAX. HRE, HWE tdHE IVDD = 2.02.7 V 30 ns IVDD = 2.32.7 V 25 ns HRE, HWE thHE IVDD = 2.02.7 V 30 ns IVDD = 2.32.7 V 25 ns IVDD = 2.02.7 V 30 ns IVDD = 2.32.7 V 25 ns HRD HRD tvHDR thHDR 0 U14867JJ5V0DS U14867JJ5V0DS ns 43 µ PD77115 PD77115 , 77115A CLKIN HCS, HA0, HA1 thHCAR tdHR trecHS twHR HRD thHDR tvHDR Hi-Z HD0 - HD15 tdHE Hi-Z thHE HRE CLKIN HCS, HA0, HA1 thHCAW tdHW twHW trecHS HWR thHDW tsuHDW HD0 - HD15 tdHE thHE HWE 44 U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A thPI MIN. tsuPI TYP. MAX. 0 ns IVDD = 2.02.7 V 15 ns IVDD = 2.32.7 V 10 ns tdPO MIN. TYP. MAX. IVDD = 2.02.7 V 30 ns IVDD = 2.32.7 V 25 ns CLKIN tdPO P0 - P7 tsuPI thPI P0 - P7 U14867JJ5V0DS U14867JJ5V0DS 45 µ PD77115 PD77115, 77115A SD MIN. TYP. MAX. SDCR tsuSDCR 5 ns SDCR thSDCR 0 ns SDDAT tsuSDD 5 ns SDDAT thSDD 0 ns MIN. TYP. MAX. 40 SDCLK tcSDC ns SDCLK twSDCH 10 ns SDCLK twSDCL 10 ns SDCLK trfSDC 10 ns 10 ns SDCR tdSDCR SDCR tvSDCR SDDAT tdSDD SDDAT tvSDD 46 U14867JJ5V0DS U14867JJ5V0DS 0 ns 10 0 ns ns µ PD77115 PD77115, 77115A SDCR tcSDC twSDCL trfSDC trfSDC trfSDC twSDCH trfSDC SDCLK tdSDCR tvSDCR SDCR tsuSDCR thSDCR SDCR SDDAT tcSDC twSDCL twSDCH SDCLK tdSDD tvSDD SDDAT tsuSDD thSDD SDDAT U14867JJ5V0DS U14867JJ5V0DS 47 µ PD77115 PD77115, 77115A JTAG MIN. TYP. MAX. TCK tcTCK 120 ns TCK twTCK 50 ns TCK trfTCK TMS, TDI tsuDI 20 ns 20 ns 25 ns 20 ns 25 ns IVDD = 2.32.7 V TRST ns IVDD = 2.02.7 V thJIN 25 IVDD = 2.32.7 V ns IVDD = 2.02.7 V tsuJIN 20 IVDD = 2.32.7 V ns IVDD = 2.02.7 V thDI 25 IVDD = 2.32.7 V TMS, TDI IVDD = 2.02.7 V 20 ns 100 ns tsuTRST TDO MIN. TYP. MAX. 48 25 ns 20 ns IVDD = 2.02.7 V 25 ns IVDD = 2.32.7 V tdJOUT IVDD = 2.02.7 V IVDD = 2.32.7 V tdDO 20 ns U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A tcTCK twTCK trfTCK twTCK trfTCK TCK tsuTRST TRST tsuDI thDI TMS, TDI Valid Valid Valid tdDO TDO tsuJIN thJIN Capture state Valid tdJOUT Update state JTAGIEEE1149 JTAGIEEE1149.1 U14867JJ5V0DS U14867JJ5V0DS 49 µ PD77115 PD77115, 77115A 9 80 FBGA9x9 D w S A ZE A ZD 9 8 7 6 5 4 3 2 1 B E J H G F E D C B A INDEX MARK w S B A y1 A2 S (UNIT:mm) E y e S b x A1 M S AB DIMENSIONS 9.00±0.10 9.00±0.10 w S ITEM D 0.20 A 1.28±0.10 A1 0.35±0.06 0.80 b 0.50 +0.05 0.10 x 0.08 y 0.10 y1 0.20 ZD 1.30 ZE U14867JJ5V0DS U14867JJ5V0DS 0.93 e 50 A2 1.30 P80F1-80-CN6 P80F1-80-CN6 µ PD77115 PD77115, 77115A 80 TQFP 12x12mm 14.0±0.2 12.0±0.2 41 60 61 40 14.0±0.2 12.0±0.2 1.2 MAX. 0.1±0.05 80 3° +7° -3° 21 1 20 1.25 0.5 1.25 0.10 0.22±0.05 M 1.0±0.2 1.0±0.05 S 0.10 S 0.5±0.2 0.145±0.05 S80GK-50-9EU-1 S80GK-50-9EU-1 U14867JJ5V0DS U14867JJ5V0DS 51 µ PD77115 PD77115, 77115A 10 http://www.necel.com/pkg/ja/jissou/index.html µ PD77115GK-9EU80TQFP12 PD77115GK-9EU80TQFP12×12 23530 210 IR35-103-2 IR35-103-2 2 3 1251072 VSP 21540 200 VP15-103-2 VP15-103-2 1251072 2 3 3003 - µ PD77115F1-CN680FBGA9 PD77115F1-CN680FBGA9×9 µ PD77115AF1- PD77115AF1-×××-CN680FBGA9 -CN680FBGA9×9 23530 210 IR35-103-2 IR35-103-2 1251072 2 3 VSP 21540 200 1251072 2 3 2565RH 2565RH 52 U14867JJ5V0DS U14867JJ5V0DS VP15-103-2 VP15-103-2 µ PD77115 PD77115, 77115A U14867JJ5V0DS U14867JJ5V0DS 53 µ PD77115 PD77115, 77115A 54 U14867JJ5V0DS U14867JJ5V0DS µ PD77115 PD77115, 77115A CMOS CMOSVILMAX.VIHMIN. VIL MAX.VIHMIN. CMOS CMOS VDD GND MOS MOS MOS MOS OFF OFF OFF U14867JJ5V0DS U14867JJ5V0DS 55 µ PD77115 PD77115, 77115A µ PD77115F1-CN6 PD77115F1-CN6, µ PD77115GK-9EU PD77115GK-9EU µ PD77115AF1- PD77115AF1-×××-CN6 · 20048 · · · · · OAAV NECNEC M8E02 M8E02.11 NEC 211-86681753 044(435)5111 NEC URL http://www.necel.co.jp/ 044-435-9494 9:0012:00 1:005:00 E-mail info@necel.com NECNEC C04.2T