PD754302 PD754304 PD754303 PD75P4308 U10123E U10797EJ2V1DS00 PD754302GS- - Datasheet Archive

 

MOS INTEGRATED CIRCUIT µPD754302,754304,754302(A),754304(A) 4-BIT SINGLE-CHIP MICROCONTROLLER The µPD754304 is one of

 

DATA SHEET MOS INTEGRATED CIRCUIT µPD754302 PD754302,754304,754302(A),754304(A) 4-BIT SINGLE-CHIP MICROCONTROLLER The µPD754304 PD754304 is one of the "75XL Series" 4-bit single-chip microcontrollers with data processing capability comparable to that of 8-bit microcontrollers. The µPD754303 PD754303(A) has a higher reliability than the µPD754304 PD754304. The microcontrollers in the 75XL Series have expanded CPU functions than those of the 75X Series and can operate at a voltage of as low as 1.8 V; therefore, they are ideal for battery-driven application systems. As the one-time PROM version of the µPD754304 PD754304, the µPD75P4308 PD75P4308 is ideal for evaluation of a system under development or for small-scale production of application systems. Detailed information about functions can be found in the following document. Be sure to read the following document before designing. µPD754304 PD754304 User's Manual: U10123E U10123E FEATURES · Low-voltage operation: VDD = 1.8 to 5.5 V · Variable instruction execution time effective for highspeed operation and power saving · Internal memory 0.95, 1.91, 3.81, or 15.3 µs (at 4.19 MHz) Program memory (ROM): 2048 × 8 bits (µPD754302 PD754302, 754302(A) 4096 × 8 bits (µPD754304 PD754304, 754304(A) Data memory (RAM): 256 × 4 bits 0.67, 1.33, 2.67, or 10.7 µs (at 6.0 MHz) · Internal serial interface (1 channel) · Powerful timer function (3 channels) · Inherits instruction set of existing 75X Series for easy replacement APPLICATIONS · µPD754302 PD754302, 754302(A) Cordless telephones, TVs, VCRs, audio systems, household appliances, office machines, etc. · µPD754304 PD754304, 754304(A) Automotive appliance, etc. The µPD754302 PD754302 and 754304 differ from the µPD754302 PD754302(A) and 754304(A) only in terms of their quality grade. Unless otherwise specified, the µPD754304 PD754304 is treated as a representative model in this Data Sheet. For the models other than the µPD754304 PD754304, µPD754304 PD754304 can be read as the other model name. If different descriptions are made for the µPD754302 PD754302 and 754304, the (A) models correspond as follows: µPD754302 PD754302 µPD754302 PD754302(A), µPD754304 PD754304 µPD754304 PD754304(A) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. U10797EJ2V1DS00 U10797EJ2V1DS00 (2nd edition) Date Published August 2005 N CP(K) Printed in Japan The mark shows major revised points. 1996 µPD754302 PD754302, 754304, 754302(A), 754304(A) ORDERING INFORMATION Parts Number µPD754302GS- PD754302GS-××× Package Quality Grade 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) Standard µPD754302GS- PD754302GS-×××-A 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) Standard µPD754304GS- PD754304GS-××× 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) Standard µPD754304GS- PD754304GS-×××-A 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) Standard µPD754302GS PD754302GS(A)-××× 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) Special µPD754304GS PD754304GS(A)-××× 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch) Special Remarks 1. Products with "-A" at the end of the part number are lead-free products. 2. ××× indicates ROM code suffix. Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E C11531E) published by NEC Electronics Corporation to know the specification of quality grade on the devices and its recommended applications. Difference between µPD75430 PD75430× and µPD75430 PD75430×(A) Parts Number Item Quality grade 2 µPD754302 PD754302 µPD754304 PD754304 µPD754302 PD754302(A) µPD754304 PD754304(A) Standard Special Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) Functional Outline Parameter Function · 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz with system clock) · 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz with system clock) Instruction execution time On-chip memory ROM 2048 × 8 bits ( µPD754302 PD754302) 4096 × 8 bits ( µPD754304 PD754304) RAM 256 × 4 bits General-purpose register · 4-bit operation: 8 × 4 banks · 8-bit operation: 4 × 4 banks Input/ CMOS input 8 On-chip pull-up resistors can be specified by software: 7 output port CMOS input/output 18 On-chip pull-up resistors can be specified by software: 18 N-ch open-drain input/output pins 4 13 V withstand voltage. On-chip pull-up resistors can be specified by mask option. Total 30 Timer 3 channels · 8-bit timer/event counter: 2 channels (16-bit timer/event counter) · Basic interval timer/watchdog timer: 1 channel Serial interface · 3-wire serial I/O mode . MSB or LSB can be selected for transferring top bit · 2-wire serial I/O mode Bit sequential buffer 16 bits Clock output (PCL) · , 524, 262, 65.5 kHz (@ 4.19 MHz with system clock) · , 750, 375, 93.8 kHz (@ 6.0 MHz with system clock) Vectored interrupts External: 3, Internal: 4 Test input External: 1 System clock oscillator Ceramic or crystal oscillator Standby function STOP/HALT mode Operating ambient TA = ­40 to +85 °C temperature Power supply voltage VDD = 1.8 to 5.5 V Package 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch) Data Sheet U10797EJ2V1DS U10797EJ2V1DS 3 µPD754302 PD754302, 754304, 754302(A), 754304(A) CONTENTS 1. PIN CONFIGURATION (Top View) ······································································································ 6 2. BLOCK DIAGRAM ································································································································8 3. PIN FUNCTION ····································································································································· 9 3.1 Port Pins ······································································································································9 3.2 Non-port Pins ···························································································································· 10 3.3 Pin Input/Output Circuits ········································································································· 11 3.4 Recommended Connections for Unused Pins ······································································· 13 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ················································ 14 4.1 Difference between Mk I and Mk II Modes ·············································································· 14 4.2 Setting Method of Stack Bank Select Register (SBS) ··························································· 15 5. MEMORY CONFIGURATION ············································································································· 16 6. PERIPHERAL HARDWARE FUNCTIONS ························································································· 20 6.1 Digital Input Ports ····················································································································· 20 6.2 Clock Generator ························································································································ 21 6.3 Clock Output Circuit ················································································································· 22 6.4 Basic Interval Timer/Watchdog Timer ····················································································· 23 6.5 Timer/Event Counter ················································································································· 24 6.6 Serial Interface ·························································································································· 27 6.7 Bit Sequential Buffer ················································································································ 29 7. INTERRUPT FUNCTION AND TEST FUNCTION ·············································································· 30 8. STANDBY FUNCTION ························································································································ 32 9. RESET FUNCTION ····························································································································· 33 10. MASK OPTION ··································································································································· 36 11. INSTRUCTION SETS ·························································································································· 37 12. ELECTRICAL SPECIFICATIONS ······································································································· 49 13. CHARACTERISTICS CURVES (REFERENCE VALUES) ································································· 61 14. PACKAGE DRAWING ························································································································ 63 15. RECOMMENDED SOLDERING CONDITIONS ·················································································· 64 4 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) APPENDIX A. COMPARISON OF FUNCTIONS AMONG µPD750004 PD750004, 754304, AND 75P4308 75P4308 ··········· 65 APPENDIX B. DEVELOPMENT TOOLS ································································································· 67 APPENDIX C. RELATED DOCUMENTS ································································································· 70 Data Sheet U10797EJ2V1DS U10797EJ2V1DS 5 µPD754302 PD754302, 754304, 754302(A), 754304(A) 1. PIN CONFIGURATION (Top View) 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch) µPD754302GS- PD754302GS-×××, µPD754302GS- PD754302GS-×××-A, µPD754302GS PD754302GS(A)-××× µPD754304GS- PD754304GS-×××, µPD754304GS- PD754304GS-×××-A, µPD754304GS PD754304GS(A)-××× VSS 1 36 P50 X1 2 35 P51 X2 3 34 P52 RESET 4 33 P53 P33 5 32 P60/KR0 P60/KR0 P32 6 31 P61/KR1 P61/KR1 P31 7 30 P62/KR2 P62/KR2 P30 8 29 P63/KR3 P63/KR3 P81 9 28 P70/KR4 P70/KR4 P80 10 27 P71/KR5 P71/KR5 P23 11 26 P72/KR6 P72/KR6 P22/PCL P22/PCL 12 25 P73/KR7 P73/KR7 P21/PTO1 P21/PTO1 13 24 P13/TI0/TI1 P13/TI0/TI1 P20/PTO0 P20/PTO0 14 23 P12/INT2 P12/INT2 P03/SI P03/SI 15 22 P11/INT1 P11/INT1 P02/SO/SB0 P02/SO/SB0 16 21 P10/INT0 P10/INT0 P01/SCK P01/SCK 17 20 VDD P00/INT4 P00/INT4 18 19 IC IC: Internally Connected (Connect directly this pin to VDD.) 6 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) PIN IDENTIFICATION P00-P03 P00-P03 : PORT0 RESET : Reset Input P10-P13 P10-P13 : PORT1 TI0, TI1 : Timer Input 0, 1 P20-P23 P20-P23 : PORT2 PTO0, PTO1 : Programmable Timer Output 0, 1 P30-P33 P30-P33 : PORT3 PCL : Programmable Clock P50-P53 P50-P53 : PORT5 INT0, 1, 4 : External Vectored Interrupt 0, 1, 4 P60-P63 P60-P63 : PORT6 INT2 : External Test Input 2 P70-P73 P70-P73 : PORT7 VSS : GND P80, P81 : PORT8 X1, X2 : System Clock Oscillation 1, 2 KR0-KR7 : Key Return 0-7 IC : Internally Connected SCK : Serial Clock VDD : Positive Power Supply SI : Serial Input SO : Serial Output SB0 : Serial data Bus 0 Data Sheet U10797EJ2V1DS U10797EJ2V1DS 7 TOUT0 INTBT INTT0 TI0/TI1/P13 TI0/TI1/P13 PTO0/P20 PTO0/P20 PTO1/P21 PTO1/P21 BIT SEQ. BUFFER (16) 8-BIT TIMER/EVENT CASCADED COUNTER#0 16-BIT 16-BIT TIMER/ 8-BIT EVENT TIMER/EVENT COUNTER COUNTER#1 4 PORT0 4 P00-P03 P00-P03 SBS 4 PORT1 4 P10-P13 P10-P13 BANK 4 PORT2 4 P20-P23 P20-P23 4 PORT3 4 P30-P33 P30-P33 4 PORT5 4 P50-P53 P50-P53 4 PORT6 4 P60-P63 P60-P63 4 PORT7 4 P70-P73 P70-P73 2 PORT8 2 P80, P81 SP (8) PROGRAM COUNTER Note1 CY ALU INTT1 CLOCKED SERIAL INTERFACE GENERAL REG. ROM Note2 PROGRAM MEMORY DECODE AND CONTROL RAM DATA MEMORY 256 × 4 BITS INTCSI TOUT0 INT0/P10 INT0/P10 INT1/P11 INT1/P11 INT2/P12 INT2/P12 INT4/P00 INT4/P00 KR0-KR3/P60-P63 KR0-KR3/P60-P63 KR4-KR7/P70-P73 KR4-KR7/P70-P73 INTERRUPT CONTROL fX/2N 8 CPU CLOCK CLOCK CLOCK OUTPUT CLOCK GENERATOR CONTROL DIVIDER PCL/P22 PCL/P22 X1 STAND BY CONTROL X2 IC VDD VSS RESET Notes 1. The µPD754302 PD754302 and µ PD754304 PD754304 program counters are 11 and 12 bits, respectively. 2. The ROM capacity of the µPD754302 PD754302 is 2048 × 8 bits, and that of the µPD754304 PD754304 is 4096 × 8 bits. µPD754302 PD754302, 754304, 754302(A), 754304(A) Data Sheet U10797EJ2V1DS U10797EJ2V1DS SI/P03 SI/P03 SO/SB0/P02 SO/SB0/P02 SCK/P01 SCK/P01 2. BLOCK DIAGRAM 8 BASIC INTERVAL TIMER/ WATCHDOG TIMER µPD754302 PD754302, 754304, 754302(A), 754304(A) 3. PIN FUNCTION 3.1 Port Pins Input/Output Alternate Function P00 Input INT4 4-bit input port (PORT0). P01 Input/Output SCK P02 Input/Output SO/SB0 For P01 to P03, on-chip pull-up resistors can be specified by software in 3-bit units. P03 Input SI P10 Input INT0 Pin Name Function 8-bit I/O After Reset I/O Circuit TYPE Note 1 × Input B F -A F -B B -C 4-bit input port (PORT1). On-chip pull-up resistors can be specified by software in 4-bit units. Noise elimination circuit can be selected (Only P10/INT0 P10/INT0) × Input B -C PTO0 4-bit input/output port (PORT2). × Input E-B P21 PTO1 On-chip pull-up resistors can be specified by software in 4-bit units. P22 PCL P23 ­ Programmable 4-bit input/output port (PORT3). This port can be specified for input/output bit-wise. On-chip pull-up resistor can be specified by software in 4-bit units. × Input E-B N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be contained bit-wise (mask option). Withstand voltage is 13 V in open-drain mode. × High level (when pull-up resistors are provided) or highimpedance M-D Programmable 4-bit input/output port (PORT6). This port can be specified for input/output bit-wise. On-chip pull-up resistors can be specified by software in 4-bit units. Input F -A Input F -A Input E-B P11 INT1 P12 INT2 P13 TI0/TI1 P20 Input/Output P30 Input/Output ­ P31 ­ P32 ­ P33 ­ P50-P53 P50-P53 P60 Note 2 Input/Output ­ Input/Output KR0 P61 KR1 P62 KR2 P63 KR3 P70 Input/Output KR4 P71 KR5 P72 KR6 P73 4-bit input/output port (PORT7). On-chip pull-up resistors can be specified by software in 4-bit units. KR7 P80 P81 Input/Output ­ ­ 2-bit input/output port (PORT8). On-chip pull-up resistors can be specified by software in 2-bit units. × Notes 1. Circled characters indicate the Schmitt-trigger input. 2. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low level input leakage current increases when input or bit manipulation instruction is executed. Data Sheet U10797EJ2V1DS U10797EJ2V1DS 9 µPD754302 PD754302, 754304, 754302(A), 754304(A) 3.2 Non-port Pins TI0/TI1 PTO0 Input/Output P13 Output P20 After Reset I/O Circuit TYPE Note Inputs external event pulses to the timer/event counter. Input B -C Timer/event counter output Input E-B Input F -A Alternate Function Input Pin Name Function PTO1 P21 PCL P22 Clock output P01 Serial clock input/output P02 Serial data output Serial data bus input/output F -B B -C SCK Input/Output SO/SB0 SI Input P03 Serial data input INT4 Input P00 Edge detection vectored interrupt input (both Input B Input B -C Input B -C Input F -A ­ ­ rising edge and falling edge detection) INT0 Input INT1 P10 P11 INT2 Input P12 KR0-KR3 Input P60-P63 P60-P63 KR4-KR7 Edge detection vectored interrupt input (detection edge can be selected). INT0/P10 INT0/P10 can select a noise elimination circuit. Asynchronous with noise elimination circuit can be selected Edge detection testable input (rising edge detection) Asynchronous Asynchronous Testable input (falling edge detection) P70-P73 P70-P73 X1 Input X2 ­ ­ Crystal/ceramic connection pin for the system clock oscillator. When inputting the external clock, input the external clock to pin X1, and the inverted phase of the external clock to pin X2. RESET Input ­ System reset input (low-level active) ­ B IC ­ ­ Internally connected. Connect directly to VDD. ­ ­ V DD ­ ­ Positive power supply ­ ­ V SS ­ ­ Ground potential ­ ­ Note 10 Circled characters indicate the Schmitt-trigger input. Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) 3.3 Pin Input/Output Circuits The µPD754304 PD754304 pin input/output circuits are shown schematically. TYPE A TYPE D VDD VDD data P-ch OUT P-ch IN N-ch output disable N-ch Push-pull output that can be placed in output high-impedance (both P-ch, N-ch off). CMOS specification input buffer. TYPE E-B TYPE B VDD P.U.R. P.U.R. enable IN P-ch data Type D IN/OUT output disable Type A Schmitt trigger input having hysteresis characteristic. P.U.R. : Pull-Up Resistor TYPE F-A TYPE B-C VDD VDD P.U.R. P.U.R. enable P.U.R. P-ch P.U.R. enable P-ch data output disable IN/OUT Type D IN Type B P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor Data Sheet U10797EJ2V1DS U10797EJ2V1DS 11 µPD754302 PD754302, 754304, 754302(A), 754304(A) TYPE F-B TYPE M-D VDD VDD P.U.R. (Mask Option) P.U.R. P.U.R. enable output disable (P) IN/OUT P-ch output disable P-ch IN/OUT data N-ch (+13 V) data VDD VDD Input instruction P-ch Note P.U.R. output disable N-ch output disable (N) Voltage limiting circuit (+13 V) P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor 12 Note If this pull-up resistor is not connected using the mask option it operates only when the input instruction is executed (if the pin is low, current flows from VDD to the pin). Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) 3.4 Recommended Connections for Unused Pins Table 3-1. List of Recommended Connections for Unused Pins Pin Recommended Connection P00/INT4 P00/INT4 Connect to V SS or V DD P01/SCK P01/SCK Connect to V SS or VDD through the resistor individually P02/SO/SB0 P02/SO/SB0 P03/SI P03/SI Connect to V SS P10/INT0-P12/INT2 P10/INT0-P12/INT2 Connect to VSS or V DD P13/TI0/TI1 P13/TI0/TI1 P20/PTO0 P20/PTO0 Input state P21/PTO1 P21/PTO1 P22/PCL P22/PCL : Connect to V SS or VDD through the resistor individually Output state : Leave open P23 P30-P33 P30-P33 P50-P53 P50-P53 Input state : Connect to V SS Output state : Connect to V SS (Pull-up resistor by mask option should not be connected) P60/KR0-P63/KR3 P60/KR0-P63/KR3 P70/KR4-P73/KR7 P70/KR4-P73/KR7 Input state : Connect to V SS or VDD through the resistor individually P80, P81 Output state : Leave open IC Connect to V DD directly Data Sheet U10797EJ2V1DS U10797EJ2V1DS 13 µPD754302 PD754302, 754304, 754302(A), 754304(A) 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Difference between Mk I and Mk II Modes The CPU of µPD754304 PD754304 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the stack bank select register (SBS). · Mk I mode: Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes. · Mk II mode: Can be used in all the 75XL CPU's including those products whose ROM capacity is more than 16K bytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I mode Mk II mode Number of stack bytes for subroutine instructions 2 bytes 3 bytes BRA !addr1 instruction CALLA !addr1 instruction Not available Available CALL !addr instruction 3 machine cycles 4 machine cycles CALLF !faddr instruction 2 machine cycles 3 machine cycles Caution The Mk II mode supports a program area exceeding 16K bytes in the 75X and 75XL series. This mode can improve software compatibility with products with a program area of more than 16K bytes. When Mk II mode is selected, the number of stack bytes when a subroutine call instruction is executed is greater by 1 byte per stack compared with the Mk I mode. When the CALL !addr or CALLF !faddr instruction is used, one more machine cycle is required. To emphasize the efficiency of the RAM and processing speed rather than software compatibility, therefore, use the Mk I mode. 14 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 1000B 1000B at the beginning of a program. When using the Mk II mode, it must be initialized to 0000B 0000B. Figure 4-1. Stack Bank Select Register Format Address 3 F84H SBS3 2 1 0 SBS2 SBS1 Symbol SBS0 SBS Stack area specification 0 0 Memory bank 0 Other than above setting prohibited 0 0 must be set in the bit 2 position. Mode switching specification 0 Mk II mode 1 Mk I mode Caution Since SBS. 3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to "0" to select the Mk II mode. Data Sheet U10797EJ2V1DS U10797EJ2V1DS 15 µPD754302 PD754302, 754304, 754302(A), 754304(A) 5. MEMORY CONFIGURATION · Program Memory (ROM) . . 2048 × 8 bits (µPD754302 PD754302) 4096 × 8 bits (µPD754304 PD754304) · Addresses 0000H 0000H and 0001H 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset and start are possible at an arbitrary address. · Addresses 0002H-000DH 0002H-000DH Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written. Interrupt execution can be started at an arbitrary address. · Addresses 0020H-007FH 0020H-007FH Table area referenced by the GETI instruction Note. Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the program steps. · Data Memory (RAM) · Data area . 256 words × 4 bits (000H-0FFH 000H-0FFH) · Peripheral hardware area . 128 words × 4 bits (F80H-FFFH F80H-FFFH) 16 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) Figure 5-1. Program Memory Map (1/2) (a) µ PD754302 PD754302 Address 7 6 0 0 0 0 H MBE RBE 5 4 0 0 0 0 0 0 (low-order 8 bits) INT0 start address (high-order 4 bits) start address (low-order 8 bits) INT1 start address (high-order 4 bits) start address (low-order 8 bits) INTCSI start address (high-order 4 bits) start address (low-order 8 bits) INTT0 start address (high-order 4 bits) start address (low-order 8 bits) INTT1 start address (high-order 4 bits) INTT1 0 0 0 C H MBE RBE 0 0 start address INTT0 0 0 0 A H MBE RBE 0 0 (high-order 4 bits) INTCSI 0 0 0 8 H MBE RBE 0 0 start address INT1 0 0 0 6 H MBE RBE 0 INTBT/INT4 INT0 0 0 0 4 H MBE RBE 0 (low-order 8 bits) INTBT/INT4 0 (high-order 4 bits) Internal reset start address 0 0 0 2 H MBE RBE Internal reset start address start address (low-order 8 bits) CALLF ! faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address _15 to _1, +2 to +16 Branch destination address and subroutine entry address when GETI instruction is executed 0020H 0020H GETI instruction reference table 007FH 007FH 0080H 0080H 07FFH 07FFH Note Can be used in the Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. Data Sheet U10797EJ2V1DS U10797EJ2V1DS 17 µPD754302 PD754302, 754304, 754302(A), 754304(A) Figure 5-1. Program Memory Map (2/2) (b) µ PD754304 PD754304 Address 7 6 0 0 0 0 H MBE RBE 5 4 0 0 0 0 0 0 (low-order 8 bits) INT0 start address (high-order 4 bits) start address (low-order 8 bits) INT1 start address (high-order 4 bits) start address (low-order 8 bits) INTCSI start address (high-order 4 bits) start address (low-order 8 bits) INTT0 start address (high-order 4 bits) start address (low-order 8 bits) INTT1 start address (high-order 4 bits) INTT1 0 0 0 C H MBE RBE 0 0 start address INTT0 0 0 0 A H MBE RBE 0 0 (high-order 4 bits) INTCSI 0 0 0 8 H MBE RBE 0 0 start address INT1 0 0 0 6 H MBE RBE 0 INTBT/INT4 INT0 0 0 0 4 H MBE RBE 0 (low-order 8 bits) INTBT/INT4 0 (high-order 4 bits) Internal reset start address 0 0 0 2 H MBE RBE Internal reset start address start address (low-order 8 bits) CALLF ! faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address _15 to _1, +2 to +16 0020H 0020H GETI instruction reference table 007FH 007FH 0080H 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 07FFH 0800H 0800H 0FFFH Note Can be used in the Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction. 18 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) Figure 5-2. Data Memory Map Data memory 000H General-purpose register area Memory bank (32 × 4) 01FH Data area static RAM (256 × 4) 0 Stack area 256 × 4 (224 × 4) 0FFH Not incorporated F80H 128 × 4 Peripheral hardware area 15 FFFH Data Sheet U10797EJ2V1DS U10797EJ2V1DS 19 µPD754302 PD754302, 754304, 754302(A), 754304(A) 6. PERIPHERAL HARDWARE FUNCTIONS 6.1 Digital Input Ports The following three types of I/O ports are provided. · CMOS input (Ports 0, 1) : · CMOS I/O (Ports 2, 3, 6 to 8) : 18 · N-ch open-drain I/O (Port 5) : Total 8 4 30 Table 6-1. Types and Features of Digital Ports Port Name PORT0 Function 4-bit input PORT1 Operation, Features When serial interface function is used, multiplexed pin has output function depending on operation mode. Input port. Remark Multiplexed with INT4, SCK, SO/SB0, and SI pins Multiplexed with INT0 through INT2 and TI0/TI1 pins. PORT2 4-bit I/O Multiplexed with PTO0, PTO1, and PCL pins. Can be set in input or output mode in 1-bit units. PORT3 Can be set in input or output mode in 4-bit units. - PORT5 4-bit I/O (N-ch opendrain, 13 V) Can be set in input or output mode in 4-bit units. Pull-up resistor can be connected in 1-bit units by mask option. PORT6 4-bit I/O Can be set in input or output mode in 1-bit units. Ports 6 and 7 are used in pairs and can input or Multiplexed with KR0 through KR3 pins. Can be set in input or output data in 8-bit units. Multiplexed with KR4 through PORT7 output mode in 4-bit units. PORT8 20 2-bit I/O Can be set in input or output mode in 2-bit units. Data Sheet U10797EJ2V1DS U10797EJ2V1DS KR7 pins. - µPD754302 PD754302, 754304, 754302(A), 754304(A) 6.2 Clock Generator · Clock generator configuration The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is shown in Figure 6-1. The operation of the clock generator is set with the processor clock control register (PCC). The instruction execution time can be changed. · 0.95, 1.91, 3.81, 15.3 µs (system clock operating at 4.19 MHz) · 0.67, 1.33, 2.67, 10.7 µs (system clock operating at 6.0 MHz) Figure 6-1. Clock Generator Block Diagram · Basic interval timer (BT) · Timer/event counters 0, 1 · Serial interface · INT0 noise eliminator · Clock output circuit X1 X2 System clock oscillator 1/1 to 1/4096 fX Divider 1/2 1/4 1/16 Oscillation stop Divider 1/4 Selector · CPU · INT0 noise eliminator · Clock output circuit Internal bus PCC PCC0 PCC1 4 HALT F/F PCC2 S HALTNote STOPNote PCC3 R PCC2, PCC3 Clear STOP Q F/F Q Wait signal from BT S RESET signal R Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. fX = System clock frequency 2. = CPU clock 3. PCC: Processor Clock Control Register 4. One clock cycle (t CY) of the CPU clock is equal to one machine cycle of the instruction. Data Sheet U10797EJ2V1DS U10797EJ2V1DS 21 µPD754302 PD754302, 754304, 754302(A), 754304(A) 6.3 Clock Output Circuit The clock output circuit outputs clock pulses from the P22/PCL P22/PCL pin, and is used to apply for remote controller waveform output or to supply clock pulse peripheral LSIs. : , 524, 262, 65.5 kHz (during 4.19-MHz operation) · Clock output (PCL) , 750, 375, 93.8 kHz (during 6.0-MHz operation) Figure 6-2. Clock Output Circuit Block Diagram From clock generator Output buffer fX/23 Selector fX/24 PCL/P22 PCL/P22 fX/26 PORT2.2 CLOM3 0 P22 output latch CLOM1 CLOM0 CLOM Bit 2 of PMGB Port 2 I/O mode specification bit 4 Internal bus Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. 22 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) 6.4 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. · Interval timer operation to generate a reference time interrupt · Watchdog timer operation to detect a runaway of program and reset the CPU · Selects and counts the wait time when the standby mode is released · Reads the contents of counting Figure 6-3. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator Clear fX/25 fX/27 MPX Clear Basic interval timer (8-bit frequency divider) Set fX/29 BT fX/212 3 Wait release signal when standby is released. BTM3 BTM2 BTM1 BTM0 BTM SET1 Note 4 BT interrupt request flag Vectored interrupt IRQBT request signal Internal reset signal WDTM SET1 Note 8 1 Internal bus Note Instruction execution Data Sheet U10797EJ2V1DS U10797EJ2V1DS 23 µPD754302 PD754302, 754304, 754302(A), 754304(A) 6.5 Timer/Event Counter The µ PD754304 PD754304 has two channels of timer/event counters. Its configuration is shown in Figures 6-4 and 6-5. The timer/event counter has the following functions. · Programmable interval timer operation · Square wave output of any frequency to the PTOn pin (n = 0, 1) · Event counter operation · Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided frequency to the PTOn pin (frequency divider operation). · Supplies the shift clock to the serial interface circuit. · Reads the count value. The timer/event counter operates in the following two modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter Channel Channel 0 Channel 1 Mode 8-bit timer/event counter mode 16-bit timer/event counter mode 24 Data Sheet U10797EJ2V1DS U10797EJ2V1DS Figure 6-4. Timer/Event Counter (Channel 0) Block Diagram Internal bus 8 TM0 PORT1.3 TMOD0 Decoder Modulo register (8) 8 Match Comparator (8) Input buffer TI0/TI1/P13 TI0/TI1/P13 MPX 8 T0 Count register (8) CP P20/PTO0 P20/PTO0 TOUT F/F Output buffer To serial interface Reset Overflow Timer/event counter (channel 1) clock input Clear INTT0 IRQT0 set signal 16-bit timer/event counter mode IRQT0 clear signal Timer operation start RESET Timer/event counter (channel 1) TM12 signal (When 16-bit timer/event counter mode) Timer/event counter (channel 1) match signal (When 16-bit timer/event counter mode) Timer/event counter (channel 1) clear signal (When 16-bit timer/event counter mode) 25 µPD754302 PD754302, 754304, 754302(A), 754304(A) Data Sheet U10797EJ2V1DS U10797EJ2V1DS fX/22 4 From clock fX/26 fX/2 generator fX/28 fX/210 PORT 2.0 Bit 2 of PMGB TOE0 T0 P20 Port 2 enable flag output latch I/O mode 8 TM06 TM05 TM04 TM03 TM02 TM01 TM00 26 Figure 6-5. Timer/Event Counter (Channel 1) Block Diagram Internal bus 8 TOE1 TM1 8 - TM16 TM15 TM14 TM13 TM12 TM11 TM10 TMOD1 Decoder PORT1.3 T1 enable flag PORT2.1 P21 output latch Bit 2 of PMGB Port 2 input/output mode Modulo register (8) 8 Match TOUT F/F Comparator (8) Input buffer TI0/TI1/P13 TI0/TI1/P13 8 MPX CP Output buffer Reset T1 Count register (8) Clear RESET Timer operation start 16 bit timer/event counter mode IRQT1 clear signal Selector Timer/event counter (channel 0) TM02 signal (When 16 bit timer/event counter mode) Timer/event counter (channel 0) match signal/operation start (When 16-bit timer/event counter mode) Timer/event counter (channel 0) comparator (When 16-bit timer/event counter mode) INTT1 IRQT1 set signal µPD754302 PD754302, 754304, 754302(A), 754304(A) Data Sheet U10797EJ2V1DS U10797EJ2V1DS Timer/event counter (channel 0) output fX/22 fX/26 From clock fX/28 generator fX/210 fX/212 P21/PTO1 P21/PTO1 µPD754302 PD754302, 754304, 754302(A), 754304(A) 6.6 Serial Interface The µ PD754304 PD754304 incorporates the clocked 8-bit serial interface, and the following three modes are provided. · Operation stop mode · 3-wire serial I/O mode · 2-wire serial I/O mode Data Sheet U10797EJ2V1DS U10797EJ2V1DS 27 28 Figure 6-6. Serial Interface Block Diagram Internal bus 8/4 Bit test 8 CSIM Bit manipulation 8 8 SBIC Slave address register (SVA) (8) Address comparator P03/SI P03/SI Matching RELT signal (8) CMDT SET CLR Selector D Q (8) P02/SO/SB0 P02/SO/SB0 P01/SCK P01/SCK Serial clock counter P01 output Iatch Serial clock control circuit INTCSI IRQCSI set signal INTCSI control circuit Serial clock selector fX/23 fX/24 fX/26 TOUT F/F (from timer/event counter 0) External SCK µPD754302 PD754302, 754304, 754302(A), 754304(A) Data Sheet U10797EJ2V1DS U10797EJ2V1DS Shift register (SIO) SO latch µPD754302 PD754302, 754304, 754302(A), 754304(A) 6.7 Bit Sequential Buffer . 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. The data memory is composed of 16 bits and the pmem.@L addressing of a bit manipulation instruction is possible. The bit can be specified indirectly by the L register. In this case, processing can be done by moving the specified bit in sequence by incrementing and decrementing the L register in the program loop. Figure 6-7. Bit Sequential Buffer Format Address Bit FC3H 3 Symbol L register 2 1 FC2H 0 3 2 BSB3 L = FH 1 FC1H 0 3 BSB2 L = CH L = BH 2 1 FC0H 0 3 BSB1 L = 8H L = 7H L = 4H L = 3H DECS L 2 1 0 BSB0 L = 0H INCS L Remarks 1. 2. In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MSB specification. Data Sheet U10797EJ2V1DS U10797EJ2V1DS 29 µPD754302 PD754302, 754304, 754302(A), 754304(A) 7. INTERRUPT FUNCTION AND TEST FUNCTION The µPD754304 PD754304 has seven kinds of interrupt sources and one kind of test source. Two types of edge detection testable inputs are provided for INT2 of the test source. The interrupt control circuit of the µPD754304 PD754304 has the following functions. (1) Interrupt function · Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IE×××) and interrupt master enable flag (IME). · Can set any interrupt start address. · Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). · Test function of interrupt request flag (IRQ×××). An interrupt generated can be checked by software. · Release the standby mode. A release interrupt can be selected by the interrupt enable flag. (2) Test function · Test request flag (IRQxxx) generation can be checked by software. · Release the standby mode. The test source to be released can be selected by the test enable flag. 30 Data Sheet U10797EJ2V1DS U10797EJ2V1DS Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus 2 1 4 IME IPS IM2 IM1 IST1 IST0 Interrupt enable flag (IE ××× ) IM0 Decoder INTBT INT4/P00 INT4/P00 INT0/P10 INT0/P10 Note Edge detector VRQn IRQ4 IRQ0 IRQ1 INTCSI INTT0 KR0/P60 KR0/P60 KR7/P73 KR7/P73 Rising edge detector Priority control circuit Vector table address generator IRQT0 INTT1 INT2/P12 INT2/P12 IRQCSI IRQT1 Selector IRQ2 Falling edge detector Standby release signal IM2 Note Noise eliminator (Standby release is disabled when noise eliminator is selected.) 31 µPD754302 PD754302, 754304, 754302(A), 754304(A) Data Sheet U10797EJ2V1DS U10797EJ2V1DS INT1/P11 INT1/P11 Selector Both edge detector Edge detector IRQBT µPD754302 PD754302, 754304, 754302(A), 754304(A) 8. STANDBY FUNCTION In order to save dissipation power while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µPD754304 PD754304. Table 8-1. Operation Status in Standby Mode Mode Item STOP mode HALT mode Set instruction STOP instruction HALT instruction Operation status Clock generator The system clock stops oscillation. Only the CPU clock halts (oscillation continues). Basic interval timer/ Watchdog timer Operation stops. Operable (The IRQBT is set in the reference interval). Serial interface Operable only when an external SCK input is selected as the serial clock. Operable Timer/event counter Operable only when a signal input to the TI0 and TI1 pins are specified as the count clock. Operable External interrupt The INT1, 2, and 4 are operable. Only the INT0 is not operated Note. CPU The operation stops. Release signal Note Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag or RESET signal input. Operable only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0). 32 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) 9. RESET FUNCTION There are two reset inputs: external RESET signal and RESET signal sent from the basic interval timer/ watchdog timer. When either one of the RESET signals are input, an internal RESET signal is generated. Figure 9-1 shows the circuit diagram of the above two inputs. Figure 9-1. Configuration of Reset Function RESET Internal RESET signal RESET signal sent from the basic interval timer/watchdog timer WDTM Internal bus Generation of the RESET signal initializes each hardware as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation Wait Note RESET signal generated Operation mode or standby mode HALT mode Operation mode Internal reset operation Note The following two times can be selected by the mask option. 2 17/fX (21.8 ms : @ 6.0 MHz, 31.3 ms: @ 4.19 MHz) 2 15/fX (5.46 ms : @ 6.0 MHz, 7.81 ms: @ 4.19 MHz) Data Sheet U10797EJ2V1DS U10797EJ2V1DS 33 µPD754302 PD754302, 754304, 754302(A), 754304(A) Table 9-1. Status of Each Hardware After Reset (1/2) RESET signal generation in the standby mode RESET signal generation in operation µPD754302 PD754302 Sets the low-order 3 bits of program memory's address 0000H 0000H to the PC10-PC8 PC10-PC8 and the contents of address 0001H 0001H to the PC7-PC0. Sets the low-order 3 bits of program memory's address 0000H 0000H to the PC10-PC8 PC10-PC8 and the contents of address 0001H 0001H to the PC7-PC0. µPD754304 PD754304 Sets the low-order 4 bits of program memory's address 0000H 0000H to the PC11-PC8 PC11-PC8 and the contents of address 0001H 0001H to the PC7-PC0. Sets the low-order 4 bits of program memory's address 0000H 0000H to the PC11-PC8 PC11-PC8 and the contents of address 0001H 0001H to the PC7-PC0. Held Undefined Skip flag (SK0-SK2) 0 0 Interrupt status flag (IST0, IST1) 0 0 Sets the bit 6 of program memory's address 0000H 0000H to the RBE and bit 7 to the MBE. Sets the bit 6 of program memory's address 0000H 0000H to the RBE and bit 7 to the MBE. Undefined Undefined 1000B 1000B 1000B 1000B Data memory (RAM) Held Undefined General-purpose register (X, A, H, L, D, E, B, C) Held Undefined Bank select register (MBS, RBS) 0, 0 0, 0 Undefined Undefined Hardware Program counter (PC) PSW Carry flag (CY) Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Basic interval Counter (BT) timer/watchdog Mode register (BTM) 0 0 timer Watchdog timer enable flag (WDTM) 0 0 Timer/event Counter (T0) 0 0 counter (T0) Modulo register (TMOD0) FFH FFH 0 0 0, 0 0, 0 0 0 FFH FFH 0 0 TOE1, TOUT F/F 0, 0 0, 0 Serial Shift register (SIO) Held Undefined interface Operation mode register (CSIM) 0 0 SBI control register (SBIC) 0 0 Held Undefined Mode register (TM0) TOE0, TOUT F/F Timer/event Counter (T1) counter (T1) Modulo register (TMOD1) Mode register (TM1) Slave address register (SVA) Clock generator, Processor clock control register (PCC) 0 0 clock output Clock output mode register (CLOM) 0 0 circuit 34 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) Table 9-1. Status of Each Hardware After Reset (2/2) RESET signal generation in the standby mode Hardware RESET signal generation in operation Reset (0) Reset (0) Interrupt Interrupt request flag (IRQ×××) function Interrupt enable flag (IE×××) 0 0 Interrupt priority select register (IPS) 0 0 INT0, 1, 2 mode registers (IM0, IM1, IM2) 0, 0, 0 0, 0, 0 Output buffer Off Off Output latch Cleared (0) Cleared (0) I/O mode registers (PMGA, B, C) 0 0 Pull-up resistor setting registers (POGA, B) 0 0 Held Undefined Digital port Bit sequential buffers (BSB0-BSB3) Data Sheet U10797EJ2V1DS U10797EJ2V1DS 35 µPD754302 PD754302, 754304, 754302(A), 754304(A) 10. MASK OPTION The µPD754304 PD754304 has the following mask options: · Mask option of P50 through P53 Pull-up resistors can be connected to these pins. (1) Specify connection of a pull-up resistor in 1-bit units. (2) Do not specify connection of a pull-up resistor. · Standby function mask option The wait time when the RESET signal is input can be selected. (1) 2 17/fX (21.8 ms: fX = 6.0 MHz, 31.3 ms: fX = 4.19 MHz) (2) 2 15/fX (5.46 ms: fX = 6.0 MHz, 7.81 ms: fX = 4.19 MHz) 36 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) 11. INSTRUCTION SETS (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to RA75X RA75X ASSEMBLER PACKAGE USERS' MANUAL-LANGUAGE (EEU-1363 EEU-1363). If there are several elements, one of them is selected. Capital letters and the + and ­ symbols are key words and are described as they are. For immediate data, appropriate numbers and labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, refer to the µPD754304 PD754304 USER'S MANUAL (U10123E U10123E). Representation format Description method reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 rp' rp'1 XA, BC, BC, XA, BC, rpa rpa1 HL, HL+, HL­, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or label 2-bit immediate data or label fmem pmem FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label addr caddr faddr 0000H-07FFH 0000H-07FFH immediate data or label (µPD754302 PD754302) 0000H-0FFFH 0000H-0FFFH immediate data or label (µPD754304 PD754304) 0000H-07FFH 0000H-07FFH immediate data or label (µPD754302 PD754302) 0000H-0FFFH 0000H-0FFFH immediate data or label (µPD754304 PD754304) 12-bit immediate data or label 11-bit immediate data or label taddr 20H-7FH 20H-7FH immediate data (where bit 0 = 0) or label PORTn IE××× RBn MBn PORT0-PORT3, PORT5-PORT8 IEBT, IET0, IET1, IE0-IE2, IE4, IECSI RB0-RB3 MB0, MB15 addr1 BC, DE, DE BC, DE, DE, HL HL DE, HL, XA', BC', DE', HL' HL, XA', BC', DE', HL' Note Note mem can be only used for even address in 8-bit data processing. Data Sheet U10797EJ2V1DS U10797EJ2V1DS 37 µPD754302 PD754302, 754304, 754302(A), 754304(A) (2) Legend in explanation of operation A : A register; 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : XA register pair; 8-bit accumulator BC : BC register pair DE : DE register pair HL : HL register pair XA' : XA' expanded register pair BC' : BC' expanded register pair DE' : DE' expanded register pair HL' : HL' expanded register pair PC : Program counter SP : Stack pointer CY : Carry flag; bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0-3, 5-8) IME : Interrupt master enable flag IPS : Interrupt priority select register IExxx : Interrupt enable flag RBS : Memory bank select register PCC : Processor clock control register . : Separation between address and bit (××) : The contents addressed by ×× ××H 38 : Register bank select register MBS : Hexadecimal data Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) (3) Explanation of symbols under addressing area column *1 MB = MBE·MBS (MBS = 0, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (000H-07FH 000H-07FH) MB = 15 (F80H-FFFH F80H-FFFH) MBE = 1 : MB = MBS (MBS = 0, 15) Data memory addressing *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 µPD754302 PD754302 addr = 0000H-07FFH 0000H-07FFH µPD754304 PD754304 addr = 0000H-0FFFH 0000H-0FFFH *7 addr = (Current PC) ­ 15 to (Current PC) ­ 1 (Current PC) + 2 to (Current PC) + 16 addr1 = (Current PC) ­ 15 to (Current PC) ­ 1 (Current PC) + 2 to (Current PC) + 16 µPD754302 PD754302 caddr = 0000H-07FFH 0000H-07FFH µPD754304 PD754304 *8 caddr = 0000H-0FFFH 0000H-0FFFH (PC12 = 0) *9 faddr = 0000H-07FFH 0000H-07FFH *10 taddr = 0020H-007FH 0020H-007FH *11 µPD754302 PD754302 addr1 = 0000H-07FFH 0000H-07FFH µPD754304 PD754304 Program memory addressing addr1 = 0000H-0FFFH 0000H-0FFFH Remarks 1. MB indicates memory bank that can be accessed. 2. In *2, MB = 0 independently of how MBE and MBS are set. 3. In *4 and *5, MB = 15 independently of how MBE and MBS are set. 4. *6 to *11 indicate the areas that can be addressed. (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. · When no skip is made: S = 0 · When the skipped instruction is a 1- or 2-byte instruction: S = 1 · When the skipped instruction is a 3-byte instruction Note : S=2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC. Data Sheet U10797EJ2V1DS U10797EJ2V1DS 39 µPD754302 PD754302, 754304, 754302(A), 754304(A) A n4 2 2 reg1 n4 2 2 XA n8 String effect A 2 2 HL n8 String effect B 2 2 rp2 n8 1 1 A (HL) *1 A, @HL+ 1 2+S A (HL), then L L+1 *1 L=0 A, @HL­ 1 2+S A (HL), then L L­1 *1 L = FH A, @rpa 1 1 A (rpa) *2 XA, @HL 2 2 XA (HL) *1 @HL, A 1 1 (HL) A *1 @HL, XA 2 2 (HL) XA *1 A, mem 2 2 A (mem) *3 XA, mem 2 2 XA (mem) *3 mem, A 2 2 (mem) A *3 mem, XA 2 2 (mem) XA *3 A, reg1 2 2 A reg1 XA, rp' 2 2 XA rp' reg1, A 2 2 reg1 A rp'1, XA 2 2 rp'1 XA A, @HL 1 1 A (HL) *1 A, @HL+ 1 2+S A (HL), then L L+1 *1 L=0 A, @HL­ 1 2+S A (HL), then L L­1 *1 L = FH A, @rpa 1 1 A (rpa) *2 XA, @HL 2 2 XA (HL) *1 A, mem 2 2 A (mem) *3 XA, mem 2 2 XA (mem) *3 A, reg1 1 1 A reg1 XA, rp' MOVT 1 A, @HL Table 1 rp2, #n8 XCH A, #n4 HL, #n8 MOV Number of machine cycles XA, #n8 Transfer Mnemonic Number of bytes reg1, #n4 Instruction group 2 2 XA rp' XA, @PCDE 1 3 Operand Operation Addressing area Skip condition String effect A µPD754302 PD754302 XA (PC10­8+DE)ROM reference µPD754304 PD754304 XA (PC11­8+DE)ROM XA, @PCXA 1 3 µPD754302 PD754302 XA (PC10­8+XA)ROM µPD754304 PD754304 XA (PC11­8+XA)ROM XA, @BCDE 3 XA (BCDE)ROM Note *6 XA, @BCXA Note 1 1 3 XA (BCXA)ROM Note *6 To use the µPD754302 PD754302, clear the most significant bit of the register C and register B to "0". To use the µPD754304 PD754304, clear the register B to "0". 40 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) CY, fmem.bit 2 2 CY (fmem.bit) *4 2 2 CY (pmem7­2+L3­2.bit(L1­0) *5 2 2 CY (H+mem3­0.bit) *1 fmem.bit, CY 2 2 (fmem.bit) CY *4 pmem.@L, CY 2 2 (pmem7­2+L3­2.bit(L1­0) CY *5 @H+mem.bit, CY 2 2 (H+mem3­0.bit) CY *1 A, #n4 1 1+S A A+n4 carry XA, #n8 2 2+S XA XA+n8 carry A, @HL 1 1+S A A+(HL) XA, rp' 2 2+S XA XA+rp' carry rp'1, XA 2 2+S rp'1 rp'1+XA carry A, @HL 1 1 A, CY A+(HL)+CY XA, rp' 2 2 XA, CY XA+rp'+CY rp'1, XA 2 2 rp'1, CY rp'1+XA+CY A, @HL 1 1+S A A­(HL) XA, rp' 2 2+S XA XA­rp' borrow rp'1, XA 2 2+S rp'1 rp'1­XA borrow A, @HL 1 1 A, CY A­(HL)­CY XA, rp' 2 2 XA, CY XA­rp'­CY rp'1, XA 2 2 rp'1, CY rp'1­XA­CY A, #n4 2 2 A A n4 A, @HL 1 1 A A (HL) XA, rp' 2 2 XA XA rp' rp'1, XA 2 2 rp'1 rp'1 XA A, #n4 2 2 A A n4 A, @HL 1 1 A A (HL) XA, rp' 2 2 XA XA rp' rp'1, XA 2 2 rp'1 rp'1 XA A, #n4 2 2 A A v n4 A, @HL 1 1 A A v (HL) XA, rp' 2 2 XA XA v rp' rp'1, XA Operation Number of machine cycles CY, @H+mem.bit Bit transfer Number of bytes CY, pmem.@L Instruction group 2 2 rp'1 rp'1 v XA RORC A 1 1 CY A0, A3 CY, An­1 An NOT A 2 2 AA INCS reg 1 1+S reg reg+1 reg=0 rp1 1 1+S rp1 rp1+1 rp1=00H @HL 2 2+S (HL) (HL)+1 *1 (HL)=0 mem 2 2+S (mem) (mem)+1 *3 (mem)=0 reg 1 1+S reg reg­1 reg=FH rp' 2 2+S rp' rp'­1 rp'=FFH Mnemonic MOV1 ADDS ADDC SUBS SUBC AND OR XOR Accumulator manipulation Increment and decrement DECS Operand Operation Data Sheet U10797EJ2V1DS U10797EJ2V1DS Addressing area *1 Skip condition carry *1 *1 borrow *1 *1 *1 *1 41 µPD754302 PD754302, 754304, 754302(A), 754304(A) 2+S Skip if reg = n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 1 1+S Skip if A = (HL) *1 A = (HL) 2 2+S Skip if XA = (HL) *1 XA = (HL) 2 2+S Skip if A = reg A=reg XA, rp' 2 2+S Skip if XA = rp' XA=rp' SET1 CY 1 1 CY 1 CLR1 CY 1 1 CY 0 SKT CY 1 1+S NOT1 CY 1 1 CY CY SET1 mem.bit 2 2 (mem.bit) 1 *3 fmem.bit 2 2 (fmem.bit) 1 *4 pmem.@L 2 2 (pmem7­2+L3­2.bit(L1­0) 1 *5 @H+mem.bit 2 2 (H+mem3­0.bit) 1 *1 mem.bit 2 2 (mem.bit) 0 *3 fmem.bit 2 2 (fmem.bit) 0 *4 pmem.@L 2 2 (pmem7­2+L3­2.bit(L1­0) 0 *5 @H+mem.bit 2 2 (H+mem3­0.bit) 0 *1 mem.bit 2 2+S Skip if (mem.bit)=1 *3 (mem.bit)=1 fmem.bit 2 2+S Skip if (fmem.bit)=1 *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7­2+L3­2.bit(L1­0)=1 *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if (H+mem3­0.bit)=1 *1 (@H+mem.bit)=1 mem.bit 2 2+S Skip if (mem.bit)=0 *3 (mem.bit)=0 fmem.bit 2 2+S Skip if (fmem.bit)=0 *4 (fmem.bit)=0 pmem.@L 2 2+S Skip if (pmem7­2+L3­2.bit(L1­0)=0 *5 (pmem.@L)=0 @H+mem.bit 2 2+S Skip if (H+mem3­0.bit)=0 *1 (@H+mem.bit)=0 fmem.bit 2 2+S Skip if (fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7­2+L3­2.bit(L1­0)=1 and clear *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if (H+mem3­0.bit)=1 and clear *1 (@H+mem.bit)=1 CY, fmem.bit 2 2 CY CY (fmem.bit) *4 CY, pmem.@L 2 2 CY CY (pmem7­2+L3­2.bit(L1­0) *5 CY, @H+mem.bit 2 2 CY CY (H+mem3­0.bit) *1 CY, fmem.bit 2 2 CY CY (fmem.bit) *4 CY, pmem.@L 2 2 CY CY (pmem7­2+L3­2.bit(L1­0) *5 CY, @H+mem.bit 2 2 CY CY (H+mem3­0.bit) *1 CY, fmem.bit 2 2 CY CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY CY v (pmem7­2+L3­2.bit(L1­0) *5 CY, @H+mem.bit Memory bit 2 A, reg manipulation reg, #n4 XA, @HL Carry flag Number of machine cycles A, @HL Comparison Number of bytes @HL, #n4 Instruction group 2 2 CY CY v (H+mem3­0.bit) *1 Mnemonic SKE manipulation CLR1 SKT SKF SKTCLR AND1 OR1 XOR1 42 Operand Operation Addressing area reg=n4 Skip if CY = 1 Data Sheet U10797EJ2V1DS U10797EJ2V1DS Skip condition CY=1 µPD754302 PD754302, 754304, 754302(A), 754304(A) Instruction group Branch Mnemonic BR Note Operand addr Number of bytes Number of machine cycles ­ ­ Operation Addressing area · µPD754302 PD754302 Skip condition *6 PC10­0 addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. · µPD754304 PD754304 PC11­0 addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. addr1 ­ ­ · µPD754302 PD754302 *11 PC10-0 PC10-0 addr Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. · µPD754304 PD754304 PC11­0 addr1 Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. !addr 3 3 · µPD754302 PD754302 *6 PC10­0 addr · µPD754304 PD754304 PC11­0 addr $addr 1 2 · µPD754302 PD754302 *7 PC10­0 addr · µPD754304 PD754304 PC11­0 addr $addr1 1 2 · µPD754302 PD754302 PC10­0 addr1 · µPD754304 PD754304 PC11­0 addr1 PCDE 2 3 · µPD754302 PD754302 PC10­0 PC10-8 PC10-8+DE · µPD754304 PD754304 PC11­0 PC11-8 PC11-8+DE PCXA 2 3 · µPD754302 PD754302 PC10­0 PC10-8 PC10-8+XA · µPD754304 PD754304 PC11­0 PC11-8 PC11-8+XA Note The above operations in the double boxes can be performed only in the Mk II mode. Data Sheet U10797EJ2V1DS U10797EJ2V1DS 43 µPD754302 PD754302, 754304, 754302(A), 754304(A) Instruction group Branch Mnemonic BR Operand Number of bytes Number of machine cycles 2 3 BCDE Operation · µPD754302 PD754302 Addressing area Skip condition *6 PC10­0 BCDE Note1 · µPD754304 PD754304 PC11­0 BCDE Note2 BCXA 2 3 · µPD754302 PD754302 *6 PC10­0 BCXA Note1 · µPD754304 PD754304 PC11­0 BCXA Note2 BRA Note3 !addr1 3 3 · µPD754302 PD754302 *11 PC10­0 addr1 · µPD754304 PD754304 PC11­0 addr1 BRCB !caddr 2 2 · µPD754302 PD754302 *8 PC10­0 caddr10­0 · µPD754304 PD754304 PC11­0 caddr11­0 Subroutine CALLANote3 !addr1 3 3 · µPD754302 PD754302 *11 (SP­2) ×, ×, MBE, RBE stack control (SP­6) (SP­3) (SP­4) PC10­0 (SP­5) 0, 0, 0, 0 PC10­0 addr1, SP SP­6 · µPD754304 PD754304 (SP­2) ×, ×, MBE, RBE (SP­6) (SP­3) (SP­4) PC11­0 (SP­5) 0, 0, 0, 0 PC11­0 addr1, SP SP­6 CALL Note3 !addr 3 3 · µPD754302 PD754302 *6 (SP­3) MBE, RBE, 0, 0 (SP­4) (SP­1) (SP­2) PC10­0 PC10­0 addr, SP SP­4 · µPD754304 PD754304 (SP­3) MBE, RBE, 0, 0 (SP­4) (SP­1) (SP­2) PC11­0 PC11­0 addr, SP SP­4 4 · µPD754302 PD754302 (SP­2) ×, ×, MBE, RBE (SP­6) (SP­3) (SP­4) PC10­0 (SP­5) 0, 0, 0, 0 PC10­0 addr, SP SP­6 · µPD754304 PD754304 (SP­2) ×, ×, MBE, RBE (SP­6) (SP­3) (SP­4) PC11­0 (SP­5) 0, 0, 0, 0 PC11­0 addr, SP SP­6 Notes 1. "0" must be set to the most significant bit of the register C and register B. 2. "0" must be set to register B. 3. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 44 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) Instruction group Subroutine Mnemonic CALLF Note Operand !faddr Number of bytes Number of machine cycles 2 2 Operation · µPD754302 PD754302 Addressing area Skip condition *9 (SP­3) MBE, RBE, 0, 0 stack control (SP­4) (SP­1) (SP­2) PC10­0 PC10­0 faddr, SP SP­4 · µPD754304 PD754304 (SP­3) MBE, RBE, 0, 0 (SP­4) (SP­1) (SP­2) PC11­0 PC11­0 0+faddr, SP SP­4 3 · µPD754302 PD754302 (SP­2) ×, ×, MBE, RBE (SP­6) (SP­3) (SP­4) PC10­0 (SP­5) 0, 0, 0, 0 PC10­0 faddr, SP SP­6 · µPD754304 PD754304 (SP­2) ×, ×, MBE, RBE (SP­6) (SP­3) (SP­4) PC11­0 (SP­5) 0, 0, 0, 0 PC11­0 0+faddr, SP SP­6 RET Note 1 3 · µPD754302 PD754302 PC10­0 (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 (SP+1), SP SP+4 · µPD754304 PD754304 PC11­0 (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 (SP+1), SP SP+4 · µPD754302 PD754302 ×, ×, MBE, RBE (SP+4) 0, 0, 0, 0, (SP+1) PC10­0 (SP) (SP+3) (SP+2), SP SP+6 · µPD754304 PD754304 ×, ×, MBE, RBE (SP+4) 0, 0, 0, 0 (SP+1) PC10­0 (SP) (SP+3) (SP+2), SP SP+6 RETS Note 1 3+S · µPD754302 PD754302 Unconditional MBE, RBE, 0, 0 (SP+1) PC10­0 (SP) (SP+3) (SP+2) SP SP+4 then skip unconditionally · µPD754304 PD754304 MBE, RBE, 0, 0 (SP+1) PC11­0 (SP) (SP+3) (SP+2) SP SP+4 then skip unconditionally Note The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Data Sheet U10797EJ2V1DS U10797EJ2V1DS 45 µPD754302 PD754302, 754304, 754302(A), 754304(A) Instruction group Subroutine Operand RETS Note1 Number of bytes Number of machine cycles 1 Mnemonic 3+S Addressing area Operation · µPD754302 PD754302 Skip condition Unconditional 0, 0, 0, 0 (SP+1) stack control PC10­0 (SP) (SP+3) (SP+2) ×, ×, MBE, RBE (SP+4) SP SP+6 then skip unconditionally · µPD754304 PD754304 0, 0, 0, 0 (SP+1) PC11­0 (SP) (SP+3) (SP+2) ×, ×, MBE, RBE (SP+4) SP SP+6 then skip unconditionally RETI Note1 1 3 · µPD754302 PD754302 MBE, RBE, 0, 0 (SP+1) PC10­0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 · µPD754304 PD754304 MBE, RBE, 0, 0 (SP+1) PC11­0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 · µPD754302 PD754302 0, 0, 0, 0 (SP+1) PC10­0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 · µPD754304 PD754304 0, 0, 0, 0 (SP+1) PC11­0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 1 (SP­1)(SP­2) rp, SP SP­2 2 2 (SP­1) MBS, (SP­2) RBS, SP SP­2 rp 1 1 rp (SP+1) (SP), SP SP+2 2 2 MBS (SP+1), RBS (SP), SP SP+2 2 2 IME (IPS.3) 1 2 2 IE××× 1 2 2 IME (IPS.3) 0 IE××× 2 2 IE××× 0 A, PORTn 2 2 A PORTn XA, PORTn 2 2 XA PORTn+1, PORTn PORTn, A 2 2 PORTn A PORTn, XA Interrupt 1 BS POP rp BS PUSH 2 2 PORTn+1, PORTn XA EI control IE××× DI Input/output IN Note2 OUT Note2 Notes 1. (n = 0-3, 5-8) (n = 6) (n = 2, 3, 5-8) (n = 6) The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and MBS must be set to 15. 46 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) HALT 2 2 Set HALT Mode (PCC.2 1) 2 2 Set STOP Mode (PCC.3 1) 1 1 No Operation RBn 2 2 RBS n (n = 0-3) MBn 2 2 MBS n (n = 0, 15) GETI Notes 1, 2 taddr Special Number of machine cycles NOP CPU control Number of bytes STOP Instruction group 1 3 · µPD754302 PD754302 Mnemonic SEL Operand Addressing area Operation Skip condition *10 · When TBR instruction PC10­0 (taddr) 2­0 + (taddr+1) ­­­­­­­­­­­­ ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ · When TCALL instruction (SP­4) (SP­1) (SP­2) PC10­0 (SP­3) MBE, RBE, 0, 0 PC10­0 (taddr) 2­0 + (taddr+1) SP SP­4 ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ ­­­­­­­­­­­­ · When instruction other than TBR and Depending on TCALL instructions the reference (taddr) (taddr+1) instruction is executed. instruction · µPD754304 PD754304 · When TBR instruction PC11­0 (taddr) 3­0 + (taddr+1) ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ ­­­­­­­­­­­­ · When TCALL instruction (SP­4) (SP­1) (SP­2) PC11­0 (SP­3) MBE, RBE, 0, 0 PC11­0 (taddr) 3­0 + (taddr+1) SP SP­4 ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ ­­­­­­­­­­­­ · When instruction other than TBR and Depending on TCALL instructions 3 the reference (taddr) (taddr+1) instruction is executed. instruction · µPD754302 PD754302 *10 · When TBR instruction PC10­0 (taddr) 2­0 + (taddr+1) ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ 4 ­­­­­­­­­­­­ · When TCALL instruction (SP­6) (SP­3) (SP­4) PC10­0 (SP­5) 0, 0, 0, 0 (SP­2) ×, ×, MBE, RBE PC10­0 (taddr) 2­0 + (taddr+1) SP SP­6 ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ 3 · When instruction other than TBR and ­­­­­­­­­­­­ Depending on TCALL instructions the reference (taddr) (taddr+1) instruction is executed. instruction Notes 1. The TBR and TCALL instructions are the table definition assembler directives of the GETI instruction. 2. The above operations in the double boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Data Sheet U10797EJ2V1DS U10797EJ2V1DS 47 µPD754302 PD754302, 754304, 754302(A), 754304(A) Instruction group Mnemonic GETI Notes 1, 2 taddr Special Operand Number of bytes Number of machine cycles 1 3 Operation · µPD754304 PD754304 Addressing area Skip condition *10 · When TBR instruction PC11­0 (taddr) 3­0 + (taddr+1) ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ 4 ­­­­­­­­­­­­ · When TCALL instruction (SP­6) (SP­3) (SP­4) PC11­0 (SP­5) 0, 0, 0, 0 (SP­2) ×, ×, MBE, RBE PC11­0 (taddr) 3­0 + (taddr+1) SP SP­6 ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ 3 · When instruction other than TBR and ­­­­­­­­­­­­ Depending on TCALL instructions Notes 1. 2. 48 the reference (taddr) (taddr+1) instruction is executed. instruction The TBR and TCALL instructions are the table definition assembler directives of the GETI instruction. The above operations in the double boxes can be performed only in the Mk II mode. Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Test Conditions Ratings Unit ­0.3 to +7.0 V ­0.3 to VDD + 0.3 V ­0.3 to VDD + 0.3 V ­0.3 to +14 V ­0.3 to VDD + 0.3 V Per pin ­10 mA For all pins ­30 mA Per pin 30 mA For all pins 220 mA TA ­40 to +85 °C Tstg ­65 to +150 °C Supply voltage V DD Input voltage V I1 Except port 5 V I2 Port 5 Pull-up resistor incorporated N-ch open-drain Output voltage VO Output current, high IOH Output current, low IOL Note Operating ambient temperature Storage temperature Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. The absolute maximum ratings are values that may physically damage the products. Be sure to use the products within the ratings. Capacitance (TA = 25 °C, VDD = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz 15 pF Output capacitance COUT Unmeasured pins returned to 0 V 15 pF I/O capacitance CIO 15 pF Data Sheet U10797EJ2V1DS U10797EJ2V1DS 49 µPD754302 PD754302, 754304, 754302(A), 754304(A) System Clock Oscillator Characteristics (TA = ­40 to +85 °C, VDD = 1.8 to 5.5 V) Resonator Recommended Constant Ceramic Parameter Testing Conditions Oscillation resonator X1 frequency (fX) X2 C2 1.0 Oscillation After VDD reaches MIN. Note 3 frequency(f X) X1 Unit 6.0Note2 MHz 4 ms voltage range Oscillation resonator MAX. value of oscillation time Crystal TYP. Note1 stabilization C1 MIN. 1.0 6.0Note2 MHz Note1 X2 Oscillation VDD = 4.5 to 5.5 V C1 ms ms Note3 C2 External X1 input clock 10 30 stabilization time X1 X2 frequency (fX) 1.0 6.0Note2 MHz Note1 X1 input high- and 83.3 500 ns low-level widths (tXH, t XL) Notes 1. Only the oscillator characteristics are shown. For the instruction execution time, refer to AC Characteristics. 2. If the oscillation frequency is 4.19 MHz < fX 6.0 MHz at 1.8 V VDD < 2.7 V, set the processor control register (PCC) to a value other than 0011. If the PCC is set to 0011, the rated cycle time of 0.95 µs is not satisfied. 3. Oscillation stabilization time is a time required for oscillation to stabilize after application of VDD, or after the STOP mode has been released. Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted lines in the figures as follows to avoid adverse influences on the wiring capacitance: · Keep the wire length as short as possible. · Do not cross other signal lines. · Do not route the wiring in the vicinity of lines though which a high fluctuating current flows. · Always keep the ground point of the capacitor of the oscillation circuit as the same potential as VSS. · Do not connect the power source pattern through which a high current flows. · Do not extract signals from the oscillation circuit. 50 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) Recommended Oscillation Circuit Constants Ceramic Resonator (TA = ­40 to +85 °C) Manufacturer Product Frequency Recommended Circuit Constants (pF) Oscillation Voltage Range (VDD) Remarks (MHz) C1 C2 MIN. MAX. 1.0 100 100 2.7 5.5 2.0 30 30 1.8 5.5 ­ ­ 30 30 CST3.58MGW 58MGW ­ ­ CSA3.58MGU 58MGU 30 30 CST3.58MGWU 58MGWU ­ ­ 30 30 CST4.00MGW 00MGW ­ ­ CSA4.00MGU 00MGU 30 30 CST4.00MGWU 00MGWU ­ ­ 30 30 CST6.00MGW 00MGW ­ ­ CSA6.00MGU 00MGU 30 30 CST6.00MGWU 00MGWU ­ ­ 1.0 100 100 1.8 5.5 KBR-2.0MS 2.0 47 47 2.0 5.5 KBR-4.0MSA 4.0 33 33 1.8 5.5 KBR-4.0MKS ­ ­ Capacitor incorporated, T A = ­20 to +80 °C PBRC 4.00A 33 33 TA = ­20 to +80 °C PBRC 4.00B ­ ­ Capacitor incorporated, T A = ­20 to +80 °C 33 33 ­ ­ Note Murata CSB1000J CSB1000J Mfg. Co., Ltd CSA2.00MG CST2.00MG CSA3.58MG CSA4.00MG CSA6.00MG Kyocera Corp. KBR-1000F/Y KBR-1000F/Y KBR-6.0MSA 3.58 4.0 6.0 6.0 Rd = 5.6 k Capacitor incorporated 1.8 5.5 Capacitor incorporated Capacitor incorporated 2.0 5.5 Capacitor incorporated 1.8 Capacitor incorporated 2.9 5.5 Capacitor incorporated 1.8 Capacitor incorporated 1.8 5.5 TA = ­20 to +80 °C T A = ­20 to +80 °C PBRC 6.00A PBRC 6.00B TDK CCR1000K2 CCR1000K2 1.0 100 100 CCR2.0MC33 0MC33 2.0 ­ ­ CCR4.19MC3 19MC3 Capacitor incorporated, T A = ­20 to +80 °C 1.8 5.5 4.19 Capacitor incorporated FCR4.19MC5 19MC5 CCR6.0MC3 6.0 Data Sheet U10797EJ2V1DS U10797EJ2V1DS 51 µPD754302 PD754302, 754304, 754302(A), 754304(A) Note If using Murata's CSB1000J CSB1000J (1.0 MHz) as the ceramic resonator, a limited resistor (Rd = 5.6 k) is required (see figure below). If using any other recommended resonator, no limited resistor is needed. X1 X2 CSB1000J CSB1000J C1 Rd C2 Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable oscillation, but do not guarantee oscillation frequency accuracy. If oscillation frequency accuracy is required for actual circuits, it is necessary to adjust the oscillation frequency of the resonator in the circuit. Please inquire directly to the maker of the resonator for data as needed. 52 Data Sheet U10797EJ2V1DS U10797EJ2V1DS µPD754302 PD754302, 754304, 754302(A), 754304(A) DC Characteristics (TA = ­40 to + 85 °C, VDD = 1.8 to 5.5 V) Parameter IOL MAX. Unit Per pin 15 mA For all pins Output current, low Symbol Test Conditions MIN. TYP. 150 mA V 0.9 VDD V DD V 2.7 VVDD5.5 V 0.8 VDD V DD V 0.9 VDD VDD V Pull-up resistor 2.7 VVDD5.5 V 0.7 VDD VDD V 1.8 VVDD