PD754202 U11132EJ2V1UM00 75F4264 U11132J U11132E U12181J U12181E U10453J - Datasheet Archive

 

Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

 

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website. Renesas Electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document. No license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of Renesas Electronics or others. You should not alter, modify, copy, or otherwise misappropriate any Renesas Electronics product, whether in whole or in part. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. When exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. Renesas Electronics has used reasonable care in preparing the information included in this document, but Renesas Electronics does not warrant that such information is error free. Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. Renesas Electronics products are classified according to the following three quality grades: "Standard", "High Quality", and "Specific". The recommended applications for each Renesas Electronics product depends on the product's quality grade, as indicated below. You must check the quality grade of each Renesas Electronics product before using it in a particular application. You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": 8. 9. 10. 11. 12. Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anticrime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. User's Manual µPD754202 PD754202 4-bit Single-Chip Microcontrollers Document No. U11132EJ2V1UM00 U11132EJ2V1UM00 (2nd edition) Date Published April 2003 N CP (K) c Printed in Japan NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. EEPROM is a trademark of NEC Electronics Corporation. MS-DOS is a trademark of Microsoft Corporation. IBM DOS, PC/AT and PC DOS are trademarks of IBM Corporation. These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. · The information in this document is current as of March, 2003. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. · No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. · NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. · Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. · While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. · NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M8E 02. 11-1 Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: · Device availability · Ordering information · Product release schedule · Availability of related technical literature · Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) · Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. NEC Electronics America, Inc. (U.S.) Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288 NEC Electronics (Europe) GmbH Duesseldorf, Germany Tel: 0211-65 03 01 Fax: 0211-65 03 327 · Sucursal en España Madrid, Spain Tel: 091-504 27 87 Fax: 091-504 28 60 · Succursale Française Vélizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 · Filiale Italiana Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99 NEC Electronics Hong Kong Ltd. · Branch The Netherlands Eindhoven, The Netherlands Tel: 040-244 58 45 Fax: 040-244 45 80 NEC Electronics Hong Kong Ltd. Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411 · Tyskland Filial Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388 NEC Electronics Shanghai, Ltd. · United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 NEC Electronics Taiwan Ltd. Shanghai, P.R. China Tel: 021-6841-1138 Fax: 021-6841-1137 Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Fax: 6250-3583 J02.11 Major Revisions in This Version Page Contents p. 261 APPENDIX A FUNCTIONS OF µPD754202 PD754202 AND 75F4264 75F4264 added p. 263 Device file names in APPENDIX B DEVELOPMENT TOOLS changed p. 277 APPENDIX F REVISION HISTORY added The mark shows major revised points. INTRODUCTION Readers This manual is intended for engineers who understand the functions of the µPD754202 PD754202 4-bit single-chip microcontroller and wish to design application systems using any of the microcontroller. Purpose This manual describes the hardware functions of the µPD754202 PD754202 organized in the following manner. Organization This manual contains the following information: · General · Pin Functions · Features of Architecture and Memory Map · Internal CPU Functions · Peripheral Hardware Functions · Interrupt Functions and Test Functions · Standby Functions · Reset Function · Mask Options · Instruction Set How to read this manual It is assumed that the readers of this manual possess general knowledge about electronics, logic circuits, and microcomputers. · To check the functions of an instruction whose mnemonic is known, Refer to APPENDIX D INSTRUCTION INDEX. · To check the functions of a specific internal circuit, Refer to APPENDIX E HARDWARE INDEX. · To understand the overall functions of the µPD754202 PD754202, Read this manual in the order of the Table of Contents. Legend Data significance : Left: higher, right: lower Active low : ××× (top bar over signal or pin name) Address of memory map : Top: low, Bottom: high Note : Point to note Caution : Important information Remark : Supplement Numeric notation : Binary Decimal . ×××× or ××××B . ×××× Hexadecimal . ××××H Related documents Some documents are preliminary editions but they are not so specified in the following tables. Documents related to devices Document Number Document Name Japanese English µPD754202 PD754202 User's Manual U11132J U11132J U11132E U11132E (this manual) µPD754202 PD754202 Data Sheet U12181J U12181J U12181E U12181E 75XL Series Selection Guide U10453J U10453J U10453E U10453E Documents related to development tools Document Number Document Name Japanese English EEU-846 EEU-846 EEU-1416 EEU-1416 IE-75300-R-EM IE-75300-R-EM User's Manual U11354J U11354J U11354E U11354E EP-754144GS-R EP-754144GS-R User's Manual U10695J U10695J U10695E U10695E RA75X RA75X Assembler Package Operation EEU-731 EEU-731 EEU-1346 EEU-1346 User's Manual Language EEU-730 EEU-730 EEU-1363 EEU-1363 Hardware IE-75000-R/IE-75001-R IE-75000-R/IE-75001-R User's Manual Software Other documents Document Number Document Name IC Package Manual Japanese English C10943X C10943X Semiconductor Device Mounting Technology Manual C10535J C10535J C10535E C10535E Quality Grades of NEC's Semiconductor Devices C11531J C11531J C11531E C11531E Reliability and Quality Control of NEC's Semiconductor Devices C10983J C10983J C10983E C10983E Electrostatic Discharge (ESD) Test MEM-539 MEM-539 - Quality Assurance Guide to Semiconductor Devices C11893J C11893J MEI-1202 MEI-1202 Microcomputer-Related Products Guide - by third parties U11416J U11416J - Caution These related documents are subject to change without notice. Be sure to use the latest edition of the documents when you design your system. [MEMO] TABLE OF CONTENTS CHAPTER 1 GENERAL . 1.1 Functional Outline . 1.2 Ordering Information . 1.3 Block Diagram . 1.4 Pin Configuration (Top View) . 1 2 2 3 4 CHAPTER 2 PIN FUNCTIONS . 2.1 Pin Functions . 2.2 Description of Pin Functions . 5 5 7 2.2.1 P30-P33 P30-P33 (PORT3), P60-P63 P60-P63 (PORT6), P80 (PORT8) . 7 2.2.2 P70-P73 P70-P73 (PORT7) . 7 2.2.3 PTO0-PTO2 . 7 2.2.4 INT0 . 8 2.2.5 KR4-KR7 . 8 2.2.6 KRREN . 8 2.2.7 X1 and X2 . 8 2.2.8 RESET . 9 2.2.9 IC . 9 2.2.10 VDD . 9 2.2.11 VSS . 9 I/O Circuits of Respective Pins . Processing of Unused Pins . 10 11 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP . 3.1 Bank Configuration of Data Memory and Addressing Mode . 13 13 2.3 2.4 3.1.1 Bank configuration of data memory . 13 3.1.2 Addressing mode of data memory . 15 Bank Configuration of General-Purpose Registers . Memory-Mapped I/O . 26 31 CHAPTER 4 INTERNAL CPU FUNCTION . 4.1 Function to Select MkI and MkII Modes . 41 41 3.2 3.3 4.1.1 Difference between MkI and MkII modes . 4.1.2 41 42 43 44 46 Configuration of data memory . 46 4.4.2 4.5 4.6 4.7 4.8 4.9 Setting stack bank select register (SBS) . Program Counter (PC) . Program Memory (ROM) . Data Memory (RAM) . 4.4.1 4.2 4.3 4.4 Specifying bank of data memory . 47 General-Purpose Register . Accumulator . Stack Pointer (SP) and Stack Bank Select Register (SBS) . Program Status Word (PSW) . Bank Select Register (BS) . 50 51 51 55 59 ­i­ CHAPTER 5 PERIPHERAL HARDWARE FUNCTION . 5.1 Digital I/O Port . 61 61 5.1.1 Types, features, and configurations of digital I/O ports . 62 5.1.2 Setting I/O mode . 66 5.1.3 Digital I/O port manipulation instruction . 68 5.1.4 Operation of digital I/O port . 70 5.1.5 Connecting pull-up resistor . 72 5.1.6 I/O timing of digital I/O port . 73 Clock Generation Circuit . 75 5.2.1 Configuration of clock generation circuit . 75 5.2.2 Function and operation of clock generation circuit . 76 5.2.3 5.2 Setting CPU clock . 82 Basic Interval Timer/Watchdog Timer . 84 5.3.1 Configuration of basic interval timer/watchdog timer . 84 5.3.2 5.3 Basic interval timer mode register (BTM) . 85 5.3.3 87 Operation as basic interval timer . 88 5.3.5 Operation as watchdog timer . 89 5.3.6 Other functions . 91 Timer Counter . 92 5.4.1 Configuration of timer counter . 92 5.4.2 Operation in 8-bit timer counter mode . 104 5.4.3 Operation in PWM pulse generator mode (PWM mode) . 113 5.4.4 Operation in 16-bit timer counter mode . 119 5.4.5 Operation in carrier generator mode (CG mode) . 127 5.4.6 5.4 Watchdog timer enable flag (WDTM) . 5.3.4 Notes on using timer counter . 140 Bit Sequential Buffer . 147 CHAPTER 6 INTERRUPT AND TEST FUNCTIONS . 6.1 Configuration of Interrupt Control Circuit . 6.2 Types of Interrupt Sources and Vector Table . 6.3 Hardware Controlling Interrupt Function . 6.4 Interrupt Sequence . 6.5 Nesting Control of Interrupts . 6.6 Service of Interrupts Sharing Vector Address . 6.7 Machine Cycles until Interrupt Servicing . 6.8 Effective Usage of Interrupts . 6.9 Application of Interrupt . 6.10 Test Function . 149 149 151 153 160 161 163 165 167 167 175 5.5 6.10.1 Types of test sources . 175 6.10.2 Hardware controlling test function . 175 CHAPTER 7 STANDBY FUNCTION . 7.1 Setting of and Operating Status in Standby Mode . 7.2 Releasing Standby Mode . 7.3 Operation After Release of Standby Mode . 7.4 Application of Standby Mode . 179 180 182 186 186 ­ ii ­ CHAPTER 8 RESET FUNCTION . 8.1 Configuration and Operation of Reset Function . 8.2 Watchdog Flag (WDF), Key Return Flag (KRF) . 191 191 195 CHAPTER 9 MASK OPTION . 9.1 Pin Mask Option . 197 197 9.1.1 P70/KR4-P73/KR7 P70/KR4-P73/KR7 mask option . 9.1.2 197 RESET pin mask option . 197 Oscillation Stabilization Wait Time Mask Option . 197 CHAPTER 10 INSTRUCTION SET . 10.1 Unique Instructions . 199 199 9.2 10.1.1 GETI instruction . 199 10.1.2 Bit manipulation instruction . 200 10.1.3 String-effect instruction . 200 10.1.4 Base number adjustment instruction . 201 10.1.5 Skip instruction and number of machine cycles required for skipping . 202 10.2 Instruction Set and Operation . 10.3 Op Code of Each Instruction . 10.4 Instruction Function and Application . 202 212 218 10.4.1 Transfer instructions . 219 10.4.2 Table reference instruction . 227 10.4.3 Bit transfer instruction . 231 10.4.4 Operation instruction . 232 10.4.5 Accumulator manipulation instruction . 239 10.4.6 Increment/decrement instruction . 240 10.4.7 Compare instruction . 241 10.4.8 Carry flag manipulation instruction . 242 10.4.9 Memory bit manipulation instruction . 243 10.4.10 Branch instruction . 246 10.4.11 Subroutine/stack control instruction . 250 10.4.12 Interrupt control instruction . 255 10.4.13 Input/output instruction . 256 10.4.14 CPU control instruction . 257 10.4.15 Special instruction . 258 APPENDIX A FUNCTIONS OF µPD754202 PD754202 AND 75F4264 75F4264 . 261 APPENDIX B DEVELOPMENT TOOLS . 263 APPENDIX C ORDERING MASK ROM . 267 APPENDIX D INSTRUCTION INDEX . D.1 Instruction Index (by function) . D.2 Instruction Index (alphabetical order) . 269 269 272 APPENDIX E HARDWARE INDEX . 275 APPENDIX F REVISION HISTORY . 277 ­ iii ­ LIST OF FIGURES (1/3) Fig. No. Title Page 3-1 Selecting MBE = 0 Mode and MBE = 1 Mode . 14 3-2 Data Memory Configuration and Addressing Range for Each Addressing Mode . 16 3-3 Updating Address of Static RAM . 20 3-4 Example of Using Register Banks . 27 3-5 Configuration of General-Purpose Registers (in 4-bit processing) . 29 3-6 Configuration of General-Purpose Registers (in 8-bit processing) . 30 3-7 I/O Map . 33 4-1 Format of Stack Bank Select Register . 42 4-2 Configuration of Program Counter . 43 4-3 Program Memory Map . 45 4-4 Data Memory Map . 48 4-5 Configuration of General-Purpose Register . 4-6 Configuration of Register Pair . 50 4-7 Accumulator . 51 4-8 Stack Pointer and Stack Bank Selection Register Configuration . 52 4-9 Data Saved to Stack Memory (MkI Mode) . 53 4-10 Data Restored from Stack Memory (MkI Mode) . 53 4-11 Data Saved to Stack Memory (MkII Mode) . 54 4-12 Data Restored from Stack Memory (MkII Mode) . 54 4-13 Configuration of Program Status Word . 55 4-14 Configuration of Bank Select Registe . 59 5-1 Data Memory Address of Digital Port . 61 5-2 P3n Configuration (n = 0 to 2) . 63 5-3 P33 Configuration . 63 5-4 P6n Configuration (n = 0, 2, 3) . 64 5-5 P61 Configuration . 64 5-6 P7n Configuration (n = 0-3) . 65 5-7 P80 Configuration . 65 5-8 Format of Each Port Mode Register . 67 5-9 Format of Pull-up Resistor Specification Register . 72 5-10 I/O Timing of Digital I/O Port . 73 5-11 ON Timing of Internal Pull-up Resistor Connected via Software . 74 5-12 Clock Generator Block Diagram . 75 5-13 Processor Clock Control Register Format . 78 5-14 Crystal/Ceramic Oscillation External Circuit . 79 5-15 Incorrect Example of Connecting Resonator . 80 5-16 CPU Clock Switching Example . 83 5-17 Block Diagram of Basic Interval Timer/Watchdog Timer . 84 5-18 Format of Basic Interval Timer Mode Register . 86 5-19 Format of Watchdog Timer Enable Flag (WDTM) . 87 5-20 Block Diagram of Timer Counter (Channel 0) . 93 5-21 Block Diagram of Timer Counter (Channel 1) . 94 ­ iv ­ LIST OF FIGURES (2/3) Fig. No. Title Page 5-22 Block Diagram of Timer Counter (Channel 2) . 95 5-23 Format of Timer Counter Mode Register (Channel 0) . 97 5-24 Format of Timer Counter Mode Register (Channel 1) . 98 5-25 Format of Timer Counter Mode Register (Channel 2) . 100 5-26 Format of Timer Counter Output Enable Flag . 102 5-27 Format of Timer Counter Control Register . 103 5-28 Setting of Timer Counter Mode Register . 105 5-29 Setting of Timer Counter Control Register . 108 5-30 Setting of Timer Counter Output Enable Flag . 108 5-31 Configuration When Timer Counter Operates . 111 5-32 Count Operation Timing . 111 5-33 Setting of Timer Counter Mode Register . 114 5-34 Setting of Timer Counter Control Register . 115 5-35 PWM Pulse Generator Operating Configuration . 117 5-36 PWM Pulse Generator Operating Timing . 117 5-37 Setting of Timer Counter Mode Registers . 120 5-38 Setting of Timer Counter Control Register . 121 5-39 Configuration When Timer Counter Operates . 124 5-40 Timing of Count Operation . 125 5-41 Setting of Timer Counter Mode Register . 128 5-42 Setting of Timer Counter Output Enable Flag . 129 5-43 Setting of Timer Counter Control Register . 129 5-44 Configuration in Carrier Generator Mode . 132 5-45 Carrier Generator Operation Timing . 133 5-46 Format of Bit Sequential Buffer . 147 6-1 Block Diagram of Interrupt Control Circuit . 150 6-2 Interrupt Vector Table . 152 6-3 Interrupt Priority Select Register . 155 6-4 Configuration of INT0 . 157 6-5 I/O Timing of Noise Rejection Circuit . 157 6-6 Format of INT0 Edge Detection Mode Register (IM0) . 158 6-7 Interrupt Service Sequence . 160 6-8 Nesting of Interrupt with High Priority . 161 6-9 Interrupt Nesting by Changing Interrupt Status Flag . 162 6-10 KR4-KR7 Block Diagram . 176 6-11 Format of INT2 Edge Detection Mode Register (IM2) . 177 7-1 Releasing Standby Mode . 182 7-2 Wait Time after Releasing STOP Mode . 184 7-3 STOP Mode Release by Key Return Reset or RESET Input . 185 ­v­ LIST OF FIGURES (3/3) Fig. No. Title Page 8-1 Configuration of Reset Circuit . 8-2 Reset Operation by RESET Signal . 192 8-3 WDF Operation in Generating Each Signal . 195 8-4 KRF Operation in Generating Each Signal . 196 ­ vi ­ 191 LIST OF TABLES Table. No. Title Page 2-1 Pin Functions of Digital I/O Ports . 2-2 Function List of Non-port Pins . 6 2-3 List of Recommended Connection of Unused Pins . 11 3-1 Addressing Modes . 17 3-2 Register Bank Selected by RBE and RBS . 26 3-3 Example of Using Different Register Banks for Normal Routine and Interrupt Routine . 26 3-4 Addressing Modes Applicable to Peripheral Hardware Unit Manipulation . 31 4-1 Differences between MkI and MkII Modes . 41 4-2 Stack Area Selected by SBS . 51 4-3 PSW Flags Saved/Restored to/from Stack . 55 4-4 Carry Flag Manipulation Instruction . 56 4-5 Contents of Interrupt Status Flags . 57 4-6 MBE, MBS, and Memory Bank Selected . 59 4-7 RBE, RBS, and Register Bank Selected . 60 5-1 Types and Features of Digital Ports . 62 5-2 I/O Pin Manipulation Instructions . 69 5-3 Operation When I/O Port Is Manipulated . 71 5-4 Specifying Connection of Pull-up Resistor . 72 5-5 Maximum Time Required for CPU Clock Switching . 82 5-6 Mode List . 92 5-7 Resolution and Longest Set Time (In 8-bit Timer Counter Mode) . 109 5-8 Resolution and Longest Set Time (16-bit timer counter mode) . 122 6-1 Types of Interrupt Sources . 151 6-2 Signals Setting Interrupt Request Flags . 154 6-3 IST1 and IST0 and Interrupt Servicing Status . 159 6-4 Identifying Interrupt Sharing Vector Address . 163 6-5 Types of Test Sources . 175 6-6 Test Request Flag Setting Signals . 175 6-7 KR4-KR7 Pins, KRREN Pin and Test Function . 177 7-1 Operation States in Standby Mode . 180 7-2 Selecting Wait Time by BTM . 184 8-1 Status of Each Hardware Unit after Reset . 193 8-2 Reset Operation by RESET Signal . 195 9-1 Selection of Mask Options . 197 10-1 Types of Bit Manipulation Addressing Modes and Specification Range . 200 ­ vii ­ 5 [MEMO] ­ viii ­ CHAPTER 1 GENERAL The µPD754202 PD754202 is a 4-bit single-chip microcontroller in the NEC 75XL series, the successor to the 75X series that boasts a wealth of variations. The µPD754202 PD754202 has extended CPU functions compared to the 75X series, enabling high-speed and low voltage (1.8 V) operation. This model is available in a small plastic shrink SOP (300 mil, 0.65-mm pitch). The features of the µPD754202 PD754202 are as follows: · Low-voltage operation: VDD = 1.8 to 6.0 V · Variable instruction execution time useful for high-speed operation and power saving 0.95 µs, 1.91 µs, 3.81 µs, 15.3 µs (at 4.19 MHz) 0.67 µs, 1.33 µs, 2.67 µs, 10.7 µs (at 6.0 MHz) · Four timer channels · Key return reset function for key-less entry · Small package (20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Application Fields · Automotive appliance such as key-less entry 1 CHAPTER 1 GENERAL 1.1 Functional Outline Item Functions Instruction execution time · 0.95, 1.91, 3.81, 15.3 µs (at 4.19 MHz) · 0.67, 1.33, 2.67, 10.7 µs (at 6.0 MHz) On-chip Mask ROM 2048 × 8 bits (0000H-0FFFH 0000H-0FFFH) memory RAM 128 × 4 bits (000H-07FH 000H-07FH) System clock oscillator Crystal/ceramic oscillator General-purpose register · 4-bit operation: 8 × 4 banks · 8-bit operation: 4 × 4 banks Input/output CMOS input 4 Pull-up resistor can be incorporated by mask option port CMOS input/output 9 On-chip pull-up resistor can be specified by software Total 13 Timer 4 channels · 8-bit timer counter (can be used as 16-bit timer counter) : 3 channels · Basic interval/watchdog timer : 1 channel Bit sequential buffer 16 bits Vectored interrupt External: 1, Internal: 4 Test input External: 1 (Key return reset function provided) Standby function STOP/HALT mode Operating ambient temperature TA = ­40 to +85 °C Operating supply voltage VDD = 1.8 to 6.0 V Package · 20-pin plastic SOP (300 mil, 1.27-mm pitch) · 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) 1.2 Ordering Information Part Number Package µPD754202GS- PD754202GS-×××-BA5 20-pin plastic SOP (300 mil, 1.27-mm pitch) µPD754202GS- PD754202GS-×××-GJG 20-pin plastic shrink SOP (300 mil, 0.65-mm pitch) Remark 2 ××× indicates a ROM code number. CHAPTER 1 GENERAL 1.3 Block Diagram BASIC INTERVAL TIMER/WATCHDOG TIMER PORT3 4 P30-P33 P30-P33 PORT6 4 P60-P63 P60-P63 PORT7 4 P70-P73 P70-P73 PORT8 P80 SP (8) INTBT RESET CY ALU 8-BIT TIMER COUNTER #0 PTO0/P30 PTO0/P30 INTT0 TOUT SBS PROGRAM COUNTER INTT1 8-BIT TIMER COUNTER #1 CASCADED 16-BIT 16-BIT TIMER 8-BIT COUNTER TIMER COUNTER #2 PTO1/P31 PTO1/P31 PTO2/P32 PTO2/P32 BANK GENERAL REG. PROGRAM MEMORY (ROM) 2048 × 8 BITS DATA MEMORY (RAM) 128 × 4 BITS INTT2 INT0/P61 INT0/P61 INTERRUPT CONTROL KRREN KR4/P70KR7/P73 KR4/P70KR7/P73 BIT SEQ. BUFFER (16) DECODE AND CONTROL 4 CPU CLOCK fX/2N CLOCK SYSTEM CLOCK STANDBY CONTROL DIVIDER GENERATOR X1 X2 IC VDD VSS RESET 3 CHAPTER 1 GENERAL 1.4 Pin Configuration (Top View) · 20-pin Plastic SOP (300 mil, 1.27 mm-pitch) µPD754202GS- PD754202GS-×××-BA5 · 20-pin Plastic Shrink SOP (300 mil, 0.65 mm-pitch) µPD754202GS- PD754202GS-×××-GJG RESET 1 20 KRREN X1 2 19 P80 X2 3 18 P30/PTO0 P30/PTO0 VSS 4 17 P31/PTO1 P31/PTO1 IC 5 16 P32/PTO2 P32/PTO2 VDD 6 15 P33 P60 7 14 P70/KR4 P70/KR4 P61/INT0 P61/INT0 8 13 P71/KR5 P71/KR5 P62 9 12 P72/KR6 P72/KR6 P63 10 11 P73/KR7 P73/KR7 IC: Internally Connected (Directly connect to VDD) Pin Name P30-P33 P30-P33 : Port 3 P60-P63 P60-P63 : Port 6 P70-P73 P70-P73 : Port 7 P80 : Port 8 KR4-KR7 : Key Return 4-7 INT0 : External Vectored Interrupt 0 PTO0-PTO2 : Programmable Timer Ouput 0-2 KRREN : Key Return Reset Enable X1, X2 : System Clock (Crystal/Ceramic) IC : Internally Connected. RESET : Ground VDD 4 : Reset VSS : Positive Power Supply CHAPTER 2 PIN FUNCTIONS 2.1 Pin Functions Table 2-1 Pin Functions of Digital I/O Ports Pin Name P30 I/O Shared with I/O PTO0 P31 PTO1 P32 PTO2 P33 ­ P60 I/O ­ P61 INT0 P62 ­ P63 ­ P70 Input KR4 P71 KR5 P72 After Reset I/O Circuit TYPE Note Programmable 4-bit input/output port (PORT3). This port can be specified input/output bitwise. On-chip pull-up resistor can be specified by software in 4-bit units. × Input E-B Programmable 4-bit input/output port (PORT6). This port can be specified input/output bitwise. On-chip pull-up resistor can be specified by software in 4-bit units. P61/INT0 P61/INT0 can select noise rejection circuit. × Input F -A 4-bit input port (PORT7). Pull-up resistor can be incorporated (mask option). × Input B -A 1-bit input/output port (PORT8). On-chip pull-up resistor can be specified by software. × Input F -A KR6 P73 8-bit I/O Function KR7 P80 I/O ­ Note Circled characters indicate the Schmitt-trigger input. 5 CHAPTER 2 PIN FUNCTIONS Table 2-2 Function List of Non-port Pins PTO0 I/O Shared with Output Pin Name P30 PTO1 I/O Circuit TYPENote Timer counter output pins Input E-B Edge-detected vectored interNoise rejection rupt input (edge to be detected circuit/asynch is selectable) selectable Noise rejection circuit selectable. Input F -A Falling edge-detected testable input Input B -A Input B P31 PTO2 After Reset Function P32 INT0 Input P61 KR4-KR7 Input P70-P73 P70-P73 KRREN Input ­ Key return reset enable pin When KRREN is at a high level in the STOP mode, a reset signal is generated at the rising edge of KRn. X1 Input ­ ­ ­ X2 ­ Connect crystal/ceramic oscillator for system clock oscillation. Input external clock to X1 and its complement to X2. Input ­ System reset input pin (low-level active) ­ B -A IC ­ ­ Internally Connected. Connect directly to VDD ­ ­ V DD ­ ­ Positive supply pin ­ ­ V SS ­ ­ Ground potential ­ ­ RESET Note 6 Circled characters indicate the Schmitt trigger input. CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P30-P33 P30-P33 (PORT3) . I/Os shared with PTO0-PTO2 P60-P63 P60-P63 (PORT6) . I/Os shared with INT0 P80 (PORT8) . I/O 4-bit I/O ports with output latch (ports 3 and 6) and 1-bit I/O port with output latch (port 8). Ports 3 and 6 also have the following functions, in addition to the I/O port function. · Port 3 : Timer counter output (PTO0-PTO2) · Port 6 : Vectored interrupt input (INT0) Selection of I/O modes of ports 3 and 6 is set by the port mode register group A (PMGA), and that of port 8 is set by the port mode register group C (PMGC). Ports 3 and 6 can be set in 1-bit unit. Furthermore, connection of internal pull-up resistors is specifiable by software for ports 3, 6 and 8. This is specified by manipulation of the pull-up resistor specification registers (POGA and POGB). Ports 3 and 6 are specified in 4bit units. Port 8 is specified in 1-bit unit. I/O for ports 3 and 6 is possible in 4-bit units or in 1-bit unit. Manipulation in 8-bit units is not possible. Generation of RESET signal sets input mode. 2.2.2 P70-P73 P70-P73 (PORT7) . inputs shared with KR4 to KR7 4-bit input port. Port 7 also has a key interrupt input (KR4-KR7) function besides the input port function. Each pin is always set to input irrespective of the operation of shared pins. These pins have Schmitt-triggered input to prevent misoperation due to noise. Internal pull-up resistors can be specifiable by mask option in 1-bit unit for port 7. 2.2.3 PTO0-PTO2 . outputs shared with port 3 These are the output pins of timer counters 0 through 2, and output square wave pulses. To output the signal of a timer counter, clear the output latch of the corresponding pin of port 2 to "0". Then, set the bit corresponding to port 3 of the port mode register group A (PMGA) to "1" to set the output mode. The outputs of TOUT F/F are cleared to "0" by the timer start instruction. For details, refer to 5.4.2 (3) Timer counter operation (at 8-bit). 7 CHAPTER 2 PIN FUNCTIONS 2.2.4 INT0 . input shared with port 6 This pin inputs interrupt signal detected by the edge. INT0 can select a noise rejection circuit. The edge to be detected can be specified by using the edge detection mode register (IM0). (1) INT0 (bits 0 and 1 of IM0) (a) Active at rising edge (b) Active at falling edge (c) Active at both rising and falling edges (d) External interrupt signal input disabled INT4 is an asynchronous input pin and the interrupt is acknowledged whenever a high-level signal is input to this pin for a fixed time, regardless of the operating clock of the CPU. A noise rejection circuit can be specified by software, and the sampling clock that rejects noise can be changed in two steps. The width of the signal that is acknowledged differs depending on the CPU operating clock. When the RESET signal is asserted, IM0 is cleared to "0", and the rising edge is selected as the active edge. INT0 can be used to release the STOP and HALT modes. However, when the noise rejection circuit is selected, INT0 cannot be used to release the STOP and HALT modes. INT0 is a Schmitt trigger input pin. 2.2.5 KR4-KR7 . inputs shared with port 7 These are key interrupt input pins. KR4 through KR7 are parallel falling edge-detected interrupt input pins. The interrupt source can be specified to KR4 through KR7 by using the edge detection mode register (IM2). When the RESET signal is asserted, these pins serve as port 7 pin and set in input mode. 2.2.6 KRREN This is a key return reset function selection pin. It is always set to input. When the KRREN pin is high and it is in STOP mode, a falling input on pins KR4/P70-KR7/P73 KR4/P70-KR7/P73 generates a system reset. At this time, STOP mode is released. When the KRREN pin is low, pins KR4/P70-KR7/P73 KR4/P70-KR7/P73 function as normal input pins or release standby. 2.2.7 X1 and X2 These pins connect a crystal/ceramic oscillator for system clock oscillation. An external clock can also be input to these pins. (a) Ceramic/crystal oscillation (b) External clock µ PD754202 PD754202 X1 µ PD754202 PD754202 ExternaI clock X1 X2 VSS Crystal resonator (4.194304 MHz TYP.) or ceramic resonator 8 X2 CHAPTER 2 PIN FUNCTIONS 2.2.8 RESET This pin inputs a low-active reset signal. The RESET signal is an asynchronous input signal and is asserted when a signal with a specific low-level width is input to this pin regardless of the operating clock. The RESET signal takes precedence over all the other operations. This pin can not only be used to initialize and start the CPU, but also to release the STOP and HALT modes. The RESET pin is a Schmitt trigger input pin. Internal pull-up resistors can be specified by mask option. 2.2.9 IC The IC (Internally Connected) pin sets a test mode in which the µPD754202 PD754202 is tested before shipment. Usually, you should directly connect the IC pin to the VDD pin with as short a wiring length as possible. If a voltage difference is generated between the IC and VDD pins because the wiring length between the IC and VDD pins is too long, or because an external noise is superimposed on the IC pin, your program may not be correctly executed. · Directly connect the IC pin to the VDD pin. Keep short as much as possible. IC VDD VDD 2.2.10 VDD Positive power supply pin. 2.2.11 VSS GND. 9 CHAPTER 2 PIN FUNCTIONS 2.3 I/O Circuits of Respective Pins The following diagrams show the I/O circuits of the respective pins of the µPD754202 PD754202. Note that in these diagrams the I/O circuits have been slightly simplified. TYPE A TYPE D VDD VDD data P-ch OUT P-ch IN N-ch CMOS specification input buffer. N-ch output disable Push-pull output that can be placed in output high-impedance (both P-ch, N-ch off). TYPE E-B TYPE B VDD P.U.R. P.U.R. enable IN P-ch data Type D IN/OUT output disable Type A Schmitt trigger input having hysteresis characteristic. P.U.R. : Pull-Up Resistor TYPE F-A TYPE B-A VDD P.U.R. VDD P.U.R. enable P.U.R (Mask Option) P-ch data IN output disable P.U.R. : Pull-Up Resistor IN/OUT Type D Type B P.U.R. : Pull-Up Resistor 10 CHAPTER 2 PIN FUNCTIONS 2.4 Processing of Unused Pins Table 2-3 List of Recommended Connection of Unused Pins Pin Recommended Connecting Method P30/PTO0 P30/PTO0 Input state : Independently connect to VSS or VDD via a resistor. P31/PTO1 P31/PTO1 Output state: Leave open. P32/PTO2 P32/PTO2 P33 P60 P61/INT0 P61/INT0 P62 P63 P70/KR4 P70/KR4 Independently connect to VDD via a resistor. P71/KR5 P71/KR5 P72/KR6 P72/KR6 P73/KR7 P73/KR7 P80 Input state : Independently connect to VSS or VDD via a resistor. Output state: Leave open. KRREN When this pin is connected to VDD, internal reset signal is generated at the falling edge of the KRn pin in the STOP mode. When this pin is connected to VSS, internal reset signal is not generated even if the falling edge of KRn pin is detected in the STOP mode. IC Connect directly to VDD. 11 [MEMO] 12 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP The 75XL architecture employed for the µPD754202 PD754202 has the following features: · Internal RAM: 4K words × 4 bits MAX. (12-bit address) · Expansibility of peripheral hardware To realize these superb features, the following techniques have been employed: (1) Bank configuration of data memory (2) Bank configuration of general-purpose registers (3) Memory mapped I/O This chapter describes these features. 3.1 Bank Configuration of Data Memory and Addressing Mode 3.1.1 Bank configuration of data memory The µPD754202 PD754202 is provided with a static RAM at the addresses 000H through 07FH of memory bank 0 of the data memory space. Peripheral hardware units (such as I/O ports and timers) are allocated to addresses F80H through FFFH of memory bank 15. The µPD754202 PD754202 employs a memory bank configuration that directly or indirectly specifies the lower 8 bits of an address by an instruction and the higher 4 bits of the address by a memory bank, to address the data memory space of 12-bit address (4K words × 4 bits). To specify a memory bank (MB), the following hardware units are provided: · Memory bank enable flag (MBE) · Memory bank select register (MBS) MBS is a register that selects a memory bank. Memory banks 0 and 15 can be set. MBE is a flag that enables or disables the memory bank selected by MBS. When MBE is 0, the specified memory bank (MB) is fixed, regardless of MBS, as shown in Fig. 3-1. When MBE is 1, however, a memory bank is selected according to the setting of MBS. To address the data memory space, MBE is usually set to 1 and the data memory of the memory bank specified by MBS is manipulated. By selecting a mode of MBE = 0 or a mode of MBE = 1 for each processing of the program, programming can be efficiently carried out. Adapted Program Processing MBE = 0 mode Effect Saving/restoring MBS unnecessary · Processing repeating internal hardware manipulation and stack RAM manipulation Changing MBS unnecessary · Subroutine processing MBE = 1 mode · Interrupt service Saving/restoring MBS unnecessary · Normal program processing 13 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Fig. 3-1 Selecting MBE = 0 Mode and MBE = 1 Mode SET 1 MBE MBE =1 CLR1 MBE MBE = 0 CLR 1 MBE Internal hardware and static RAM manipulation repeated. MBE =0 SET 1 MBE RET (Interrupt service) ; MBE = 0 by vector table MBE = 0 MBE =1 RETI Remark Solid line: MBE = 1, dotted line: MBE = 0 Because MBE is automatically saved or restored during subroutine processing, it can be changed even while subroutine processing is being executed. MBE can also be saved or restored automatically during interrupt service, so that MBE during interrupt service can be specified as soon as the interrupt service is started, by setting the interrupt vector table. This feature is useful for high-speed interrupt service. To change MBS by using subroutine processing or interrupt service, save or restore it to stack by using the PUSH or POP instruction. MBE is set by using the SET1 or CLR1 instruction. Use the SEL instruction to set MBS. Examples 1. To clear MBE and fix memory bank CLR1 MBE 2. SET1 MBE SEL 14 ; MBE 0 To select the memory bank 15 ; MBE 1 MB15 ; MBS 15 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 3.1.2 Addressing mode of data memory The 75XL architecture employed for the µPD754202 PD754202 provides the seven types of addressing modes as shown in Table 3-1. This means that the data memory space can be efficiently addressed by the bit length of the data to be processed and that programming can be carried out efficiently. (1) 1-bit direct addressing (mem.bit) This mode is used to directly address each bit of the entire data memory space by using the operand of an instruction. The memory bank (MB) to be specified is fixed to 0 in the mode of MBE = 0 if the address specified by the operand ranges from 00H to 7FH, and to 15 if the address specified by the operand is 80H to FFH. In the mode of MBE = 0, therefore, both the data area of addresses 000H through 07FH and the peripheral hardware area of F80H through FFFH can be addressed. In the mode of MBE = 1, MB = MBS. This addressing mode can be used with four instructions: bit set and the two reset (SET1 and CLR1) instructions, and the two bit test instructions (SKT and SKF). Example To set FLAG1, reset FLAG2, and test whether FLAG3 is 0 FLAG1 EQU 03FH.1 ; Bit 1 of address 3FH FLAG2 EQU 057H.2 ; Bit 2 of address 57H FLAG3 EQU 077H.0 ; Bit 0 of address 77H SET1 MBE ; MBE 1 SEL ; MBS 0 MB0 SET1 FLAG1 ; FLAG1 1 CLR1 FLAG2 ; FLAG2 0 SKF ; FLAG3 = FLAG3 0? 15 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Fig. 3-2 Data Memory Configuration and Addressing Range for Each Addressing Mode Addressing mode mem mem. bit @HL @H+mem. bit Memory bank enable flag MBE = 0 MBE = 1 MBE = 0 MBE = 1 000H Generalpurpose register area 01FH 020H MBS = 0 MBS = 0 MBS = 15 MBS = 15 Data area (SRAM) 07FH Memory bank 0 0FFH Not contained F80H FB0H FBFH FC0H Peripheral hardware area (memory bank 15) FF0H FFFH Remark 16 ­ : don't care @DE @DL ­ Stack addressing fmem. bit pmem. @L ­ SBS = 0 ­ ­ CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Table 3-1 Addressing Modes Addressing Mode 1-bit direct addressing Representation mem.bit Specified Address Bit specified bit at address specified by MB and mem · When MBE = 0 When mem = 00H-7FH 00H-7FH : MB = 0 When mem = 80H-FFH 80H-FFH : MB = 15 · When MBE = 1 4-bit direct addressing mem : MB = MBS Address specified by MB and mem. · When MBE = 0 When mem = 00H-7FH 00H-7FH : MB = 0 When mem = 80H-FFH 80H-FFH : MB = 15 · When MBE = 1 8-bit direct addressing : MB = MBS Address specified by MB and mem (mem is even address) · When MBE = 0 When mem = 00H-7FH 00H-7FH : MB = 0 When mem = 80H-FFH 80H-FFH : MB = 15 · When MBE = 1 4-bit register indirect : MB = MBS @HL Address specified by MB and HL. Where, MB = MBE . MBS @HL+ Address specified by MB and HL. However, MB = MBE . MBS. @HL­ HL+ automatically increments L register after addressing. addressing HL­ automatically decrements L register after addressing. @DE @DL 8-bit register indirect Address specified by DE in memory bank 0 Address specified by DL in memory bank 0 @HL Address specified by MB and HL (contents of L register are even addressing number) Where, MB = MBE . MBS Bit manipulation fmem.bit addressing Bit specified by bit at address specified by fmem fmem = FB0H-FBFH (interrupt-related hardware) FF0H-FFFH (I/O port) pmem.@L Bit specified by lower 2 bits of L register at address specified by higher 10 bits of pmem and lower 2 bits of L register. Where, pmem = FC0H-FFFH @H+mem.bit Bit specified by bit at address specified by MB, H, and lower 4 bits of mem. Where, MB = MBE . MBS Stack addressing - Address specified by SP in memory bank 0 17 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (2) 4-bit direct addressing (mem) This addressing mode is used to directly address the entire memory space in 4-bit units by using the operand of an instruction. Like the 1-bit direct addressing mode, the area that can be addressed is fixed to the data area of addresses 000H through 07FH and the peripheral hardware area of F80H through FFFH in the mode of MBE = 0. In the mode of MBE = 1, MB = MBS. This addressing mode is applicable to the MOV, XCH, INCS, IN, and OUT instructions. (3) 8-bit direct addressing (mem) This addressing mode is used to directly address the entire data memory space in 8-bit units by using the operand of an instruction. The address that can be specified by the operand is an even address. The 4-bit data of the address specified by the operand and the 4-bit data of the the address higher than the specified address are used in pairs and processed in 8-bit units by the 8-bit accumulator (XA register pair). The memory bank that is addressed is the same as that addressed in the 4-bit direct addressing mode. This addressing mode is applicable to the MOV, XCH, IN, and OUT instructions. (4) 4-bit register indirect addressing (@rpa) This addressing mode is used to indirectly address the data memory space in 4-bit units by using a data pointer (a pair of general-purpose registers) specified by the operand of an instruction. As the data pointer, three register pairs can be specified: HL that can address the entire data memory space by using MBE and MBS, and DE and DL that always address memory bank 0, regardless of the specification by MBE and MBS. The user selects a register pair depending on the data memory bank to be used in order to carry out programming efficiently. When the HL register pair is specified, auto-increment/auto-decrement mode is used, which increments or decrements the L register by one at the same time the instruction is executed, resulting in reducing the number of program steps. Example To transfer data 50H through 57H to addresses 60H through 67H DATA1 EQU 57H DATA2 EQU 67H SET1 MBE SEL MB0 MOV D, #DATA1 SHR4 MOV HL, #DATA2 AND 0FFH ; HL 17H MOV A, @DL ; A (DL) XCH A, @HL ; A (HL) DECS L ; LL­1 BR LOOP : LOOP The addressing mode that uses register pair HL as the data pointer is widely used to transfer, operate, compare, and input/output data. The addressing mode using register pair DE or DL is used with the MOV and XCH instructions. By using this addressing mode in combination with the increment/decrement instruction of a general-purpose register or a register pair, the addresses of the data memory can be updated as shown in Fig. 3-3. 18 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Examples 1. To compare data 50H through 57H with data 60H through 67H DATA1 EQU 57H DATA2 EQU 67H SET1 MBE SEL MB0 MOV D, #DATA1 SHR 4 MOV HL, #DATA2 AND 0FFH LOOP : MOV A, @DL SKE A, @HL BR NO DECS L BR ; A = (HL)? ; NO ; YES, L L ­ 1 LOOP 2. To clear data memory of 004H through 07FH CLR1 RBE CLR1 MBE MOV XA, #00H MOV HL, #04H @HL, A ; (HL) A INCS L ; L L+1 BR LOOP INCS H LOOP : MOV ; H H+1 NOP SKE H, #08H BR LOOP 19 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Fig. 3-3 Updating Address of Static RAM XFH X0H 0XH DECS D DECS L @DL 4-bit transfer DECS D DECS E INCS L DECS DE INCS D @DE 4-bit transfer INCS D Direct addressing bit manipulation 4-bit transfer 8-bit transfer DECS H Auto decrement DECS L DECS HL @HL 4-bit manipulation 8-bit manipuIation INCS H FXH 20 DECS H Auto increment INCS L INCS HL @H+mem. bit manipulation INCS H INCS E INCS DE CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (5) 8-bit register indirect addressing (@HL) This addressing mode is used to indirectly address the entire data memory space in 8-bit units by using a data pointer (HL register pair). In this addressing mode, data is processed in 8-bit units, that is, the 4-bit data at an address specified by the data pointer with bit 0 (bit 0 of the L register) cleared to 0 and the 4-bit data at the address higher are used in pairs and processed with the data of the 8-bit accumulator (XA register). The memory bank is specified in the same manner as when the HL register is specified in the 4-bit register indirect addressing mode, by using MBE and MBS. This addressing mode is applicable to the MOV, XCH, and SKE instructions. Examples 1. To compare whether the count register (T0) value of timer counter 0 is equal to the data at addresses 30H and 31H DATA EQU 30H CLR1 MBE MOV HL, #DATA MOV XA, T0 SKE XA, @HL ; XA = (HL)? ; XA count register 0 2. To clear data memory at 004H through 07FH CLR1 RBE CLR1 MBE MOV XA, #00H MOV HL, #04H LOOP : MOV INCS @HL, XA ; (HL) XA L INCS L BR LOOP INCS H NOP SKE H, #08H BR LOOP 21 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (6) Bit manipulation addressing This addressing mode is used to manipulate the entire memory space in bit units (such as Boolean processing and bit transfer). While the 1-bit direct addressing mode can be only used with the instructions that set, reset, or test a bit, this addressing mode can be used in various ways such as Boolean processing by the AND1, OR1, and XOR1 instructions, and test and reset by the SKTCLR instruction. Bit manipulation addressing can be implemented in the following three ways, which can be selected depending on the data memory address to be used. (a) Specific address bit direct addressing (fmem.bit) This addressing mode is to manipulate the hardware units that use bit manipulation especially often, such as I/O ports and interrupt-related flags, regardless of the setting of the memory bank. Therefore, the data memory addresses to which this addressing mode is applicable are FF0H through FFFH, to which the I/O ports are mapped, and FB0H through FBFH, to which the interrupt-related hardware units are mapped. The hardware units in these two data memory areas can be manipulated in bit units at any time in the direct addressing mode, regardless of the setting of MBS and MBE. Examples 1. To test timer 0 interrupt request flag (IRQT0) and, if it is set, clear the flag and reset P63 SKTCLR IRQT0 ; IRQT0 = 1? BR NO ; NO CLR1 PORT6.3 ; YES 2. To reset P63 if both P30 and P71 pins are 1 P30 P63 P71 (i) SET1 CY ; CY 1 AND1 CY, PORT3.0 ; CY P30 AND1 CY, PORT7.1 ; CY P71 SKT CY ; CY = 1? BR SETP CLR1 PORT6.3 ; P63 0 PORT6.3 ; P63 1 · · · SETP : SET1 · · · (ii) SKT PORT3.0 BR SETP SKT PORT7.1 ; P30 = 1? ; P71 = 1? BR SETP CLR1 PORT6.3 ; P63 0 PORT6.3 ; P63 1 · · · SETP: 22 SET1 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (b) Specific address bit register indirect addressing (pmem, @L) This addressing mode is to indirectly specify and successively manipulate the bits of the peripheral hardware units such as I/O ports. The data memory addresses to which this addressing mode can be applied are FC0H through FFFH. This addressing mode specifies the higher 10 bits of a 12-bit data memory address directly by using an operand, and the lower 2 bits by using the L register. This addressing mode can also be used independently of the setting of MBE and MBS. Example To output pulses to the respective bits of port 6 P60 P61 P62 P63 LOOP2 : MOV L, #0 LOOP1 : SET1 PORT6.@L; Bits of port 6 (L1-0) 1 CLR1 PORT6.@L; Bits of port 6 (L1-0) 0 INCS L SKE L, #4H BR LOOP1 BR LOOP2 23 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (c) Special 1-bit direct addressing (@H+mem.bit) This addressing mode enables bit manipulation in the entire memory space. The higher 4 bits of the data memory address of the memory bank specified by MBE and MBS are indirectly specified by the H register, and the lower 4 bits and the bit address are directly specified by the operand. This addressing mode can be used to manipulate the respective bits of the entire data memory area in various ways. Example To reset bit 2 (FLAG3) at address 32H if both bits 3 (FLAG1) at address 30H and bit 0 (FLAG2) at address 31H are 0 or 1 FLAG1 FLAG2 FLAG1 EQU 30H.3 FLAG2 EQU 31H.0 FLAG3 EQU FLAG3 32H.2 SEL MB0 MOV H, #FLAG1 SHR 6 CLR1 CY ; CY 0 OR1 CY, @H+FLAG1 ; CY CY FLAG1 XOR1 CY, @H+FLAG2 ; CY CY FLAG2 SET1 @H+FLAG3 ; FLAG3 1 SKT 24 CY ; CY = 1? CLR1 @H+FLAG3 ; FLAG3 0 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (7) Stack addressing This addressing mode is used to save or restore data when interrupt service or subroutine processing is executed. The address of data memory bank 0 pointed to by the stack pointer (8 bits) is specified in this addressing mode. In addition to being used during interrupt service or subroutine processing, this addressing is also used to save or restore register contents by using the PUSH or POP instruction. Examples 1. To save or restore register contents during subroutine processing SUB : PUSH XA PUSH HL PUSH BS ; Saves MBS and RBE · · · POP BS POP HL POP XA RET 2. To transfer contents of register pair HL to register pair DE PUSH HL POP DE ; DE HL 3. To branch to address specified by registers [XABC] PUSH BC PUSH XA RET ; To branch address XABC 25 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 3.2 Bank Configuration of General-Purpose Registers The µPD754202 PD754202 is provided with four register banks with each bank consisting of eight general-purpose registers: X, A, B, C, D, E, H, and L. The general-purpose register area consisting of these registers is mapped to the addresses 00H through 1FH of memory bank 0 (refer to Fig. 3-5 Configuration of General-Purpose Registers (in 4-bit processing). To specify a general-purpose register bank, a register bank enable flag (RBE) and a register bank select register (RBS) are provided. RBS selects a register bank, and RBE determines whether the register bank selected by RBS is valid or not. The register bank (RB) that is enabled when an instruction is executed is as follows: RB = RBE · RBS Table 3-2 Register Bank Selected by RBE and RBS RBS RBE Register Bank 3 2 1 0 0 0 0 × × Fixed to bank 0 1 0 0 0 0 Bank 0 selected 0 1 Bank 1 selected 1 0 Bank 2 selected 1 1 Bank 3 selected Fixed to 0 Remark × = don't care RBE is automatically saved or restored during subroutine processing and therefore can be set while subroutine processing is under execution. When interrupt service is executed, RBE is automatically saved or restored, and RBE can be set during interrupt service depending on the setting of the interrupt vector table as soon as the interrupt service is started. Consequently, if different register banks are used for normal processing and interrupt service as shown in Table 3-3, it is not necessary to save or restore general-purpose registers when an interrupt is serviced, and only RBS needs to be saved or restored if two interrupts are nested. This means that the interrupt service speed can be increased. Table 3-3 Example of Using Different Register Banks for Normal Routine and Interrupt Routine Normal processing Single interrupt service Uses register bank 0 with RBE = 0 Nesting of two interrupts Uses register bank 1 with RBE = 1 (at this time, RBS must be saved or restored) Nesting of three or more interrupts 26 Uses register banks 2 or 3 with RBE = 1 Registers must be saved or restored by PUSH or POP instructions CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Fig. 3-4 Example of Using Register Banks SET1 RBE SEL RB2 ; RBE = 1 ; RBE = 0 in vector table in vector table PUSH BS SEL RB1 RB = 2 RB = 0 RB = 1 RETI ; RBE = 0 in vector table PUSH rp RB = 0 POP BS RETI POP rp RETI If RBS is to be changed in the course of subroutine processing or interrupt service, it must be saved or restored by using the PUSH or POP instruction. RBE is set by using the SET1 or CLR1 instruction. RBS is set by using the SEL instruction. SET1 RBE ; RBE 1 CLR1 RBE ; RBE 0 SEL RB0 ; RBS 0 SEL Example RB3 ; RBS 3 The general-purpose register area provided to the µPD754202 PD754202 can be used not only as 4-bit registers but also as 8-bit register pairs. This feature allows the µPD754202 PD754202 to provide transfer, operation, comparison, and increment/ decrement instructions comparable to those of 8-bit microcontrollers and allows you to program using mainly only general-purpose registers. 27 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP (1) To use as 4-bit registers When the general-purpose register area is used as a 4-bit register area, a total of eight general-purpose registers, X, A, B, C, D, E, H, and L, specified by RBE and RBS can be used as shown in Fig. 3-5. Of these registers, A plays a central role in transferring, operating, and comparing 4-bit data as a 4-bit accumulator. The other registers can transfer, compare, and increment or decrement data with the accumulator. (2) To use as 8-bit registers When the general-purpose register area is used as an 8-bit register area, a total of eight 8-bit register pairs can be used as shown in Fig. 3-6: register pairs XA, BC, DE, and HL of a register bank specified by RBE and RBS, and register pairs XA', BC', DE', and HL' of the register bank whose bit 0 is complemented in respect to the register bank (RB). Of these register pairs, XA serves as an 8-bit accumulator, playing the central role in transferring, operating, and comparing 8-bit data. The other register pairs can transfer, compare, and increment or decrement data with the accumulator. The HL register pair is mainly used as a data pointer. The DE and DL register pairs are also used as auxiliary data pointers. INCS HL ; Skips if HL HL + 1, HL=00H ADDS XA, BC ; Skips if XA XA + BC and carry occurs SUBC DE', XA ; DE' DE' ­ XA ­ CY MOV Examples 1. XA, XA' ; XA XA' MOVT 2. XA, @PCDE ; XA (PC10­8 + DE) SKE XA, BC ROM, table reference ; Skips if XA = BC To test whether the value of the count register (T0) of timer counter is greater than the value of register pair BC' and, if not, wait until it becomes greater CLR1 NO : MBE XA, T0 ; Reads count register XA, BC' ; XA BC'? BR YES ; YES BR 28 MOV SUBS NO ; NO CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Fig. 3-5 Configuration of General-Purpose Registers (in 4-bit processing) A X 00H 01H L H 02H 03H Register bank 0 (RBE.RBS = 0) E D 04H 05H B C 07H 06H A X 08H 09H L H 0AH 0BH Register bank 1 (RBE.RBS = 1) E D 0CH 0DH C B 0EH 0FH A X 10H 11H L H 12H 13H Register bank 2 (RBE.RBS = 2) E D 14H 15H C B 16H 17H A X 18H 19H L H 1AH 1BH Register bank 3 (RBE.RBS = 3) E D 1CH 1DH B C 1FH 1EH 29 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Fig. 3-6 Configuration of General-Purpose Registers (in 8-bit processing) XA XA' 00H 00H HL HL' 02H 02H DE DE' 04H 04H BC BC' 06H 06H When RBE.RBS = 0 XA' XA 08H 08H HL' HL 0AH 0AH DE' DE 0CH 0CH BC' BC 0EH 0EH XA XA' 10H 10H HL HL' 12H 12H DE DE' 14H 14H BC BC' 16H XA' 16H When RBE. RBS = 2 XA 18H HL' 18H HL 1AH DE' 1AH DE 1CH BC' 1CH BC 1EH 30 When RBE.RBS = 1 1EH When RBE. RBS = 3 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 3.3 Memory-Mapped I/O The µPD754202 PD754202 employs memory-mapped I/O that maps peripheral hardware units such as I/O ports and timers to addresses F80H through FFFH on the data memory space, as shown in Fig. 3-2. Therefore, no special instructions to control the peripheral hardware units are provided, and all the hardware units are controlled by using memory manipulation instructions. (Some mnemonics that make the program easy to read are provided for hardware control.) To manipulate peripheral hardware units, the addressing modes shown in Table 3-4 can be used. Table 3-4 Addressing Modes Applicable to Peripheral Hardware Unit Manipulation Applicable Addressing Mode Bit manipulation Hardware Units All hardware units that can be manipulated in 1-bit units Specified in direct addressing mode fmem.bit regardless IST1, IST0, MBE, RBE of setting of MBE and MBS IE×××, IRQ×××, PORTn.× Specified in indirect addressing mode pmem.@L regardless of setting of MBE and MBS 4-bit manipulation Specified in direct addressing mode mem.bit with MBE = 0 or (MBE = 1, MBS = 15) BSBn.× PORTn.× Specifies in direct addressing mode mem with MBE=0 or (MBE = 1, MBS = 15) All hardware units that can be manipulated in 4-bit units Specified in register indirect addressing @HL with (MBE = 1, MBS = 15) 8-bit manipulation Specified in direct addressing mem with MBE = 0 or (MBE = 1, MBS = 15), where mem is even number. All hardware units that can be manipulated in 8-bit units Specified in register indirect addressing @HL with MBE = 1, MBS = 15, where contents of L register are even number Example CLR1 MBE ; MBE = 0 SET1 TM0. 3 ; Starts timer 0 EI IE0 ; Enables INT0 DI IET1 ; Disables INTT1 SKTCLR IRQ2 ; Tests and clears INT2 request flag SET1 PORT3, @L ; Sets port 3 IN A, PORT6 ; A port 6 31 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Fig. 3-7 shows the I/O map of the µPD754202 PD754202. The meanings of the symbols shown in this figure are as follows: · Symbol . Name indicating the address of an internal hardware unit It can be written in operands of instructions · R/W . Indicates whether a hardware unit in question can be read or written R/W : Read/write R : Read only W : Write only · Number of bits that can be manipulated . Indicates the bit units in which a hardware unit in question can be manipulated : Can be manipulated in specified units (1, 4, or 8 bits) : Only some bits can be manipulated. For the bits that can be manipulated, refer to Remark. ­ : Cannot be manipulated in specified units (1, 4, or 8 bits). · Bit manipulation addressing . Indicates a bit manipulation addressing mode that can be used to manipulate a hardware unit in question in 1-bit units 32 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Fig. 3-7 I/O Map (1/8) Hardware name (symbol) Address R/W b3 F80H F82H b2 b1 b0 Stack pointer (SP) F83H 1-bit R/W Register bank selection register (RBS) . 4-bit ­ 8-bit ­ Bit manipulation addressing ­ ­ ­ . Bank selection register (BS) Number of bits that can be manipulated Remarks Bit 0 is fixed to 0. Note 1 R ­ Memory bank selection register (MBS) F84H Stack bank selection register (SBS) F85H Basic interval timer mode register (BTM) W F86H Basic interval timer (BT) R ­ ­ ­ F88H Modulo register for setting timer counter 2 high-level period (TMOD2H) R/W ­ ­ ­ F8AH Unmounted F8BH WDTMNote 2 F8CH to F8FH Unmounted Notes 1. ­ ­ R/W ­ ­ ­ ­ ­ W ­ mem.bit ­ Bit manipulation can be performed only on bit 3. mem.bit The manipulation is possible separately with RBS and MBS in the 4-bit manipulation. The manipulation is possible with BS in the 8-bit manipulation. Write data into MBS and RBS with the SEL MBn (n = 0 or 15) and SEL RBn (n = 0-3) instructions. 2. WDTM: Watchdog Timer Enable flag (W); Cannot be cleared, once set, by an instruction. 33 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Fig. 3-7 I/O Map (2/8) Hardware name (symbol) Address R/W b3 F90H b2 b1 b0 Timer counter 2 mode register (TM2) Number of bits that can be manipulated 1-bit R/W 4-bit 8-bit Bit manipulation addressing ­ ­ ­ F92H (W) ­ Remarks ­ TOE2 REMC NRZB NRZ . R/W ­ Bit manipulation can be performed only on bit 3 Bit 3 can be written only Timer counter 2 control register (TC2) . 0 ­ ­ F94H Timer counter 2 count register (T2) F96H Timer counter 2 modulo register (TMOD2) F98H to F9FH Unmounted 34 ­ ­ R ­ ­ ­ R/W ­ ­ ­ ­ Only 0 can be written on bit 3 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Fig. 3-7 I/O Map (3/8) Hardware name (symbol) Address R/W b3 FA0H b2 b1 b0 Timer counter 0 mode register (TM0) Number of bits that can be manipulated 1-bit R/W 4-bit 8-bit Bit manipulation addressing TOE0Note 1 FA3H Timer counter 0 count register (T0) FA6H FA8H mem.bit ­ Bit manipulation can be performed only on bit 3 ­ Unmounted FA4H ­ ­ FA2H (W) Remarks ­ ­ ­ W ­ ­ mem.bit R ­ ­ ­ Timer counter 0 modulo register (TMOD0) R/W ­ ­ ­ Timer counter 1 mode register (TM1) R/W (W) ­ mem.bit ­ ­ ­ FAAH TOE1Note 2 FABH Unmounted FACH Timer counter 1 count register (T1) FAEH Timer counter 1 modulo register (TMOD1) Bit manipulation can be performed only on bit 3 ­ ­ ­ W ­ ­ mem.bit R ­ ­ ­ R/W ­ ­ ­ Notes 1. TOE0: Timer counter output enable flag (channel 0) (W) 2. TOE1: Timer counter output enable flag (channel 1) (W) 35 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Fig. 3-7 I/O Map (4/8) Hardware name (symbol) Address R/W b3 FB0H b2 b1 b0 Number of bits that can be manipulated 1-bit IST1 IST0 MBE RBE . R/W (R/W) 4-bit (R/W) 8-bit (R) Bit manipulation addressing fmem.bit Remarks R only possible as 8-bit manipulation. Program status word (PSW) . CYNote 1 SK2Note 1 SK1Note 1 Note 2 SK0Note 1 ­ FB2H Interrupt priority selection register (IPS) R/W ­ ­ Note 3 FB3H Processor clock control register (PCC) R/W ­ ­ Note 4 FB4H INT0 edge detection mode register (IM0) R/W ­ ­ ­ FB5H Unmounted FB6H INT2 edge detection mode register (IM2)Note 5 R/W ­ ­ ­ FB7H Unmounted ­ fmem.bit ­ fmem.bit FB8H INTA register (INTA) . R/W ­ FB9H to FBBH FBCH FBDH FBEH FBFH ­ IEBT IRQBT Bit manipulation can be performed by reserved word only. Unmounted INTE register (INTE) . R/W IET1 IRQT1 IET0 IRQT0 INTF register (INTF) . R/W IET2 IRQT2 ­ ­ INTG register (INTG) . R/W ­ ­ IE0 IRQ0 INTH register (INTH) . R/W ­ ­ IE2 IRQ2 Remarks 1. 2. Notes 1. Bit manipulation can be performed by reserved word only. ­ ­ ­ IE××× is an interrupt enable flag. IRQ××× is an interrupt request flag. These are not registered as reserved words. 2. Use CY manipulation instruction to write to CY. 3. IME (bit 3) can only be manipulated by an EI/DI instruction. 4. PCC3 (bit 3) and PCC2 (bit 2) can be manipulated by a STOP/HALT instruction. 5. This register specifies the falling edge of KRn pin as the set signal of interrupt request flag (IRQ2). This register is initialized to 00H after reset. Therefore, write 01H to set the falling edge of KRn pin to IRQ2. 36 CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP Fig. 3-7 I/O Map (5/8) Hardware name (symbol) Address R/W b3 b2 b1 b0 Number of bits that can be manipulated 1-bit 4-bit 8-bit Bit manipulation addressing FC0H Bit sequential buffer 0 (BSB0) R/W mem.bit FC1H Bit sequential