PD753104 PD753108 PD75308B U10890E PD753106 PD75P3116 U10086EJ5V1DS00 - Datasheet Archive

 

Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology

 

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry. Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office. 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Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of Renesas Electronics. Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. DATA SHEET MOS INTEGRATED CIRCUIT µPD753104 PD753104, 753106, 753108 4-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD753108 PD753108 is one of the 75XL Series 4-bit single-chip microcontroller chips and has a data processing capability comparable to that of an 8-bit microcontroller. The existing 75X Series containing an LCD controller/driver supplies an 80-pin package. The µPD753108 PD753108 supplies a 64-pin package, which is suitable for small-scale systems. It features expanded CPU functions and can provide high-speed operation at a low supply voltage of 1.8 V compared with the existing µPD75308B PD75308B. Detailed function descriptions are provided in the following user's manual. Be sure to read it before designing. µPD753108 PD753108 User's Manual: U10890E U10890E FEATURES · Low voltage operation: VDD = 1.8 to 5.5 V · Can be driven by two 1.5 V batteries · Internal memory · Program memory (ROM): 4096 × 8 bits (µPD753104 PD753104) 6144 × 8 bits (µPD753106 PD753106) 8192 × 8 bits (µPD753108 PD753108) · Data memory (RAM): 512 × 4 bits · Capable of high-speed operation and variable instruction execution time for power saving · 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz with main system clock) · 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz with main system clock) · 122 µs (@ 32.768 kHz with subsystem clock) · Internal programmable LCD controller/driver · Small package: 64-pin plastic QFP (14 × 14), 64-pin plastic LQFP (14 × 14), 64-pin plastic LQFP (12 × 12), 64-pin plastic TQFP (12 × 12) · One-time PROM version: µPD75P3116 PD75P3116 APPLICATIONS Remote controllers, cameras, hemadynamometers, electronic scale, gas meters, etc. Unless otherwise indicated, references in this data sheet to the µPD753108 PD753108 mean the µPD753104 PD753104 and µPD753106 PD753106. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. U10086EJ5V1DS00 U10086EJ5V1DS00 (5th edition) Date Published August 2005 N CP(K) Printed in Japan The mark shows major revised points. 1995, 2000 µPD753104 PD753104, 753106, 753108 ORDERING INFORMATION Part Number Package µ PD753104GC- PD753104GC-×××-AB8 64-pin plastic QFP (14 × 14) µ PD753104GC- PD753104GC-×××-8BS 64-pin plastic LQFP (14 × 14) µ PD753104GC- PD753104GC-×××-8BS-A 64-pin plastic LQFP (14 × 14) µ PD753104GK- PD753104GK-×××-8A8 64-pin plastic LQFP (12 × 12) µ PD753104GK- PD753104GK-×××-9ET 64-pin plastic TQFP (12 × 12) µ PD753104GK- PD753104GK-×××-9ET-A 64-pin plastic TQFP (12 × 12) µ PD753106GC- PD753106GC-×××-AB8 64-pin plastic QFP (14 × 14) µ PD753106GC- PD753106GC-×××-8BS 64-pin plastic LQFP (14 × 14) µ PD753106GC- PD753106GC-×××-8BS-A 64-pin plastic LQFP (14 × 14) µ PD753106GK- PD753106GK-×××-8A8 64-pin plastic LQFP (12 × 12) µ PD753106GK- PD753106GK-×××-9ET 64-pin plastic TQFP (12 × 12) µ PD753106GK- PD753106GK-×××-9ET-A 64-pin plastic TQFP (12 × 12) µ PD753108GC- PD753108GC-×××-AB8 64-pin plastic QFP (14 × 14) µ PD753108GC- PD753108GC-×××-8BS 64-pin plastic LQFP (14 × 14) µ PD753108GC- PD753108GC-×××-8BS-A 64-pin plastic LQFP (14 × 14) µ PD753108GK- PD753108GK-×××-8A8 64-pin plastic LQFP (12 × 12) µ PD753108GK- PD753108GK-×××-9ET 64-pin plastic TQFP (12 × 12) µ PD753108GK- PD753108GK-×××-9ET-A 64-pin plastic TQFP (12 × 12) Remarks 1. Products with "-A" at the end of the part number are lead-free products. 2. ××× indicates ROM code suffix. 2 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 OVERVIEW OF FUNCTIONS Parameter Function · 0.95, 1.91, 3.81, 15.3 µs (@ 4.19 MHz with main system clock) · 0.67, 1.33, 2.67, 10.7 µs (@ 6.0 MHz with main system clock) · 122 µs (@ 32.768 kHz with subsystem clock) Instruction execution time ROM 4096 × 8 bits ( µPD753104 PD753104), 6144 × 8 bits (µPD753106 PD753106), 8192 × 8 bits (µPD753108 PD753108) RAM Internal memory 512 × 4 bits General-purpose register · 4-bit operation: 8 × 4 banks · 8-bit operation: 4 × 4 banks I/O port CMOS input 8 On-chip pull-up resistors which can be specified by means of software setting: 7 CMOS I/O 20 On-chip pull-up resistors which can be specified by means of software setting: 12 Also used for segment pins: 8 N-ch open-drain I/O pins 4 On-chip pull-up resistors which can be specified by mask option, 13 V withstand voltage Total 32 LCD controller/driver · Segment selection: 16/20/24 segments (can be changed to CMOS I/O port in 4 time-unit; max. 8) · Display mode selection: Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) · On-chip split resistor for LCD drive can be specified by mask option Timer 5 channels · 8-bit timer/event counter: 3 channels (16-bit timer/event counter, carrier generator, timer with gate) · Basic interval timer/watchdog timer: 1 channel · Watch timer: 1 channel Serial interface · 3-wire serial I/O mode . MSB or LSB can be selected for transferring first bit · 2-wire serial I/O mode · SBI mode Bit sequential buffer (BSB) 16 bits Clock output (PCL) · , 524, 262, 65.5 kHz (@ 4.19 MHz with main system clock) · , 750, 375, 93.8 kHz (@ 6.0 MHz with main system clock) Buzzer output (BUZ) · 2, 4, 32 kHz Vectored interrupt External: 3, Internal: 5 Test input External: 1, Internal: 1 System clock oscillator · Ceramic or crystal oscillator for main system clock oscillation · Crystal oscillator for subsystem clock oscillation Standby function STOP/HALT mode Supply voltage V DD = 1.8 to 5.5 V Package · · · · (@ 4.19 MHz with main system clock or @ 32.768 kHz with subsystem clock) · 2.93, 5.86, 46.9 kHz (@ 6.0 MHz with main system clock) 64-pin 64-pin 64-pin 64-pin plastic plastic plastic plastic QFP LQFP LQFP TQFP (14 (14 (12 (12 × × × × 14) 14) 12) 12) Data Sheet U10086EJ5V1DS U10086EJ5V1DS 3 µPD753104 PD753104, 753106, 753108 CONTENTS 1. PIN CONFIGURATION (TOP VIEW) . 6 2. BLOCK DIAGRAM .8 3. PIN FUNCTIONS .9 3.1 Port Pins . 9 3.2 Non-Port Pins . 11 3.3 Pin I/O Circuits . 13 3.4 Recommended Connections of Unused Pins . 15 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE . 16 4.1 Difference Between Mk I Mode and Mk II Mode . 16 4.2 Setting Method of Stack Bank Select Register (SBS) . 17 5. MEMORY CONFIGURATION . 18 6. PERIPHERAL HARDWARE FUNCTION . 23 6.1 Digital I/O Port . 23 6.2 Clock Generator . 23 6.3 Subsystem Clock Oscillator Control Functions . 25 6.4 Clock Output Circuit . 26 6.5 Basic Interval Timer/Watchdog Timer . 27 6.6 Watch Timer . 28 6.7 Timer/Event Counter . 29 6.8 Serial Interface . 33 6.9 LCD Controller/Driver . 35 6.10 Bit Sequential Buffer . 37 7. INTERRUPT FUNCTION AND TEST FUNCTION . 38 8. STANDBY FUNCTION . 40 9. RESET FUNCTION . 41 10. MASK OPTION . 44 11. INSTRUCTION SET . 45 12. ELECTRICAL SPECIFICATIONS . 59 13. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) . 75 14. PACKAGE DRAWINGS . 78 15. RECOMMENDED SOLDERING CONDITIONS . 82 4 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 APPENDIX A. µPD75308B PD75308B, 753108 AND 75P3116 75P3116 FUNCTIONAL LIST . 84 APPENDIX B. DEVELOPMENT TOOLS . 86 APPENDIX C. RELATED DOCUMENTS . 95 Data Sheet U10086EJ5V1DS U10086EJ5V1DS 5 µPD753104 PD753104, 753106, 753108 1. PIN CONFIGURATION (TOP VIEW) · 64-pin plastic QFP (14 × 14) µPD753104GC- PD753104GC-×××-AB8, 753106GC- 753106GC-×××-AB8, 753108GC- 753108GC-×××-AB8 · 64-pin plastic LQFP (14 × 14) µPD753104GC- PD753104GC-×××-8BS, 753104GC- 753104GC-×××-8BS-A, 753106GC- 753106GC-×××-8BS, 753106GC- 753106GC-×××-8BS-A, µPD753108GC- PD753108GC-×××-8BS, 753108GC- 753108GC-×××-8BS-A · 64-pin plastic LQFP (12 × 12) µPD753104GK- PD753104GK-×××-8A8, 753106GK- 753106GK-×××-8A8, 753108GK- 753108GK-×××-8A8 · 64-pin plastic TQFP (12 × 12) COM3 COM2 COM1 COM0 S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 µPD753104GK- PD753104GK-×××-9ET, 753104GK- 753104GK-×××-9ET-A, 753106GK- 753106GK-×××-9ET, 753106GK- 753106GK-×××-9ET-A, µPD753108GK- PD753108GK-×××-9ET, 753108GK- 753108GK-×××-9ET-A BIAS 1 48 S12 VLC0 2 47 S13 VLC1 3 46 S14 VLC2 4 45 S15 P30/LCDCL P30/LCDCL 5 44 S16/P93 S16/P93 P31/SYNC P31/SYNC 6 43 S17/P92 S17/P92 P32 7 42 S18/P91 S18/P91 P33 8 41 S19/P90 S19/P90 6 29 30 31 32 P10/INT0 P10/INT0 P11/INT1 P11/INT1 P12/INT2/TI1/TI2 P12/INT2/TI1/TI2 P13/TI0 P13/TI0 P63/KR3 P63/KR3 Note 28 P20/PTO0 P20/PTO0 P03/SI/SB1 P03/SI/SB1 33 P02/SO/SB0 P02/SO/SB0 16 27 P62/KR2 P62/KR2 26 P21/PTO1 P21/PTO1 P01/SCK P01/SCK P22/PCL/PTO2 P22/PCL/PTO2 34 25 35 15 24 14 P61/KR1 P61/KR1 VDD P60/KR0 P60/KR0 P00/INT4 P00/INT4 P23/BUZ P23/BUZ 23 36 22 13 X2 P53 X1 S23/P80 S23/P80 21 S22/P81 S22/P81 37 XT2 38 12 ICNote 11 P52 20 P51 19 S21/P82 S21/P82 XT1 S20/P83 S20/P83 39 18 40 10 17 9 RESET VSS P50 Connect the IC (Internally Connected) pin directly to VDD. Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 Pin Identification P00 to P03: P10 to P13: P20 to P23: P30 to P33: P50 to P53: P60 to P63: P80 to P83: P90 to P93: KR0 to KR3: SCK: SI: SO: SB0, SB1: RESET: S0 to S23: COM0 to COM3: Port 0 Port 1 Port 2 Port 3 Port 5 Port 6 Port 8 Port 9 Key return 0 to 3 Serial clock Serial input Serial output Serial data bus 0, 1 Reset Segment output 0 to 23 Common output 0 to 3 VLC0 to V LC2: BIAS: LCDCL: SYNC: TI0 to TI2: PTO0 to PTO2: BUZ: PCL: INT0, INT1, INT4: INT2: X1, X2: XT1, XT2: VDD: VSS: IC: Data Sheet U10086EJ5V1DS U10086EJ5V1DS LCD power supply 0 to 2 LCD power supply bias control LCD clock LCD synchronization Timer input 0 to 2 Programmable timer output 0 to 2 Buzzer clock Programmable clock External vectored interrupt 0, 1, 4 External test input 2 Main system clock oscillation 1, 2 Subsystem clock oscillation 1, 2 Positive power supply Ground Internally connected 7 4 P00 to P03 INTW Port 1 4 P10 to P13 SBS Port 2 4 P20 to P23 Bank fLCD Basic interval timer/ watchdog timer Port 3 4 P30 to P33 Port 5 4 P50 to P53 Port 6 4 P60 to P63 Port 8 CY Program counter 4 P80 to P83 Port 9 4 P90 to P93 SP (8) ALU INTBT TI0/P13 TI0/P13 PTO0/P20 PTO0/P20 INTT0 INTT1 Data Sheet U10086EJ5V1DS U10086EJ5V1DS TI1/TI2/P12/INT2 TI1/TI2/P12/INT2 PTO1/P21 PTO1/P21 PTO2/PCL/P22 PTO2/PCL/P22 TOUT0 General-purpose register 8-bit timer/event counter #0 TOUT0 Program memoryNote (ROM) Decode and control 8-bit timer/event Cascaded counter #1 16-bit timer/ 8-bit event timer/event counter counter #2 Data memory (RAM) 512 × 4 bits LCD controller/ driver INT1 INT0/P10 INT0/P10 INT1/P11 INT1/P11 INT4/P00 INT4/P00 INT2/P12/TI1/TI2 INT2/P12/TI1/TI2 KR0/P60 KR0/P60 to KR3/P63 KR3/P63 4 Interrupt control Clock output control Clock divider PCL/PTO2/P22 PCL/PTO2/P22 CPU clock N System clock generator Main Stand by control fLCD IC Bit sequential buffer (16) Note S20/P83 S20/P83 to S23/P80 S23/P80 4 Sub X1 X2 XT1XT2 S16/P93 S16/P93 to S19/P90 S19/P90 The ROM capacity depends on the product. VDD VSS RESET COM0 to COM3 BIAS VLC0 VLC1 VLC2 SYNC/P31 SYNC/P31 LCDCL/P30 LCDCL/P30 µPD753104 PD753104, 753106, 753108 INTCSI TOUT0 fx/2 S0 to S15 4 Clocked serial interface 16 4 INTT2 SI/SB1/P03 SI/SB1/P03 SO/SB0/P02 SO/SB0/P02 SCK/P01 SCK/P01 2. BLOCK DIAGRAM 8 Port 0 Watch timer BUZ/P23 BUZ/P23 µPD753104 PD753104, 753106, 753108 3. PIN FUNCTIONS 3.1 Port Pins (1/2) P00 I/O Alternate Function Input Pin Name INT4 Function 4-bit input port (Port 0). An on-chip pull-up resistor can be specified by means of software setting in 3-bit units. 8-Bit I/O After Reset I/O Circuit TypeNote 1 No Input (B) P01 SCK P02 SO/SB0 (F)-B P03 SI/SB1 (M)-C P10 Input INT0 P11 INT1 P12 TI1/TI2/INT2 P13 (F)-A 4-bit input port (Port 1). An on-chip pull-up resistor can be specified by means of software setting in 4-bit units. P10/INT0 P10/INT0 can select noise eliminator. No Input (B)-C 4-bit I/O port (Port 2). An on-chip pull-up resistor can be specified by means of software setting in 4-bit units. No Input E-B Programmable 4-bit I/O port (Port 3). Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software setting in 4-bit units. No Input E-B N-ch open-drain 4-bit I/O port (Port 5). An on-chip pull-up resistor can be specified in 1-bit units (mask option). Withstand voltage is 13 V in open-drain mode. No High level (when pullup resistors are provided) or highimpedance M-D TI0 P20 I/O PTO0 P21 PTO1 P22 PCL/PTO2 P23 BUZ P30 I/O LCDCL P31 SYNC P32 ­ P33 ­ P50 to P53Note 2 Notes 1. 2. I/O ­ Characters in parentheses indicate the Schmitt-triggered input. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low-level input leakage current increases when input or bit manipulation instruction is executed. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 9 µPD753104 PD753104, 753106, 753108 3.1 Port Pins (2/2) Pin Name P60 I/O I/O Alternate Function KR0 P61 KR1 P62 KR2 P63 Function 8-Bit I/O After Reset I/O Circuit TypeNote 1 Programmable 4-bit I/O port (Port 6). Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by means of software setting in 4-bit units. No Input (F)-A 4-bit I/O port (Port 8). An on-chip pull-up resistor can be specified by means of software setting in 4-bit unitsNote 2. Yes Input H Input H KR3 P80 I/O S23 P81 S22 P82 S21 P83 S20 P90 I/O S19 P91 S18 P92 S17 P93 4-bit I/O port (Port 9). An on-chip pull-up resistor can be specified by means of software setting in 4-bit unitsNote 2. S16 Notes 1. 2. Characters in parentheses indicate the Schmitt-triggered input. When these pins are used as segment signal output pins, do not connect the on-chip pull-up resistor by means of software. 10 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 3.2 Non-Port Pins (1/2) Pin Name TI0 I/O Input Alternate After Reset I/O Circuit TypeNote 1 External event pulse input to the timer/event counter. Input (B)-C Timer/event counter output Input E-B Input (F)-A Function Function P13 TI1 P12/INT2/TI2 P12/INT2/TI2 TI2 P12/INT2/TI1 P12/INT2/TI1 PTO0 Output P20 PTO1 P21 PTO2 P22/PCL P22/PCL PCL P22/PTO2 P22/PTO2 BUZ P23 Optional frequency output (for buzzer output or system clock trimming) P01 Serial clock I/O SO/SB0 P02 Serial data output Serial data bus I/O (F)-B SI/SB1 P03 Serial data input Serial data bus I/O (M)-C SCK I/O Clock output INT4 Input P00 Edge detection vectored interrupt input (both rising edge and falling edge detection) Input (B) INT0 Input P10 Edge detection vectored interrupt input (detection edge can be selected). INT0/P10 INT0/P10 can select noise eliminator. Rising edge detection testable input Input (B)-C Input (F)-A INT1 P11 INT2 P12/TI1/TI2 P12/TI1/TI2 KR0 to KR3 Noise eliminator/ asynchronous selection Asynchronous Asynchronous Input P60 to P63 S0 to S15 Output ­ Segment signal output Note 2 G-A S16 to S19 Output P93 to P90 Segment signal output Input H S20 to S23 Output P83 to P80 Segment signal output Input H COM0 to COM3 Output ­ Common signal output Note 2 G-B ­ ­ LCD drive power On-chip split resistor is enabled (mask option). ­ ­ BIAS Output ­ Output for external split resistor disconnect Note 3 ­ LCDCL Note 4 Output P30 Clock output for externally expanded driver Input E-B SYNC Note 4 Output P31 Clock output for externally expanded driver synchronization Input E-B V LC0 to V LC2 Notes 1. 2. 3. 4. Falling edge detection testable input Characters in parentheses indicate the Schmitt-triggered input. Each display output selects the following VLCX as input source. S0 to S15: V LC1, COM0 to COM2: VLC2, COM3: VLC0 When a split resistor is contained . Low level When no split resistor is contained . High impedance These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 11 µPD753104 PD753104, 753106, 753108 3.2 Non-Port Pins (2/2) Alternate Function After Reset I/O Circuit TypeNote ­ Crystal/ceramic connection pin for the main system clock oscillation. When the external clock is used, input the external clock to pin X1, and the inverted phase of the external clock to pin X2. ­ ­ ­ Crystal connection pin for the subsystem clock oscillation. When the external clock is used, input the external clock to pin XT1, and the inverted phase of the external clock to pin XT2. Pin XT1 can be used as a 1-bit input (test) pin. ­ ­ Input ­ System reset input (low-level active) ­ (B) IC ­ ­ Internally connected. Connect directly to VDD. ­ ­ V DD ­ ­ Positive power supply ­ ­ V SS ­ ­ Ground potential ­ ­ Pin Name I/O X1 Input X2 Function ­ XT1 Input XT2 ­ RESET Note 12 Characters in parentheses indicate the Schmitt-triggered input. Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 3.3 Pin I/O Circuits The µPD753108 PD753108 pin I/O circuits are shown schematically. (1/2) Type A Type D VDD VDD Data P-ch OUT P-ch IN Output disable N-ch N-ch Push-pull output that can be placed in output high-impedance (both P-ch and N-ch off). CMOS standard input buffer Type E-B Type B VDD P.U.R. P.U.R. enable P-ch IN Data Type D IN/OUT Output disable Type A Schmitt-triggered input with hysteresis characteristics P.U.R. : Pull-Up Resistor Type B-C Type F-A VDD VDD P.U.R. P.U.R. enable P.U.R. P-ch P.U.R. enable P-ch Data Output disable IN/OUT Type D IN Type B P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor Data Sheet U10086EJ5V1DS U10086EJ5V1DS 13 µPD753104 PD753104, 753106, 753108 (2/2) Type F-B Type H VDD P.U.R. P.U.R enable P-ch Output disable (P) SEG data VDD IN/OUT Type G-A P-ch IN/OUT Data Output disable Data N-ch Output disable Output disable (N) Type E-B P.U.R. : Pull-Up Resistor Type G-A Type M-C VDD P-ch N-ch VLC0 VLC1 P.U.R. P-ch N-ch P.U.R. enable P-ch P-ch N-ch IN/OUT Data OUT N-ch Output disable SEG data N-ch P-ch N-ch VLC2 N-ch P.U.R. : Pull-Up Resistor Type G-B Type M-D VDD VLC0 VLC1 P.U.R. (Mask option) IN/OUT P-ch N-ch Data P-ch N-ch P-ch Output disable N-ch OUT Input instruction COM data VDD P-ch Note P.U.R. N-ch P-ch P-ch N-ch VLC2 Voltage limitation circuit (+13 V withstand voltage) N-ch Note 14 N-ch (+13 V withstand voltage) The pull-up resistor operates only when an input instruction is executed (current flows from VDD to the pin when the pin is low). Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 3.4 Recommended Connections of Unused Pins Table 3-1. List of Recommended Connections for Unused Pins Pin Name Recommended Connection P00/INT4 P00/INT4 Connect to V SS or VDD. P01/SCK P01/SCK At input: Independently connect to VSS or VDD via a resistor. P02/SO/SB0 P02/SO/SB0 At output: Leave open. P03/SI/SB1 P03/SI/SB1 Connect to V SS. P10/INT0 P10/INT0, P11/INT1 P11/INT1 Connect to VSS or VDD. P12/TI1/TI2/INT2 P12/TI1/TI2/INT2 P13/TI0 P13/TI0 P20/PTO0 P20/PTO0 At input: Independently connect to VSS or VDD via a resistor. P21/PTO1 P21/PTO1 At output: Leave open. P22/PCL/PTO2 P22/PCL/PTO2 P23/BUZ P23/BUZ P30/LCDCL P30/LCDCL P31/SYNC P31/SYNC P32 P33 P50 to P53 At input: Connect to VSS. At output: Connect to VSS (do not connect a pull-up resistor of mask option). P60/KR0 P60/KR0 to P63/KR3 P63/KR3 At input: Independently connect to VSS or VDD via a resistor. At output: Leave open. S0 to S15 Leave open. COM0 to COM3 S16/P93 S16/P93 to S19/P90 S19/P90 At input: Independently connect to VSS or VDD via a resistor. S20/P83 S20/P83 to S23/P80 S23/P80 At output: Leave open. V LC0 to VLC2 Connect to V SS. BIAS Only if all of VLC0 to VLC2 are unused, connect to VSS. In other cases, leave open. XT1Note Connect to V SS. XT2Note Leave open. IC Connect directly to V DD. Note When the subsystem clock is not used, specify SOS.0 = 1 (so as not to use the on-chip feedback resistor). Data Sheet U10086EJ5V1DS U10086EJ5V1DS 15 µPD753104 PD753104, 753106, 753108 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Difference Between Mk I Mode and Mk II Mode The CPU of the µPD753108 PD753108 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by bit 3 of the stack bank select register (SBS). · Mk I mode: Upward compatible with the µ PD75308B PD75308B. Can be used in the 75XL CPU with a ROM capacity of up to 16 KB. · Mk II mode: Incompatible with the µPD75308B PD75308B. Can be used in all the 75XL CPU's including those products whose ROM capacity is more than 16 KB. Table 4-1. Differences Between Mk I Mode and Mk II Mode Mk I Mode Mk II Mode Number of stack bytes for subroutine instructions 2 bytes 3 bytes BRA !addr1 instruction CALLA !addr1 instruction Not available Available CALL !addr instruction 3 machine cycles 4 machine cycles CALLF !faddr instruction 2 machine cycles 3 machine cycles Caution The Mk II mode supports a program area exceeding 16 KB for the 75X and 75XL Series. Therefore, this mode is effective for enhancing software compatibility with products exceeding 16 KB. When the Mk II mode is selected, the number of stack bytes used during execution of subroutine call instructions increases by one byte per stack compared to the Mk I mode. When the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by one machine cycle. Therefore, use the Mk I mode if the RAM efficiency and processing performance are more important than software compatibility. 16 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the stack bank select register (SBS). Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 100×BNote at the beginning of a program. When using the Mk II mode, it must be initialized to 000×BNote. Note Set the desired value in the × position. Figure 4-1. Stack Bank Select Register Format Address 3 F84H SBS3 2 1 0 SBS2 SBS1 Symbol SBS0 SBS Stack area specification 0 0 Memory bank 0 0 1 Memory bank 1 Other than above setting prohibited 0 0 must be set in the bit 2 position. Mode switching specification 0 Mk II mode 1 Mk I mode Caution Since SBS3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS3 to "0" to select the Mk II mode. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 17 µPD753104 PD753104, 753106, 753108 5. MEMORY CONFIGURATION Program Memory (ROM) . 4096 × 8 bits (µ PD753104 PD753104) . 6144 × 8 bits (µ PD753106 PD753106) . 8192 × 8 bits (µ PD753108 PD753108) · Addresses 0000H 0000H and 0001H 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset start is possible from any address. · Addresses 0002H 0002H to 000DH 000DH Vector table wherein the program start address and the values set for the RBE and MBE by each vectored interrupt are written. Interrupt servicing can start from any address. · Addresses 0020H 0020H to 007FH 007FH Table area referenced by the GETI instructionNote. Note The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the number of program steps. Data Memory (RAM) · Data area . 512 words × 4 bits (000H to 1FFH) · Peripheral hardware area . 128 words × 4 bits (F80H to FFFH) 18 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 Figure 5-1. Program Memory Map (1/3) (a) µPD753104 PD753104 Address 7 6 0 0 0 H MBE RBE 5 4 0 0 0 0 0 0 (lower 8 bits) INT0 start address (higher 4 bits) start address (lower 8 bits) INT1 start address (higher 4 bits) start address (lower 8 bits) INTCSI start address (higher 4 bits) start address (lower 8 bits) INTT0 start address (higher 4 bits) start address (lower 8 bits) INTT1/INTT2 start address (higher 4 bits) INTT1/INTT2 0 0 C H MBE RBE 0 0 start address INTT0 0 0 A H MBE RBE 0 0 (higher 4 bits) INTCSI 0 0 8 H MBE RBE 0 0 start address INT1 0 0 6 H MBE RBE 0 INTBT/INT4 INT0 0 0 4 H MBE RBE 0 (lower 8 bits) INTBT/INT4 0 (higher 4 bits) Internal reset start address 0 0 2 H MBE RBE Internal reset start address start address (lower 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address ­15 to ­1, +2 to +16 BRCB !caddr instruction branch address 020H GETI instruction reference table 07FH 080H Branch destination address and subroutine entry address when GETI instruction is executed 7FFH 800H FFFH Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the lower eight bits of PC by executing the BR PCDE or BR PCXA instruction. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 19 µPD753104 PD753104, 753106, 753108 Figure 5-1. Program Memory Map (2/3) (b) µPD753106 PD753106 Address 7 6 0 0 0 0 H MBE RBE 5 0 0 0 (lower 8 bits) INT0 start address (higher 5 bits) start address (lower 8 bits) INT1 start address (higher 5 bits) start address (lower 8 bits) INTCSI start address (higher 5 bits) start address (lower 8 bits) INTT0 start address (higher 5 bits) start address (lower 8 bits) INTT1/INTT2 start address (higher 5 bits) INTT1/INTT2 0 0 0 C H MBE RBE 0 start address INTT0 0 0 0 A H MBE RBE 0 (higher 5 bits) INTCSI 0 0 0 8 H MBE RBE 0 start address INT1 0 0 0 6 H MBE RBE 0 INTBT/INT4 INT0 0 0 0 4 H MBE RBE (lower 8 bits) INTBT/INT4 0 (higher 5 bits) Internal reset start address 0 0 0 2 H MBE RBE Internal reset start address start address (lower 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address ­15 to ­1, +2 to +16 BRCB !caddr instruction branch address 0020H 0020H GETI instruction reference table 007FH 007FH 0080H 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 07FFH 0800H 0800H 0FFFH 1000H 1000H BRCB !caddr instruction branch address 17FFH 17FFH Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the lower eight bits of PC by executing the BR PCDE or BR PCXA instruction. 20 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 Figure 5-1. Program Memory Map (3/3) (c) µPD753108 PD753108 Address 7 6 0 0 0 0 H MBE RBE 5 0 0 0 (lower 8 bits) INT0 start address (higher 5 bits) start address (lower 8 bits) INT1 start address (higher 5 bits) start address (lower 8 bits) INTCSI start address (higher 5 bits) start address (lower 8 bits) INTT0 start address (higher 5 bits) start address (lower 8 bits) INTT1/INTT2 start address (higher 5 bits) INTT1/INTT2 0 0 0 C H MBE RBE 0 start address INTT0 0 0 0 A H MBE RBE 0 (higher 5 bits) INTCSI 0 0 0 8 H MBE RBE 0 start address INT1 0 0 0 6 H MBE RBE 0 INTBT/INT4 INT0 0 0 0 4 H MBE RBE (lower 8 bits) INTBT/INT4 0 (higher 5 bits) Internal reset start address 0 0 0 2 H MBE RBE Internal reset start address start address (lower 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction CALL !addr instruction subroutine entry address BR $addr instruction relative branch address ­15 to ­1, +2 to +16 BRCB !caddr instruction branch address 0020H 0020H GETI instruction reference table 007FH 007FH 0080H 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 07FFH 0800H 0800H 0FFFH 1000H 1000H BRCB !caddr instruction branch address 1FFFH Note Can be used in Mk II mode only. Remark In addition to the above, a branch can be taken to the address indicated by changing only the lower eight bits of PC by executing the BR PCDE or BR PCXA instruction. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 21 µPD753104 PD753104, 753106, 753108 Figure 5-2. Data Memory Map Data memory 000H General-purpose register area Memory bank (32 × 4) 01FH 0 256 × 4 (224 × 4) Stack areaNote Data area static RAM (512 × 4) 0FFH 100H 256 × 4 (224 × 4) 1 Display data memory 1DFH 1E0H (24 × 4) 1F7H 1F8H 1FFH (8 × 4) Not incorporated F80H 128 × 4 Peripheral hardware area FFFH Note 22 Either memory bank 0 or 1 can be selected for the stack area. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 15 µPD753104 PD753104, 753106, 753108 6. PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Port There are three kinds of I/O port. · CMOS input ports (Ports 0, 1): 8 · CMOS I/O ports (Ports 2, 3, 6, 8, 9): 20 · N-ch open-drain I/O ports (Port 5): Total 4 32 Table 6-1. Types and Features of Digital Ports Port Name Port 0 Function Port 2 4-bit I/O Port 3 When the serial interface function is used, the alternate function pins function as output ports depending on the operation mode. Also used for the INT4, SCK, SO/SB0, SI/SB1 pins. Also used for the INT0 to INT2/TI1/TI2, TI0 pins. Input/output can be specified in 4-bit units. Also used for the PTO0 to PTO2/PCL, BUZ pins. Input/output can be specified in 1-bit units. Port 1 Remarks 4-bit input only port. 4-bit input Operation and Features Also used for the LCDCL, SYNC pins. Port 5 4-bit I/O (N-ch opendrain, 13 V withstand voltage) Input/output can be specified in 4-bit units. On-chip pull-up resistor can be specified in 1-bit units by mask option. Port 6 4-bit I/O Input/output can be specified in 1-bit units. Also used for the KR0 to KR3 pins. Input/output can be specified in 4-bit units. Also used for the S20 to S23 pins. Port 8 Port 9 Ports 8 and 9 are paired and data can be input/ output in 8-bit units. - Also used for the S16 to S19 pins. 6.2 Clock Generator The clock generator is a device that generates the clock which is supplied to peripheral hardware on the CPU and is configured as shown in Figure 6-1. The clock generator operates according to how the processor clock control register (PCC) and system clock control register (SCC) are set. There are two kinds of clocks, main system clock and subsystem clock. The instruction execution time can also be changed. · 0.95, 1.91, 3.81, 15.3 µ s (main system clock: @ 4.19 MHz operation) · 0.67, 1.33, 2.67, 10.7 µ s (main system clock: @ 6.0 MHz operation) · 122 µs (subsystem clock: @ 32.768 kHz operation) Data Sheet U10086EJ5V1DS U10086EJ5V1DS 23 µPD753104 PD753104, 753106, 753108 Figure 6-1. Clock Generator Block Diagram · Basic interval timer (BT) · Timer/event counter · Serial interface · Watch timer · LCD controller/driver · INT0 noise eliminator · Clock output circuit XT1 VDD XT2 Subsystem clock oscillator fXT Main system clock oscillator LCD controller/driver fX Watch timer X1 VDD X2 1/1 to 1/4096 Divider 1/2 1/4 1/16 Selector WM.3 SCC Oscillation stop Divider SCC3 Selector 1/4 Internal bus SCC0 PCC · CPU · INT0 noise eliminator · Clock output circuit PCC0 PCC1 4 HALT F/F PCC2 S HALTNote PCC3 STOPNote R PCC2, PCC3 Clear STOP F/F Q Q Wait release signal from BT S RESET signal R Standby release signal from interrupt controller Note Instruction execution Remarks 1. fX = Main system clock frequency 2. 3. = CPU clock 4. PCC: Processor Clock Control register 5. SCC: System Clock Control register 6. 24 fXT = Subsystem clock frequency One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction. Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 6.3 Subsystem Clock Oscillator Control Functions The µPD753108 PD753108 subsystem clock oscillator has the following two control functions. · Selects by means of software whether an on-chip feedback resistor is to be used or notNote. · Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage is high (V DD 2.7 V). Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the on-chip feedback resistor) by software, connect XT1 to VSS, and leave XT2 open. This makes it possible to reduce the current consumption in the subsystem clock oscillator. The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (See Figure 6-2.) Figure 6-2. Subsystem Clock Oscillator SOS.0 Feedback resistor Inverter SOS.1 XT1 XT2 VDD Data Sheet U10086EJ5V1DS U10086EJ5V1DS 25 µPD753104 PD753104, 753106, 753108 6.4 Clock Output Circuit The clock output circuit is provided to output the clock pulses from the P22/PTO2/PCL P22/PTO2/PCL pin to the remote control wave outputs and peripheral LSI's. Clock output (PCL): , 524, 262, 65.5 kHz (main system clock: @ 4.19 MHz operation) , 750, 375, 93.8 kHz (main system clock: @ 6.0 MHz operation) Figure 6-3. Clock Output Circuit Block Diagram From clock generator Selector From timer/event counter (channel 2) fX/23 Selector Output buffer fX/24 PCL/PTO2/P22 PCL/PTO2/P22 fX/26 PORT2.2 CLOM3 0 CLOM1 CLOM0 P22 output latch CLOM Bit 2 of PMGB Port 2 I/O mode specification bit 4 Internal bus Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. 26 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 6.5 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. Interval timer operation to generate a reference time interrupt Watchdog timer operation to detect a runaway of program and reset the CPU Selects and counts the wait time when the standby mode is released Reads the contents of counting Figure 6-4. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator Clear fX/25 fX/27 MPX Clear Basic interval timer (8-bit frequency divider) Set fX/29 BT fX/212 3 Wait release signal when standby is released. BTM3 BTM2 BTM1 BTM0 BTM SET1Note 4 BT interrupt request flag Vectored interrupt IRQBT request signal Internal reset signal WDTM SET1Note 8 1 Internal bus Note Instruction execution Data Sheet U10086EJ5V1DS U10086EJ5V1DS 27 µPD753104 PD753104, 753106, 753108 6.6 Watch Timer The µPD753108 PD753108 has one watch timer channel which has the following functions. Sets the test flag (IRQW) at 0.5-second intervals. The standby mode can be released by the IRQW. 0.5-second interval can be created by both the main system clock (4.19 MHz) and subsystem clock (32.768 kHz). Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23/BUZ P23/BUZ pin, usable for buzzer and trimming of system clock oscillation frequencies. Clears the frequency divider to make the watch start with zero seconds. Figure 6-5. Watch Timer Block Diagram fW (512 Hz : 1.95 ms) 26 fW (256 Hz : 3.91 ms) 27 fX 128 From clock generator (32.768 kHz) Selector fW (32.768 kHz) fXT (32.768 kHz) Divider fW 214 fLCD INTW IRQW set signal Selector 2 Hz 0.5 sec 4 kHz 2 kHz fW fW 23 24 Clear Selector Output buffer P23/BUZ P23/BUZ WM WM7 PORT2.3 0 WM5 WM4 WM3 8 WM2 WM1 WM0 P23 output latch Bit 2 of PMGB Port 2 I/O mode Bit test instruction Internal bus Remark The values enclosed in parentheses are applied when fX = 4.19 MHz and fXT = 32.768 kHz. 28 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 6.7 Timer/Event Counter The µPD753108 PD753108 has three channels of timer/event counters. Its configuration is shown in Figures 6-6 to 6-8. The timer/event counter has the following functions. Programmable interval timer operation Square wave output of any frequency to the PTOn pin (n = 0 to 2) Event counter operation Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided frequency to the PTOn pin (frequency divider operation). Supplies the serial shift clock to the serial interface circuit. Reads the count value. The timer/event counter operates in the following four modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter Channel Channel 0 Channel 1 Channel 2 Yes Yes Yes NoNote No Yes PWM pulse generator mode No No Yes 16-bit timer/event counter mode No Yes NoNote Yes No Yes Mode 8-bit timer/event counter mode Gate control function Gate control function Carrier generator mode Note Used for gate control signal generation Data Sheet U10086EJ5V1DS U10086EJ5V1DS 29 30 Figure 6-6. Timer/Event Counter (Channel 0) Block Diagram Internal bus 8 SET1Note 8 8 ­ TM06 TM05 TM04 TM03 TM02 0 TOE0 TMOD0 TM0 T0 enable flag Modulo register (8) ­ PORT2.0 P20 output latch Bit 2 of PMGB Port 2 I/O mode To serial interface 8 PORT1.3 TOUT0 Data Sheet U10086EJ5V1DS U10086EJ5V1DS Match Comparator (8) TOUT F/F Output buffer 8 Input buffer PTO0/P20 PTO0/P20 Reset T0 TI0/P13 TI0/P13 fX/24 INTT0 IRQT0 set signal Count register (8) MPX CP From fX/26 clock fX/28 generator fX/210 Clear Timer operation start To timer/event counter (channel 2) Note Instruction execution Caution When setting data to TM0, be sure to set bit 1 to 0. µPD753104 PD753104, 753106, 753108 RESET IRQT0 clear signal Figure 6-7. Timer/Event Counter (Channel 1) Block Diagram Internal bus 8 SET1 Note TOE1 TM1 ­ 8 TM16 TM15 TM14 TM13 TM12 TM11 TM10 T1 enable flag TMOD1 Decoder PORT1.2 PORT2.1 P21 output latch Bit 2 of PMGB Port 2 I/O mode Modulo register (8) 8 Data Sheet U10086EJ5V1DS U10086EJ5V1DS Match Comparator (8) Input buffer TI1/TI2/P12/INT2 TI1/TI2/P12/INT2 5 fX/2 fX/26 From clock 8 generator fX/2 10 fX/2 fX/212 MPX CP P21/PTO1 P21/PTO1 Output buffer Reset 8 Timer/event counter (channel 2) output TOUT F/F T1 Count register (8) Clear 16-bit timer/event counter mode IRQT1 clear signal Selector Timer/event counter (channel 2) match signal (When 16-bit timer/event counter mode) Timer/event counter (channel 2) reload signal Timer/event counter (channel 2) comparator (When 16-bit timer/event counter mode) Note Instruction execution INTT1 IRQT1 set signal 31 µPD753104 PD753104, 753106, 753108 RESET Timer operation start 32 Figure 6-8. Timer/Event Counter (Channel 2) Block Diagram Internal bus TMOD2H TM2 8 PORT1.2 Decoder 8 MPX (8) 8 Data Sheet U10086EJ5V1DS U10086EJ5V1DS TI1/TI2/P12/INT2 TI1/TI2/P12/INT2 fX fX/2 fX/24 From clock fX/26 generator fX/28 fX/210 Match TOUT F/F Reset 8 MPX CP PORT2.2 Bit 2 of PMGB P22 Port 2 output latch I/O TC2 TOE2 REMC NRZB NRZ Reload Comparator (8) Input buffer 8 TMOD2 Modulo register (8) TGCE High-level period setting modulo register (8) TM26 TM25 TM24 TM23 TM22 TM21 TM20 8 T2 Count register (8) Overflow P22/PCL/PTO2 P22/PCL/PTO2 Output buffer Selector 8 Selector SET1Note Selector 8 Timer/event counter (channel 1) clock input Carrier generator mode Clear INTT2 IRQT2 set signal 16-bit timer/event counter mode IRQT2 clear signal Timer operation start RESET Timer/event counter (channel 1) clear signal (When 16-bit timer/event counter mode) Timer/event counter (channel 1) match signal (When 16-bit timer/event counter mode) Note Instruction execution From clock output circuit Timer/event counter (channel 1) match signal (When carrier generator mode) µPD753104 PD753104, 753106, 753108 Timer event counter (channel 0) TOUT F/F µPD753104 PD753104, 753106, 753108 6.8 Serial Interface The µ PD753108 PD753108 incorporates a clock-synchronous 8-bit serial interface. The serial interface can be used in the following four modes. · Operation stop mode · 3-wire serial I/O mode · 2-wire serial I/O mode · SBI mode Data Sheet U10086EJ5V1DS U10086EJ5V1DS 33 34 Figure 6-9. Serial Interface Block Diagram Internal bus 8/4 Bit test 8 8 CSIM 8 Bit manipulation Bit test Slave address register (SVA) (8) SBIC RELT Address comparator Match CMDT (8) P03/SI/SB1 P03/SI/SB1 SO latch SET CLR Selector Shift register (SIO) D Q BSYE P02/SO/SB0 P02/SO/SB0 ACKE Data Sheet U10086EJ5V1DS U10086EJ5V1DS ACKT (8) Busy/ acknowledge output circuit Selector Bus release/ command/ acknowledge detector RELD CMDD ACKD Serial clock counter P01 output Iatch Serial clock controller INTCSI controller IRQCSI set signal Serial clock selector fX/23 fX/24 fX/26 TOUT0 (from timer/event counter (channel 0) External SCK µPD753104 PD753104, 753106, 753108 INTCSI P01/SCK P01/SCK µPD753104 PD753104, 753106, 753108 6.9 LCD Controller/Driver The µPD753108 PD753108 incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the LCD panel directly. The µ PD753108 PD753108 LCD controller/driver has the following functions: Display data memory is read automatically by DMA operation and segment and common signals are generated. Display mode can be selected from among the following five: Static 1/2 duty (time-divided by 2), 1/2 bias 1/3 duty (time-divided by 3), 1/2 bias 1/3 duty (time-divided by 3), 1/3 bias 1/4 duty (time-divided by 4), 1/3 bias A frame frequency can be selected from among four in each display mode. A maximum of 24 segment signal output pins (S0 to S23) and four common signal output pins (COM0 to COM3). The segment signal output pins (S0 to S23) can be changed to the I/O ports (Port 8 and Port 9). Split resistor can be incorporated to supply LCD drive power (mask option). · Various bias methods and LCD drive voltages are applicable. · When display is off, current flowing through the split resistor is cut. Display data memory not used for display can be used for normal data memory. It can also operate by using the subsystem clock. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 35 36 Figure 6-10. LCD Controller/Driver Block Diagram Internal bus 4 4 8 4 Port 8 output latch 4 4 Port 9 output latch Port mode 3 2 1 0 3 2 1 0 LCD/port selection register 4 8 1F7H 3 2 1 0 1F0H 1EFH 3 2 1 0 3 2 1 0 1E0H 3 2 1 0 3 2 1 0 register group C 0 1 3 2 1 0 3 2 1 0 3 2 1 0 4 Display mode register Display control register 4 4 Port 3 Port mode output latch register group A 1 0 1 0 Decoder Data Sheet U10086EJ5V1DS U10086EJ5V1DS 1 2 Port 9 I/O buffer 3 0 1 2 Segment driver Segment driver Common driver 3 S23/P80 S23/P80 S16/P93 S16/P93 S15 S0 LCD drive voltage control COM3 COM2 COM1 COM0 VLC2 VLC1 VLC0 LCD drive mode switching P31/SYNC P31/SYNC P30/LCDCL P30/LCDCL µPD753104 PD753104, 753106, 753108 Port 8 I/O buffer 0 Timing fLCD controller µPD753104 PD753104, 753106, 753108 6.10 Bit Sequential Buffer The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. Figure 6-11. Bit Sequential Buffer (16 Bits) Format Address Bit FC3H 3 Symbol L register 2 1 FC2H 0 3 2 BSB3 L = FH 1 FC1H 0 3 BSB2 L = CH L = BH 2 1 FC0H 0 3 BSB1 L = 8H L = 7H 2 1 0 BSB0 L = 4H L = 3H L = 0H DECS L INCS L Remarks 1. In the pmem.@L addressing, the specified bit moves corresponding to the L register. 2. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 37 µPD753104 PD753104, 753106, 753108 7. INTERRUPT FUNCTION AND TEST FUNCTION The µPD753108 PD753108 has eight types of interrupt sources and two types of test sources. Of these test sources, INT2 has two types of edge detection testable inputs. The interrupt controller of the µPD753108 PD753108 has the following functions. (1) Interrupt function · Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IE×××) and interrupt master enable flag (IME). · Can set any interrupt start address. · Multiple interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). · Test function of interrupt request flag (IRQ×××). An interrupt generation can be checked by software. · Release the standby mode. An interrupt to be released can be selected by the interrupt enable flag. (2) Test function · Test request flag (IRQ×××) generation can be checked by software. · Release the standby mode. The test source to be released can be selected by the test enable flag. 38 Data Sheet U10086EJ5V1DS U10086EJ5V1DS Figure 7-1. Interrupt Controller Block Diagram Internal bus 2 1 4 IME IPS IM2 IM1 IST1 IST0 Interrupt enable flag (IE×××) IM0 Decoder INTBT INT4/P00 INT4/P00 INT0/P10 INT0/P10 Note INT1/P11 INT1/P11 Selector Both edge detector Edge detector Data Sheet U10086EJ5V1DS U10086EJ5V1DS Edge detector IRQBT VRQn IRQ4 IRQ0 IRQ1 INTT0 KR3/P63 KR3/P63 IRQT2 INTW KR0/P60 KR0/P60 IRQT1 INTT2 Rising edge detector IRQT0 INTT1 INT2/P12 INT2/P12 IRQCSI Vector table address generator IRQW Selector IRQ2 Falling edge detector IM2 Note Noise eliminator (Standby release is disabled when noise eliminator is selected.) Standby release signal 39 µPD753104 PD753104, 753106, 753108 INTCSI Priority controller µPD753104 PD753104, 753106, 753108 8. STANDBY FUNCTION In order to reduce power dissipation while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µ PD753108 PD753108. Table 8-1. Operation Status in Standby Mode Mode Item STOP Mode HALT Mode Set instruction STOP instruction HALT instruction System clock when set Settable only when the main system clock is used. Settable both by the main system clock and subsystem clock. Operation status Clock generator Main system clock stops oscillation. Only the CPU clock halts (oscillation continues). Basic interval timer/ watchdog timer Operation stops. Operable only when the main system clock is oscillated. BT mode : IRQBT is set in the reference time interval WT mode : Reset signal is generated by BT overflow Serial interface Operable only when an external SCK input is selected as the serial clock. Operable only when an external SCK input is selected as the serial clock or when the main system clock is oscillated. Timer/event counter Operable only when a signal input to the TI0 to TI2 pins is specified as the count clock. Operable only when a signal input to the TI0 to TI2 pins is specified as the count clock or when the main system clock is oscillated. Watch timer Operable when fXT is selected as the count clock. Operable. LCD controller/driver Operable only when fXT is selected as the Operable. LCDCL. External interrupt The INT1, 2, and 4 are operable. Only the INT0 is not operatedNote. CPU The operation stops. Release signal Note · Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag · Test request signal sent from the test source enabled by the test enable flag · RESET pin Can operate only when the noise eliminator is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0). 40 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 9. RESET FUNCTION There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/ watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 91 shows the configuration of the above two inputs. Figure 9-1. Configuration of Reset Function RESET Internal reset signal Reset signal sent from the basic interval timer/watchdog timer WDTM Internal bus Generation of the RESET signal initializes each hardware as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation Wait Note RESET signal generated Operation mode or standby mode HALT mode Operation mode Internal reset operation Note The following two times can be selected by the mask option. 2 17/fX (21.8 ms: @ 6.00 MHz operation, 31.3 ms: @ 4.19 MHz operation) 2 15/fX (5.46 ms: @ 6.00 MHz operation, 7.81 ms: @ 4.19 MHz operation) Data Sheet U10086EJ5V1DS U10086EJ5V1DS 41 µPD753104 PD753104, 753106, 753108 Table 9-1. Status of Each Hardware After Reset (1/2) RESET Signal Generation in the Standby Mode RESET Signal Generation in Operation Sets the lower 4 bits of program memory's address 0000H 0000H to the PC11 to PC8 and the contents of address 0001H 0001H to the PC7 to PC0. Sets the lower 4 bits of program memory's address 0000H 0000H to the PC11 to PC8 and the contents of address 0001H 0001H to the PC7 to PC0. µPD753106 PD753106, Sets the lower 5 bits of program µPD753108 PD753108 memory's address 0000H 0000H to the PC12 to PC8 and the contents of address 0001H 0001H to the PC7 to PC0. Sets the lower 5 bits of program memory's address 0000H 0000H to the PC12 to PC8 and the contents of address 0001H 0001H to the PC7 to PC0. Hardware Program counter (PC) PSW µPD753104 PD753104 Carry flag (CY) Held Undefined Skip flag (SK0 to SK2) 0 0 Interrupt status flag (IST0, IST1) 0 0 Sets the bit 6 of program memory's address 0000H 0000H to the RBE and bit 7 to the MBE. Sets the bit 6 of program memory's address 0000H 0000H to the RBE and bit 7 to the MBE. Undefined Undefined 1000B 1000B 1000B 1000B Data memory (RAM) Held Undefined General-purpose register (X, A, H, L, D, E, B, C) Held Undefined Bank select register (MBS, RBS) 0, 0 0, 0 Undefined Undefined Bank enable flag (MBE, RBE) Stack pointer (SP) Stack bank select register (SBS) Basic interval Counter (BT) timer/watchdog Mode register (BTM) 0 0 timer Watchdog timer enable flag (WDTM) 0 0 Timer/event Counter (T0) 0 0 counter (T0) Modulo register (TMOD0) FFH FFH 0 0 0, 0 0, 0 0 0 FFH FFH 0 0 0, 0 0, 0 0 0 Mode register (TM0) TOE0, TOUT F/F Timer/event Counter (T1) counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer/event Counter (T2) counter (T2) Modulo register (TMOD2) FFH FFH High-level period setting modulo register (TMOD2H) FFH FFH 0 0 0, 0 0, 0 0, 0, 0 0, 0, 0 TGCE 0 0 Mode register (WM) 0 0 Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB Watch timer 42 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 Table 9-1. Status of Each Hardware After Reset (2/2) Hardware RESET Signal Generation in Operation Shift register (SIO) Held Undefined Operation mode register (CSIM) 0 0 SBI control register (SBIC) Serial interface RESET Signal Generation in the Standby Mode 0 0 Held Undefined Slave address register (SVA) Clock generator, Processor clock control register (PCC) 0 0 clock output System clock control register (SCC) 0 0 circuit Clock output mode register (CLOM) 0 0 Sub-oscillator control register (SOS) 0 0 LCD controller/ Display mode register (LCDM) 0 0 driver Display control register (LCDC) 0 0 LCD/port selection register (LPS) 0 0 Reset (0) Reset (0) Interrupt Interrupt request flag (IRQ×××) function Interrupt enable flag (IE×××) 0 0 Interrupt priority selection register (IPS) 0 0 INT0, 1, 2 mode registers (IM0, IM1, IM2) 0, 0, 0 0, 0, 0 Output buffer Off Off Output latch Cleared (0) Cleared (0) I/O mode registers (PMGA, B, C) 0 0 Pull-up resistor setting register (POGA, B) 0 0 Held Undefined Digital port Bit sequential buffer (BSB0 to BSB3) Data Sheet U10086EJ5V1DS U10086EJ5V1DS 43 µPD753104 PD753104, 753106, 753108 10. MASK OPTION The µPD753108 PD753108 has the following mask options. Mask options of P50 to P53 Selects whether or not to internally connect a pull-up resistor. Connect pull-up resistor internally in 1-bit units. Do not connect pull-up resistor internally. VLC0 to V LC2 pins, BIAS pin mask option Selects whether or not to internally connect LCD-driving split resistors. Do not connect split resistor internally. Connect four 10 k (TYP.) split resistors simultaneously internally. Connect four 100 k (TYP.) split resistors simultaneously internally. Standby function mask option Selects the wait time with the RESET signal. 2 17/fx (21.8 ms: @ fx = 6.0 MHz operation, 31.3 ms: @ fx = 4.19 MHz operation) 2 15/fx (5.46 ms: @ fx = 6.0 MHz operation, 7.81 ms: @ fx = 4.19 MHz operation) 44 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 11. INSTRUCTION SET (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to RA75X RA75X Assembler Package Language User's Manual (U12385E U12385E). If there are several elements, one of them is selected. Capital letters and the + and ­ symbols are key words and are described as they are. For immediate data, appropriate numbers and labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the register flags can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, see User's Manual. Expression Format Description Method reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp rp1 rp2 rp' rp'1 XA, BC, BC, XA, BC, rpa rpa1 HL, HL+, HL­, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or label Note 2-bit immediate data or label fmem pmem FB0H to FBFH, FF0H to FFFH immediate data or label FC0H to FFFH immediate data or label addr 0000H 0000H to 0FFFH immediate data or label (µPD753104 PD753104) BC, DE, DE BC, DE, DE, HL HL DE, HL, XA', BC', DE', HL' HL, XA', BC', DE', HL' caddr faddr taddr 20H to 7FH immediate data (where bit 0 = 0) or label PORTn IE××× RBn MBn Port 0 to Port 3, Port 5, Port 6, Port 8, Port 9 IEBT, IET0 to IET2, IE0 to IE2, IE4, IECSI, IEW RB0 to RB3 MB0, MB1, MB15 addr1 (Mk II mode only) immediate data immediate data immediate data immediate data immediate data data or label data or label or or or or or label label label label label (µPD753106 PD753106) (µPD753108 PD753108) (µPD753104 PD753104) (µPD753106 PD753106) (µPD753108 PD753108) 0000H 0000H to 17FFH 17FFH 0000H 0000H to 1FFFH 0000H 0000H to 0FFFH 0000H 0000H to 17FFH 17FFH 0000H 0000H to 1FFFH 12-bit immediate 11-bit immediate Note mem can be only used for even address in 8-bit data processing. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 45 µPD753104 PD753104, 753106, 753108 (2) Legend in explanation of operation A: A register; 4-bit accumulator B: B register C: C register D: D register E: E register H: H register L: L register X: X register XA: XA register pair; 8-bit accumulator BC: BC register pair DE: DE register pair HL: HL register pair XA': XA' expanded register pair BC': BC' expanded register pair DE': DE' expanded register pair HL': HL' expanded register pair PC: Program counter SP: Stack pointer CY: Carry flag; bit accumulator PSW: Program status word MBE: Memory bank enable flag RBE: Register bank enable flag PORTn: Port n (n = 0 to 3, 5, 6, 8, 9) IME: Interrupt master enable flag IPS: Interrupt priority selection register IE×××: Interrupt enable flag RBS: Register bank selection register MBS: Memory bank selection register PCC: Processor clock control register .: Separation between address and bit (××): 46 The contents addressed by ×× ××H: Hexadecimal data Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 (3) Explanation of symbols under addressing area column *1 MB = MBE·MBS (MBS = 0, 1, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1 : MB = MBS (MBS = 0, 1, 15) *4 MB = 15, fmem = FB0H to FBFH, FF0H to FFFH *5 MB = 15, pmem = FC0H to FFFH *6 µPD753104 PD753104 addr = 000H to FFFH µPD753106 PD753106 addr = 0000H 0000H to 17FFH 17FFH µPD753108 PD753108 Data memory addressing addr = 0000H 0000H to 1FFFH *7 addr = (Current PC) ­ 15 to (Current PC) ­ 1 (Current PC) + 2 to (Current PC) + 16 addr1 = (Current PC) ­ 15 to (Current PC) ­ 1 (Current PC) + 2 to (Current PC) + 16 µPD753104 PD753104 caddr = 000H to FFFH µPD753106 PD753106 caddr = 0000H 0000H to 0FFFH (PC 12 = 0) or 1000H 1000H to 17FFH 17FFH (PC12 = 1) µPD753108 PD753108 *8 caddr = 0000H 0000H to 0FFFH (PC 12 = 0) or 1000H 1000H to 1FFFH (PC12 = 1) *9 faddr = 0000H 0000H to 07FFH 07FFH *10 taddr = 0020H 0020H to 007FH 007FH *11 µPD753104 PD753104 addr1 = 000H to FFFH µPD753106 PD753106 addr1 = 0000H 0000H to 17FFH 17FFH µPD753108 PD753108 Program memory addressing addr1 = 0000H 0000H to 1FFFH Remarks 1. MB indicates memory bank that can be accessed. 2. In *2, MB = 0 independently of how MBE and MBS are set. 3. In *4 and *5, MB = 15 independently of how MBE and MBS are set. 4. *6 to *11 indicate the areas that can be addressed. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 47 µPD753104 PD753104, 753106, 753108 (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. · When no skip is made: S = 0 · When the skipped instruction is a 1- or 2-byte instruction: S = 1 · When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC. 48 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 Instruction Group Transfer A, #n4 1 1 A n4 2 2 reg1 n4 2 2 XA n8 String effect A HL, #n8 2 2 HL n8 String effect B rp2, #n8 2 2 rp2 n8 A, @HL 1 1 A (HL) *1 A, @HL+ 1 2+S A (HL), then L L+1 *1 L=0 A, @HL­ 1 2+S A (HL), then L L­1 *1 L = FH A, @rpa1 1 1 A (rpa1) *2 XA, @HL 2 2 XA (HL) *1 @HL, A 1 1 (HL) A *1 @HL, XA 2 2 (HL) XA *1 A, mem 2 2 A (mem) *3 XA, mem 2 2 XA (mem) *3 mem, A 2 2 (mem) A *3 mem, XA 2 2 (mem) XA *3 A, reg 2 2 A reg XA, rp' 2 2 XA rp' reg1, A 2 2 reg1 A rp'1, XA XCH Number of Machine Cycles XA, #n8 MOV Number of Bytes reg1, #n4 Mnemonic 2 2 rp'1 XA A, @HL 1 1 A (HL) *1 A, @HL+ 1 2+S A (HL), then L L+1 *1 L=0 A, @HL­ 1 2+S A (HL), then L L­1 *1 L = FH A, @rpa1 1 1 A (rpa1) *2 XA, @HL 2 2 XA (HL) *1 A, mem 2 2 A (mem) *3 XA, mem 2 2 XA (mem) *3 A, reg1 1 1 A reg1 XA, rp' 2 2 XA rp' Operand Operation Data Sheet U10086EJ5V1DS U10086EJ5V1DS Addressing Area Skip Condition String effect A 49 µPD753104 PD753104, 753106, 753108 Instruction Group Table reference Mnemonic MOVT Operand XA, @PCDE Number of Bytes Number of Machine Cycles 1 3 Operation Addressing Area Skip Condition µPD753104 PD753104 XA (PC11­8+DE)ROM µPD753106 PD753106, 753108 XA (PC12­8+DE)ROM XA, @PCXA 1 3 µPD753104 PD753104 XA (PC11­8+XA)ROM µPD753106 PD753106, 753108 XA (PC12­8+XA)ROM XA, @BCDE CY, fmem.bit 2 2 CY (fmem.bit) *4 2 2 CY (pmem7­2+L3­2.bit(L1­0) *5 2 2 CY (H+mem3­0.bit) *1 2 2 (fmem.bit) CY *4 2 2 (pmem7­2+L3­2.bit(L1­0) CY *5 2 2 (H+mem3­0.bit) CY *1 A, #n4 1 1+S A A+n4 carry 2 2+S XA XA+n8 carry A, @HL 1 1+S A A+(HL) XA, rp' 2 2+S XA XA+rp' carry rp'1, XA 2 2+S rp'1 rp'1+XA carry A, @HL 1 1 A, CY A+(HL)+CY XA, rp' 2 2 XA, CY XA+rp'+CY rp'1, XA 2 2 rp'1, CY rp'1+XA+CY A, @HL 1 1+S A A­(HL) XA, rp' 2 2+S XA XA­rp' borrow rp'1, XA 2 2+S rp'1 rp'1­XA borrow A, @HL 1 1 A, CY A­(HL)­CY XA, rp' 2 2 XA, CY XA­rp'­CY rp'1, XA Note *6 XA, #n8 SUBC XA (BCXA)ROMNote @H+mem.bit, CY SUBS 3 pmem.@L, CY ADDC 1 fmem.bit, CY ADDS *6 CY, @H+mem.bit Operation XA (BCDE)ROMNote CY, pmem.@L MOV1 3 XA, @BCXA Bit transfer 1 2 2 rp'1, CY rp'1­XA­CY carry *1 *1 borrow *1 Set "0" in B register if the µPD753104 PD753104 is used. Only lower one bit of B register will be valid if the µ PD753106 PD753106 or 753108 is used. 50 *1 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 Number of Machine Cycles A, #n4 2 2 A A n4 1 1 A A (HL) XA, rp' 2 2 XA XA rp' rp'1, XA 2 2 rp'1 rp'1 XA A, #n4 2 2 A A n4 A, @HL 1 1 A A (HL) XA, rp' 2 2 XA XA rp' rp'1, XA 2 2 rp'1 rp'1 XA A, #n4 2 2 A A v n4 A, @HL 1 1 A A v (HL) XA, rp' 2 2 XA XA v rp' rp'1, XA 2 2 rp'1 rp'1 v XA RORC A 1 1 CY A0, A3 CY, An­1 An NOT A 2 2 AA INCS reg 1 1+S reg reg+1 reg = 0 rp1 1 1+S rp1 rp1+1 rp1 = 00H @HL 2 2+S (HL) (HL)+1 *1 (HL) = 0 mem 2 2+S (mem) (mem)+1 *3 (mem) = 0 reg 1 1+S reg reg­1 reg = FH rp' 2 2+S rp' rp'­1 rp' = FFH reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA, rp' Operation Number of Bytes A, @HL Instruction Group 2 2+S Skip if XA = rp' XA = rp' SET1 CY 1 1 CY 1 CLR1 CY 1 1 CY 0 SKT CY 1 1+S NOT1 CY 1 1 Mnemonic AND OR XOR Accumulator manipulation Increment and decrement DECS Comparison Carry flag manipulation SKE Operand Operation Skip if CY = 1 Addressing Area Skip Condition *1 *1 *1 CY = 1 CY CY Data Sheet U10086EJ5V1DS U10086EJ5V1DS 51 µPD753104 PD753104, 753106, 753108 *4 2 2 (pmem7­2+L3­2.bit(L1­0) 1 *5 2 2 (H+mem3­0.bit) 1 *1 mem.bit 2 2 (mem.bit) 0 *3 2 2 (fmem.bit) 0 *4 2 2 (pmem7­2+L3­2.bit(L1­0) 0 *5 2 2 (H+mem3­0.bit) 0 *1 mem.bit 2 2+S Skip if (mem.bit) = 1 *3 (mem.bit) = 1 2 2+S Skip if (fmem.bit) = 1 *4 (fmem.bit) = 1 2 2+S Skip if (pmem7­2+L3­2.bit(L1­0) = 1 *5 (pmem.@L) = 1 2 2+S Skip if (H+mem3­0.bit) = 1 *1 (@H+mem.bit) = 1 mem.bit 2 2+S Skip if (mem.bit) = 0 *3 (mem.bit) = 0 2 2+S Skip if (fmem.bit) = 0 *4 (fmem.bit) = 0 pmem.@L 2 2+S Skip if (pmem7­2+L3­2.bit(L1­0) = 0 *5 (pmem.@L) = 0 @H+mem.bit 2 2+S Skip if (H+mem3­0.bit) = 0 *1 (@H+mem.bit) = 0 fmem.bit 2 2+S Skip if (fmem.bit) = 1 and clear *4 (fmem.bit) = 1 pmem.@L 2 2+S Skip if (pmem7­2+L3­2.bit(L1­0) = 1 and clear *5 (pmem.@L) = 1 @H+mem.bit 2 2+S Skip if (H+mem3­0.bit) = 1 and clear *1 (@H+mem.bit) = 1 CY, fmem.bit 2 2 CY CY (fmem.bit) *4 CY, pmem.@L 2 2 CY CY (pmem7­2+L3­2.bit(L1­0) *5 CY, @H+mem.bit 2 2 CY CY (H+mem3­0.bit) *1 CY, fmem.bit 2 2 CY CY (fmem.bit) *4 CY, pmem.@L 2 2 CY CY (pmem7­2+L3­2.bit(L1­0) *5 CY, @H+mem.bit 2 2 CY CY (H+mem3­0.bit) *1 CY, fmem.bit 2 2 CY CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY CY v (pmem7­2+L3­2.bit(L1­0) *5 CY, @H+mem.bit 52 (fmem.bit) 1 fmem.bit XOR1 2 @H+mem.bit OR1 2 pmem.@L AND1 *3 fmem.bit SKTCLR (mem.bit) 1 @H+mem.bit SKF 2 pmem.@L SKT 2 fmem.bit CLR1 mem.bit @H+mem.bit SET1 Number of Machine Cycles pmem.@L Memory bit manipulation Mnemonic Number of Bytes fmem.bit Instruction Group 2 2 CY CY v (H+mem3­0.bit) *1 Operand Operation Data Sheet U10086EJ5V1DS U10086EJ5V1DS Addressing Area Skip Condition µPD753104 PD753104, 753106, 753108 Instruction Group Branch Mnemonic BRNote Operand addr Number of Bytes Number of Machine Cycles ­ ­ Operation µPD753104 PD753104 PC11­0 addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. Addressing Area Skip Condition *6 µPD753106 PD753106, 753108 PC12­0 addr Select appropriate instruction from among BR !addr, BRCB !caddr and BR $addr according to the assembler being used. addr1 ­ ­ µPD753104 PD753104 PC11-0 PC11-0 addr1 Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. *11 µPD753106 PD753106, 753108 PC12­0 addr1 Select appropriate instruction from among BR !addr, BRA !addr1, BRCB !caddr and BR $addr1 according to the assembler being used. !addr 3 3 µPD753104 PD753104 PC11­0 addr *6 µPD753106 PD753106, 753108 PC12­0 addr $addr 1 2 µPD753104 PD753104 PC11­0 addr *7 µPD753106 PD753106, 753108 PC12­0 addr $addr1 1 2 µPD753104 PD753104 PC11­0 addr1 µPD753106 PD753106, 753108 PC12­0 addr1 Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 53 µPD753104 PD753104, 753106, 753108 Instruction Group Branch Mnemonic BR Operand Number of Bytes Number of Machine Cycles 2 3 PCDE Operation Addressing Area Skip Condition µPD753104 PD753104 PC11­0 PC11-8 PC11-8+DE µPD753106 PD753106, 753108 PC12­0 PC12-8 PC12-8+DE PCXA 2 3 µPD753104 PD753104 PC11­0 PC11-8 PC11-8+XA µPD753106 PD753106, 753108 PC12­0 PC12-8 PC12-8+XA BCDE 2 3 µPD753104 PD753104 PC11­0 BCDENote 1 *6 µPD753106 PD753106, 753108 PC12­0 BCDENote 2 BCXA 2 3 µPD753104 PD753104 PC11­0 BCXANote 1 *6 µPD753106 PD753106, 753108 PC12­0 BCXANote 2 BRANote 3 !addr1 3 3 µPD753104 PD753104 PC11­0 addr1 *11 µPD753106 PD753106, 753108 PC12­0 addr1 BRCB !caddr 2 2 µPD753104 PD753104 PC11­0 caddr11­0 *8 µPD753106 PD753106, 753108 PC12­0 PC12+caddr11­0 Subroutine stack control CALLANote 3 !addr1 3 3 µPD753104 PD753104 (SP­2) ×, ×, MBE, RBE (SP­6) (SP­3) (SP­4) PC11­0 (SP­5) 0, 0, 0, 0 PC11­0 addr1, SP SP­6 *11 µPD753106 PD753106, 753108 (SP­2) ×, ×, MBE, RBE (SP­6) (SP­3) (SP­4) PC11­0 (SP­5) 0, 0, 0, PC12 PC12­0 addr1, SP SP­6 Notes 1. 2. 3. "0" must be set to B register. Only lower one bit is valid in B register. The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 54 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 Instruction Group Subroutine stack control Mnemonic CALLNote Operand !addr Number of Bytes Number of Machine Cycles 3 3 Operation µPD753104 PD753104 (SP­3) MBE, RBE, 0, 0 (SP­4) (SP­1) (SP­2) PC11­0 PC11­0 addr, SP SP­4 Addressing Area Skip Condition *6 µPD753106 PD753106, 753108 (SP­3) MBE, RBE, 0, PC12 (SP­4) (SP­1) (SP­2) PC11­0 PC12­0 addr, SP SP­4 4 µPD753104 PD753104 (SP­2) ×, ×, MBE, RBE (SP­6) (SP­3) (SP­4) PC11­0 (SP­5) 0, 0, 0, 0 PC11­0 addr, SP SP­6 µPD753106 PD753106, 753108 (SP­2) ×, ×, MBE, RBE (SP­6) (SP­3) (SP­4) PC11­0 (SP­5) 0, 0, 0, PC12 PC12­0 addr, SP SP­6 CALLFNote !faddr 2 2 µPD753104 PD753104 (SP­3) MBE, RBE, 0, 0 (SP­4) (SP­1) (SP­2) PC11­0 PC11­0 0+faddr, SP SP­4 *9 µPD753106 PD753106, 753108 (SP­3) MBE, RBE, 0, PC12 (SP­4) (SP­1) (SP­2) PC11­0 PC12­0 00+faddr, SP SP­4 3 µPD753104 PD753104 (SP­2) ×, ×, MBE, RBE (SP­6) (SP­3) (SP­4) PC11­0 (SP­5) 0, 0, 0, 0 PC11­0 0+faddr, SP SP­6 µPD753106 PD753106, 753108 (SP­2) ×, ×, MBE, RBE (SP­6) (SP­3) (SP­4) PC11­0 (SP­5) 0, 0, 0, PC12 PC12­0 00+faddr, SP SP­6 Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 55 µPD753104 PD753104, 753106, 753108 Instruction Group Subroutine stack control Mnemonic RETNote Operand Number of Bytes Number of Machine Cycles 1 3 Operation Addressing Area Skip Condition µPD753104 PD753104 PC11­0 (SP) (SP+3) (SP+2) MBE, RBE, 0, 0 (SP+1), SP SP+4 µPD753106 PD753106, 753108 PC11­0 (SP) (SP+3) (SP+2) MBE, RBE, 0, PC12 (SP+1), SP SP+4 µPD753104 PD753104 ×, ×, MBE, RBE (SP+4) 0, 0, 0, 0, (SP+1) PC11­0 (SP) (SP+3) (SP+2), SP SP+6 µPD753106 PD753106, 753108 ×, ×, MBE, RBE (SP+4) MBE, 0, 0, PC12 (SP+1) PC11­0 (SP) (SP+3) (SP+2), SP SP+6 RETSNote 1 3+S µPD753104 PD753104 MBE, RBE, 0, 0 (SP+1) PC11­0 (SP) (SP+3) (SP+2) SP SP+4 then skip unconditionally Unconditional µPD753106 PD753106, 753108 MBE, RBE, 0, PC12 (SP+1) PC11­0 (SP) (SP+3) (SP+2) SP SP+4 then skip unconditionally µPD753104 PD753104 0, 0, 0, 0 (SP+1) PC11­0 (SP) (SP+3) (SP+2) ×, ×, MBE, RBE (SP+4) SP SP+6 then skip unconditionally µPD753106 PD753106, 753108 0, 0, 0, PC12 (SP+1) PC11­0 (SP) (SP+3) (SP+2) ×, ×, MBE, RBE (SP+4) SP SP+4 then skip unconditionally Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 56 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 Instruction Group Subroutine stack control Operand RETINote 1 Number of Bytes Number of Machine Cycles 1 Mnemonic 3 Addressing Area Operation Skip Condition µPD753104 PD753104 MBE, RBE, 0, 0 (SP+1) PC11­0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 µPD753106 PD753106, 753108 MBE, RBE, 0, PC12 (SP+1) PC11­0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 µPD753104 PD753104 0, 0, 0, 0 (SP+1) PC11­0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 µPD753106 PD753106, 753108 0, 0, 0, PC12 (SP+1) PC11­0 (SP) (SP+3) (SP+2) PSW (SP+4) (SP+5), SP SP+6 rp 1 1 (SP­1) (SP­2) rp, SP SP­2 BS 2 2 (SP­1) MBS, (SP­2) RBS, SP SP­2 rp 1 1 rp (SP+1) (SP), SP SP+2 BS 2 2 MBS (SP+1), RBS (SP), SP SP+2 2 2 IME (IPS.3) 1 2 2 IE××× 1 2 2 IME (IPS.3) 0 IE××× 2 2 IE××× 0 A, PORTn 2 2 A PORTn XA, PORTn 2 2 XA PORTn+1, PORTn PORTn, A 2 2 PORTn A PORTn, XA 2 2 PORTn+1, PORTn XA HALT 2 2 Set HALT Mode (PCC.2 1) STOP 2 2 Set STOP Mode (PCC.3 1) NOP 1 1 No Operation RBn 2 2 RBS n (n = 0 to 3) MBn 2 2 MBS n (n = 0, 1, 15) PUSH POP Interrupt control EI IE××× DI Input/output IN Note 2 OUTNote 2 CPU control Special SEL Notes 1. (n = 0 to 3, 5, 6, 8, 9) (n = 8) (n = 3, 5, 6, 8, 9) (n = 8) The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1, and MBS must be set to 15. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 57 µPD753104 PD753104, 753106, 753108 Instruction Group Mnemonic GETINotes 1, 2 Special Operand taddr Number of Bytes Number of Machine Cycles 1 3 Operation µPD753104 PD753104 · When TBR instruction PC11­0 (taddr) 3­0 + (taddr+1) Addressing Area Skip Condition *10 ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ ­­­­­­­­­­­­­ · When TCALL instruction (SP­4) (SP­1) (SP­2) PC11­0 (SP­3) MBE, RBE, 0, 0 PC11­0 (taddr) 3­0 + (taddr+1) SP SP­4 ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ ­­­­­­­­­­­­­ · When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. Depending on the reference instruction µPD753106 PD753106, 753108 · When TBR instruction PC12­0 (taddr) 4­0 + (taddr+1) ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ ­­­­­­­­­­­­­ · When TCALL instruction (SP­4) (SP­1) (SP­2) PC11­0 (SP­3) MBE, RBE, 0, PC12 PC12­0 (taddr) 4­0 + (taddr+1) SP SP­4 ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ ­­­­­­­­­­­­­ · When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 µPD753104 PD753104 · When TBR instruction PC11­0 (taddr) 3­0 + (taddr+1) ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ ­­­­ 4 *10 ­­­­­­­­­­­­­ · When TCALL instruction (SP­6) (SP­3) (SP­4) PC11­0 (SP­5) 0, 0, 0, 0 (SP­2) ×, ×, MBE, RBE PC11­0 (taddr) 3­0 + (taddr+1) SP SP­6 ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ ­­­­ 3 · When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. 3 ­­­­­­­­­­­­­ µPD753106 PD753106, 753108 · When TBR instruction PC12­0 (taddr) 4­0 + (taddr+1) ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ ­­­­ 4 3 Depending on the reference instruction ­­­­­­­­­­­­­ · When TCALL instruction (SP­6) (SP­3) (SP­4) PC11­0 (SP­5) 0, 0, 0, PC12 (SP­2) ×, ×, MBE, RBE PC12­0 (taddr) 4­0 + (taddr+1) SP SP­6 ­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­­ ­­­­ Notes 1. Depending on the reference instruction · When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed. ­­­­­­­­­­­­­ Depending on the reference instruction The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. 2. The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 58 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 12. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (T A = 25°C) Parameter Symbol Test Conditions Rating Unit ­0.3 to +7.0 V Supply voltage V DD Input voltage V I1 Except port 5 ­0.3 to V DD + 0.3 V V I2 Port 5 On-chip pull-up resistor ­0.3 to VDD + 0.3 V When N-ch open-drain ­0.3 to +14 V ­0.3 to VDD + 0.3 V Per pin ­10 mA Total of all pins ­30 mA Per pin 30 mA Total of all pins 220 Output voltage VO Output current, high IOH Output current, low IOL ­40 to +85 Operating ambient temperature TA Storage temperature Tstg Note mA Note °C ­65 to +150 °C When LCD is driven in normal mode: TA = ­10 to +85°C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. CAPACITANCE (TA = 25°C, VDD = 0 V) Parameter Input capacitance Symbol CIN Output capacitance COUT I/O capacitance Test Conditions Unmeasured pins returned to 0 V. CIO Data Sheet U10086EJ5V1DS U10086EJ5V1DS TYP. MAX. Unit 15 pF 15 pF 15 f = 1 MHz MIN. pF 59 µPD753104 PD753104, 753106, 753108 MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = ­40 to +85°C, VDD = 1.8 to 5.5 V) Resonator Recommended Constant Ceramic resonator frequency (fx) C1 resonator C2 External 6.0Note 2 MHz 4 ms 6.0Note 2 MHz ms lation voltage range MIN. 1.0 Note 1 Oscillation VDD = 4.5 to 5.5 V 10 V DD = 1.8 to 5.5 V 30 1.0 X2 frequency (fx) 6.0Note 2 MHz 83.3 500 ns Note 1 X1 input high-/low-level width (tXH, t XL) Notes 1. Unit After VDD reaches oscil- X1 input X1 MAX. stabilization time Note 3 VDD clock Oscillation frequency (fx) C1 TYP. Note 1 Oscillation X2 X1 MIN. 1.0 stabilization time Note 3 C2 VDD Crystal Test Conditions Oscillation X2 X1 Parameter The oscillation frequency and X1 input frequency indicate only oscillator characteristics. Refer to the AC Characteristics for instruction execution time. 2. When the oscillation frequency is 4.19 MHz < fx 6.0 MHz at 1.8 V V DD < 2.7 V, setting the processor clock control register (PCC) to 0011 results in 1 machine cycle time being less than the required 0.95 µ s. Therefore, set PCC to a value other than 0011. 3. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD or releasing the STOP mode. Caution When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. · Keep the wiring length as short as possible. · Do not cross the wiring with other signal lines. · Do not route the wiring near a signal line through which a high fluctuating current flows. · Always make the ground point of the oscillator capacitor the same potential as VDD. · Do not ground the capacitor to a ground pattern through which a high current flows. · Do not fetch signals from the oscillator. 60 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (TA = ­40 to +85°C, VDD = 1.8 to 5.5 V) Resonator Recommended Constant Crystal XT1 Parameter TYP. MAX. Unit 32 R frequency (fXT) C4 C3 MIN. 32.768 35 kHz 1.0 2 s Oscillation XT2 resonator Oscillation VDD = 4.5 to 5.5 V stabilization timeNote 2 VDD = 1.8 to 5.5 V VDD External Note 1 XT1 input frequency XT1 10 32 100 kHz 5 15 µs XT2 (fXT) clock Test Conditions Note 1 XT1 input high-/lowlevel width (tXTH, tXTL) Notes 1. 2. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. The oscillation stabilization time is necessary for oscillation to stabilize after applying VDD. Caution When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. · Keep the wiring length as short as possible. · Do not cross the wiring with other signal lines. · Do not route the wiring near a signal line through which a high fluctuating current flows. · Always make the ground point of the oscillator capacitor the same potential as VDD. · Do not ground the capacitor to a ground pattern through which a high current flows. · Do not fetch signals from the oscillator. The subsystem clock oscillator is designed as a low-amplification circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant of the subsystem clock, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 61 µPD753104 PD753104, 753106, 753108 RECOMMENDED OSCILLATOR CONSTANT Ceramic Resonator (TA = ­20 to +85°C) Manufacturer Product Name Frequency (MHz) Oscillator Constant (pF) C1 C2 Oscillation Voltage Range (VDD) MIN. Kyocera KBR-1000F/Y KBR-1000F/Y 1.0 100 100 1.8 Corporation KBR-2.0MS 2.0 82 82 4.19 33 33 MAX. 2.2 KBR-4.19MSA 19MSA Remarks 1.8 KBR-4.19MKS 19MKS - PBRC 4.19A 33 PBRC 4.19B KBR-6.0MSA - 33 KBR-6.0MKS - On-chip capacitor product 33 33 PBRC 6.00B On-chip capacitor product - - - PBRC 6.00A - 33 - 6.0 5.5 - On-chip capacitor product 33 - - - On-chip capacitor product Ceramic Resonator (TA = ­40 to +85°C) Manufacturer Product Name Frequency (MHz) Oscillator Constant (pF) C1 TDK CCR1000K2 CCR1000K2 1.0 CCR2.0MC33 0MC33 2.0 FCR4.19MC5 19MC5 150 C2 MIN. 2.0 - Remarks MAX. 4.19 - 150 Oscillation Voltage Range (VDD) 5.5 1.8 - On-chip capacitor product CCR4.19MC3 19MC3 FCR6.0MC5 6.0 2.0 CCR6.0MC3 2.2 Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. 62 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 Ceramic Resonator Manufacturer Product Name Frequency (MHz) Oscillator Constant (pF) C1 Murata Mfg. Co., Ltd. Oscillation Voltage Range (VDD) C2 MIN. CSB1000J CSB1000J 1.0 100 100 2.4 CSA2.00MG 2.0 30 30 MAX. 1.8 CSTCC2M00G56-R0 CSTCC2M00G56-R0 - 5.5 - 3.0 30 CSTCC3M00G56-R0 CSTCC3M00G56-R0 30 - TA = ­20 to +80°C TA = ­20 to +80°C - TA = ­40 to +85°C, On-chip capacitor product CSTLS3M00G56-B0 CSTLS3M00G56-B0 CSTCR4M00G55-R0 CSTCR4M00G55-R0 TA = ­20 to +80°C Rd = 5.6 kNote TA = ­40 to +85°C, On-chip capacitor product CSTLS2M00G56-B0 CSTLS2M00G56-B0 CSA3.00MG Remarks 4.0 CSTLS4M00G56-B0 CSTLS4M00G56-B0 CSA4.19MG 4.19 30 CSTCR4M19G55-R0 CSTCR4M19G55-R0 30 - TA = ­20 to +80°C - TA = ­40 to +85°C, On-chip capacitor product CSTLS4M19G56-B0 CSTLS4M19G56-B0 CSA5.00MG 5.0 30 30 2.2 CSA5.00MGU 00MGU 1.8 CSTCR5M00G53-R0 CSTCR5M00G53-R0 - - TA = ­40 to +85°C, On-chip capacitor product CSTLS5M00G53-B0 CSTLS5M00G53-B0 CSA6.00MG 6.0 30 30 2.5 CSA6.00MGU 00MGU TA = ­20 to +80°C 1.8 CSTCR6M00G53-R0 CSTCR6M00G53-R0 - - TA = ­40 to +85°C, On-chip capacitor product CSTLS6M00G53-B0 CSTLS6M00G53-B0 Note TA = ­20 to +80°C If using the CSB1000J CSB1000J (1.0 MHz) ceramic resonator manufactured by Murata Mfg. Co., Ltd., a limiting resistor (Rd = 5.6 k) is required (see figure below). A limiting resistor is not required if using the other recommended resonators. Recommended Main System Clock Circuit Example (using Murata Mfg. Co., Ltd. CSB1000J CSB1000J) X1 X2 CSB1000J CSB1000J C1 Rd C2 VDD Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. Data Sheet U10086EJ5V1DS U10086EJ5V1DS 63 µPD753104 PD753104, 753106, 753108 Crystal Resonator Manufacturer Product Name Frequency (MHz) Oscillator Constant (pF) C1 Kinseki HC-49/U HC-49/U 2.0 15 C2 15 Oscillation Voltage Range (VDD) MIN. Remarks MAX. 1.8 5.5 6.0 2.5 5.5 4.19 1.8 5.5 6.0 2.5 TA = ­20 to +70°C 5.5 4.19 HC-49/U-S HC-49/U-S TA = ­10 to +70°C Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. 64 Data Sheet U10086EJ5V1DS U10086EJ5V1DS µPD753104 PD753104, 753106, 753108 DC CHARACTERISTICS (TA = ­40 to +85°C, VDD = 1.8 to 5.5 V) Parameter IOL MAX. Unit Per pin 15 mA Total of all pins Output current, low Symbol Test Conditions MIN. TYP. 150 mA 0.9VDD V DD V 2.7 VDD 5.5 V 0.8VDD V DD V 0.9VDD V DD V On-chip pull-up 2.7 VDD 5.5 V 0.7VDD V DD V 1.8 VDD < 2.7 V 0.9VDD V DD V 2.7 VDD 5.5 V 0.7VDD 13 V open-drain 1.8 VDD < 2.7 V 0.9VDD 13 V VDD­0.1 V DD V 2.7 VDD 5.5 V 0 0.3VDD V 1.8 VDD < 2.7 V 0 0.1VDD V 2.7 VDD 5.5 V 0 0.2VDD V 1.8 VDD < 2.7 V 0 0.1VDD V 0 0.1 V Ports 2, 3, 8, 9 Ports 0, 1, 6, RESET Port 5 VIH4 Input voltage, low V When N-ch VIH3 V DD resistor VIH2 0.7VDD 1.8 VDD < 2.7 V VIH1 2.7 VDD 5.5 V 1.8 VDD < 2.7 V Input voltage, high X1, XT1 VIL1 Ports 2, 3, 5, 8, 9 VIL2 Ports 0, 1, 6, RESET VIL3 X1, XT1 Output voltage, high VOH SCK, SO, ports 2, 3, 6, 8, 9 IOH = ­1.0 mA Output voltage, low VOL1 SCK, SO, ports 2, 3, 5, 6, 8, 9 VDD­0.5 IOL = 15 mA, V 0.2 2.0 V 0.4 V 0.2VDD V VDD = 4.5 to 5.5 V IOL = 1.6 mA VOL2 SB0, SB1 N-ch open-drain pull-up resistor 1 k Input leakage ILIH1 VIN = V DD Pins other than X1, XT1 3 µA current, high ILIH2 X1, XT1 20 µA ILIH3 VIN = 13 V Port 5 (When N-ch open-drain) 20 µA Input leaka