PD753012A PD753017A PD75316B PD753017 U11282E PD753016A PD75P3018A - Datasheet Archive

 

MOS INTEGRATED CIRCUIT µPD753012A, 753016A, 753017A 4-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD753017A is

 

DATA SHEET MOS INTEGRATED CIRCUIT µPD753012A PD753012A, 753016A, 753017A 4-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION The µPD753017A PD753017A is one of the 75XL series 4-bit single-chip microcontroller chips and has a data processing capability comparable to that of an 8-bit microcontroller. It has an on-chip LCD controller/driver with a larger ROM capacity and extended CPU functions compared with the conventional µPD75316B PD75316B, and can provide high-speed operation at a low supply voltage of 1.8 V. It can be supplied in a small plastic TQFP package (12 × 12 mm) and is suitable for small sets using LCD panels. Detailed descriptions of functions are provided in the following document. Be sure to read the document before designing. µPD753017 PD753017 User's Manual : U11282E U11282E FEATURES · Low voltage operation: VDD = 1.8 to 5.5 V · Can be driven by two 1.5 V batteries · Capable of high-speed operation and variable instruction execution time for power saving · 0.95, 1.91, 3.81, 15.3 µs (at 4.19 MHz operation) · On-chip memory · 0.67, 1.33, 2.67, 10.7 µs (at 6.0 MHz operation) · Program memory (ROM): 12288 × 8 bits (µPD753012A PD753012A) · 122 µs (at 32.768 kHz operation) 16384 × 8 bits (µPD753016A PD753016A) · Internal programmable LCD controller/driver 24576 × 8 bits (µPD753017A PD753017A) · Small plastic TQFP (12 × 12 mm) · Data memory (RAM): · Suitable for small sets such as cameras 1024 × 4 bits · One-time PROM: µPD75P3018A PD75P3018A APPLICATION Remote controllers, camera-integrated VCRs, cameras, gas meters, etc. In this document, unless otherwise specified, the description is made based on µPD753017A PD753017A as typical product. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U11662EJ2V1DS00 U11662EJ2V1DS00 (2nd edition) Date Published August 2000 N CP(K) Printed in Japan The mark shows major revised points. © 1996, 2000 µPD753012A PD753012A, 753016A, 753017A ORDERING INFORMATION Part number Package µPD753012AGC-XXX-3B9 PD753012AGC-XXX-3B9 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm) µPD753012AGC-XXX-8BT PD753012AGC-XXX-8BT 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm) µPD753012AGK-XXX-BE9 PD753012AGK-XXX-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm) µPD753012AGK-XXX-9EU PD753012AGK-XXX-9EU 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.00 mm) µPD753016AGC-XXX-3B9 PD753016AGC-XXX-3B9 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm) µPD753016AGC-XXX-8BT PD753016AGC-XXX-8BT 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm) µPD753016AGK-XXX-BE9 PD753016AGK-XXX-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm) µPD753016AGK-XXX-9EU PD753016AGK-XXX-9EU 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.00 mm) µPD753017AGC-XXX-3B9 PD753017AGC-XXX-3B9 80-pin plastic QFP (14 × 14 mm, resin thickness 2.7 mm) µPD753017AGC-XXX-8BT PD753017AGC-XXX-8BT 80-pin plastic QFP (14 × 14 mm, resin thickness 1.4 mm) µPD753017AGK-XXX-BE9 PD753017AGK-XXX-BE9 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.05 mm) µPD753017AGK-XXX-9EU PD753017AGK-XXX-9EU 80-pin plastic TQFP (fine pitch) (12 × 12 mm, resin thickness 1.00 mm) Remark 2 XXX indicates ROM code suffix. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A FUNCTION OUTLINE Parameter Function · 0.95, 1.91, 3.81, 15.3 µs (main system clock: at 4.19 MHz operation) · 0.67, 1.33, 2.67, 10.7 µs (main system clock: at 6.0 MHz operation) · 122 µs (subsystem clock: at 32.768 kHz operation) Instruction execution time Internal memory ROM 12288 × 8 bits (µPD753012A PD753012A) 16384 × 8 bits (µPD753016A PD753016A) 24576 × 8 bits (µPD753017A PD753017A) RAM 1024 × 4 bits General purpose register · 4-bit operation: 8 × 4 banks · 8-bit operation: 4 × 4 banks Input/ output port CMOS input 8 On-chip pull-up resistors can be specified by using CMOS input/output 16 software: 23 CMOS output 8 Also used for segment pins N-ch open-drain input/output 8 Withstands 13 V, on-chip pull-up resistors can be specified by using mask option Total 40 LCD controller/driver · Segment number selection · Display mode selection : 24/28/32 segments (can be changed to CMOS output port in 4 time-unit; max. 8) : Static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias), 1/4 duty (1/3 bias) On-chip split resistor for LCD drive can be specified by using mask option Timer 5 channels · 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter, carrier generator, timer with gate) · Basic interval timer/watchdog timer: 1 channel · Watch timer: 1 channel Serial interface · 3-wire serial I/O mode . MSB or LSB can be selected for transferring first bit · 2-wire serial I/O mode · SBI mode Bit sequential buffer 16 bits Clock output (PCL) · , 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation) · , 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation) Buzzer output (BUZ) · 2, 4, 32 kHz Vectored interrupt External: 3, Internal: 5 Test input External: 1, Internal: 1 System clock oscillator · Ceramic or crystal oscillator for main system clock oscillation · Crystal oscillator for subsystem clock oscillation Standby function STOP/HALT mode Power supply voltage VDD = 1.8 to 5.5 V Package · 80-pin plastic QFP (14 × 14 mm) · 80-pin plastic TQFP (fine pitch) (12 × 12 mm) (main system clock: at 4.19 MHz operation or subsystem clock: at 32.768 kHz operation) · 2.93, 5.86, 46.9 kHz (main system clock: at 6.0 MHz operation) Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 3 µPD753012A PD753012A, 753016A, 753017A CONTENTS 1. PIN CONFIGURATION (Top View) . 6 2. BLOCK DIAGRAM . 8 3. PIN 3.1 3.2 3.3 3.4 FUNCTION . 9 Port Pins . 9 Non-port Pins . 11 Pin Input/Output Circuits . 13 Recommended Connection for Unused Pins . 15 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE . 16 4.1 Differences between Mk I Mode and Mk II Mode . 16 4.2 Setting Method of Stack Bank Select Register (SBS) . 17 5. MEMORY CONFIGURATION .18 6. PERIPHERAL HARDWARE FUNCTIONS . 23 6.1 Digital Input/Output Ports . 23 6.2 Clock Generator .24 6.3 Subsystem Clock Oscillator Control Functions . 25 6.4 Clock Output Circuit .26 6.5 Basic Interval Timer/Watchdog Timer . 27 6.6 Watch Timer .28 6.7 Timer/Event Counter .29 6.8 Serial Interface . 33 6.9 LCD Controller/Driver . 35 6.10 Bit Sequential Buffer . 37 7. INTERRUPT FUNCTION AND TEST FUNCTION . 38 8. STANDBY FUNCTION .40 9. RESET FUNCTION . 41 10. MASK OPTION . 44 11. INSTRUCTION SET . 45 12. ELECTRICAL SPECIFICATIONS . 57 13. CHARACTERISTICS CURVES (REFERENCE VALUES) . 71 14. PACKAGE DRAWINGS . 73 15. RECOMMENDED SOLDERING CONDITIONS . 77 4 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A APPENDIX A. µPD75316B PD75316B, 753017A AND 75P3018A 75P3018A FUNCTION LIST . 79 APPENDIX B. DEVELOPMENT TOOLS . 81 APPENDIX C. RELATED DOCUMENTS . 85 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 5 µPD753012A PD753012A, 753016A, 753017A 1. PIN CONFIGURATION (Top View) · 80-pin plastic QFP (14 × 14 mm) µPD753012AGC-XXX-3B9 PD753012AGC-XXX-3B9, 753012AGC-XXX-8BT 753012AGC-XXX-8BT, 753016AGC-XXX-3B9 753016AGC-XXX-3B9, 753016AGC-XXX-8BT 753016AGC-XXX-8BT µPD753017AGC-XXX-3B9 PD753017AGC-XXX-3B9, 753017AGC-XXX-8BT 753017AGC-XXX-8BT · 80-pin plastic TQFP (fine pitch) (12 × 12 mm) µPD753012AGK-XXX-BE9 PD753012AGK-XXX-BE9, 753012AGK-XXX-9EU 753012AGK-XXX-9EU, 753016AGK-XXX-BE9 753016AGK-XXX-BE9, 753016AGK-XXX-9EU 753016AGK-XXX-9EU 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 2 3 4 5 6 7 8 9 10 11 12 13 14 59 58 57 56 55 54 53 52 51 50 49 48 47 15 16 17 18 19 20 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 COM0 COM1 COM2 S29/BP5 S29/BP5 S30/BP6 S30/BP6 S31/BP7 S31/BP7 1 COM3 BIAS VLC0 VLC1 VLC2 P40 P41 P42 P43 VSS P50 P51 P52 P53 P00/INT4 P00/INT4 P01/SCK P01/SCK P02/SO/SB0 P02/SO/SB0 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24/BP0 S24/BP0 S25/BP1 S25/BP1 S26/BP2 S26/BP2 S27/BP3 S27/BP3 S28/BP4 S28/BP4 S7 S6 S5 S4 S3 S2 S1 S0 RESET P73/KR7 P73/KR7 P72/KR6 P72/KR6 P71/KR5 P71/KR5 P70/KR4 P70/KR4 P63/KR3 P63/KR3 P62/KR2 P62/KR2 P61/KR1 P61/KR1 S11 S10 S9 S8 µPD753017AGK-XXX-BE9 PD753017AGK-XXX-BE9, 753017AGK-XXX-9EU 753017AGK-XXX-9EU Note Connect the IC (Internally Connected) pin directly to VDD. 6 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 P60/KR0 P60/KR0 X2 X1 ICNote XT2 XT1 VDD P33 P32 P31/SYNC P31/SYNC P30/LCDCL P30/LCDCL P23/BUZ P23/BUZ P22/PCL/PTO2 P22/PCL/PTO2 P21/PTO1 P21/PTO1 P20/PTO0 P20/PTO0 P13/TI0 P13/TI0 P12/INT2/TI1/TI2 P12/INT2/TI1/TI2 P11/INT1 P11/INT1 P10/INT0 P10/INT0 P03/SI/SB1 P03/SI/SB1 µPD753012A PD753012A, 753016A, 753017A Pin Identification BIAS : LCD Power Supply Bias Control PCL BP0-BP7 : Bit Port PTO0-PTO2 : Programmable Timer Output 0-2 : Programmable Clock BUZ : Buzzer Clock RESET : Reset Input COM0-COM3 : Common Output 0-3 S0-S31 S0-S31 : Segment Output 0-31 IC : Internally Connected SB0, SB1 INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4 : Serial Bus 0, 1 SCK : Serial Clock INT2 : External Test Input 2 SI : Serial Input KR0-KR7 : Key Return SO : Serial Output LCDCL : LCD Clock SYNC : LCD Synchronization P00-P03 P00-P03 : Port 0 TI0-TI2 : Timer Input 0-2 P10-P13 P10-P13 : Port 1 VDD : Positive Power Supply P20-P23 P20-P23 : Port 2 VLC0-VLC2 : LCD Power Supply 0-2 P30-P33 P30-P33 : Port 3 VSS : Ground P40-P43 P40-P43 : Port 4 X1, X2 : Main System Clock Oscillation 1, 2 P50-P53 P50-P53 : Port 5 XT1, XT2 : Subsystem Clock Oscillation 1, 2 P60-P63 P60-P63 : Port 6 P70-P73 P70-P73 : Port 7 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 7 INTT1 TI1/TI2/ P12/INT2 P12/INT2 TIMER/EVENT COUNTER #1 PTO2/P22/PCL PTO2/P22/PCL TOUT0 TIMER/EVENT COUNTER #2 INTT2 BASIC INTERVAL /WATCHDOG TIMER P10-P13 P10-P13 PORT2 4 P20-P23 P20-P23 PORT3 4 P30-P33 P30-P33 4 P40-P43 P40-P43 PORT5 4 P50-P53 P50-P53 PORT6 4 P60-P63 P60-P63 PORT7 4 P70-P73 P70-P73 24 S0-S23 S0-S23 8 INTT0 4 PORT4 PTO0/P20 PTO0/P20 P00-P03 P00-P03 S24/BP0S31/BP7 S24/BP0S31/BP7 4 COM0-COM3 3 VLC0-VLC2 SP (8) TIMER/EVENT COUNTER #0 TI0/P13 TI0/P13 4 PORT1 PROGRAM COUNTERNote 1 INTBT CY ALU SBS BANK TOUT0 WATCH TIMER BUZ/P23 BUZ/P23 GENERAL REG. INTW SI/SB1/P03 SI/SB1/P03 fLCD CLOCKED SERIAL INTERFACE SO/SB0/P02 SO/SB0/P02 ROMNote 2 PROGRAM MEMORY DECODE AND CONTROL RAM DATA MEMORY 1024 X 4 BITS SCK/P01 SCK/P01 INTCSI TOUT0 INT0/P10 INT0/P10 INT1/P11 INT1/P11 LCD CONTROLLER /DRIVER INTERRUPT CONTROL INT2/P12 INT2/P12 INT4/P00 INT4/P00 CPU CLOCK fx/2N KR0/P60- KR0/P60- 8 KR7/P73 KR7/P73 BIT SEQ. BUFFER (16) CLOCK OUTPUT CONTROL PCL/PTO2/P22 PCL/PTO2/P22 Notes 1. 2. CLOCK DIVIDER SYSTEM CLOCK GENERATOR SUB MAIN XT1 XT2 X1 X2 fLCD STAND BY CONTROL SYNC/P31 SYNC/P31 IC VDD VSS RESET µPD753012A PD753012A and 753016A have a 14-bit configuration, and µPD753017A PD753017A has a 15-bit configuration. Capacity of the ROM depends on the product. BIAS LCDCL/P30 LCDCL/P30 µPD753012A PD753012A, 753016A, 753017A Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 PORT0 2. BLOCK DIAGRAM 8 PTO1/P21 PTO1/P21 µPD753012A PD753012A, 753016A, 753017A 3. PIN FUNCTION 3.1 Port Pins (1/2) P00 I/O Alternate Function Input Pin Name INT4 P01 SCK P02 SO/SB0 P03 Function 4-bit input port (PORT0). For P01 to P03, connection of on-chip pullup resistors can be specified by software in 3-bit units. 8-bit I/O Circuit After Reset I/O Type Note 1 No Input SI/SB1 P10 Input INT0 P11 INT1 P12 TI1/TI2/INT2 P13 TI0 P20 I/O PTO0 P21 PTO1 P22 -A -B -C 4-bit input port (PORT1). Connection of on-chip pull-up resistors can be specified by software in 4-bit units. Only P10/INT0 P10/INT0 can select noise elimination circuit. No input -C 4-bit input/output port (PORT2). Connection of on-chip pull-up resistors can be specified by software in 4-bit units. No Input E-B Programmable 4-bit input/output port (PORT3). This port can be specified for input/output bit-wise. Connection of on-chip pull-up resistor can be specified by software in 4-bit units. No Input E-B Yes High level (when pullup resistors are provided) or high impedance M-D High level (when pullup resistors are provided) or high impedance M-D PCL/PTO2 P23 BUZ P30 I/O LCDCL P31 SYNC P32 ­ P33 ­ P40-P43 P40-P43 Note 2 I/O ­ N-ch open-drain 4-bit input/output port (PORT4). A pull-up resistor can be contained bit-wise (mask option). Withstand voltage is 13 V in open-drain mode. P50-P53 P50-P53 Note 2 I/O ­ N-ch open-drain 4-bit input/output port (PORT5). A pull-up resistor can be contained bit-wise (mask option). Withstand voltage is 13 V in open-drain mode. Notes 1. 2. Circuit types enclosed in brackets indicate the Schmitt trigger input. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low level input leakage current increases when input or bit manipulation instruction is executed. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 9 µPD753012A PD753012A, 753016A, 753017A 3.1 Port Pins (2/2) P60 I/O Alternate Function I/O Pin Name KR0 P61 KR1 P62 KR2 P63 KR3 P70 I/O KR4 P71 KR5 P72 Programmable 4-bit input/output port (PORT6). This port can be specified for input/output bit-wise. Connection of on-chip pull-up resistors can be specified by software in 4-bit units. Yes -A Input 4-bit input/output port (PORT7). Connection of on-chip pull-up resistors can be specified by software in 4-bit units. Input -A Note 2 H-A KR6 P73 8-bit I/O Circuit After Reset I/O TypeNote 1 Function KR7 BP0 Output S24 BP1 S25 BP2 S26 BP3 No 1-bit output port (BIT PORT). Also used for segment output pins. S27 BP4 Output S28 BP5 S29 BP6 S30 BP7 S31 Notes 1. 2. Circuit types enclosed in brackets indicate the Schmitt trigger input. BP0 through BP7 select VLC1 as an input source. However, the output levels change depending on the external circuit of BP0 through BP7 and VLC1. Example Because BP0 through BP7 are mutually connected inside the µPD753017A PD753017A, the output levels of BP0 through BP7 are determined by R1, R2, and R 3. VDD µ PD753017A PD753017A R2 BP0 ON VLC1 BP1 R1 ON R3 10 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A 3.2 Non-port Pins (1/2) TI0 I/O Alternate Function Input Pin Name P13 TI1 P12/INT2 P12/INT2 After Reset I/O Circuit Type Note 1 Inputs external event pulses to the timer/event counter. Input -C Timer/event counter output Input E-B Input -A Function TI2 PTO0 Output P20 PTO1 P21 PTO2 P22/PCL P22/PCL PCL P22/PTO2 P22/PTO2 BUZ P23 Optional frequency output (for buzzer output or system clock trimming) P01 Serial clock input/output SO/SB0 P02 Serial data output Serial data bus input/output -B SI/SB1 P03 Serial data input Serial data bus input/output -C SCK I/O Clock output INT4 Input P00 Edge detection vectored interrupt input (both rising edge and falling edge detection) Input INT0 Input P10 Noise elimination circuit/asynchronous selection Input -C P11 Edge detection vectored interrupt input (detection edge can be selected) INT0/P10 INT0/P10 can select noise elimination circuit. Rising edge detection testable input Asynchronous Input -C INT1 Asynchronous INT2 Input P12/TI1/TI2 P12/TI1/TI2 KR0-KR3 Input P60-P63 P60-P63 Falling edge detection testable input Input -A KR4-KR7 Input P70-P73 P70-P73 Falling edge detection testable input Input -A S0-S23 S0-S23 Output ­ Segment signal output Note 2 G-A S24-S31 S24-S31 Output BP0-BP7 Segment signal output Note 2 H-A COM0-COM3 Output ­ Common signal output Note 2 G-B ­ ­ LCD drive power On-chip split resistor is enable (mask option). ­ ­ BIAS Output ­ Output for external split resistor disconnect Note 3 ­ LCDCL Note 4 Output P30 Clock output for externally expanded driver Input E-B SYNC Note 4 Output P31 Clock output for externally expanded driver synchronization Input E-B V LC0 -VLC2 Notes 1. Circuit types enclosed in brackets indicate the Schmitt trigger input. 2. Each display output selects the following VLCX as input source. 3. When a split resistor is contained . Low level S0-S31 S0-S31: VLC1, COM0-COM2: VLC2, COM3: VLC0 When no split resistor is contained . High impedance 4. These pins are provided for future system expansion. At present, these pins are used only as pins P30 and P31. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 11 µPD753012A PD753012A, 753016A, 753017A 3.2 Non-port Pins (2/2) I/O Alternate Function Function After Reset I/O Circuit Type Note X1 Input ­ Crystal/ceramic connection pin for the mainsystem clock oscillation. When inputting the external clock, input the external clock to pin X1, and the inverted phase of the external clock to pin X2. ­ ­ X2 ­ ­ XT1 Input ­ Crystal connection pin for the subsystem clock oscillation. When the external clock is used, input the external clock to pin XT1, and the inverted phase of the external clock to pin XT2. Pin XT1 can be used as a 1-bit input (test) pin. ­ ­ XT2 ­ Input ­ System reset input (low level active) ­ IC ­ ­ Internally connected. Connect directly to VDD. ­ ­ V DD ­ ­ Positive power supply ­ ­ V SS ­ ­ GND ­ ­ Pin Name RESET Note 12 Circuit types enclosed in brackets indicate the Schmitt trigger input. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A 3.3 Pin Input/Output Circuits The µPD753017A PD753017A pin input/output circuits are shown schematically. TYPE A TYPE D VDD VDD data P-ch OUT P-ch IN N-ch output disable N-ch Push-pull output that can be placed in output high impedance (both P-ch and N-ch off). CMOS standard input buffer TYPE E-B TYPE B VDD P.U.R. P.U.R. enable IN P-ch data Type D IN/OUT output disable Type A Schmitt trigger input with hysteresis characteristics P.U.R. : Pull-Up Resistor TYPE F-A TYPE B-C VDD VDD P.U.R. P.U.R. enable P.U.R. P-ch P.U.R. enable P-ch data output disable IN/OUT Type D IN Type B P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 13 µPD753012A PD753012A, 753016A, 753017A TYPE F-B TYPE H-A VDD P.U.R. P.U.R. enable P-ch output disable (P) SEG data VDD OUT TYPE G-A P-ch IN/OUT data output disable Bit Port data N-ch output disable output disable (N) TYPE D P.U.R. : Pull-Up Resistor TYPE G-A TYPE M-C VDD VLC0 P.U.R. VLC1 P.U.R. enable P-ch N-ch P-ch IN/OUT OUT SEG data data N-ch output disable N-ch VLC2 N-ch P.U.R. : Pull-Up Resistor TYPE G-B TYPE M-D VDD P.U.R. (Mask Option) IN/OUT VLC0 data VLC1 P-ch output disable N-ch OUT input instruction VDD P-ch Note COM or SEG data P.U.R. N-ch P-ch Voltage limitation circuit (+13 V withstand voltage) VLC2 N-ch Note 14 N-ch (+13 V withstand voltage) The pull-up resistor operates only when an input instruction is executed (current flows from VDD to the pin when the pin is low). Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A 3.4 Recommended Connection for Unused Pins Table 3-1. List of Recommended Connection for Unused Pins Pin Recommended Connection P00/INT4 P00/INT4 Connect to VSS or V DD P01/SCK P01/SCK Connect to VSS or VDD via a resistor individually P02/SO/SB0 P02/SO/SB0 P03/SI/SB1 P03/SI/SB1 Connect to VSS P10/INT0 P10/INT0, P11/INT1 P11/INT1 Connect to VSS or V DD P12/TI1/TI2/INT2 P12/TI1/TI2/INT2 P13/TI0 P13/TI0 P20/PTO0 P20/PTO0 Input: Connect to VSS or VDD via a resistor individually P21/PTO1 P21/PTO1 Output: Leave open P22/PTO2/PCL P22/PTO2/PCL P23/BUZ P23/BUZ P30/LCDCL P30/LCDCL P31/SYNC P31/SYNC P32 P33 P40-P43 P40-P43 Input: Connect to VSS P50-P53 P50-P53 Output: Connect to VSS (do not connect a pull-up resistor of mask option) P60/KR0-P63/KR3 P60/KR0-P63/KR3 Input: Connect to VSS or VDD via a resistor individually P70/KR4-P73/KR7 P70/KR4-P73/KR7 Output: Leave open S0-S23 S0-S23 Leave open S24/BP0-S31/BP7 S24/BP0-S31/BP7 COM0-COM3 VLC0-VLC2 Connect to VSS BIAS Only if all of VLC0-V LC2 are unused, connect to VSS. In other cases, leave open. XT1 Connect to VSS XT2Note Leave open IC Connect to VDD directly Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the internal feedback resistor). Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 15 µPD753012A PD753012A, 753016A, 753017A 4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE 4.1 Differences between Mk I Mode and Mk II Mode The CPU of µPD753017A PD753017A has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by the bit 3 of the stack bank select register (SBS). · Mk I mode: Upward compatible with µPD75316B PD75316B. Can be used in the 75XL CPU with a ROM capacity of up to 16K bytes. · Mk II mode: Incompatible with µPD75316B PD75316B. Can be used in all the 75XL CPU's including those products whose ROM capacity is more than 16K bytes. Table 4-1. Differences between Mk I Mode and Mk II Mode Mk I Mode Mk II Mode Program memory (bytes) · µPD753012A PD753012A : 12288 · µPD753016A PD753016A, 753017A : 16384 · µPD753012A PD753012A : 12288 · µPD753016A PD753016A : 16384 · µPD753017A PD753017A : 24576 Number of stack bytes for subroutine instructions 2 bytes 3 bytes BRA !addr1 instruction CALLA !addr1 instruction Not available Available CALL !addr instruction 3 machine cycles 4 machine cycles CALLF !faddr instruction 2 machine cycles 3 machine cycles Caution The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL series. Therefore, this mode is effective for enhancing software compatibility with products exceeding 16 Kbytes. When the Mk II mode is selected, the number of stack bytes used during execution of subroutine call instructions increases by one byte per stack compared to the Mk I mode. When the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes longer by one machine cycle. Therefore, use the Mk I mode if the RAM efficiency and processing performance are more important than software compatibility. 16 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A 4.2 Setting Method of Stack Bank Select Register (SBS) Switching between the Mk I mode and Mk II mode can be done by the stack bank select register (SBS). Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 10XXBNote at the beginning of a program. When using the Mk II mode, it must be initialized to 00XXBNote. Note Set the desired value in the XX positions. Figure 4-1. Stack Bank Select Register Format Address 3 F84H SBS3 2 1 SBS2 SBS1 0 Symbol SBS0 SBS Stack area specification 0 0 Memory bank 0 0 1 Memory bank 1 1 0 Memory bank 2 1 1 Memory bank 3 0 Be sure to set bit 2 to 0. Mode switching specification 0 1 Caution Mk II mode Mk I mode Since SBS. 3 is set to "1" after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to "0" to select the Mk II mode. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 17 µPD753012A PD753012A, 753016A, 753017A 5. MEMORY CONFIGURATION · Program memory (ROM) . 12288 × 8 bits (µPD753012A PD753012A) . 16384 × 8 bits (µPD753016A PD753016A) . 24576 × 8 bits (µPD753017A PD753017A) · Addresses 0000H 0000H and 0001H 0001H Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset start is possible from any address. · Addresses 0002H 0002H to 000DH 000DH Vector table wherein the program start address and the values set for the RBE and MBE by each vectored interrupt are written. Interrupt processing can start from any address. · Addresses 0020H 0020H to 007FH 007FH Table area referenced by the GETI instructionNote. Note The GETI instruction realizes a 1-byte instruction on behalf of any 2-byte/3-byte instruction, or two 1byte instructions. It is used to decrease the number of program steps. · Data memory (RAM) · · 18 Data area .1024 words × 4 bits (000H to 3FFH) Peripheral hardware area.128 × 4 bits (F80H to FFFH) Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A Figure 5-1. Program Memory Map (1/3) (a) µ PD753012A PD753012A 7 0000H 0000H MBE 6 RBE 5 0 Internal reset start address (high-order 6 bits) Internal reset start address (Iow-order 8 bits) 000CH 000CH MBE MBE RBE RBE RBE (high-order 6 bits) (Iow-order 8 bits) INT1 start address (high-order 6 bits) (Iow-order 8 bits) INTCSI start address (high-order 6 bits) (Iow-order 8 bits) INTT0 start address (high-order 6 bits) INTT0 start address 000AH 000AH MBE RBE INT0 start address INTCSI start address 0008H 0008H MBE RBE (Iow-order 8 bits) INT1 start address 0006H 0006H MBE RBE (high-order 6 bits) INT0 start address 0004H 0004H MBE INTBT/INT4 start address INTBT/INT4 start address 0002H 0002H (Iow-order 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction BRCB !caddr instruction branch address CALL !addr instruction subroutine entry address INTT1, INTT2 start address (high-order 6 bits) INTT1, INTT2 start address (Iow-order 8 bits) BR $addr instruction relative branch address (­15 to ­1, +2 to +16) 0020H 0020H GETI instruction reference table Branch destination address and subroutine entry address when GETI instruction is executed 007FH 007FH 0080H 0080H 07FFH 07FFH 0800H 0800H 0FFFH 1000H 1000H BRCB !caddr instruction branch address 1FFFH 2000H 2000H BRCB !caddr instruction branch address 2FFFH Note Can be used only in the Mk II mode. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order 8 bits of PC by executing the BR PCDE, BR PCXA instruction. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 19 µPD753012A PD753012A, 753016A, 753017A Figure 5-1. Program Memory Map (2/3) (b) µPD753016A PD753016A 7 0000H 0000H 6 MBE RBE 5 0 Internal reset start address (high-order 6 bits) Internal reset start address (Iow-order 8 bits) 000CH 000CH MBE MBE RBE RBE RBE (high-order 6 bits) (Iow-order 8 bits) INT1 start address (high-order 6 bits) (Iow-order 8 bits) INTCSI start address (high-order 6 bits) (Iow-order 8 bits) INTT0 start address (high-order 6 bits) INTT0 start address 000AH 000AH MBE RBE INT0 start address INTCSI start address 0008H 0008H MBE RBE (Iow-order 8 bits) INT1 start address 0006H 0006H MBE RBE (high-order 6 bits) INT0 start address 0004H 0004H MBE INTBT/INT4 start address INTBT/INT4 start address 0002H 0002H (Iow-order 8 bits) CALLF !faddr instruction entry address Branch address of BR BCXA, BR BCDE, BR !addr, BRA !addr1Note or CALLA !addr1Note instruction BRCB !caddr instruction branch address CALL !addr instruction subroutine entry address INTT1,INTT2 start address (high-order 6 bits) INTT1,INTT2 start address (Iow-order 8 bits) BR $addr instruction relative branch address (­15 to ­1, +2 to +16) 0020H 0020H GETI instruction reference table 007FH 007FH 0080H 0080H Branch destination address and subroutine entry address when GETI instruction is executed 07FFH 07FFH 0800H 0800H 0FFFH 1000H 1000H BRCB !caddr instruction branch address 1FFFH 2000H 2000H BRCB !caddr instruction branch address 2FFFH 3000H 3000H BRCB !caddr instruction branch address 3FFFH Note Can be used only in the Mk II mode. Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order 8 bits of PC by executing the BR PCDE, BR PCXA instruction. 20 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A Figure 5-1. Program Memory Map (3/3) (c) µ PD753017A PD753017A 7 0000H 0000H 6 MBE RBE 5 0 Internal reset start address (high-order 6 bits) Internal reset start address (Iow-order 8 bits) 000CH 000CH MBE MBE RBE RBE RBE (high-order 6 bits) (Iow-order 8 bits) INT1 start address (high-order 6 bits) (Iow-order 8 bits) INTCSI start address (high-order 6 bits) (Iow-order 8 bits) INTT0 start address (high-order 6 bits) INTT0 start address 000AH 000AH MBE RBE INT0 start address INTCSI start address 0008H 0008H MBE RBE (Iow-order 8 bits) INT1 start address 0006H 0006H MBE RBE (high-order 6 bits) INT0 start address 0004H 0004H MBE INTBT/INT4 start address INTBT/INT4 start address 0002H 0002H (Iow-order 8 bits) CALLF !faddr instruction entry address BRCB !caddr instruction branch address BR !addr instruction branch address CALL !addr instruction branch address INTT1,INTT2 start address (high-order 6 bits) INTT1,INTT2 start address (Iow-order 8 bits) Branch address of BR BCDE, GETI instruction BR BCXA, branch/call BRA !addr1Note or address CALLA !addr1Note instruction 0020H 0020H GETI instruction reference table 007FH 007FH 0080H 0080H BR $addr1 instruction relative branch address (­15 to ­1, +2 to +16) 07FFH 07FFH 0800H 0800H 0FFFH 1000H 1000H 1FFFH 2000H 2000H 2FFFH 3000H 3000H 3FFFH 4000H 4000H 4FFFH 5000H 5000H BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address BRCB !caddr instruction branch address 5FFFH Note Can be used only in the Mk II mode. Caution The interrupt vector start address shown above consists of 14 bits. Set it in 16K space (0000H3FFFH 0000H3FFFH). Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order 8 bits of PC by executing the BR PCDE, BR PCXA instruction. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 21 µPD753012A PD753012A, 753016A, 753017A Figure 5-2. Data Memory Map Data memory Memory bank 000H (32 × 4) General purpose register area 01FH 020H 0 256 × 4 (224 × 4) 0FFH 100H 256 × 4 (224 × 4) 1DFH 1E0H (32 × 4) Display data memory Stack areaNote 1 1FFH 200H Data area static RAM (1024 × 4) 256 × 4 2 256 × 4 3 2FFH 300H 3FFH Not incorporated F80H Peripheral hardware area 128 × 4 FFFH Note For stack area, one memory bank can be selected among memory banks 0 to 3. 22 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 15 µPD753012A PD753012A, 753016A, 753017A 6. PERIPHERAL HARDWARE FUNCTIONS 6.1 Digital Input/Output Ports There are four types of I/O ports as follows. · CMOS input (PORT0, 1) : · CMOS input/output (PORT2, 3, 6, 7) : 16 · N-channel open-drain input/output (PORT4, 5) : · Bit port output (BP0-BP7) : Total 8 8 8 40 Table 6-1. Types and Features of Digital Ports Port (Pin Name) PORT0 (P00-P03 P00-P03) Function 4-bit input Also used for the INT4, SCK, SO/SB0, SI/SB1 pins. Input-only port Also used for the INT0INT2 and TI0-TI2 pins. Can be set to input mode or output mode in 4-bit units. Also used for the PTO0PTO2, PCL, BUZ pins. Can be set to input mode or output mode in 1/4-bit units. Also used for the LCDCL, SYNC pins. 4-bit I/O (N-channel open-drain, 13 V withstanding) Can be set to input mode or output mode in 4-bit units. Ports 4 and 5 are paired and data can be input/ output in 8-bit units. On-chip pull-up resistor can be specified bit-wise by mask option. 4-bit I/O Can be set to input mode or output mode in 1/4-bit units. Ports 6 and 7 are paired and data can be input/ output in 8-bit units. Also used for the KR0-KR3 pins. 4-bit I/O PORT3 (P30-P33 P30-P33) PORT4 (P40-P43 P40-P43) PORT5 (P50-P53 P50-P53) PORT6 (P60-P63 P60-P63) PORT7 (P70-P73 P70-P73) BP0-BP7 Remarks When the serial interface function is used, the alternate function pins function as output ports depending on the operation mode. PORT1 (P10-P13 P10-P13) PORT2 (P20-P23 P20-P23) Operation and Features Can be set to input mode or output mode in 4-bit units. 1-bit output Outputs data bit-wise. Can be switched to LCD drive segment output S24-S31 S24-S31 by software. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 Also used for the KR4-KR7 pins. - 23 µPD753012A PD753012A, 753016A, 753017A 6.2 Clock Generator Operation of the clock generator is determined by the processor clock control register (PCC) and system clock control register (SCC). The two clocks, the main system clock and subsystem clock, are available. The instruction excution time can be altered. · 0.95 µ s, 1.91 µs, 3.81 µs, 15.3 µs (main system clock : at 4.19 MHz operation) · 0.67 µ s, 1.33 µs, 2.67 µs, 10.7 µs (main system clock : at 6.0 MHz operation) · 122 µs (subsystem clock : at 32.768 kHz operation) Figure 6-1. Clock Generator Block Diagram · Basic interval timer (BT) · Timer/event counter · Serial interface · Watch timer · LCD controller/driver · INT0 noise elimination circuit · Clock output circuit XT1 VDD XT2 Subsystem clock oscillator fXT Main system clock oscillator LCD controller/driver fX Watch timer X1 VDD X2 1/1 to 1/4096 Divider 1/2 1/4 1/16 Selector WM.3 SCC Oscillation stop Divider SCC3 Selector 1/4 Internal bus SCC0 · CPU · INT0 noise elimination circuit · Clock output circuit PCC PCC0 PCC1 4 HALT F/F PCC2 S HALTNote STOPNote PCC3 R PCC2, PCC3 Clear STOP F/F Q Q Wait release signal from BT S RESET signal R Standby release signal from interrupt control circuit Note Instruction execution Remarks 1. fX = Main system clock frequency 2. 3. = CPU clock 4. PCC: Processor Clock Control Register 5. SCC: System Clock Control Register 6. 24 fXT = Subsystem clock frequency One clock cycle (tCY) of equal to one machine cycle of the instruction. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A 6.3 Subsystem Clock Oscillator Control Functions The µPD753017A PD753017A subsystem clock oscillator has the following two control functions. · Selects by software whether an internal feedback resistor is to be used or notNote. · Reduces current consumption by decreasing the drive current of the on-chip inverter when the supply voltage is high (VDD 2.7 V). Note When the subsystem clock is not used, set SOS.0 to 1 (so as not to use the internal feedback resistor) by software, connect XT1 to VSS, and open XT2. This makes it possible to reduce the current consumption in the subsystem clock oscillator. The above functions can be used by switching the bits 0 and 1 of the sub-oscillator control register (SOS). (See Figure 6-2.) Figure 6-2. Subsystem Clock Oscillator SOS.0 Feedback resistor Inverter SOS.1 XT1 XT2 VDD Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 25 µPD753012A PD753012A, 753016A, 753017A 6.4 Clock Output Circuit The clock output circuit is provided to output the clock pulses from the P22/PTO2/PCL P22/PTO2/PCL pin to the application of remote control wave outputs and peripheral LSI's. · Clock output (PCL) : , 524, 262, 65.5 kHz (at 4.19 MHz operation) , 750, 375, 93.8 kHz (at 6.0 MHz operation) Figure 6-3. Clock Output Circuit Block Diagram From clock generator From timer/event counter (channel 2) Output buffer Selector fX/23 Selector fX/24 PCL/PTO2/P22 PCL/PTO2/P22 fX/26 PORT2.2 CLOM3 0 CLOM1 CLOM0 CLOM P22 output latch Bit 2 of PMGB Port 2 I/O mode specification bit 4 Internal bus Remark Special care has been taken in designing the chip so that small-width pulses may not be output when switching clock output enable/disable. 26 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A 6.5 Basic Interval Timer/Watchdog Timer The basic interval timer/watchdog timer has the following functions. · Interval timer operation to generate a reference time interrupt · Watchdog timer operation to detect a runaway of program and reset the CPU · Selects and counts the wait time when the standby mode is released · Reads the contents of counting Figure 6-4. Basic Interval Timer/Watchdog Timer Block Diagram From clock generator Clear Clear fX/25 fX/27 MPX Basic interval timer (8-bit frequency divider) Set fX/29 BT fX/212 3 Wait release signal when standby is released. BTM3 BTM2 BTM1 BTM0 BTM SET1Note 4 BT interrupt request flag Vectored interrupt IRQBT request signal Internal reset signal WDTM SET1Note 8 1 Internal bus Note Instruction execution Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 27 µPD753012A PD753012A, 753016A, 753017A 6.6 Watch Timer The µPD753017A PD753017A has one channel of watch timer. The watch timer has the following functions. · Sets the test flag (IRQW) with 0.5 sec interval. The standby mode can be released by the IRQW. · 0.5 sec interval can be created by both the main system clock (4.19 MHz) and subsystem clock (32.768 kHz). · Convenient for program debugging and checking as interval becomes 128 times longer (3.91 ms) with the fast feed mode. · Outputs the frequencies (2.048, 4.096, 32.768 kHz) to the P23/BUZ P23/BUZ pin, usable for buzzer and trimming of system clock oscillation frequencies. · Clears the frequency divider to make the clock start with zero seconds. Figure 6-5. Watch Timer Block Diagram fW (512 Hz : 1.95 ms) 26 fW (256 Hz : 3.91 ms) 27 fX 128 From clock generator (32.768 kHz) Selector fW (32.768 kHz) fXT (32.768 kHz) Divider fW 214 fLCD Selector INTW IRQW set signal 2 Hz 0.5 sec 4 kHz 2 kHz fW fW 23 24 Clear Selector Output buffer P23/BUZ P23/BUZ WM WM7 PORT2.3 0 WM5 WM4 WM3 8 WM2 WM1 WM0 P23 output latch PMGB bit 2 Port 2 input/ output mode Bit test instruction Internal bus The values enclosed in parentheses are applied when fX = 4.19 MHz and fXT = 32.768 kHz. 28 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A 6.7 Timer/Event Counter The µPD753017A PD753017A has three channels of timer/event counter. The timer/event counter has the following functions. · Programmable interval timer operation · Square wave output of any frequency to the PTOn pin (n = 0, 1) · Event counter operation · Divides the frequency of signal input via the TIn pin to 1-Nth of the original signal and outputs the divided frequency to the PTOn pin (frequency division operation). · Supplies the shift clock to the serial interface circuit (channel 0 only). · Calls the count value. The timer/event counter operates in the following four modes as set by the mode register. Table 6-2. Operation Modes of Timer/Event Counter Channel Channel 0 Channel 1 Channel 2 Yes Yes Yes NoNote No Yes PWM pulse generator mode No No Yes 16-bit timer/event counter mode No Yes NoNote Yes No Yes Mode 8-bit timer/event counter mode Gate control function Gate control function Carrier generator mode Note Used for gate control signal generation Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 29 30 Figure 6-6. Timer/Event Counter Block Diagram (Channel 0) Internal bus 8 8 SET1 8 ­ TM06 TM05 TM04 TM03 TM02 ­ TOE0 TMOD0 TM0 TO enable flag Modulo register (8) ­ PORT2.0 PMGB bit 2 Port 2 P20 input/output output latch mode To serial interface 8 PORT1.3 TOUT0 Match Comparator (8) TOUT F/F Output buffer 8 Reset T0 TI0 fX/24 From clock generator INTT0 IRQT0 set signal Count register (8) MPX CP fX/26 fX/28 Clear fX/210 Timer operation start RESET IRQT0 clear signal To timer/event counter (channel 2) µPD753012A PD753012A, 753016A, 753017A Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 Input buffer P20/PTO0 P20/PTO0 Figure 6-7. Timer/Event Counter Block Diagram (Channel 1) Internal bus 8 TOE1 TM1 ­ 8 TM16 TM15 TM14 TM13 TM12 TM11 TM10 T1 enable flag TMOD1 Decoder PORT1.2 PORT2.1 P21 output latch PMGB.2 Port 2 input/output mode Modulo register (8) 8 TI1/TI2/P12/INT2 TI1/TI2/P12/INT2 Match Comparator (8) Input buffer fX/26 From clock 8 generator fX/2 fX/210 CP Output buffer Reset 8 MPX P21/PTO1 P21/PTO1 T1 Count register (8) Clear fX/212 RESET Timer operation start 16-bit timer/event counter mode IRQT1 clear signal Selector Timer/event counter match signal (channel 2) (When 16-bit timer/event counter mode) Timer/event counter reload signal (channel 2) Timer/event counter comparator (channel 2) (When 16-bit timer/event counter mode) INTT1 IRQT1 set signal 31 µPD753012A PD753012A, 753016A, 753017A Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 Timer/event counter output (channel 2) fX/25 TOUT F/F 32 Figure 6-8. Timer/Event Counter Block Diagram (Channel 2) Internal bus MPX (8) 8 Comparator (8) Input buffer Reload TOUT F/F Reset 8 MPX CP TOE2 REMC NRZB NRZ T2 Count register (8) Overflow P22/PCL/PTO2 P22/PCL/PTO2 Output buffer Timer/event counter clock input (channel 1) Carrier generator mode Clear INTT2 IRQT2 set signal 16-bit timer/event counter mode IRQT2 clear signal Timer operation start RESET Timer event counter TOUT F/F (channel 0) Timer/event counter clear signal (channel 1) (When 16-bit timer/event counter mode) Timer/event counter match signal (channel 1) (When 16-bit timer/event counter mode) Timer/event counter match signal (channel 1) (When carrier generator mode) From clock output circuit µPD753012A PD753012A, 753016A, 753017A Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 fX fX/2 From clock fX/24 generator fX/26 fX/28 fX/210 Match PORT2.2 PMGB.2 P22 Port 2 output latch input/output TC2 TGCE Selector 8 Decoder TI1/TI2/ P12/INT2 P12/INT2 Modulo register (8) 8 Modulo register for high level period setup (8) PORT1.2 8 TMOD2 Selector TM26 TM25 TM24 TM23 TM22 TM21 TM20 8 TMOD2H TM2 Selector 8 8 µPD753012A PD753012A, 753016A, 753017A 6.8 Serial Interface The µPD753017A PD753017A is provided with an 8-bit clocked serial interface. This serial interface operates in the following four modes: · Operation stop mode · 3-wire serial I/O mode · 2-wire serial I/O mode · SBI mode Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 33 34 Figure 6-9. Serial Interface Block Diagram Internal bus 8/4 Bit test 8 8 CSIM 8 Bit manipulation Bit test Slave address register (SVA) (8) SBIC Match signal RELT CMDT Address comparator (8) P03/SI/SB1 P03/SI/SB1 SO latch SET CLR Selector Shift register (SIO) D Q BSYE ACKE P02/SO/SB0 P02/SO/SB0 Busy/ acknowledge output circuit Selector Bus release/ command/ acknowledge detection circuit RELD CMDD ACKD INTCSI P01/SCK P01/SCK Serial clock counter P01 output Iatch Serial clock control circuit INTCSI control circuit IRQCSI set signal Serial clock selector External SCK fX/23 fX/24 fX/26 TOUT0 (from timer/ event counter 0) µPD753012A PD753012A, 753016A, 753017A Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 ACKT (8) µPD753012A PD753012A, 753016A, 753017A 6.9 LCD Controller/Driver The µ PD753017A PD753017A incorporates a display controller which generates segment and common signals according to the display data memory contents and incorporates segment and common drivers which can drive the LCD panel directly. The µPD753017A PD753017A LCD controller/driver functions are as follows: · Display data memory is read automatically by DMA operation and segment and common signals are generated. · Display mode can be selected from among the following five: 1 Static 2 1/2 duty (time multiplexing by 2), 1/2 bias 3 1/3 duty (time multiplexing by 3), 1/2 bias 4 1/3 duty (time multiplexing by 3), 1/3 bias 5 1/4 duty (time multiplexing by 4), 1/3 bias · A frame frequency can be selected from among four in each display mode. · A maximum of 32 segment signal output pins (S0-S31 S0-S31) and four common signal output pins (COM0-COM3). · The segment signal output pins (S24-S27 S24-S27 and S28-S31 S28-S31) can be changed to the output ports in 4-pin units. · Split-resistor can be incorporated to supply LCD drive power (mask option). · Various bias methods and LCD drive voltages can be applicable. · When display is off, current flow to the split resistor is cut. · Display data memory not used for display can be used for normal data memory. · It can also operate by using the subsystem clock. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 35 36 Figure 6-10. LCD Controller/Driver Block Diagram Internal bus 4 Display data memory 8 1FEH 3 2 1 0 1F9H 3 2 1 0 1F8H 3 2 1 0 1E0H 3 2 1 0 3 2 1 0 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 1FFH 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 4 4 8 Display mode register Display control register Port 3 output latch 1 0 Port mode register group A Timing controller 1 0 fLCD Multiplexer S31/BP7 S31/BP7 S30/BP6 S30/BP6 S24/BP0 S24/BP0 Common driver S23 S0 COM3 COM2 COM1 COM0 LCD drive voltage control VLC2 VLC1 VLC0 LCD drive mode changer Segment driver P31/ P30/ SYNC LCDCL µPD753012A PD753012A, 753016A, 753017A Selector µPD753012A PD753012A, 753016A, 753017A 6.10 Bit Sequential Buffer . 16 Bits The bit sequential buffer (BSB) is a special data memory for bit manipulation and the bit manipulation can be easily performed by changing the address specification and bit specification in sequence, therefore it is useful when processing a long data bit-wise. Figure 6-11. Bit Sequential Buffer Format Address FC3H Bit 3 Symbol 2 FC2H 1 0 3 2 BSB3 L register L = FH FC1H 1 0 3 BSB2 L = CH L = BH 2 1 FC0H 0 3 BSB1 L = 8H L = 7H L = 4H DECS L 2 1 0 BSB0 L = 3H L = 0H INCS L Remarks 1. 2. In the pmem.@L addressing, the specified bit moves corresponding to the L register. In the pmem.@L addressing, the BSB can be manipulated regardless of MBE/MBS specification. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 37 µPD753012A PD753012A, 753016A, 753017A 7. INTERRUPT FUNCTION AND TEST FUNCTION µPD753017A PD753017A has eight types of interrupt sources and two types of test sources. Among the test sources, INT2 is provided with two testable inputs for edge detection. µPD753017A PD753017A has the following functions in the interrupt control circuit. (1) Interrupt function · Vectored interrupt function for hardware control, enabling/disabling the interrupt acceptance by the interrupt enable flag (IEXXX) and interrupt master enable flag (IME). · Can set any interrupt start address. · Nesting interrupts wherein the order of priority can be specified by the interrupt priority select register (IPS). · Test function of interrupt request flag (IRQXXX). An interrupt generated can be checked by software. · Release the standby mode. A release interrupt can be selected by the interrupt enable flag. (2) Test function · Test request flag (IRQXXX) generation can be checked by software. · Release the standby mode. The test source to be released can be selected by the test enable flag. 38 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 Figure 7-1. Interrupt Control Circuit Block Diagram Internal bus 2 1 4 IME IPS IM2 IM1 IST1 IST0 Interrupt enable flag (IE×××) IM0 Decoder INTBT INT4/P00 INT4/P00 INT0/P10 INT0/P10 Note Edge detector IRQBT VRQn IRQ4 IRQ0 IRQ1 INTCSI INTT0 KR0/P60 KR0/P60 KR3/P63 KR3/P63 IRQT2 INTW Rising edge detector IRQT1 INTT2 Vector table address generator IRQT0 INTT1 INT2/P12 INT2/P12 IRQCSI Priority control circuit IRQW Selector IRQ2 Falling edge detector IM2 Note Noise elimination circuit (Standby release is disabled when noise elimination circuit is selected.) Standby release signal 39 µPD753012A PD753012A, 753016A, 753017A Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 INT1/P11 INT1/P11 Selector Both edge detector Edge detector µPD753012A PD753012A, 753016A, 753017A 8. STANDBY FUNCTION In order to save power consumption while a program is in a standby mode, two types of standby modes (STOP mode and HALT mode) are provided for the µ PD753017A PD753017A. Table 8-1. Operation Status in Standby Mode STOP Mode HALT Mode Set instruction STOP instruction HALT instruction System clock when set Settable only when the main system clock is used. Settable both by the main system clock and subsystem clock. Operation status Clock generator Only the main system clock stops oscillation. Only the CPU clock halts (oscillation continues). Basic interval timer/ watchdog timer Operation stops Operation. (The IRQBT is set in the reference interval.)Note 1 Serial interface Operable only when an external SCK input is selected as the serial clock. OperableNote 1 Timer/event counter Operable only when a signal input to the TI0-TI2 pins is specified as the count clock. OperableNote 1 Watch timer Operable when fXT is selected as the count clock. Operable LCD controller/driver Operable only when fXT is selected as the LCDCL. Operable External interrupt The INT1, 2, and 4 are operable. Only the INT0 is not operated.Note 2 CPU The operation stops. Release signals Notes 1. 2. · Interrupt request signal sent from the operable hardware enabled by the interrupt enable flag. · Test request signal sent from the test source enabled by the test enable flag. · RESET input Cannot operate only when the main system clock stops. Can operate only when the noise elimination circuit is not used (IM02 = 1) by bit 2 of the edge detection mode register (IM0). 40 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A 9. RESET FUNCTION There are two reset inputs: external reset signal (RESET) and reset signal sent from the basic interval timer/ watchdog timer. When either one of the reset signals are input, an internal reset signal is generated. Figure 91 shows the circuit diagram of the above two inputs. Figure 9-1. Configuration of Reset Function RESET Internal reset signal Reset signal sent from the basic interval timer/watchdog timer WDTM Internal bus The µPD753017A PD753017A is set by the RESET signal generated and each hardware is initialized as listed in Table 9-1. Figure 9-2 shows the timing chart of the reset operation. Figure 9-2. Reset Operation by RESET Signal Generation Wait Note RESET signal generated Operation mode or standby mode HALT mode Operation mode Internal reset operation Note The following two times can be selected by the mask option. 2 17/fX (21.8 ms : at 6.0 MHz operation, 31.3 ms : at 4.19 MHz operation) 2 15/fX (5.46 ms : at 6.0 MHz operation, 7.81 ms : at 4.19 MHz operation) Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 41 µPD753012A PD753012A, 753016A, 753017A Table 9-1. Status of Each Hardware after Reset (1/2) RESET Signal Generation in Standby Mode RESET Signal Generation in Operation Sets the low-order 6 bits of program memory's address 0000H 0000H to the PC13-PC8 PC13-PC8 and the contents of address 0001H 0001H to the PC7-PC0. Resets the PC14 of the µPD753017A PD753017A to 0. Sets the low-order 6 bits of program memory's address 0000H 0000H to the PC13-PC8 PC13-PC8 and the contents of address 0001H 0001H to the PC7-PC0. Resets the PC14 of the µPD753017A PD753017A to 0. Held Undefined Skip flag (SK0-SK2) 0 0 Interrupt status flag (IST0) 0 0 Hardware Program counter (PC) PSW Carry flag (CY) Bank enable flag (MBE, RBE) Sets the bit 6 of program memory's address 0000H 0000H to the RBE and bit 7 to the MBE. Stack pointer (SP) Sets the bit 6 of program memory's address 0000H 0000H to the RBE and bit 7 to the MBE. Undefined Undefined 1000B 1000B 1000B 1000B Data memory (RAM) Held Undefined General-purpose register (X, A, H, L, D, E, B, C) Held Undefined Bank select register (MBS, RBS) 0, 0 0, 0 Undefined Undefined Stack bank select register (SBS) Basic interval Counter (BT) timer/ Mode register (BTM) 0 0 watchdog timer Watchdog timer enable flag (WDTM) 0 0 Timer/event Counter (T0) 0 0 counter (T0) Modulo register (TMOD0) FFH FFH 0 0 0, 0 0, 0 0 0 FFH FFH 0 0 0, 0 0, 0 0 0 Mode register (TM0) TOE0, TOUT F/F Timer/event Counter (T1) counter (T1) Modulo register (TMOD1) Mode register (TM1) TOE1, TOUT F/F Timer/event Counter (T2) counter (T2) Modulo register (TMOD2) FFH FFH High level period setting modulo register (TMOD2H) FFH FFH 0 0 0, 0 0, 0 0, 0, 0 0, 0, 0 TGE 0 0 Mode register (WM) 0 0 Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB Watch timer 42 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A Table 9-1. Status of Each Hardware after Reset (2/2) Hardware RESET Signal Generation in Operation Shift register (SIO) Held Undefined Operation mode register (CSIM) 0 0 SBI control register (SBIC) Serial interface RESET Signal Generation in Standby Mode 0 0 Held Undefined Slave address register (SVA) Clock generator, Processor clock control register (PCC) 0 0 clock output System clock control register (SCC) 0 0 circuit Clock output mode register (CLOM) 0 0 Sub-oscillator control register (SOS) 0 0 LCD controller/ Display mode register (LCDM) 0 0 driver Display control register (LCDC) 0 0 Interrupt Interrupt request flag (IRQXXX) Reset (0) Reset (0) function Interrupt enable flag (IEXXX) 0 0 Interrupt master enable flag (IME) 0 0 INT0, 1, 2 mode registers (IM0, IM1, IM2) 0, 0, 0 0, 0, 0 Interrupt priority selection register (IPS) 0 0 Output buffer Off Off Output latch Cleared (0) Cleared (0) I/O mode registers (PMGA, PMGB) 0 0 Pull-up resistor specification register (POGA) 0 0 Held Undefined Digital port Bit sequential buffer (BSB0-BSB3) Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 43 µPD753012A PD753012A, 753016A, 753017A 10. MASK OPTION The µPD753017A PD753017A has the following mask options. · P40-P43 P40-P43, P50-P53 P50-P53 mask options On-chip pull-up resistors can be connected. On-chip pull-up resistors are specifiable bit-wise. On-chip pull-up resistors are not specifiable. · VLC0-VLC2 pins, BIAS pin mask option On-chip split resistor for LCD drive can be connected. Split resistor is not connected. Four 10 k (TYP.) split resistors are connected at the same time. Four 100 k (TYP.) split resistors are connected at the same time. · Standby function mask option Wait times can be selected by a RESET signal. 2 17/fX (21.8 ms : at fX = 6.0 MHz, 31.3 ms : at fX = 4.19 MHz) 215/fX (5.46 ms : at fX = 6.0 MHz, 7.81 ms : at fX = 4.19 MHz) · Subsystem clock mask option Use of the internal feedback resistor can be selected. Internal feedback resistor can be used. (Switched ON/OFF via software) Internal feedback resistor cannot be used. (Switched out in hardware) 44 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A 11. INSTRUCTION SET (1) Expression formats and description methods of operands The operand is described in the operand column of each instruction in accordance with the description method for the operand expression format of the instruction. For details, refer to RA75X RA75X Assembler Package User's Manual-Language (U12385E U12385E). If there are several elements, one of them is selected. Capital letters and the + and ­ symbols are key words and are described as they are. For immediate data, appropriate numbers and labels are described. Instead of the labels such as mem, fmem, pmem, and bit, the symbols of the registers can be described. However, there are restrictions in the labels that can be described for fmem and pmem. For details, see User's Manual. Expression Format Description Method reg reg1 X, A, B, C, D, E, H, L X, B, C, D, E, H, L rp XA, BC, DE, HL rp1 rp2 rp' rp'1 BC, BC, XA, BC, rpa rpa1 HL, HL+, HL­, DE, DL DE, DL n4 n8 4-bit immediate data or label 8-bit immediate data or label mem bit 8-bit immediate data or labelNote 2-bit immediate data or label fmem pmem FB0H-FBFH, FF0H-FFFH immediate data or label FC0H-FFFH immediate data or label addr addr1 caddr faddr 0000H-2FFFH 0000H-2FFFH immediate data or label (µPD753012A PD753012A) 0000H-3FFFH 0000H-3FFFH immediate data or label (µPD753016A PD753016A, 753017A) 0000H-5FFFH 0000H-5FFFH immediate data or label 12-bit immediate data or label 11-bit immediate data or label taddr 20H-7FH 20H-7FH immediate data (where bit0 = 0) or label PORTn IEXXX RBn MBn PORT0-PORT7 IEBT, IET0-IET2, IE0-IE2, IE4, IECSI, IEW RB0-RB3 MB0, MB1, MB2, MB3, MB15 Note DE, HL DE BC, DE, HL, XA', BC', DE', HL' DE, HL, XA', BC', DE', HL' mem can be only used even address in 8-bit data processing. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 45 µPD753012A PD753012A, 753016A, 753017A (2) Legend in explanation of operation A : A register; 4-bit accumulator B : B register C : C register D : D register E : E register H : H register L : L register X : X register XA : XA register pair; 8-bit accumulator BC : BC register pair DE : DE register pair HL : HL register pair XA' : XA' expanded register pair BC' : BC' expanded register pair DE' : DE' expanded register pair HL' : HL' expanded register pair PC : Program counter SP : Stack pointer CY : Carry flag; bit accumulator PSW : Program status word MBE : Memory bank enable flag RBE : Register bank enable flag PORTn : Port n (n = 0-7) IME : Interrupt master enable flag IPS : Interrupt priority selection register IEXXX : Interrupt enable flag RBS : Memory bank selection register PCC : Processor clock control register . : Separation between address and bit (XX) : The contents addressed by XX XXH 46 : Register bank selection register MBS : Hexadecimal data Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A (3) Explanation of symbols under addressing area column *1 MB = MBE·MBS (MBS = 0-3, 15) *2 MB = 0 *3 MBE = 0 : MB = 0 (000H-07FH 000H-07FH) MB = 15 (F80H-FFFH F80H-FFFH) MBE = 1 : MB = MBS (MBS = 0-3, 15) Data memory addressing *4 MB = 15, fmem = FB0H-FBFH, FF0H-FFFH *5 MB = 15, pmem = FC0H-FFFH *6 µPD753012A PD753012A addr = 0000H-2FFFH 0000H-2FFFH µPD753016A PD753016A 753017A addr = 0000H-3FFFH 0000H-3FFFH µPD753012A PD753012A 753016A 753017A (In Mk I mode) addr = (Current PC) ­ 15 to (Current PC) ­ 1 (Current PC) + 2 to (Current PC) + 16 µPD753017A PD753017A (In Mk II mode) addr1 = (Current PC) ­ 15 to (Current PC) ­ 1 (Current PC) + 2 to (Current PC) + 16 µPD753012A PD753012A caddr = 0000H-0FFFH 0000H-0FFFH (PC13, 12 = 00B) or 1000H-1FFFH 1000H-1FFFH (PC13, 12 = 01B) or 2000H-2FFFH 2000H-2FFFH (PC13, 12 = 10B) µPD753016A PD753016A caddr = 0000H-0FFFH 0000H-0FFFH 1000H-1FFFH 1000H-1FFFH 2000H-2FFFH 2000H-2FFFH 3000H-3FFFH 3000H-3FFFH (PC13, 12 (PC13, 12 (PC13, 12 (PC13, 12 caddr = 0000H-0FFFH 0000H-0FFFH 1000H-1FFFH 1000H-1FFFH 2000H-2FFFH 2000H-2FFFH 3000H-3FFFH 3000H-3FFFH 4000H-4FFFH 4000H-4FFFH 5000H-5FFFH 5000H-5FFFH (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 (PC14, 13, 12 *7 *8 µPD753017A PD753017A *9 µPD753012A PD753012A or or or or or addr1 = 0000H-3FFFH 0000H-3FFFH µPD753017A PD753017A 000B) 001B) 010B) 011B) 100B) 101B) addr1 = 0000H-2FFFH 0000H-2FFFH µPD753016A PD753016A = = = = = = Program memory addressing taddr = 0020H-007FH 0020H-007FH *11 00B) or 01B) or 10B) or 11B) faddr = 0000H-07FFH 0000H-07FFH *10 = = = = addr1 = 0000H-5FFFH 0000H-5FFFH Remarks 1. MB indicates memory bank that can be accessed. 2. In *2, MB = 0 independently of how MBE and MBS are set. 3. In *4 and *5, MB = 15 independently of how MBE and MBS are set. 4. *6 to *11 indicate the areas that can be addressed. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 47 µPD753012A PD753012A, 753016A, 753017A (4) Explanation of number of machine cycles column S denotes the number of machine cycles required by skip operation when a skip instruction is executed. The value of S varies as follows. · When no skip is made: S = 0 · When the skipped instruction is a 1- or 2-byte instruction: S = 1 · When the skipped instruction is a 3-byte instructionNote: S = 2 Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr or CALLA !addr1 instruction Caution The GETI instruction is skipped in one machine cycle. One machine cycle is equal to one cycle of CPU clock (= tCY); time can be selected from among four types by setting PCC. 48 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A Instruction Group Transfer A, #n4 1 1 A n4 2 2 reg1 n4 2 2 XA n8 String effect A HL, #n8 2 2 HL n8 String effect B rp2, #n8 2 2 rp2 n8 A, @HL 1 1 A (HL) *1 A, @HL+ 1 2+S A (HL), then L L+1 *1 L=0 A, @HL­ 1 2+S A (HL), then L L­1 *1 L = FH A, @rpa1 1 1 A (rpa1) *2 XA, @HL 2 2 XA (HL) *1 @HL, A 1 1 (HL) A *1 @HL, XA 2 2 (HL) XA *1 A, mem 2 2 A (mem) *3 XA, mem 2 2 XA (mem) *3 mem, A 2 2 (mem) A *3 mem, XA 2 2 (mem) XA *3 A, reg1 2 2 A reg1 XA, rp' 2 2 XA rp' reg1, A 2 2 reg1 A rp'1, XA XCH Number of Machine Cycles XA, #n8 MOV Number of Bytes reg1, #n4 Mnemonic 2 2 rp'1 XA A, @HL 1 1 A (HL) *1 A, @HL+ 1 2+S A (HL), then L L+1 *1 L=0 A, @HL­ 1 2+S A (HL), then L L­1 *1 L = FH A, @rpa1 1 1 A (rpa1) *2 XA, @HL 2 2 XA (HL) *1 A, mem 2 2 A (mem) *3 XA, mem 2 2 XA (mem) *3 A, reg1 1 1 A reg1 XA, rp' 2 2 XA rp' Operand Operation Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 Addressing Area Skip Condition String effect A 49 µPD753012A PD753012A, 753016A, 753017A Instruction Group Table reference Mnemonic MOVTNote 1 Operand XA, @PCDE Number of Bytes Number of Machine Cycles 1 3 Operation Addressing Area Skip Condition XA (PC13­8+DE)ROM q µPD753017A PD753017A XA (PC14­8+DE)ROM XA, @PCXA 1 3 XA (PC13­8+XA)ROM q µPD753017A PD753017A XA (PC14­8+XA)ROM XA, @BCDENote 2 1 3 XA (B1,0+CDE)ROM q µPD753017A PD753017A XA (B2­0+CDE)ROM XA, @BCXANote 2 1 3 XA (B1,0+CXA)ROM q µPD753017A PD753017A XA (B2­0+CXA)ROM *6 *11 *6 *11 CY (pmem7­2+L3­2.bit(L1­0) *5 2 2 CY (H+mem3­0.bit) *1 2 2 (fmem.bit) CY *4 2 2 (pmem7­2+L3­2.bit(L1­0) CY *5 2 2 (H+mem3­0.bit) CY *1 A, #n4 1 1+S A A+n4 carry 2 2+S XA XA+n8 carry 1 1+S A A+(HL) XA, rp' 2 2+S XA XA+rp' carry rp'1, XA 2 2+S rp'1 rp'1+XA carry A, @HL 1 1 A, CY A+(HL)+CY XA, rp' 2 2 XA, CY XA+rp'+CY rp'1, XA 2 2 rp'1, CY rp'1+XA+CY A, @HL 1 1+S A A­(HL) XA, rp' 2 2+S XA XA­rp' borrow rp'1, XA 2 2+S rp'1 rp'1­XA borrow A, @HL 1 1 A, CY A­(HL)­CY XA, rp' 2 2 XA, CY XA­rp'­CY rp'1, XA Notes 1. 2 A, @HL SUBC 2 XA, #n8 SUBS *4 @H+mem.bit, CY ADDC CY (fmem.bit) pmem.@L, CY ADDS 2 fmem.bit, CY Operation 2 CY, @H+mem.bit MOV1 CY, fmem.bit CY, pmem.@L Bit transfer 2 2 rp'1, CY rp'1­XA­CY Only the following bits are valid for the B register. µPD753012A PD753012A, 753016A : low-order 2 bits µPD753017A PD753017A : low-order 3 bits Remark When the µPD753017A PD753017A is set in the Mk I mode, PC14 is fixed to 0. 50 carry *1 *1 borrow *1 The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. *1 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A Number of Machine Cycles A, #n4 2 2 A A n4 1 1 A A (HL) XA, rp' 2 2 XA XA rp' rp'1, XA 2 2 rp'1 rp'1 XA A, #n4 2 2 A A n4 A, @HL 1 1 A A (HL) XA, rp' 2 2 XA XA rp' rp'1, XA 2 2 rp'1 rp'1 XA A, #n4 2 2 A A v n4 A, @HL 1 1 A A v (HL) XA, rp' 2 2 XA XA v rp' rp'1, XA 2 2 rp'1 rp'1 v XA RORC A 1 1 CY A0, A3 CY, An­1 An NOT A 2 2 AA INCS reg 1 1+S reg reg+1 reg = 0 rp1 1 1+S rp1 rp1+1 rp1 = 00H @HL 2 2+S (HL) (HL)+1 *1 (HL) = 0 mem 2 2+S (mem) (mem)+1 *3 (mem) = 0 reg 1 1+S reg reg­1 reg = FH rp' 2 2+S rp' rp'­1 rp' = FFH reg, #n4 2 2+S Skip if reg = n4 reg = n4 @HL, #n4 2 2+S Skip if (HL) = n4 *1 (HL) = n4 A, @HL 1 1+S Skip if A = (HL) *1 A = (HL) XA, @HL 2 2+S Skip if XA = (HL) *1 XA = (HL) A, reg 2 2+S Skip if A = reg A = reg XA, rp' Operation Number of Bytes A, @HL Instruction Group 2 2+S Skip if XA = rp' XA = rp' SET1 CY 1 1 CY 1 CLR1 CY 1 1 CY 0 SKT CY 1 1+S NOT1 CY 1 1 Mnemonic AND OR XOR Accumulator manipulation Increment and Decrement DECS Comparison Carry flag manipulation SKE Operand Operation Skip if CY = 1 Addressing Area Skip Condition *1 *1 *1 CY = 1 CY CY Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 51 µPD753012A PD753012A, 753016A, 753017A *4 2 2 (pmem7­2+L3­2.bit(L1­0) 1 *5 2 2 (H+mem3­0.bit) 1 *1 mem.bit 2 2 (mem.bit) 0 *3 2 2 (fmem.bit) 0 *4 2 2 (pmem7-2+L3-2.bit(L1-0) 0 *5 2 2 (H+mem3-0.bit) 0 *1 mem.bit 2 2+S Skip if (mem.bit)=1 *3 (mem.bit)=1 2 2+S Skip if (fmem.bit)=1 *4 (fmem.bit)=1 2 2+S Skip if (pmem7­2+L3­2.bit(L1­0)=1 *5 (pmem.@L)=1 2 2+S Skip if (H+mem3­0.bit)=1 *1 (@H+mem.bit)=1 mem.bit 2 2+S Skip if (mem.bit)=0 *3 (mem.bit)=0 2 2+S Skip if (fmem.bit)=0 *4 (fmem.bit)=0 pmem.@L 2 2+S Skip if (pmem7­2+L3­2.bit(L1­0)=0 *5 (pmem.@L)=0 @H+mem.bit 2 2+S Skip if (H+mem3­0.bit)=0 *1 (@H+mem.bit)=0 fmem.bit 2 2+S Skip if (fmem.bit)=1 and clear *4 (fmem.bit)=1 pmem.@L 2 2+S Skip if (pmem7­2+L3­2.bit(L1­0)=1 and clear *5 (pmem.@L)=1 @H+mem.bit 2 2+S Skip if (H+mem3­0.bit)=1 and clear *1 (@H+mem.bit)=1 CY, fmem.bit 2 2 CY CY (fmem.bit) *4 CY, pmem.@L 2 2 CY CY (pmem7­2+L3­2.bit(L1­0) *5 CY, @H+mem.bit 2 2 CY CY (H+mem3­0.bit) *1 CY, fmem.bit 2 2 CY CY (fmem.bit) *4 CY, pmem.@L 2 2 CY CY (pmem7­2+L3­2.bit(L1­0) *5 CY, @H+mem.bit 2 2 CY CY (H+mem3­0.bit) *1 CY, fmem.bit 2 2 CY CY v (fmem.bit) *4 CY, pmem.@L 2 2 CY CY v (pmem7­2+L3­2.bit(L1­0) *5 CY, @H+mem.bit 52 (fmem.bit) 1 fmem.bit XOR1 2 @H+mem.bit OR1 2 pmem.@L AND1 *3 fmem.bit SKTCLR (mem.bit) 1 @H+mem.bit SKF 2 pmem.@L SKT 2 fmem.bit CLR1 mem.bit @H+mem.bit SET1 Number of Machine Cycles pmem.@L Memory bit manipulation Mnemonic Number of Bytes fmem.bit Instruction Group 2 2 CY CY v (H+mem3­0.bit) *1 Operand Operation Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 Addressing Area Skip Condition µPD753012A PD753012A, 753016A, 753017A Number of Machine Cycles addr ­ ­ PC13­0 addr Select appropriate instruction from among the following instructions according to the assembler being used. BR !addr BRCB !caddr BR $addr *6 ­ ­ q µPD753012A PD753012A, 753016A PC13­0 addr1 Select appropriate instruction from among the following instructions according to the assembler being used. BR !addr BRA !addr1 BRCB !caddr BR $addr1 *11 Mnemonic BRNote 1 Branch Number of Bytes addr1 Instruction Group Operand Operation Addressing Area Skip Condition q µPD753017A PD753017A PC14­0 addr1 Select appropriate instruction from among the following instructions according to the assembler being used. BR !addr BRA !addr1 BRCB !caddr BR $addr1 !addr 3 3 PC13­0 addr *6 q µPD753017A PD753017A PC14 0, PC13­0 addr $addr 1 2 PC13­0 addr $addr1 1 2 q µPD753017A PD753017A PC14­0 addr1 PCDE 2 3 PC13­0 PC13­8+DE *7 q µPD753017A PD753017A PC14­0 PC14­8+DE PCXA 2 3 PC13­0 PC13­8+XA q µPD753017A PD753017A PC14­0 PC14­8+XA Notes 1. 2 3 3 *6 *11 PC13­0 BCXA *6 q µPD753017A PD753017A PC14­0 BCXA BCXANote 2 2 PC13­0 BCDE q µPD753017A PD753017A PC14­0 BCDE BCDENote 2 *11 The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. 2. Only the following bits are valid for the B register. µPD753012A PD753012A, 753016A : low-order 2 bits µPD753017A PD753017A : low-order 3 bits Remark When the µPD753017A PD753017A is set in the Mk I mode, PC 14 is fixed to 0. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 53 µPD753012A PD753012A, 753016A, 753017A Number of Machine Cycles !addr 3 3 q µPD753012A PD753012A, 753016A PC13­0 addr 3 3 q µPD753017A PD753017A PC14­0 addr1 !caddr 2 2 PC13­0 PC13,12+caddr11-0 Mnemonic BRANote Branch Number of Bytes !addr1 Instruction Group BRCBNote Operand Operation Addressing Area Skip Condition *6 *11 *8 q µPD753017A PD753017A PC14­0 PC14,13,12+caddr11­0 *6 3 3 q µPD753017A PD753017A (SP­6)(SP­3)(SP­4) PC11­0 (SP­5) 0, PC14, 13, 12 (SP­2) ×, ×, MBE, RBE PC14­0 addr1, SP SP­6 *11 !addr 3 3 (SP­4)(SP­1)(SP­2) PC11­0 (SP­3) MBE, RBE, PC13, PC12 PC13­0 addr, SP SP­4 q µPD753012A PD753012A, 753016A (SP­6)(SP­3)(SP­4) PC11­0 (SP­5) 0, 0, PC13, 12 (SP­2) ×, ×, MBE, RBE PC13­0 addr, SP SP­6 q µPD753017A PD753017A (SP­6)(SP­3)(SP­4) PC11­0 (SP­5) 0, PC14, 13, 12 (SP­2) ×, ×, MBE, RBE PC14 0, PC13­0 addr, SP SP­6 2 (SP­4)(SP­1)(SP­2) PC11­0 (SP­3) MBE, RBE, PC13, PC12 PC13­0 000+faddr, SP SP­4 q µPD753012A PD753012A, 753016A (SP­6)(SP­3)(SP­4) PC11­0 (SP­5) 0, 0, PC13, 12 (SP­2) ×, ×, MBE, RBE PC13­0 000+faddr, SP SP­6 3 Note q µPD753012A PD753012A, 753016A (SP­6)(SP­3)(SP­4) PC11­0 (SP­5) 0, 0, PC13, 12 (SP­2) ×, ×, MBE, RBE PC13­0 addr, SP SP­6 3 CALLFNote 3 4 CALLNote 3 4 CALLANote !addr !addr1 Subroutine stack control q µPD753017A PD753017A (SP­6)(SP­3)(SP­4) PC11­0 (SP­5) 0, PC14, 13, 12 (SP­2) ×, ×, MBE, RBE PC14­0 0000+faddr, SP SP­6 !faddr 2 *9 The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Remark When the µPD753017A PD753017A is set in the Mk I mode, PC14 is fixed to 0. 54 *6 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A Instruction Group Subroutine stack control Mnemonic RETNote Number of Bytes Number of Machine Cycles 1 Operand 3 Operation Addressing Area Skip Condition MBE, RBE, PC13, PC12 (SP+1) PC11­0 (SP)(SP+3)(SP+2), SP SP+4 q µPD753012A PD753012A, 753016A ×, ×, MBE, RBE (SP+4) 0, 0, PC13, PC12 (SP+1) PC11­0 (SP)(SP+3)(SP+2), SP SP+6 q µPD753017A PD753017A ×, ×, MBE, RBE (SP+4) 0, PC14, PC13, PC12 (SP+1) PC11­0 (SP)(SP+3)(SP+2), SP SP+6 RETSNote 1 3+S MBE, RBE, PC13, PC12 (SP+1) PC11­0 (SP)(SP+3)(SP+2), SP SP+4 then skip unconditionally Unconditional q µPD753012A PD753012A, 753016A ×, ×, MBE, RBE (SP+4) 0, 0, PC13, PC12 (SP+1) PC11­0 (SP)(SP+3)(SP+2), SP SP+6 then skip unconditionally q µPD753017A PD753017A ×, ×, MBE, RBE (SP+4) 0, PC14, PC13, PC12 (SP+1) PC11­0 (SP)(SP+3)(SP+2), SP SP+6 then skip unconditionally RETINote !faddr 1 3 MBE, RBE, PC13, PC12 (SP+1) PC11­0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 q µPD753012A PD753012A, 753016A 0, 0, PC13, PC12 (SP+1) PC11­0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 q µPD753017A PD753017A 0, PC14, PC13, PC12 (SP+1) PC11­0 (SP)(SP+3)(SP+2) PSW (SP+4)(SP+5), SP SP+6 Note The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. Remark When the µPD753017A PD753017A is set in the Mk I mode, PC14 is fixed to 0. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 55 µPD753012A PD753012A, 753016A, 753017A Number of Machine Cycles rp 1 1 (SP­1)(SP­2) rp, SP SP­2 2 2 (SP­1) MBS, (SP­2) RBS, SP SP­2 rp 1 1 rp (SP+1)(SP), SP SP+2 BS 2 2 MBS (SP+1), RBS (SP), SP SP+2 2 2 IME(IPS.3) 1 2 2 IEXXX 1 2 2 IME(IPS.3) 0 IEXXX 2 2 IEXXX 0 A, PORTn 2 2 A PORTn (n = 0-7) XA, PORTn 2 2 XA PORTn+1, PORTn (n = 4, 6) PORTn, A 2 2 PORTn A (n = 2-7) PORTn, XA 2 2 PORTn+1, PORTn XA (n = 4, 6) HALT 2 2 Set HALT mode (PCC.2 1) STOP 2 2 Set STOP mode (PCC.3 1) NOP 1 1 No operation RBn 2 2 RBS n (n = 0-3) MBn Subroutine stack control Number of Bytes BS Instruction Group 2 2 MBS n (n = 0-3, 15) taddr 1 3 · When TBR instruction PC13­0 (taddr)5­0+(taddr+1) Mnemonic PUSH POP Interrupt control Operand EI IEXXX DI Input/output INNote 1 OUTNote 1 CPU control Special SEL GETINotes 2, 3 Addressing Area Operation Skip Condition *10 · When TCALL instruction (SP­4)(SP­1)(SP­2) PC11­0 (SP­3) MBE, RBE, PC13, PC12 PC13­0 (taddr)5­0+(taddr+1) SP SP­4 · When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed 1 µPD753017A PD753017A · When TBR instruction PC13­0 (taddr)5­0+(taddr+1) PC14 0 3. q · When TCALL instruction (SP­6)(SP­3)(SP­4) PC11­0 (SP­5) 0, 0, PC13, 12 (SP­2) ×, ×, MBE, RBE PC13­0 (taddr)5­0+(taddr+1) SP SP­6, PC14 0 3 2. 3 4 Notes 1. · When instruction other than TBR and TCALL instructions (taddr) (taddr+1) instruction is executed Depending on the reference instruction While the IN instruction and OUT instruction are being executed, the MBE must be set to 0 or 1 and MBS must be set to 15. The above operations in the shaded boxes can be performed only in the Mk II mode. The other operations can be performed only in the Mk I mode. The TBR and TCALL instructions are the table definition assembler pseudo instructions of the GETI instruction. Remark When the µPD753017A PD753017A is set in the Mk I mode, PC14 is fixed to 0. 56 Depending on the reference instruction Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A 12. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25 °C) Parameter Symbol Conditions Ratings Unit Supply voltage V DD ­0.3 to +7.0 V Input voltage V I1 Other than ports 4, 5 ­0.3 to VDD + 0.3 V V I2 Ports Pull-up resistor provided ­0.3 to VDD + 0.3 V 4, 5 N-ch open-drain ­0.3 to +14 V Output voltage VO High-level output current IOH ­0.3 to VDD + 0.3 V Per pin ­10 mA Low-level output current I OL Total of all pins ­30 mA Per pin 30 mA Operating ambient temperature TA 220 mA ­40 to +85 °C Storage temperature Tstg ­65 to +150 °C Total of all pins Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Capacitance (TA = 25°C, V DD = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CIN f = 1 MHz 15 pF Output capacitance COUT Unmeasured pins returned to 0 V 15 pF I/O capacitance CIO 15 pF Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 57 µPD753012A PD753012A, 753016A, 753017A Main System Clock Oscillator Characteristics (TA = ­40 to +85°C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit Ceramic resonator X1 C2 Oscillation stabilization timeNote 3 VDD Crystal resonator X1 C2 Oscillation stabilization timeNote 3 MIN. TYP. 1.0 VDD = 4.5 to 5.5 V Unit 6.0Note 2 MHz ms 6.0Note 2 MHz 10 After VDD has reached MIN. value of oscillation voltage range MAX. 4 1.0 Oscillation frequency (fX)Note 1 X2 C1 Conditions Oscillation frequency (fX)Note 1 X2 C1 Parameter ms 30 VDD Notes 1. X1 X2 X1 input frequency (fX)Note 1 1.0 6.0Note 2 MHz X1 input high-, low-level width (tXH, t XL) External clock 83.3 500 ns The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. 2. If the oscillation frequency is 4.19 MHz < fX 6.0 MHz at 1.8 V VDD < 2.7 V, do not set the processor clock control register (PCC) to 0011. If PCC = 0011, one machine cycle time is less than 0.95 µs, falling short of the rated value of 0.95 µs. 3. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied or STOP mode has been released. Caution When using the main system clock oscillator, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: · Keep the wiring length as short as possible. · Do not cross the wiring with other signal lines. · Do not route the wiring in the vicinity of a line through which a high alternating current flows. · Always keep the ground point of the capacitor of the oscillator at the same potential as VDD . · Do not ground to a power supply pattern through which a high current flows. · Do not extract signals from the oscillator. 58 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A Recommended Oscillator Constant Ceramic resonator (TA = ­20 to +80°C) Manufacturer Part Number Frequency (MHz) Recommended Circuit Constant (pF) Oscillation Voltage Range (V) C1 TDK Corp. C2 MIN. MAX. 1.8 5.5 Remarks CCR1000K2 CCR1000K2 1.0 100 100 CCR2.0MC33 0MC33 2.0 ­ ­ CCR4.19MC3 19MC3 ­ 4.19 On-chip capacitor FCR4.19MC5 19MC5 CCR6.0MC3 Murata Mfg. Co., Ltd. 6.0 CSB1000J CSB1000J Note 1.0 100 100 2.1 CSA2.00MG040 00MG040 2.0 100 100 1.9 ­ ­ 30 30 ­ ­ 30 30 ­ ­ CST2.00MG040 00MG040 CSA4.19MG 4.19 CST4.19MGW 19MGW CSA6.00MG 6.0 CST6.00MGW 00MGW Kyocera Corp. KBR-1000F/Y KBR-1000F/Y 1.0 100 100 KBR-2.0MS 2.0 68 4.0 33 ­ 33 33 ­ ­ ­ On-chip capacitor 1.8 ­ On-chip capacitor 2.3 ­ On-chip capacitor 33 ­ Rd = 5.6 k 68 KBR-4.0MSA/MSB 5.5 KBR-4.0MKC 1.8 5.5 ­ On-chip capacitor KBR-4.0MKD KBR-4.0MKS PBRC4.00A 4.0 PBRC4.00B KBR-4.19MSA 19MSA 33 33 KBR-4.19MSB 19MSB 4.19 33 33 KBR-4.19MKC 19MKC ­ ­ 33 33 ­ On-chip capacitor ­ On-chip capacitor KBR-4.19MKD 19MKD KBR-4.19MKS 19MKS PBRC4.19A PBRC4.19B ­ ­ 33 33 ­ ­ PBRC6.00A 33 33 PBRC6.00B ­ ­ KBR-6.0MSA/MSB KBR-6.0MKC 6.0 ­ On-chip capacitor ­ On-chip capacitor KBR-6.0MKD KBR-6.0MKS Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 ­ On-chip capacitor 59 µPD753012A PD753012A, 753016A, 753017A Note When using the CSB1000J CSB1000J (1.0 MHz) by Murata Mfg. Co., Ltd. as a ceramic resonator, a limiting resistor (Rd = 5.6 k) is necessary (refer to the figure below). The resistor is not necessary when using the other recommended resonators. X1 X2 CSB1000J CSB1000J Rd C1 C2 Caution The oscillator constant and oscillation voltage range indicate conditions of stable oscillation. Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency precision, the oscillation frequency must be adjusted on the implementation circuit. For details, please contact directly the manufacturer of the resonator you will use. 60 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A Subsystem Clock Oscillator Characteristics (TA = ­40 to +85°C, VDD = 1.8 to 5.5 V) Resonator Recommended Circuit Crystal resonator Parameter Conditions XT1 TYP. MAX. Unit 32 Oscillation frequency (f XT)Note 1 MIN. 32.768 35 kHz 1.0 2 s XT2 R C3 C4 Oscillation stabilization timeNote 2 VDD = 4.5 to 5.5 V VDD External clock 10 XT1 input frequency (f XT)Note 1 Notes 1. 100 kHz XT1 input high-, low-level width (t XTH, tXTL) XT1 32 5 15 µs XT2 The oscillation frequency shown above indicates characteristics of the oscillator only. For the instruction execution time, refer to AC Characteristics. 2. The oscillation stabilization time is the time required for oscillation to be stabilized after VDD has been applied. Caution When using the subsystem clock oscillator, wire the portion enclosed in the dotted line in the above figure as follows to prevent adverse influence due to wiring capacitance: · Keep the wiring length as short as possible. · Do not cross the wiring with other signal lines. · Do not route the wiring in the vicinity of a line through which a high alternating current flows. · Always keep the ground point of the capacitor of the oscillator at the same potential as VDD. · Do not ground to a power supply pattern through which a high current flows. · Do not extract signals from the oscillation circuit. The subsystem clock oscillator has a low amplification factor to reduce current consumption and is more susceptible to noise than the main system clock oscillator. Therefore, exercise utmost care in wiring the subsystem clock oscillator. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 61 µPD753012A PD753012A, 753016A, 753017A DC Characteristics (TA = ­40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Low-level output Symbol High-level input VIH1 MAX. Unit Per pin 15 mA Total of all pins IOL current Conditions 150 mA Ports 2, 3 MIN. TYP. VDD = 2.7 to 5.5 V VIH2 VDD V 0.9 V DD VDD V 0.8 V DD VDD V 0.9 V DD VDD V Pull-up resistor VDD = 2.7 to 5.5 V 0.7 V DD VDD V provided VDD = 1.8 to 2.7 V 0.9 V DD VDD V VDD = 2.7 to 5.5 V 0.7 V DD 13 V VDD = 1.8 to 2.7 V Ports 4, 5 VDD = 2.7 to 5.5 V VDD = 1.8 to 2.7 V VIH3 Ports 0, 1, 6, 7, RESET 0.7 V DD VDD = 1.8 to 2.7 V voltage 0.9 V DD 13 V N-ch open-drain VIH4 X1, XT1 VIL1 Ports 2, 3, 4, 5 VIL2 Ports 0, 1, 6, 7, RESET VIL3 X1, XT1 VDD­0.1 High-level output voltage VOH SCK, SO, Ports 2, 3, 6, 7, BP0-BP7 IOH = ­1 mA Low-level output VOL1 SCK, SO, Ports 2-7, IOL = 15 mA BP0-BP7 VDD = 5.0 V ±10% voltage V 0 0.3 V DD V VDD = 1.8 to 2.7 V 0 0.1 V DD V VDD = 2.7 to 5.5 V 0 0.2 V DD V 0 0.1 V DD V 0 voltage VDD VDD = 2.7 to 5.5 V VDD = 1.8 to 2.7 V Low-level input 0.1 V VDD­0.5 V 0.2 IOL = 1.6 mA 2.0 V 0.4 V 0.2 VDD V Pins other than X1, XT1, ports 4, 5 3 µA X1, XT1 20 µA Ports 4, 5 (N-ch open-drain) 20 µA VOL2 SB0, SB1 N-ch open-drain ILIH1 VIN = V DD ILIH3 VIN = 13 V Low-level input ILIL1 VIN = 0 V leakage current ILIL2 X1, XT1 ILIL3 Ports 4, 5 (N-ch open-drain) Pull-up resistor 1 k High-level input leakage current ILIH2 ­3 µA ­20 µA ­3 Pins other than X1, XT1, ports 4, 5 µA When input instruction is not executed ­30 µA open-drain) VDD = 5 V ­10 ­27 µA When input VDD = 3 V ­3 ­8 µA 3 µA Ports 4, 5 (N-ch instruction is executed High-level output ILOH1 VOUT = VDD leakage current SCK, SO/SB0, SB1, ports 2, 3, 6, 7, ports 4, 5 (pull-up resistor provided), BP0-BP7 ILOH2 VOUT = 13 V Ports 4, 5 (N-ch open-drain) 20 µA ILOL VOUT = 0 V ­3 µA Internal pull-up RL1 VIN = 0 V resistor R L2 Low-level output leakage current 62 Ports 0, 1, 2, 3, 6, 7 (except P00 pin) 50 100 200 k Ports 4, 5 (mask option selected) 15 30 60 k Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A DC Characteristics (TA = ­40 to +85°C, VDD = 1.8 to 5.5 V) Parameter LCD drive Symbol VLCD MIN. Note 2 I VAC LCD split MAX. Unit resistorNote 3 VODC 2.2 V DD V 1.8 V DD V 1 200 k 10 20 k 0 ±0.2 V 0 VLCD0 = VLCD ±0.2 V 6.6 mA VLCD1 = VLCD × 2/3 VLCD2 = VLCD × 1/3 (common) LCD output voltage µA 100 5 IO = ±1.0 µA Note 4 4 50 VAC0 = 1, V DD = 2.0 V ±10% RLCD2 LCD output voltage VAC0 = 0 RLCD1 deviation TYP. VAC0 = 1 voltageNote 1 VAC current Conditions VODS 1.8 V VLCD VDD IO = ±0.5 µA deviationNote 4 (segment) Supply I DD1 currentNotes 2, 5 I DD2 I DD1 I DD2 I DD3 6.00 MHzNote 6 crystal oscillation C1 = C2 = 22 pF Note 6 4.19 MHz crystal oscillation C1 = C2 = 22 pF 32.768 kHz Note 9 crystal oscillation VDD = 5.0 V ±10%Note 7 VDD = 3.0 V ±10%Note 8 2.2 0.6 2.0 mA HALT VDD = 5.0 V ±10% 0.72 2.1 mA mode VDD = 3.0 V ±10% 0.27 0.8 mA 1.7 5.1 mA VDD = 5.0 V ±10%Note 7 VDD = 3.0 V ±10%Note 8 0.3 0.9 mA HALT VDD = 5.0 V ±10% 0.7 2.0 mA mode VDD = 3.0 V ±10% 0.23 0.7 mA Low voltage modeNote 10 VDD = 3.0 V ±10% 15 45 µA Low current consumption mode Note 11 VDD = 2.0 V ±10% 8 24 µA VDD = 3.0 V, TA = 25°C 15 30 µA VDD = 3.0 V ±10% 12 36 µA VDD = 3.0 V, TA = 25°C 12 24 µA HALT mode I DD5 XT1 = 0 VNote 12 STOP mode Low voltage modeNote 10 VDD = 3.0 V ±10% 8.5 25 µA VDD = 2.0 V ±10% 4 12 µA V DD = 3.0 V, T A = 25°C 8.5 17 µA Low current consumption mode Note 11 I DD4 VDD = 3.0 V ±10% 3.5 12 µA 3.5 7 µA 0.05 10 µA 0.02 5 µA 0.02 3 µA V DD = 3.0 V, T A = 25°C VDD = 5.0 V ±10% VDD = 3.0 V ±10% T A = 25°C When 1.8 V VDD < 2.7 V, T A = ­10 to +85°C. Clear VAC0 to 0 in the low current consumption mode and STOP mode. When VAC0 is set to 1, the current increases by about 1 µA. 3. Either R LCD1 or R LCD2 can be selected by mask option. 4. Voltage deviation is the difference between the ideal values (VLCDn; n = 0, 1, 2) of the segment and common outputs and the output voltage. 5. The current flowing through the internal pull-up resistor and the LCD divider resistor is not included. 6. Including the case when the subsystem clock oscillates. 7. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011. 8. When the device operates in low-speed mode with PCC set to 0000. 9. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001 and oscillation of the main system clock stopped. 10. When the sub-oscillator control register (SOS) is set to 0000. 11. When SOS is set to 0010. 12. When SOS is set to 00X1, and the feedback resistor of the sub-oscillator is not used (X: don't care). Notes 1. 2. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 63 µPD753012A PD753012A, 753016A, 753017A AC Characteristics (TA = ­40 to +85°C, VDD = 1.8 to 5.5 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 0.67 64 µs (minimum instruction main system clock 0.95 64 µs execution time = 1 Operates with 114 125 µs machine cycle) subsystem clock 0 1 MHz 0 275 kHz CPU clock cycle time Note 1 TI0, TI1, TI2 input frequency tCY fTI VDD = 2.7 to 5.5 V Operates with VDD = 2.7 to 5.5 V 122 µs 1.8 µs IM02 = 0 Note 2 µs IM02 = 1 10 µs 10 µs KR0-KR7 tTIH, tTIL 0.48 INT1, 2, 4 TI0, TI1, TI2 input high-, 10 µs 10 µs VDD = 2.7 to 5.5 V low-level width Interrupt input high-, tINTH, t INTL INT0 low-level width RESET low-level width Notes 1. tRSL The cycle time of the CPU clock () is determined by the oscillation frequency tCY vs VDD of the connected resonator, the system (with main system clock) clock control register (SCC), and 64 60 processor clock control register (PCC). The figure on the right shows the supply voltage V DD vs. cycle time t CY characteristics when the device operates 5 with the main system clock. 4 2t CY or 128/fX depending on the setting of the interrupt mode register (IM0). Operation guaranteed range Cycle time tCY [ µ s] 2. 6 3 2 1 0.5 0 1 2 3 4 5 Supply voltage VDD [V] 64 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 6 µPD753012A PD753012A, 753016A, 753017A Serial transfer operation 2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (TA = ­40 to +85°C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol t KL1 VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 1300 SINote 1 setup time t SIK1 tKCY1/2­50 VDD = 2.7 to 5.5 V ns ns 150 SINote 1 hold time t KSI1 VDD = 2.7 to 5.5 V ns 400 t KSO1 output delay time RL = 1 k, Note 2 VDD = 2.7 to 5.5 V ns 600 (from SCK ) SCK SONote 1 ns 500 (to SCK ) Notes 1. ns tKCY1/2­150 VDD = 2.7 to 5.5 V tKH1 ns 3800 SCK high-, low-level width t KCY1 Conditions ns 0 250 ns 0 CL = 100 pF 1000 ns Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. 2. 2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (TA = ­40 to +85°C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol t KL2 VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 800 VDD = 2.7 to 5.5 V t SIK2 400 VDD = 2.7 to 5.5 V t KSI2 VDD = 2.7 to 5.5 V output delay time ns 400 t KSO2 RL = 1 k, Note 2 VDD = 2.7 to 5.5 V CL = 100 pF ns 600 (from SCK ) SCK SONote 1 ns 150 SINote 1 hold time 2. ns ns 100 (to SCK ) Notes 1. ns 1600 tKH2 SINote 1 setup time ns 3200 SCK high-, low-level width t KCY2 Conditions ns 0 300 ns 0 1000 ns Read as SB0 or SB1 when using the 2-wire serial I/O mode. RL and CL respectively indicate the load resistance and load capacitance of the SO output line. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 65 µPD753012A PD753012A, 753016A, 753017A SBI mode (SCK ··· internal clock output (master): (TA = ­40 to +85°C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKL3 VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 1300 SB0, 1 setup time tSIK3 t KCY3/2­50 VDD = 2.7 to 5.5 V ns ns tKCY3/2­150 VDD = 2.7 to 5.5 V tKH3 ns 3800 SCK high-, low-level width tKCY3 Conditions ns 150 SB0, 1 hold time (from SCK ) tKSI3 SCK SB0, 1 output tKSO3 delay time ns 500 (to SCK ) ns tKCY3/2 RL = 1 k, Note VDD = 2.7 to 5.5 V ns 250 0 CL = 100 pF 0 1000 ns ns SCK SB0, 1 tKSB tKCY3 ns SB0, 1 SCK tSBK tKCY3 ns SB0, 1 low-level width tSBL tKCY3 ns SB0, 1 high-level width tSBH tKCY3 ns Note RL and C L respectively indicate the load resistance and load capacitance of the SB0, 1 output line. SBI mode (SCK ··· external clock input (slave): (TA = ­40 to +85°C, VDD = 1.8 to 5.5 V) Parameter SCK cycle time Symbol tKL4 VDD = 2.7 to 5.5 V MIN. TYP. MAX. Unit 800 VDD = 2.7 to 5.5 V tSIK4 ns 400 VDD = 2.7 to 5.5 V ns 1600 tKH4 SB0, 1 setup time ns 3200 SCK high-, low-level width tKCY4 Conditions ns 100 SB0, 1 hold time (from SCK ) tKSI4 SCK SB0, 1 output tKSO4 delay time ns 150 (to SCK ) ns tKCY4/2 RL = 1 k, Note VDD = 2.7 to 5.5 V CL = 100 pF ns 0 300 0 1000 ns ns SCK SB0, 1 tKSB tKCY4 ns SB0, 1 SCK tSBK tKCY4 ns SB0, 1 low-level width tSBL tKCY4 ns SB0, 1 high-level width tSBH tKCY4 ns Note 66 RL and C L respectively indicate the load resistance and load capacitance of the SB0, 1 output line. Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A AC timing test points (except X1 and XT1 inputs) VIH (MIN.) VIH (MIN.) VIL (MAX.) VIL (MAX.) VOH (MIN.) VOH (MIN.) VOL (MAX.) VOL (MAX.) Clock timing 1/fX tXL tXH VDD ­ 0.1 V X1 input 0.1 V 1/fXT tXTL tXTH VDD ­ 0.1 V XT1 input 0.1 V TI0, TI1, TI2 timing 1/fTI tTIL tTIH TI0, TI1, TI2 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 67 µPD753012A PD753012A, 753016A, 753017A Serial transfer timing 3-wire serial I/O mode tKCY1,2 tKL1,2 tKH1,2 SCK tSIK1,2 tKSI1,2 Input data SI tKSO1,2 Output data SO 2-wire serial I/O mode tKCY1,2 tKL1,2 tKH1,2 SCK tSIK1,2 tKSI1,2 SB0, 1 tKSO1,2 68 Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 µPD753012A PD753012A, 753016A, 753017A Serial transfer timing Bus release signal transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSBL tSBH tSIK3, 4 tSBK tKSI3, 4 SB0, 1 tKSO3, 4 Command signal transfer tKCY3, 4 tKL3, 4 tKH3, 4 SCK tKSB tSIK3, 4 tSBK tKSI3, 4 SB0, 1 tKSO3, 4 Interrupt input timing tINTL tINTH INT0, 1, 2, 4 KR0-7 RESET input timing tRSL RESET Data Sheet U11662EJ2V1DS00 U11662EJ2V1DS00 69 µPD753012A PD753012A, 753016A, 753017A Data retention characteristics of data memory in STOP mode and at low supply voltage (TA = ­40 to +85°C) Parameter Symbol Conditions MIN. Data retention power supply voltage VDDDR Release signal setup time tSREL tWAIT MAX. Unit 5.5 V 0 Oscillation stabilization wait time Note 1 TYP. 1.8 Notes 1. µs Released by RESET Note 2 ms Released by interrupt request Note 3 ms The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable operation when oscillation is started. 2. Either 217/fX o