V850ES/JG2 PD70F3715 PD70F3716 PD70F3717 PD70F3718 PD70F3719 U17715EJ1V0UD00 - Datasheet Archive

 

V850ES/JG2 32-Bit Single-Chip Microcontrollers Hardware µPD70F3715 µPD70F3716 µPD70F3717 µPD70F3718

 

Preliminary User's Manual V850ES/JG2 V850ES/JG2 32-Bit Single-Chip Microcontrollers Hardware µPD70F3715 PD70F3715 µPD70F3716 PD70F3716 µPD70F3717 PD70F3717 µPD70F3718 PD70F3718 µPD70F3719 PD70F3719 Document No. U17715EJ1V0UD00 U17715EJ1V0UD00 (1st edition) Date Published October 2005 N CP(K) 2005 Printed in Japan [MEMO] 2 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 3 IECUBE and MINICUBE are registered trademarks of NEC Electronics Corporation in Japan and Germany. · The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the product prior to its production. · Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. · No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. · NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. · Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. · While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. · NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics products depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above). M5D 02. 11-1 4 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors. They will verify: · Device availability · Ordering information · Product release schedule · Availability of related technical literature · Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) · Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. [GLOBAL SUPPORT] http://www.necel.com/en/support/support.html NEC Electronics America, Inc. (U.S.) NEC Electronics (Europe) GmbH NEC Electronics Hong Kong Ltd. Santa Clara, California Tel: 408-588-6000 800-366-9782 Duesseldorf, Germany Tel: 0211-65030 Hong Kong Tel: 2886-9318 · Sucursal en España Madrid, Spain Tel: 091-504 27 87 · Succursale Française Vélizy-Villacoublay, France Tel: 01-30-67 58 00 · Filiale Italiana Milano, Italy Tel: 02-66 75 41 · Branch The Netherlands Eindhoven, The Netherlands Tel: 040-265 40 10 · Tyskland Filial NEC Electronics Hong Kong Ltd. Seoul Branch Seoul, Korea Tel: 02-558-3737 NEC Electronics Shanghai Ltd. Shanghai, P.R. China Tel: 021-5888-5400 NEC Electronics Taiwan Ltd. Taipei, Taiwan Tel: 02-2719-2377 NEC Electronics Singapore Pte. Ltd. Novena Square, Singapore Tel: 6253-8311 Taeby, Sweden Tel: 08-63 87 200 · United Kingdom Branch Milton Keynes, UK Tel: 01908-691-133 J05.6 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 5 PREFACE Readers This manual is intended for users who wish to understand the functions of the V850ES/JG2 V850ES/JG2 and design application systems using these products. Purpose This manual is intended to give users an understanding of the hardware functions of the V850ES/JG2 V850ES/JG2 shown in the Organization below. Organization This manual is divided into two parts: Hardware (this manual) and Architecture (V850ES V850ES Architecture User's Manual). Hardware Architecture · Pin functions · CPU function · Register set · On-chip peripheral functions · Instruction format and instruction set · Flash memory programming · Interrupts and exceptions · Electrical specifications (target) How to Read This Manual · Data types · Pipeline operation It is assumed that the readers of this manual have general knowledge in the fields of electrical engineering, logic circuits, and microcontrollers. To understand the overall functions of the V850ES/JG2 V850ES/JG2 Read this manual according to the CONTENTS. To find the details of a register where the name is known Use APPENDIX A REGISTER INDEX. To know the electrical specifications of the V850ES/JG2 V850ES/JG2 See CHAPTER 28 ELECTRICAL SPECIFICATIONS (TARGET). To understand the details of an instruction function Refer to the V850ES V850ES Architecture User's Manual available separately. Register format The name of the bit whose number is in angle brackets () in the figure of the register format of each register is defined as a reserved word in the device file. The "yyy bit of the xxx register" is described as the "xxx.yyy bit" in this manual. Note with caution that if "xxx.yyy" is described as is in a program, however, the compiler/assembler cannot recognize it correctly. 6 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD Conventions Data significance: Higher digits on the left and lower digits on the right Active low representation: xxx (overscore over pin or signal name) Memory map address: Higher addresses on the top and lower addresses on the bottom Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information Numeric representation: Binary . xxxx or xxxxB Decimal . xxxx Hexadecimal . xxxxH Prefix indicating power of 2 (address space, memory capacity): K (kilo): 210 = 1,024 M (mega): 220 = 1,0242 G (giga): 230 = 1,0243 Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents related to V850ES/JG2 V850ES/JG2 Document Name Document No. V850ES V850ES Architecture User's Manual U15943E U15943E V850ES/JG2 V850ES/JG2 Hardware User's Manual This manual Documents related to development tools Document Name CA850 CA850 Ver. 3.00 C Compiler Package Document No. Operation U17293E U17293E C Language U17291E U17291E Assembly Language U17292E U17292E Link Directives U17294E U17294E PM+ Ver. 6.00 Project Manager U17178E U17178E ID850QB ID850QB Ver. 3.10 Integrated Debugger Operation U17435E U17435E SM850 SM850 Ver. 2.50 System Simulator Operation U16218E U16218E SM850 SM850 Ver. 2.00 or Later System Simulator External Part User Open U14873E U14873E Interface Specification SM+ System Simulator U17247E U17247E Basics U13430E U13430E U17419E U17419E Technical U13431E U13431E Task Debugger RX850 RX850 Pro Ver. 3.20 Real-Time OS U17246E U17246E Installation RX850 RX850 Ver. 3.20 or Later Real-Time OS Operation User Open Interface U17420E U17420E Basics U13773E U13773E Installation U17421E U17421E Technical U13772E U13772E Task Debugger U17422E U17422E AZ850 AZ850 Ver. 3.30 System Performance Analyzer U17423E U17423E PG-FP4 Flash Memory Programmer U15260E U15260E Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 7 CONTENTS CHAPTER 1 INTRODUCTION.17 1.1 1.2 1.3 1.4 1.5 1.6 General .17 Features.20 Application Fields.21 Ordering Information.21 Pin Configuration (Top View) .22 Function Block Configuration .25 1.6.1 Internal block diagram.25 1.6.2 Internal units .26 CHAPTER 2 PIN FUNCTIONS .29 2.1 2.2 2.3 2.4 List of Pin Functions .29 Pin States .39 Pin I/O Circuit Types, I/O Buffer Power Supplies, and Connection of Unused Pins .40 Cautions .44 CHAPTER 3 CPU FUNCTION .45 3.1 3.2 Features.45 CPU Register Set .46 3.2.1 3.2.2 3.3 Program register set .47 System register set .48 Operation Modes .54 3.3.1 3.4 Specifying operation mode .54 Address Space.55 3.4.1 CPU address space .55 3.4.2 Wraparound of CPU address space .56 3.4.3 Memory map.57 3.4.4 Areas .59 3.4.5 Recommended use of address space.66 3.4.6 Peripheral I/O registers .69 3.4.7 Special registers .79 3.4.8 Cautions.83 CHAPTER 4 PORT FUNCTIONS .87 4.1 4.2 4.3 Features.87 Basic Port Configuration .87 Port Configuration .88 4.3.1 4.3.2 Port 1 .96 4.3.3 Port 3 .97 4.3.4 Port 4 .103 4.3.5 Port 5 .105 4.3.6 Port 7 .109 4.3.7 8 Port 0 .93 Port 9 .111 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 4.3.8 Port CT . 121 4.3.10 Port DH. 123 4.3.11 4.4 4.5 4.6 Port CM . 119 4.3.9 Port DL . 125 Block Diagrams .128 Port Register Settings When Alternate Function Is Used.158 Cautions .166 4.6.1 Cautions on setting port pins . 166 4.6.2 Cautions on bit manipulation instruction for port n register (Pn) . 169 4.6.3 Cautions on on-chip debug pins . 170 4.6.4 Cautions on P05/INTP2/DRST P05/INTP2/DRST pin . 170 4.6.5 Cautions on P10, P11, and P53 pins when power is turned on . 170 4.6.6 Hysteresis characteristics . 170 CHAPTER 5 BUS CONTROL FUNCTION.171 5.1 5.2 Features.171 Bus Control Pins .172 5.2.1 5.2.2 5.3 5.4 5.5 Pin status when internal ROM, internal RAM, or on-chip peripheral I/O is accessed. 172 Pin status in each operation mode . 172 Memory Block Function.173 External Bus Interface Mode Control Function.174 Bus Access .175 5.5.1 Bus size setting function. 175 5.5.3 5.6 Number of clocks for access. 175 5.5.2 Access by bus size . 176 Wait Function.183 5.6.1 External wait function . 184 5.6.3 Relationship between programmable wait and external wait . 185 5.6.4 5.7 5.8 Programmable wait function . 183 5.6.2 Programmable address wait function . 186 Idle State Insertion Function .187 Bus Hold Function .188 5.8.1 Bus hold procedure . 189 5.8.3 5.9 5.10 Functional outline . 188 5.8.2 Operation in power save mode. 189 Bus Priority .190 Bus Timing .191 CHAPTER 6 CLOCK GENERATION FUNCTION .197 6.1 6.2 6.3 6.4 Overview.197 Configuration .198 Registers .200 Operation.205 6.4.1 6.5 Operation of each clock. 205 6.4.2 Clock output function . 205 PLL Function.206 6.5.1 Overview . 206 6.5.2 Registers . 206 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 9 6.5.3 Usage .209 CHAPTER 7 16-BIT 16-BIT TIMER/EVENT COUNTER P (TMP) . 210 7.1 7.2 7.3 7.4 7.5 Overview. 210 Functions. 210 Configuration . 211 Registers . 213 Operation. 225 7.5.1 External event count mode (TPnMD2 to TPnMD0 bits = 001) .236 7.5.3 External trigger pulse output mode (TPnMD2 to TPnMD0 bits = 010) .244 7.5.4 One-shot pulse output mode (TPnMD2 to TPnMD0 bits = 011).256 7.5.5 PWM output mode (TPnMD2 to TPnMD0 bits = 100) .263 7.5.6 Free-running timer mode (TPnMD2 to TPnMD0 bits = 101) .272 7.5.7 Pulse width measurement mode (TPnMD2 to TPnMD0 bits = 110).289 7.5.8 7.6 7.7 Interval timer mode (TPnMD2 to TPnMD0 bits = 000) .226 7.5.2 Timer output operations .295 Selector Function . 296 Cautions . 297 CHAPTER 8 16-BIT 16-BIT TIMER/EVENT COUNTER Q (TMQ). 298 8.1 8.2 8.3 8.4 8.5 Overview. 298 Functions. 298 Configuration . 299 Registers . 301 Operation. 317 8.5.1 8.5.2 External event count mode (TQ0MD2 to TQ0MD0 bits = 001) .327 8.5.3 External trigger pulse output mode (TQ0MD2 to TQ0MD0 bits = 010) .336 8.5.4 One-shot pulse output mode (TQ0MD2 to TQ0MD0 bits = 011).349 8.5.5 PWM output mode (TQ0MD2 to TQ0MD0 bits = 100) .358 8.5.6 Free-running timer mode (TQ0MD2 to TQ0MD0 bits = 101) .369 8.5.7 Pulse width measurement mode (TQ0MD2 to TQ0MD0 bits = 110).389 8.5.8 8.6 Interval timer mode (TQ0MD2 to TQ0MD0 bits = 000) .318 Timer output operations .395 Cautions . 396 CHAPTER 9 16-BIT 16-BIT INTERVAL TIMER M (TMM) . 397 9.1 9.2 9.3 9.4 Overview. 397 Configuration . 398 Register . 399 Operation. 400 9.4.1 Interval timer mode .400 9.4.2 Cautions.404 CHAPTER 10 WATCH TIMER FUNCTIONS . 405 10.1 10.2 10.3 10 Functions. 405 Configuration . 406 Control Registers . 408 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 10.4 Operation.412 10.4.1 Operation as watch timer. 412 10.4.2 Operation as interval timer. 413 10.4.3 Cautions . 414 CHAPTER 11 FUNCTIONS OF WATCHDOG TIMER 2.415 11.1 11.2 11.3 11.4 Functions .415 Configuration .416 Registers .417 Operation.419 CHAPTER 12 REAL-TIME OUTPUT FUNCTION (RTO) .420 12.1 12.2 12.3 12.4 12.5 12.6 Function .420 Configuration .421 Registers .423 Operation.425 Usage.426 Cautions .426 CHAPTER 13 A/D CONVERTER .427 13.1 13.2 13.3 13.4 13.5 Overview.427 Functions .427 Configuration .428 Registers .431 Operation.442 13.5.1 13.5.2 Conversion operation timing . 443 13.5.3 Trigger mode . 444 13.5.4 Operation mode. 446 13.5.5 13.6 13.7 Basic operation. 442 Power-fail compare mode. 450 Cautions .455 How to Read A/D Converter Characteristics Table.459 CHAPTER 14 D/A CONVERTER .463 14.1 14.2 14.3 14.4 Functions .463 Configuration .463 Registers .464 Operation.466 14.4.1 Operation in normal mode . 466 14.4.2 Operation in real-time output mode . 466 14.4.3 Cautions . 467 CHAPTER 15 ASYNCHRONOUS SERIAL INTERFACE A (UARTA) .468 15.1 Mode Switching of UARTA and Other Serial Interfaces.468 15.1.1 CSIB4 and UARTA0 mode switching . 468 15.1.2 UARTA2 and I2C00 I2C00 mode switching . 469 15.1.3 UARTA1 and I2C02 I2C02 mode switching . 470 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 11 15.2 15.3 15.4 15.5 15.6 Features. 471 Configuration . 472 Registers . 474 Interrupt Request Signals. 480 Operation. 481 15.6.1 Data format .481 15.6.2 SBF transmission/reception format .483 15.6.3 SBF transmission.485 15.6.4 SBF reception .486 15.6.5 UART transmission.487 15.6.6 Continuous transmission procedure.488 15.6.7 UART reception .490 15.6.8 Reception errors .491 15.6.9 Parity types and operations .493 15.6.10 Receive data noise filter.494 15.7 15.8 Dedicated Baud Rate Generator . 495 Cautions . 503 CHAPTER 16 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIB). 504 16.1 Mode Switching of CSIB and Other Serial Interfaces . 504 16.1.1 16.2 16.3 16.4 16.5 CSIB4 and UARTA0 mode switching.504 16.1.2 CSIB0 and I2C01 I2C01 mode switching .505 Features. 506 Configuration . 507 Registers . 509 Operation. 516 16.5.1 Single transfer mode (master mode, reception mode) .517 16.5.3 Continuous mode (master mode, transmission/reception mode) .518 16.5.4 Continuous mode (master mode, reception mode) .519 16.5.5 Continuous reception mode (error) .520 16.5.6 Continuous mode (slave mode, transmission/reception mode).521 16.5.7 Continuous mode (slave mode, reception mode).522 16.5.8 16.6 16.7 16.8 Single transfer mode (master mode, transmission/reception mode) .516 16.5.2 Clock timing .523 Output Pins . 525 Operation Flow. 526 Baud Rate Generator. 532 16.8.1 16.9 Baud rate generation .533 Cautions . 534 CHAPTER 17 I2C BUS . 535 17.1 Mode Switching of I2C Bus and Other Serial Interfaces . 535 17.1.1 17.1.2 12 CSIB0 and I2C01 I2C01 mode switching .536 17.1.3 17.2 17.3 17.4 UARTA2 and I2C00 I2C00 mode switching.535 UARTA1 and I2C02 I2C02 mode switching.537 Features. 538 Configuration . 539 Registers . 543 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 17.5 I2C Bus Mode Functions .559 17.5.1 17.6 Pin configuration. 559 2 I C Bus Definitions and Control Methods .560 17.6.1 17.6.2 Addresses . 561 17.6.3 Transfer direction specification . 562 17.6.4 ACK . 563 17.6.5 Stop condition. 564 17.6.6 Wait state . 565 17.6.7 17.7 Start condition. 560 Wait state cancellation method. 567 2 I C Interrupt Request Signals (INTIICn).568 17.7.1 17.7.2 Slave device operation (when receiving slave address data (address match). 571 17.7.3 Slave device operation (when receiving extension code) . 575 17.7.4 Operation without communication . 579 17.7.5 Arbitration loss operation (operation as slave after arbitration loss) . 579 17.7.6 17.8 17.9 17.10 17.11 17.12 17.13 17.14 Master device operation . 568 Operation when arbitration loss occurs (no communication after arbitration loss) . 581 Interrupt Request Signal (INTIICn) Generation Timing and Wait Control .588 Address Match Detection Method .590 Error Detection .590 Extension Code .590 Arbitration .591 Wakeup Function .592 Communication Reservation .593 17.14.1 When communication reservation function is enabled (IICFn.IICRSVn bit = 0) . 593 17.14.2 When communication reservation function is disabled (IICFn.IICRSVn bit = 1) . 597 17.15 Cautions .598 17.16 Communication Operations .599 17.16.1 Master operation 1. 599 17.16.2 Master operation 2. 601 17.16.3 Slave operation. 602 17.17 Timing of Data Communication .605 CHAPTER 18 DMA FUNCTION (DMA CONTROLLER) .612 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 18.10 18.11 18.12 18.13 Features.612 Configuration .613 Registers .614 Transfer Targets .621 Transfer Modes.621 Transfer Types.622 DMA Channel Priorities .623 Time Related to DMA Transfer.623 DMA Transfer Start Factors .624 DMA Abort Factors.625 End of DMA Transfer.625 Operation Timing.625 Cautions .630 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 13 CHAPTER 19 INTERRUPT/EXCEPTION PROCESSING FUNCTION. 635 19.1 19.2 Features. 635 Non-Maskable Interrupts . 639 19.2.1 Restore .642 19.2.3 19.3 Operation .641 19.2.2 NP flag .643 Maskable Interrupts. 644 19.3.1 Restore .646 19.3.3 Priorities of maskable interrupts.647 19.3.4 Interrupt control register (xxICn) .651 19.3.5 Interrupt mask registers 0 to 3 (IMR0 to IMR3).653 19.3.6 In-service priority register (ISPR).655 19.3.7 ID flag .656 19.3.8 19.4 Operation .644 19.3.2 Watchdog timer mode register 2 (WDTM2) .656 Software Exception . 657 19.4.1 19.4.2 Restore .658 19.4.3 19.5 Operation .657 EP flag .659 Exception Trap. 660 19.5.1 19.5.2 19.6 Illegal opcode definition .660 Debug trap .662 External Interrupt Request Input Pins (NMI and INTP0 to INTP7) . 664 19.6.1 19.7 19.8 19.9 Noise elimination .664 19.6.2 Edge detection.664 Interrupt Acknowledge Time of CPU . 669 Periods in Which Interrupts Are Not Acknowledged by CPU . 670 Cautions . 670 CHAPTER 20 KEY INTERRUPT FUNCTION . 671 20.1 20.2 20.3 Function. 671 Register . 672 Cautions . 672 CHAPTER 21 STANDBY FUNCTION . 673 21.1 21.2 21.3 Overview. 673 Registers . 675 HALT Mode. 678 21.3.1 21.4 Setting and operation status .678 21.3.2 Releasing HALT mode.678 IDLE1 Mode . 680 21.4.1 21.4.2 21.5 Setting and operation status .680 Releasing IDLE1 mode .680 IDLE2 Mode . 682 21.5.1 Releasing IDLE2 mode .682 21.5.3 14 Setting and operation status .682 21.5.2 Securing setup time when releasing IDLE2 mode .684 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 21.6 STOP Mode .685 21.6.1 21.6.2 Releasing STOP mode. 685 21.6.3 21.7 Setting and operation status . 685 Securing oscillation stabilization time when releasing STOP mode. 688 Subclock Operation Mode .689 21.7.1 21.7.2 21.8 Setting and operation status . 689 Releasing subclock operation mode . 689 Sub-IDLE Mode .691 21.8.1 Setting and operation status . 691 21.8.2 Releasing sub-IDLE mode. 691 CHAPTER 22 RESET FUNCTIONS.693 22.1 22.2 22.3 Overview.693 Registers to Check Reset Source.694 Operation.695 22.3.1 Reset operation via RESET pin . 695 22.3.2 Reset operation by watchdog timer 2 . 697 22.3.3 Reset operation by low-voltage detector. 699 22.3.4 Operation after reset release . 700 22.3.5 Reset function operation flow . 703 CHAPTER 23 CLOCK MONITOR .704 23.1 23.2 23.3 23.4 Functions .704 Configuration .704 Register .705 Operation.706 CHAPTER 24 LOW-VOLTAGE DETECTOR (LVI).709 24.1 24.2 24.3 24.4 Functions .709 Configuration .709 Registers .710 Operation.712 24.4.1 24.5 24.6 To use for internal reset signal . 712 24.4.2 To use for interrupt . 713 RAM Retention Voltage Detection Operation.714 Emulation Function.715 CHAPTER 25 REGULATOR .716 25.1 25.2 Outline .716 Operation.717 CHAPTER 26 FLASH MEMORY.718 26.1 26.2 26.3 26.4 Features.718 Memory Configuration .719 Functional Outline.720 Rewriting by Dedicated Flash Programmer .722 26.4.1 Programming environment . 722 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 15 26.4.2 Flash memory control .731 26.4.4 Selection of communication mode .732 26.4.5 Communication commands .733 26.4.6 26.5 Communication mode .723 26.4.3 Pin connection .734 Rewriting by Self Programming . 738 26.5.1 Overview.738 26.5.2 Features.739 26.5.3 Standard self programming flow .740 26.5.4 Flash functions.741 26.5.5 Pin processing .741 26.5.6 Internal resources used .742 CHAPTER 27 ON-CHIP DEBUG FUNCTION . 743 27.1 27.2 27.3 27.4 27.5 27.6 Features. 743 Connection Circuit Example. 743 Interface Signals . 744 Register . 746 Operation. 747 ROM Security Function. 748 27.6.1 27.7 Security ID .748 27.6.2 Setting .749 Cautions . 750 CHAPTER 28 ELECTRICAL SPECIFICATIONS (TARGET). 751 CHAPTER 29 PACKAGE DRAWINGS . 785 APPENDIX A REGISTER INDEX . 787 APPENDIX B INSTRUCTION SET LIST . 797 B.1 B.2 16 Conventions . 797 Instruction Set (in Alphabetical Order) . 800 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD CHAPTER 1 INTRODUCTION The V850ES/JG2 V850ES/JG2 is one of the products in the NEC Electronics V850 Series of single-chip microcontrollers designed for low-power operation for real-time control applications. 1.1 General The V850ES/JG2 V850ES/JG2 is a 32-bit single-chip microcontroller that includes the V850ES V850ES CPU core and peripheral functions such as ROM/RAM, a timer/counter, serial interfaces, an A/D converter, and a D/A converter. In addition to high real-time response characteristics and 1-clock-pitch basic instructions, the V850ES/JG2 V850ES/JG2 features multiply instructions, saturated operation instructions, bit manipulation instructions, etc., realized by a hardware multiplier, as optimum instructions for digital servo control applications. Moreover, as a real-time control system, the V850ES/JG2 V850ES/JG2 enables an extremely high cost-performance for applications that require low power consumption, such as home audio, printers, and digital home electronics. Table 1-1 lists the products of the V850ES/JG2 V850ES/JG2. A model of the V850ES/JG2 V850ES/JG2 with expanded I/O, timer/counter, and serial interface functions, V850ES/JJ2 V850ES/JJ2, is also available. See Table 1-2 V850ES/JJ2 V850ES/JJ2 Product List. Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 17 CHAPTER 1 INTRODUCTION Table 1-1. V850ES/JG2 V850ES/JG2 Product List Part Number µPD70F3715 PD70F3715 µPD70F3716 PD70F3716 µPD70F3717 PD70F3717 µPD70F3718 PD70F3718 µPD70F3719 PD70F3719 Internal Flash memory 128 KB 256 KB 384 KB 512 KB 640 KB memory RAM 12 KB 24 KB 32 KB 40 KB 48 KB Memory Logical space 64 MB space External memory area 16 MB Address bus: 22 bits External bus interface Data bus: 8/16 bits Multiplex bus mode/separate bus mode 32 bits × 32 registers General-purpose register Main clock (oscillation frequency) Ceramic/crystal/external clock (in PLL mode: fX = 2.5 to 5 MHz (multiplied by 4) or fX = 2.5 MHz (multiplied by 8), in clock through mode: fX = 2.5 to 10 MHz) Subclock (oscillation frequency) Crystal/external clock (fXT = 32.768 kHz) Internal oscillator fR = 200 kHz (TYP.) Minimum instruction execution time 50 ns (main clock (fXX) = 20 MHz) 32 × 32 = 64: 200 to 250 ns (at 20 MHz) DSP function 32 × 32 + 32 = 32: 300 ns (at 20 MHz) 16 × 16 = 32: 50 to 100 ns (at 20 MHz) 16 × 16 + 32 = 32: 150 ns (at 20 MHz) I/O port Timer I/O: 84 (of which 5 V tolerant/N-ch open-drain output selectable: 40) 16-bit timer/event counter P: 6 channels 16-bit timer/event counter Q: 1 channel 16-bit interval timer M: 1 channel Watch timer: 1 channel Watchdog timer: 1 channel 6 bits × 1 channel Real-time output port 10-bit resolution × 12 channels A/D converter 8-bit resolution × 2 channels D/A converter Serial interface UART/CSI: 1 channel 2 UART/I C bus: 2 channels CSI: 3 channels 2 CSI/I C bus: DMA controller Interrupt source Power save function Reset On-chip debug function Operating power supply voltage Operating ambient temperature Package 1 channel 4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory) Note External: 9 (9) , internal: 48 HALT/IDLE1/IDLE2/STOP/subclock/sub-DLE mode RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI) Provided (RUN/break) 2.85 to 3.6 V -40 to +85°C 100-pin plastic LQFP (fine pitch) (14 × 14 mm) 100-pin plastic QFP (14 × 20 mm) Note The figure in parentheses indicates the number of external interrupts that can release STOP mode. 18 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD CHAPTER 1 INTRODUCTION Table 1-2. V850ES/JJ2 V850ES/JJ2 Product List Part Number µPD70F3720 PD70F3720 µPD70F3721 PD70F3721 µPD70F3722 PD70F3722 µPD70F3723 PD70F3723 µPD70F3724 PD70F3724 Internal Flash memory 128 KB 256 KB 384 KB 512 KB 640 KB memory RAM 12 KB 24 KB 32 KB 40 KB 48 KB Memory Logical space 64 MB space External memory area 16 MB Address bus: 24 bits External bus interface Data bus: 8/16 bits Multiplex bus mode/separate bus mode Chip select signal: 4 32 bits × 32 registers General-purpose register Main clock (oscillation frequency) Ceramic/crystal/external clock (in PLL mode: fX = 2.5 to 5 MHz (multiplied by 4) or fX = 2.5 MHz (multiplied by 8), in clock through mode: fX = 2.5 to 10 MHz) Subclock (oscillation frequency) Crystal/external clock (fXT = 32.768 kHz) Internal oscillator fR = 200 kHz (TYP.) Minimum instruction execution time 50 ns (main clock (fXX) = 20 MHz) 32 × 32 = 64: 200 to 250 ns (at 20 MHz) DSP function 32 × 32 + 32 = 32: 300 ns (at 20 MHz) 16 × 16 = 32: 50 to 100 ns (at 20 MHz) 16 × 16 + 32 = 32: 150 ns (at 20 MHz) I/O port Timer I/O: 128 (of which 5 V tolerant/N-ch open-drain output selectable: 60) 16-bit timer/event counter P: 9 channels 16-bit timer/event counter Q: 1 channel 16-bit interval timer M: 1 channel Watch timer: 1 channel Watchdog timer: 1 channel 6 bits × 2 channels Real-time output port 10-bit resolution × 16 channels A/D converter 8-bit resolution × 2 channels D/A converter Serial interface UART: 1 channel UART/CSI: 1 channel 2 UART/I C bus: 2 channels CSI: 4 channels 2 CSI/I C bus: DMA controller Interrupt source Power save function Reset On-chip debug function Operating power supply voltage Operating ambient temperature Package 1 channel 4 channels (transfer target: on-chip peripheral I/O, internal RAM, external memory) External: 10 (10) Note , internal: 61 HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode RESET pin input, watchdog timer 2 (WDT2), clock monitor (CLM), low-voltage detector (LVI) Provided (RUN/break) 2.85 to 3.6 V -40 to +85°C 144-pin plastic LQFP (fine pitch) (20 × 20 mm) Note The figure in parentheses indicates the number of external interrupts that can release STOP mode. Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 19 CHAPTER 1 INTRODUCTION 1.2 Features Minimum instruction execution time: 50 ns (operating with main clock (fXX) of 20 MHz) General-purpose registers: 32 bits × 32 registers CPU features: Signed multiplication (16 × 16 32): 1 to 2 clocks Signed multiplication (32 × 32 64): 1 to 5 clocks Saturated operations (overflow and underflow detection functions included) 32-bit shift instruction: 1 clock Bit manipulation instructions Load/store instructions with long/short format Memory space: 64 MB of linear address space (for programs and data) External expansion: Up to 16 MB (including 1 MB used as internal ROM/RAM) · Internal memory: RAM: 12/24/32/40/48 KB (see Table 1-1) Flash memory: 128/256/384/512/640 KB (see Table 1-1) · External bus interface: Separate bus/multiplexed bus output selectable 8/16 bit data bus sizing function Wait function · Programmable wait function · External wait function Idle state function Bus hold function Interrupts and exceptions: Non-maskable interrupts: 2 sources Maskable interrupts: Timer function: 32 sources Exception trap: I/O lines: 55 sources Software exceptions: 2 sources I/O ports: 84 16-bit interval timer M (TMM): 1 channel 16-bit timer/event counter P (TMP): 6 channels 16-bit timer/event counter Q (TMQ): 1 channel Watch timer: Real-time output port: Serial interface: 1 channel Watchdog timer: 1 channel 6 bits × 1 channel Asynchronous serial interface A (UARTA) 3-wire variable-length serial interface B (CSIB) I2C bus interface (I2C) UARTA/CSIB: 1 channel UARTA/I2C: 1 channel CSIB: A/D converter: 2 channels CSIB/I2C: 3 channels 10-bit resolution: 12 channels D/A converter: 8-bit resolution: 2 channels DMA controller: 4 channels On-chip debug function: JTAG interface Clock generator: During main clock or subclock operation 7-level CPU clock (fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, fXT) Clock-through mode/PLL mode selectable 20 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD CHAPTER 1 INTRODUCTION Internal oscillation clock: 200 kHz (TYP.) Power-save functions: HALT/IDLE1/IDLE2/STOP/subclock/sub-IDLE mode Package: 100-pin plastic QFP (14 × 20) (µPD70F3715 PD70F3715, 70F3716 70F3716, 70F3717 70F3717 only) 100-pin plastic LQFP (fine pitch) (14 × 14) 1.3 Application Fields Home audio, printers, digital home electronics, other consumer devices 1.4 Ordering Information Part Number µPD70F3715GF-JBT-A PD70F3715GF-JBT-A µPD70F3715GC-8EA-A PD70F3715GC-8EA-A µPD70F3716GF-JBT-A PD70F3716GF-JBT-A µPD70F3716GC-8EA-A PD70F3716GC-8EA-A µPD70F3717GF-JBT-A PD70F3717GF-JBT-A µPD70F3717GC-8EA-A PD70F3717GC-8EA-A µPD70F3718GC-8EA-A PD70F3718GC-8EA-A µPD70F3719GC-8EA-A PD70F3719GC-8EA-A Remark Package Internal Flash Memory 100-pin plastic QFP (14 × 20) 128 KB 100-pin plastic LQFP (fine pitch) (14 × 14) 128 KB 100-pin plastic QFP (14 × 20) 256 KB 100-pin plastic LQFP (fine pitch) (14 × 14) 256 KB 100-pin plastic QFP (14 × 20) 384 KB 100-pin plastic LQFP (fine pitch) (14 × 14) 384 KB 100-pin plastic LQFP (fine pitch) (14 × 14) 512 KB 100-pin plastic LQFP (fine pitch) (14 × 14) 640 KB Products with -A at the end of the part number are lead-free products. Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 21 CHAPTER 1 INTRODUCTION 1.5 Pin Configuration (Top View) 100-pin plastic QFP (14 × 20) µPD70F3716GF-JBT-A PD70F3716GF-JBT-A µPD70F3717GF-JBT-A PD70F3717GF-JBT-A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P72/ANI2 P72/ANI2 P73/ANI3 P73/ANI3 P74/ANI4 P74/ANI4 P75/ANI5 P75/ANI5 P76/ANI6 P76/ANI6 P77/ANI7 P77/ANI7 P78/ANI8 P78/ANI8 P79/ANI9 P79/ANI9 P710/ANI10 P710/ANI10 P711/ANI11 P711/ANI11 PDH1/A17 PDH1/A17 PDH0/A16 PDH0/A16 PDL15/AD15 PDL15/AD15 PDL14/AD14 PDL14/AD14 PDL13/AD13 PDL13/AD13 PDL12/AD12 PDL12/AD12 PDL11/AD11 PDL11/AD11 PDL10/AD10 PDL10/AD10 PDL9/AD9 PDL8/AD8 µPD70F3715GF-JBT-A PD70F3715GF-JBT-A 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P34/TIP10/TOP10 P34/TIP10/TOP10 P35/TIP11/TOP11 P35/TIP11/TOP11 P36 P37 EVSS EVDD P38/TXDA2/SDA00 P38/TXDA2/SDA00 P39/RXDA2/SCL00 P39/RXDA2/SCL00 P50/TIQ01/KR0/TOQ01/RTP00 P50/TIQ01/KR0/TOQ01/RTP00 P51/TIQ02/KR1/TOQ02/RTP01 P51/TIQ02/KR1/TOQ02/RTP01 P52/TIQ03/KR2/TOQ03/RTP02/DDI P52/TIQ03/KR2/TOQ03/RTP02/DDI P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO P54/SOB2/KR4/RTP04/DCK P54/SOB2/KR4/RTP04/DCK P55/SCKB2/KR5/RTP05/DMS P55/SCKB2/KR5/RTP05/DMS P90/A0/KR6/TXDA1/SDA02 P90/A0/KR6/TXDA1/SDA02 P91/A1/KR7/RXDA1/SCL02 P91/A1/KR7/RXDA1/SCL02 P92/A2/TIP41/TOP41 P92/A2/TIP41/TOP41 P93/A3/TIP40/TOP40 P93/A3/TIP40/TOP40 P94/A4/TIP31/TOP31 P94/A4/TIP31/TOP31 P95/A5/TIP30/TOP30 P95/A5/TIP30/TOP30 P71/ANI1 P71/ANI1 P70/ANI0 P70/ANI0 AVREF0 AVSS P10/ANO0 P10/ANO0 P11/ANO1 P11/ANO1 AVREF1 PDH4/A20 PDH4/A20 PDH5/A21 PDH5/A21 FLMD0Note 1 VDD REGCNote 2 VSS X1 X2 RESET XT1 XT2 P02/NMI P02/NMI P03/INTP0/ADTRG P03/INTP0/ADTRG P04/INTP1 P04/INTP1 P05/INTP2/DRST P05/INTP2/DRST P06/INTP3 P06/INTP3 P40/SIB0/SDA01 P40/SIB0/SDA01 P41/SOB0/SCL01 P41/SOB0/SCL01 P42/SCKB0 P42/SCKB0 P30/TXDA0/SOB4 P30/TXDA0/SOB4 P31/RXDA0/INTP7/SIB4 P31/RXDA0/INTP7/SIB4 P32/ASCKA0/SCKB4/TIP00/TOP00 P32/ASCKA0/SCKB4/TIP00/TOP00 P33/TIP01/TOP01 P33/TIP01/TOP01 Notes 1. Connect this pin to VSS in the normal mode. 2. Connect the REGC pin to VSS via a 4.7 µF capacitor. 22 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD PDL7/AD7 PDL6/AD6 PDL5/AD5/FLMD1 PDL4/AD4 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 BVDD BVSS PCT6/ASTB PCT4/RD PCT1/WR1 PCT0/WR0 PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PDH3/A19 PDH3/A19 PDH2/A18 PDH2/A18 P915/A15/INTP6/TIP50/TOP50 P915/A15/INTP6/TIP50/TOP50 P914/A14/INTP5/TIP51/TOP51 P914/A14/INTP5/TIP51/TOP51 P913/A13/INTP4 P913/A13/INTP4 P912/A12/SCKB3 P912/A12/SCKB3 P911/A11/SOB3 P911/A11/SOB3 P910/A10/SIB3 P910/A10/SIB3 P99/A9/SCKB1 P99/A9/SCKB1 P98/A8/SOB1 P98/A8/SOB1 P97/A7/SIB1/TIP20/TOP20 P97/A7/SIB1/TIP20/TOP20 P96/A6/TIP21/TOP21 P96/A6/TIP21/TOP21 CHAPTER 1 INTRODUCTION 100-pin plastic LQFP (fine pitch) (14 × 14) µPD70F3717GC-8EA-A PD70F3717GC-8EA-A µPD70F3718GC-8EA-A PD70F3718GC-8EA-A µPD70F3719GC-8EA-A PD70F3719GC-8EA-A 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P70/ANI0 P70/ANI0 P71/ANI1 P71/ANI1 P72/ANI2 P72/ANI2 P73/ANI3 P73/ANI3 P74/ANI4 P74/ANI4 P75/ANI5 P75/ANI5 P76/ANI6 P76/ANI6 P77/ANI7 P77/ANI7 P78/ANI8 P78/ANI8 P79/ANI9 P79/ANI9 P710/ANI10 P710/ANI10 P711/ANI11 P711/ANI11 PDH1/A17 PDH1/A17 PDH0/A16 PDH0/A16 PDL15/AD15 PDL15/AD15 PDL14/AD14 PDL14/AD14 PDL13/AD13 PDL13/AD13 PDL12/AD12 PDL12/AD12 PDL11/AD11 PDL11/AD11 PDL10/AD10 PDL10/AD10 PDL9/AD9 PDL8/AD8 PDL7/AD7 PDL6/AD6 PDL5/AD5/FLMD1 µPD70F3715GC-8EA-A PD70F3715GC-8EA-A µPD70F3716GC-8EA-A PD70F3716GC-8EA-A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PDL4/AD4 PDL3/AD3 PDL2/AD2 PDL1/AD1 PDL0/AD0 BVDD BVSS PCT6/ASTB PCT4/RD PCT1/WR1 PCT0/WR0 PCM3/HLDRQ PCM2/HLDAK PCM1/CLKOUT PCM0/WAIT PDH3/A19 PDH3/A19 PDH2/A18 PDH2/A18 P915/A15/INTP6/TIP50/TOP50 P915/A15/INTP6/TIP50/TOP50 P914/A14/INTP5/TIP51/TOP51 P914/A14/INTP5/TIP51/TOP51 P913/A13/INTP4 P913/A13/INTP4 P912/A12/SCKB3 P912/A12/SCKB3 P911/A11/SOB3 P911/A11/SOB3 P910/A10/SIB3 P910/A10/SIB3 P99/A9/SCKB1 P99/A9/SCKB1 P98/A8/SOB1 P98/A8/SOB1 P31/RXDA0/INTP7/SIB4 P31/RXDA0/INTP7/SIB4 P32/ASCKA0/SCKB4/TIP00/TOP00 P32/ASCKA0/SCKB4/TIP00/TOP00 P33/TIP01/TOP01 P33/TIP01/TOP01 P34/TIP10/TOP10 P34/TIP10/TOP10 P35/TIP11/TOP11 P35/TIP11/TOP11 P36 P37 EVSS EVDD P38/TXDA2/SDA00 P38/TXDA2/SDA00 P39/RXDA2/SCL00 P39/RXDA2/SCL00 P50/TIQ01/KR0/TOQ01/RTP00 P50/TIQ01/KR0/TOQ01/RTP00 P51/TIQ02/KR1/TOQ02/RTP01 P51/TIQ02/KR1/TOQ02/RTP01 P52/TIQ03/KR2/TOQ03/RTP02/DDI P52/TIQ03/KR2/TOQ03/RTP02/DDI P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO P53/SIB2/KR3/TIQ00/TOQ00/RTP03/DDO P54/SOB2/KR4/RTP04/DCK P54/SOB2/KR4/RTP04/DCK P55/SCKB2/KR5/RTP05/DMS P55/SCKB2/KR5/RTP05/DMS P90/A0/KR6/TXDA1/SDA02 P90/A0/KR6/TXDA1/SDA02 P91/A1/KR7/RXDA1/SCL02 P91/A1/KR7/RXDA1/SCL02 P92/A2/TIP41/TOP41 P92/A2/TIP41/TOP41 P93/A3/TIP40/TOP40 P93/A3/TIP40/TOP40 P94/A4/TIP31/TOP31 P94/A4/TIP31/TOP31 P95/A5/TIP30/TOP30 P95/A5/TIP30/TOP30 P96/A6/TIP21/TOP21 P96/A6/TIP21/TOP21 P97/A7/SIB1/TIP20/TOP20 P97/A7/SIB1/TIP20/TOP20 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 AVREF0 AVSS P10/ANO0 P10/ANO0 P11/ANO1 P11/ANO1 AVREF1 PDH4/A20 PDH4/A20 PDH5/A21 PDH5/A21 FLMD0Note 1 VDD REGCNote 2 VSS X1 X2 RESET XT1 XT2 P02/NMI P02/NMI P03/INTP0/ADTRG P03/INTP0/ADTRG P04/INTP1 P04/INTP1 P05/INTP2/DRST P05/INTP2/DRST P06/INTP3 P06/INTP3 P40/SIB0/SDA01 P40/SIB0/SDA01 P41/SOB0/SCL01 P41/SOB0/SCL01 P42/SCKB0 P42/SCKB0 P30/TXDA0/SOB4 P30/TXDA0/SOB4 Notes 1. Connect this pin to VSS in the normal mode. 2. Connect the REGC pin to VSS via a 4.7 µF capacitor. Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 23 CHAPTER 1 INTRODUCTION Pin names A0 to A21: Address bus PDH0 to PDH5: Port DH AD0 to AD15: Address/data bus PDL0 to PDL15 PDL15: Port DL ADTRG: A/D trigger input RD: Read strobe ANI0 to ANI11 ANI11: Analog input REGC: Regulator control ANO0, ANO1: Analog output RESET: Reset ASCKA0: Asynchronous serial clock RTP00 RTP00 to RTP05 RTP05: Real-time output port ASTB: Address strobe RXDA0 to RXDA2: Receive data AVREF0, AVREF1: Analog reference voltage SCKB0 to SCKB4: Serial clock AVSS: Analog VSS SCL00 SCL00 to SCL02 SCL02: Serial clock BVDD: Power supply for bus interface SDA00 SDA00 to SDA02 SDA02: Serial data BVSS: Ground for bus interface SIB0 to SIB4: Serial input CLKOUT: Clock output SOB0 to SOB4: Serial output DCK: Debug clock TIP00 TIP00, TIP01 TIP01, DDI: Debug data input TIP10 TIP10, TIP11 TIP11, DDO: Debug data output TIP20 TIP20, TIP21 TIP21, DMS: Debug mode select TIP30 TIP30, TIP31 TIP31, DRST: Debug reset TIP40 TIP40, TIP41 TIP41, EVDD: Power supply for port TIP50 TIP50, TIP51 TIP51, EVSS: Ground for port TIQ00 TIQ00 to TIQ03 TIQ03: FLMD0, FLMD1: Flash programming mode TOP00, TOP01, HLDAK: Hold acknowledge TOP10, TOP11, HLDRQ: Hold request TOP20, TOP21, INTP0 to INTP7: External interrupt input TOP30, TOP31, KR0 to KR7: Key return TOP40, TOP41, NMI: Non-maskable interrupt request TOP50, TOP51, P02 to P06: Port 0 TOQ00 to TOQ03: Timer output P10, P11: Port 1 TXDA0 to TXDA2: Transmit data P30 to P39: Port 3 VDD: Power supply P40 to P42: Port 4 VSS: Ground P50 to P55: Port 5 WAIT: Wait P70 to P711: Port 7 WR0: Lower byte write strobe P90 to P915: Port 9 WR1: Upper byte write strobe PCM0 to PCM3: Port CM X1, X2: Crystal for main clock XT1, XT2: Crystal for subclock PCT0, PCT1, PCT4, PCT6: 24 Port CT Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD Timer input CHAPTER 1 INTRODUCTION 1.6 Function Block Configuration 1.6.1 Internal block diagram NMI INTP0 to INTP7 TIQ00 TIQ00 to TIQ03 TIQ03 TOQ00 to TOQ03 TIP00 TIP00 to TIP50 TIP50, TIP01 TIP01 to TIP51 TIP51 TOP00 to TOP50, TOP01 to TOP51 CPU ROM INTC Note 1 16-bit timer/ counter Q: 1 ch 16-bit timer/ counter P: 6 ch RAM 32-bit barrel shifter Instruction queue PC Multiplier 16 × 16 32 System registers Note 2 BCU ALU A0 to A21 AD0 to AD15 General-purpose registers 32 bits × 32 DMAC HLDRQ HLDAK ASTB RD WAIT WR0, WR1 16-bit interval timer M: 1 ch RTO CSIB0 I2C01 I2C01 SOB1 SIB1 SCKB1 CSIB1 SOB2 SIB2 SCKB2 CSIB2 SOB3 SIB3 SCKB3 PCM0 to PCM3 PCT0, PCT1, PCT4, PCT6 PDH0 to PDH5 PDL0 to PDL15 PDL15 P90 to P915 P70 to P711 P50 to P55 P40 to P42 P30 to P39 P10, P11 P02 to P06 SOB0/SDA01 SOB0/SDA01 SIB0/SCL01 SIB0/SCL01 SCKB0 Internal oscillator Ports A/D converter CSIB3 CG PLL CLKOUT XT1 XT2 X1 X2 RESET LVI VDD Regulator VSS REGC ANI0 to ANI11 ANI11 AVSS AVREF0 ADTRG FLMD0 FLMD1 BVDD BVSS TXDA0/SOB4 RXDA0/SIB4 ASCKA0/SCKB4 UARTA0 CSIB4 TXDA1/SDA02 TXDA1/SDA02 RXDA1/SCL02 RXDA1/SCL02 UARTA1 I2C02 I2C02 D/A converter AVREF1 ANO0, ANO1 EVDD Key return function KR0 to KR7 DRST Watchdog timer 2 TXDA2/SDA00 TXDA2/SDA00 RXDA2/SCL00 RXDA2/SCL00 CLM RTP00 RTP00 to RTP05 RTP05 2 UARTA2 I C00 Watch timer EVSS On-chip debug function DMS DDI DCK DDO Notes 1. 128/256/384/512/640 KB (flash memory) (see Table 1-1) 2. 12/24/32/40/48 KB (see Table 1-1) Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 25 CHAPTER 1 INTRODUCTION 1.6.2 Internal units (1) CPU The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic operations, data transfers, and almost all other instruction processing. Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits 32 bits) and a barrel shifter (32 bits) contribute to faster complex processing. (2) Bus control unit (BCU) The BCU starts a required external bus cycle based on the physical address obtained by the CPU. When an instruction is fetched from external memory space and the CPU does not send a bus cycle start request, the BCU generates a prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an instruction queue. (3) ROM This is a 640/512/384/256/128 KB flash memory mapped to addresses 0000000H 0000000H to 009FFFFH/0000000H 009FFFFH/0000000H to 007FFFFH/0000000H 007FFFFH/0000000H to 005FFFFH/0000000H 005FFFFH/0000000H to 003FFFFH/0000000H 003FFFFH/0000000H to 001FFFFH 001FFFFH. It can be accessed from the CPU in one clock during instruction fetch. (4) RAM This is a 48/40/32/24/12 KB RAM mapped to addresses 3FF3000H 3FF3000H to 3FFEFFFH/3FF5000H 3FFEFFFH/3FF5000H to 3FFEFFFH/3FF7000H 3FFEFFFH/3FF7000H to 3FFEFFFH/3FF9000H 3FFEFFFH/3FF9000H to 3FFEFFFH/3FFC000H 3FFEFFFH/3FFC000H to 3FFEFFFH. It can be accessed from the CPU in one clock during data access. (5) Interrupt controller (INTC) This controller handles hardware interrupt requests (NMI, INTP0 to INTP7) from on-chip peripheral hardware and external hardware. Eight levels of interrupt priorities can be specified for these interrupt requests, and multiplexed servicing control can be performed. (6) Clock generator (CG) A main clock oscillator and subclock oscillator are provided and generate the main clock oscillation frequency (fX) and subclock frequency (fXT), respectively. There are two modes: In the clock-through mode, fX is used as the main clock frequency (fXX) as is. In the PLL mode, fX is used multiplied by 4 or 8. The CPU clock frequency (fCPU) can be selected from among fXX, fXX/2, fXX/4, fXX/8, fXX/16, fXX/32, and fXT. (7) Internal oscillator An internal oscillator is provided on chip. The oscillation frequency is 200 kHz (TYP). The internal oscillator supplies the clock for watchdog timer 2 and timer M. (8) Timer/counter Six-channel 16-bit timer/event counter P (TMP), one-channel 16-bit timer/event counter Q (TMQ), and onechannel 16-bit interval timer M (TMM), are provided on chip. (9) Watch timer This timer counts the reference time period (0.5 s) for counting the clock (the 32.768 kHz subclock or the 32.768 kHz clock fBRG from prescaler 3). The watch timer can also be used as an interval timer for the main clock. 26 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD CHAPTER 1 INTRODUCTION (10) Watchdog timer 2 A watchdog timer is provided on chip to detect inadvertent program loops, system abnormalities, etc. The internal oscillation clock, the main clock, or the subclock can be selected as the source clock. Watchdog timer 2 generates a non-maskable interrupt request signal (INTWDT2) or a system reset signal (WDT2RES) after an overflow occurs. (11) Serial interface The V850ES/JG2 V850ES/JG2 includes three kinds of serial interfaces: asynchronous serial interface A (UARTA), 3-wire variable-length serial interface B (CSIB), and an I2C bus interface (I2C). In the case of UARTA, data is transferred via the TXDA0 to TXDA2 pins and RXDA0 to RXDA2 pins. In the case of CSIB, data is transferred via the SOB0 to SOB4 pins, SIB0 to SIB4 pins, and SCKB0 to SCKB4 pins. In the case of I2C, data is transferred via the SDA00 SDA00 to SDA02 SDA02 and SCL00 SCL00 to SCL02 SCL02 pins. (12) A/D converter This 10-bit A/D converter includes 12 analog input pins. Conversion is performed using the successive approximation method. (13) D/A converter A two-channel, 8-bit-resolution D/A converter that uses the R-2R ladder method is provided on chip. (14) DMA controller A 4-channel DMA controller is provided on chip. This controller transfers data between the internal RAM and on-chip peripheral I/O devices in response to interrupt requests sent by on-chip peripheral I/O. (15) Key interrupt function A key interrupt request signal (INTKR) can be generated by inputting a falling edge to the key input pins (8 channels). (16) Real-time output function The real-time output function transfers preset 6-bit data to output latches upon the occurrence of a timer compare register match signal. (17) On-chip debug function An on-chip debug function that uses the JTAG (Joint Test Action Group) communication specifications is provided. Switching between the normal port function and on-chip debugging function is done with the control pin input level and the OCDM register. Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 27 CHAPTER 1 INTRODUCTION (18) Ports The following general-purpose port functions and control pin functions are available. Port I/O Alternate Function P0 NMI, external interrupt, A/D converter trigger, debug reset P1 2-bit I/O D/A converter analog output P3 10-bit I/O External interrupt, serial interface, timer I/O P4 3-bit I/O Serial interface P5 6-bit I/O Timer I/O, real-time output, key interrupt input, serial interface P7 12-bit I/O A/D converter analog input P9 16-bit I/O External address bus, serial interface, key interrupt input, timer I/O, external interrupt PCM 4-bit I/O External control signal PCT 4-bit I/O External control signal PDH 6-bit I/O External address bus PDL 28 5-bit I/O 16-bit I/O External address/data bus Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD CHAPTER 2 PIN FUNCTIONS 2.1 List of Pin Functions The names and functions of the pins in the V850ES/JG2 V850ES/JG2 are described below. There are four types of pin I/O buffer power supplies: AVREF0, AVREF1, BVDD, and EVDD. The relationship between these power supplies and the pins is described below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply Corresponding Pins AVREF0 Port 7 AVREF1 Port 1 BVDD Ports CM, CT, DH (bits 0 to 3), DL EVDD RESET, ports 0, 3 to 5, 9, DH (bits 4, 5) Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 29 CHAPTER 2 PIN FUNCTIONS (1) Port pins (1/3) Pin Name Pin No. GF 19 17 P03 20 18 P04 21 19 P05 22 20 P06 23 21 P10 5 3 P11 6 4 Function Alternate Function GC P02 I/O Note I/O Port 0 NMI 5-bit I/O port Input/output can be specified in 1-bit units. N-ch open-drain output can be specified in 1-bit units. 5 V tolerant. INTP0/ADTRG INTP1 INTP2/DRST INTP3 I/O Port 1 2-bit I/O port ANO0 ANO1 Input/output can be specified in 1-bit units. P30 P31 27 28 25 I/O TXDA0/SOB4 Port 3 10-bit I/O port 26 Input/output can be specified in 1-bit units. RXDA0/INTP7/SIB4 P32 29 27 P33 30 28 P34 31 29 TIP10/TOP10 TIP10/TOP10 P35 32 30 TIP11/TOP11 TIP11/TOP11 P36 33 31 - P37 34 32 - P38 37 35 TXDA2/SDA00 TXDA2/SDA00 P39 38 36 RXDA2/SCL00 RXDA2/SCL00 P40 24 22 P41 25 26 39 37 P51 40 38 I/O ASCKA0/SCKB4/TIP00/TOP00 ASCKA0/SCKB4/TIP00/TOP00 TIP01/TOP01 TIP01/TOP01 SIB0/SDA01 SIB0/SDA01 Port 4 3-bit I/O port Input/output can be specified in 1-bit units. 24 P50 5 V tolerant. 23 P42 N-ch open-drain output can be specified in 1-bit units. N-ch open-drain output can be specified in 1-bit units. SOB0/SCL01 SOB0/SCL01 SCKB0 5 V tolerant. I/O Port 5 6-bit I/O port Input/output can be specified in 1-bit units. TIQ01/KR0/TOQ01/RTP00 TIQ01/KR0/TOQ01/RTP00 TIQ02/KR1/TOQ02/RTP01 TIQ02/KR1/TOQ02/RTP01 P52 41 39 P53 42 40 P54 43 41 SOB2/KR4/RTP04/DCK SOB2/KR4/RTP04/DCK P55 44 42 SCKB2/KR5/RTP05/DMS SCKB2/KR5/RTP05/DMS N-ch open-drain output can be specified in 1-bit units. 5 V tolerant. TIQ03/KR2/TOQ03/RTP02/DDI TIQ03/KR2/TOQ03/RTP02/DDI SIB2/KR3/TIQ00/TOQ00/RTP03/ SIB2/KR3/TIQ00/TOQ00/RTP03/ DDO Note Incorporates a pull-down resistor. It can be disconnected by clearing the OCDM.OCDM0 bit to 0. Remark GF: 100-pin plastic QFP (14 × 20) GC: 100-pin plastic LQFP (fine pitch) (14 × 14) 30 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD CHAPTER 2 PIN FUNCTIONS (2/3) Pin Name Pin No. GF I/O Function Alternate Function GC P70 2 100 I/O P71 1 99 Port 7 12-bit I/O port Input/output can be specified in 1-bit units. ANI0 ANI1 P72 100 98 P73 99 97 ANI3 P74 98 96 ANI4 P75 97 95 ANI5 P76 96 94 ANI6 P77 95 93 ANI7 P78 94 92 ANI8 P79 93 91 ANI9 P710 92 90 ANI10 ANI10 P711 91 89 ANI11 ANI11 P90 45 43 P91 46 44 I/O Port 9 16-bit I/O port ANI2 A0/KR6/TXDA1/SDA02 A0/KR6/TXDA1/SDA02 A1/KR7/RXDA1/SCL02 A1/KR7/RXDA1/SCL02 P92 47 45 Input/output can be specified in 1-bit units. N-ch open-drain output can be specified in 1-bit units. P93 48 46 5 V tolerant. P94 49 47 A4/TIP31/TOP31 A4/TIP31/TOP31 P95 50 48 A5/TIP30/TOP30 A5/TIP30/TOP30 P96 51 49 A6/TIP21/TOP21 A6/TIP21/TOP21 P97 52 50 A7/SIB1/TIP20/TOP20 A7/SIB1/TIP20/TOP20 P98 53 51 A8/SOB1 P99 54 52 A9/SCKB1 P910 55 53 A10/SIB3 A10/SIB3 P911 56 54 A11/SOB3 A11/SOB3 P912 57 55 A12/SCKB3 A12/SCKB3 P913 58 56 A13/INTP4 A13/INTP4 P914 59 57 A14/INTP5/TIP51/TOP51 A14/INTP5/TIP51/TOP51 P915 60 58 A15/INTP6/TIP50/TOP50 A15/INTP6/TIP50/TOP50 PCM0 63 61 PCM1 64 62 PCM2 65 66 64 PCT0 67 65 PCT1 68 66 Port CM 4-bit I/O port Input/output can be specified in 1-bit units. 63 PCM3 I/O PCT4 69 67 PCT6 70 A3/TIP40/TOP40 A3/TIP40/TOP40 WAIT CLKOUT HLDAK HLDRQ I/O Port CT 4-bit I/O port Input/output can be specified in 1-bit units. 68 Remark A2/TIP41/TOP41 A2/TIP41/TOP41 WR0 WR1 RD ASTB GF: 100-pin plastic QFP (14 × 20) GC: 100-pin plastic LQFP (fine pitch) (14 × 14) Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 31 CHAPTER 2 PIN FUNCTIONS (3/3) Pin Name Pin No. GF 89 87 PDH1 90 88 Function Alternate Function GC PDH0 I/O I/O Port DH 6-bit I/O port Input/output can be specified in 1-bit units. A16 A17 PDH2 61 59 PDH3 62 60 A19 PDH4 8 6 A20 PDH5 9 7 A21 PDL0 73 71 PDL1 74 72 I/O Port DL 16-bit I/O port Input/output can be specified in 1-bit units. A18 AD0 AD1 PDL2 75 73 PDL3 76 74 AD3 PDL4 77 75 AD4 PDL5 78 76 AD5/FLMD1 PDL6 79 77 AD6 PDL7 80 78 AD7 PDL8 81 79 AD8 PDL9 82 80 AD9 PDL10 PDL10 83 81 AD10 PDL11 PDL11 84 82 AD11 PDL12 PDL12 85 83 AD12 PDL13 PDL13 86 84 AD13 PDL14 PDL14 87 85 AD14 PDL15 PDL15 88 86 AD15 Remark GF: 100-pin plastic QFP (14 × 20) GC: 100-pin plastic LQFP (fine pitch) (14 × 14) 32 Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD AD2 CHAPTER 2 PIN FUNCTIONS (2) Non-port pins (1/6) Pin Name Pin No. I/O Function Alternate Function Address bus for external memory (when using separate bus) N-ch open-drain output selectable. 5 V tolerant. P90/KR6/TXDA1/SDA02 P90/KR6/TXDA1/SDA02 GF GC A0 45 43 A1 46 44 A2 47 45 A3 48 46 P93/TIP40/TOP40 P93/TIP40/TOP40 A4 49 47 P94/TIP31/TOP31 P94/TIP31/TOP31 A5 50 48 P95/TIP30/TOP30 P95/TIP30/TOP30 A6 51 49 P96/TIP21/TOP21 P96/TIP21/TOP21 A7 52 50 P97/SIB1/TIP20/TOP20 P97/SIB1/TIP20/TOP20 A8 53 51 P98/SOB1 P98/SOB1 A9 54 52 P99/SCKB1 P99/SCKB1 A10 55 53 P910/SIB3 P910/SIB3 A11 56 54 P911/SOB3 P911/SOB3 A12 57 55 P912/SCKB3 P912/SCKB3 A13 58 56 P913/INTP4 P913/INTP4 A14 59 57 P914/INTP5/TIP51/TOP51 P914/INTP5/TIP51/TOP51 A15 60 58 P915/INTP6/TIP50/TOP50 P915/INTP6/TIP50/TOP50 A16 89 87 A17 90 88 PDH1 A18 61 59 PDH2 A19 62 60 PDH3 A20 8 6 PDH4 A21 9 7 PDH5 AD0 73 71 AD1 74 72 PDL1 AD2 75 73 PDL2 AD3 76 74 PDL3 AD4 77 75 PDL4 AD5 78 76 PDL5/FLMD1 AD6 79 77 PDL6 AD7 80 78 PDL7 AD8 81 79 PDL8 AD9 82 80 PDL9 AD10 83 81 PDL10 PDL10 AD11 84 82 PDL11 PDL11 AD12 85 83 PDL12 PDL12 AD13 86 84 PDL13 PDL13 AD14 87 85 PDL14 PDL14 AD15 88 86 PDL15 PDL15 Remark Output Output I/O Address bus for external memory Address bus/data bus for external memory P91/KR7/RXDA1/SCL02 P91/KR7/RXDA1/SCL02 P92/TIP41/TOP41 P92/TIP41/TOP41 PDH0 PDL0 GF: 100-pin plastic QFP (14 × 20) GC: 100-pin plastic LQFP (fine pitch) (14 × 14) Preliminary User's Manual U17715EJ1V0UD U17715EJ1V0UD 33 CHAPTER 2 PIN FUNCTIONS (2/6) Pin Name Pin No. GF I/O Function Alternate Function GC ADTRG 20 18 ANI0 2 100 Input Input ANI1 1 99 P71 ANI2 100 98 P72 ANI3 99 97 P73 ANI4 98 96 P74 ANI5 97 95 P75 ANI6 96 94 P76 ANI7 95 93 P77 ANI8 94 92 P78 ANI9 93 91 P79 ANI10 ANI10 92 90 P710 ANI11 ANI11 91 89 P711 ANO0 5 3 ANO1 6 4 ASCKA0 29 27 Input ASTB 70 68 Output AVREF0 3 1 - Output A/D converter external trigger input. 5 V tolerant. P03/INTP0 P03/INTP0 Analog voltage input for A/D converter P70 Analog voltage output for D/A converter P10 P11 UARTA0 baud rate clock input. 5 V tolerant. P32/SCKB4/TIP00/TOP00 P32/SCKB4/TIP00/TOP00 Address strobe signal output for external memory PCT6 - Reference voltage input for A/D converter/positive power supply for port 7 AVREF1 7 - Reference voltage input for D/A converter/positive power 5 supply for port 1 AVSS 4 2 - - Ground potential for A/D and D/A converters (same potential as VSS) BVDD 72 70 - - Positive power supply pin for bus interface and alternatefunction ports BVSS 71 69 - - CLKOUT 64 62 Output Internal system clock output DCK 43 41 Input Debug clock input. 5 V tolerant. P54/SOB2/KR4/RTP04 P54/SOB2/KR4/RTP04 DDI 41 39 Input Debug data input. 5 V tolerant. P52/TIQ03/KR2/TOQ03/RTP02 P52/TIQ03/KR2/TOQ03/RTP02 DDONote 42 40 Output Debug data output. N-ch open-drain output selectable. P53/SIB2/KR3/TIQ00/TOQ00/ P53/SIB2/KR3/TIQ00/TOQ00/ 5 V tolerant. RTP03 RTP03 Ground potential for bus interface and alternate-function ports PCM1 DMS 44 42 Input Debug mode select input. 5 V tolerant. P55/SCKB2/KR5/RTP05 P55/SCKB2/KR5/RTP05 DRST 22 20 Input Debug reset input. 5 V tolerant. P05/INTP2 P05/INTP2 EVDD 36 34 - Positive power supply for external (same potential as VDD) - Ground potential for external (same potential as VSS) - Flash memory programming mode setting pin - EVSS 35